JP2018182279A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves easy carrier abstraction.SOLUTION: A semiconductor device comprises: a semiconductor substrate; a first conductivity type drift region provided inside the semiconductor substrate; a plurality of gate trenches provided from a top face of the semiconductor substrate to the drift region; a dummy trench provided between two gate trenches and from the top face of the semiconductor substrate to the drift region; a second conductivity type base region provided in a region of the semiconductor substrate adjacent to any gate trench and between the top face of the semiconductor substrate and the drift region; and a second conductivity type first well region which is provided in a region of the semiconductor substrate adjacent to the dummy trench to a position deeper than a bottom edge of the dummy trench and has a higher doping concentration than the base region.SELECTED DRAWING: Figure 2A

Description

  The present invention relates to a semiconductor device.

2. Description of the Related Art Conventionally, a power semiconductor device such as a gate insulating bipolar transistor (IGBT) is known (see, for example, Patent Document 1). In a semiconductor element such as an IGBT, the ON voltage can be reduced by accumulating carriers such as holes in the drift region.
Patent Document 1: JP-A-2015-72950

  If the carrier extraction is insufficient at the time of turn-off of the semiconductor device with respect to the concentration of carriers accumulated in the drift region, the withstand voltage of the semiconductor device is reduced.

  In a first aspect of the present invention, a semiconductor device provided with a semiconductor substrate is provided. The semiconductor device may include a drift region of the first conductivity type provided inside the semiconductor substrate. The semiconductor device may include a plurality of gate trench portions provided from the upper surface of the semiconductor substrate to the drift region. The semiconductor device may include a dummy trench portion provided between two gate trench portions and provided from the upper surface of the semiconductor substrate to the drift region. The semiconductor device may include a base region of the second conductivity type provided between the upper surface of the semiconductor substrate and the drift region in a region of the semiconductor substrate adjacent to any of the gate trench portions. The semiconductor device may include a first well region of a second conductivity type provided in the region of the semiconductor substrate adjacent to the dummy trench portion to a position deeper than the lower end of the dummy trench portion and having a doping concentration higher than that of the base region. .

  Two or more dummy trench portions may be provided between the two gate trench portions. A dummy mesa portion may be formed between the two dummy trench portions in the semiconductor substrate. The first well region may be provided in the dummy mesa portion. The first well region may be provided in contact with both of the two dummy trench portions.

  The first well region may cover at least a portion of the bottom of the dummy trench portion. The dummy trench portion may have a first dummy sidewall adjacent to the first well region. At the bottom of the dummy trench portion, the first well region may cover at least a part of the region between the center in the width direction and the first dummy sidewall. The dummy trench portion may have a second dummy sidewall opposite to the first dummy sidewall. The first well region may cover the bottom of the dummy trench portion to the second dummy sidewall side than the center in the width direction of the bottom portion of the dummy trench portion.

  The dummy trench portion and the gate trench portion may be formed to the same depth. The dummy trench portion may be formed deeper than the gate trench portion.

  The semiconductor device may include a collector region of the second conductivity type provided between the lower surface of the semiconductor substrate and the drift region. The semiconductor device may include a lower surface side region of the first conductivity type provided at the same depth position as the collector region in at least a partial region below the dummy mesa portion.

  The dummy trench portion may have a long side and a short side on the upper surface of the semiconductor substrate. The collector region and the lower surface side region may be alternately arranged along the longitudinal direction of the dummy trench portion below the dummy mesa portion.

  A storage region having a doping concentration higher than that of the drift region may be provided in a region adjacent to the gate trench portion inside the semiconductor substrate. The doping concentration of the first conductivity type in the region adjacent to the dummy trench in the semiconductor substrate and at the same depth position as the storage region may be lower than that in the storage region.

  The storage region may be provided continuously from a position in contact with one trench portion to a position in contact with the other trench portion in a mesa portion at least one of which is sandwiched by two trench portions having a gate trench portion. A storage region may not be provided in the dummy mesa portion.

  The storage region may be in contact with the gate trench portion in the mesa portion sandwiched between the adjacent gate trench portion and the dummy trench portion. The accumulation region may be provided not in contact with the dummy trench portion.

  The gate trench portion may have a long side and a short side on the upper surface of the semiconductor substrate. The gate trench portion may have a first gate sidewall along the longitudinal direction of the gate trench and a second gate sidewall opposite to the first gate sidewall inside the semiconductor substrate. Inside the semiconductor substrate, a first mesa portion adjacent to a first gate sidewall of the gate trench portion and a second mesa portion adjacent to a second gate sidewall of the gate trench portion may be provided. Emitter regions of the first conductivity type and contact regions of the second conductivity type are arranged on the upper surfaces of the first and second mesa portions so as to be alternately exposed along the longitudinal direction of the gate trench portion. Good. At least a partial area of at least one emitter area in the first mesa may be disposed at a position facing the contact area in the second mesa.

  The semiconductor device may further include an emitter region of the first conductivity type provided on the upper surface of the semiconductor substrate adjacent to the gate trench portion. The contact width of the contact formed on the first well region may be larger than the contact width of the contact formed on the emitter region.

  The mesa width of the mesa portion between the dummy trench portions may be larger than the mesa width of the mesa portion sandwiched by two trench portions, at least one of which is a gate trench portion.

  In the dummy mesa portion, an accumulation region having a doping concentration higher than that of the drift region may be provided.

  The film thickness of the dummy insulating film in the dummy trench portion may be larger than the film thickness of the gate insulating film in the gate trench portion.

  A second aspect of the present invention provides a semiconductor device provided with a semiconductor substrate. The semiconductor device may be provided from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate, and may include a gate trench portion having a long side and a short side on the upper surface of the semiconductor substrate and having a first gate sidewall and a second gate sidewall. The first gate sidewall may be provided along the longitudinal direction inside the semiconductor substrate. The second gate sidewall may be a second gate sidewall opposite to the first gate sidewall. The semiconductor device may include a first mesa portion adjacent to a first gate sidewall of the gate trench portion inside the semiconductor substrate. The semiconductor device may include a second mesa portion adjacent to a second gate sidewall of the gate trench portion. The emitter regions of the first conductivity type and the contact regions of the second conductivity type are arranged alternately on the upper surfaces of the first mesa portion and the second mesa portion along the longitudinal direction of the gate trench portion. May be done. At least a partial area of at least one emitter area in the first mesa may be disposed at a position facing the contact area in the second mesa.

  At least a partial region of at least one contact region in the first mesa may be disposed at a position facing the emitter region in the second mesa. In the first mesa portion, the emitter region may be formed longer in the longitudinal direction of the gate trench portion than the contact region. In the first mesa portion, the contact region may be formed longer in the longitudinal direction of the gate trench portion than the emitter region.

  In the first mesa portion, the lengths of the emitter region and the contact region in the longitudinal direction of the gate trench may be the same. In the first mesa portion, a trench portion extending in the short direction of the gate trench portion may not be formed in the region where the emitter region or the contact region is formed.

  The above summary of the invention does not enumerate all of the features of the present invention. A subcombination of these feature groups can also be an invention.

It is a figure which shows partially the upper surface of the semiconductor device 100 which concerns on embodiment of this invention. It is a figure which shows an example of the aa cross section in FIG. It is a figure which shows an example of the aa cross section in FIG. It is a figure which shows an example of the aa cross section in FIG. It is an example of distribution map of doping concentration when the c-c cross section and the d-d cross section of FIG. 2A are cut. It is another example of distribution chart of doping concentration when the c-c cross section and the d-d cross section of FIG. 2A are cut. FIG. 6 is a view showing another example of the upper surface of the semiconductor device 100. It is a figure which shows an example of the aa cross section in FIG. It is a figure which shows an example of the aa cross section in FIG. It is an example of a distribution map of doping concentration when the c-c cross section and the d-d cross section of FIG. 4B are cut. It is another example of distribution chart of doping concentration when the c-c cross section and the d-d cross section of FIG. 4B are cut. It is a figure which shows an example of the aa cross section in FIG. FIG. 6 is a view showing another example of the upper surface of the semiconductor device 100. It is a figure which shows an example of the aa cross section in FIG. It is a figure which shows the other example of the aa cross section in FIG. It is a figure which shows the other example of the aa cross section in FIG. It is a figure which shows the other example of the aa cross section in FIG. It is a figure which shows the other example of the aa cross section in FIG. FIG. 6 is an enlarged cross-sectional view of the vicinity of the first well region 13; FIG. 13 is a cross-sectional view showing an example in which the position of the end 36 of the first well region 13 covering the bottom 35 is changed in the structure shown in FIG. 11; FIG. 13 is a cross-sectional view showing an example in which the position of the end 36 of the first well region 13 covering the bottom 35 is changed in the structure shown in FIG. 11; FIG. 16 is a view showing another example of the dummy trench portion 30 and the gate trench portion 40. FIG. 7 is a view showing another example of the first well region 13; FIG. 6 is a view showing another example of the aa cross section of the semiconductor device 100. It is a figure which shows an example of the bb cross section shown in FIG. It is a figure which shows partially the upper surface of the semiconductor device 200 which concerns on other embodiment of this invention. It is a figure which shows an example of the aa cross section in FIG. It is a figure which shows the other example of the aa cross section in FIG. It is a figure which shows the example of arrangement | positioning of the emitter area | region 12 and the contact area | region 15 in the upper surface of the 1st mesa part 71-1 and the 2nd mesa part 71-2. It is a figure which shows the other example of arrangement | positioning of the emitter area | region 12 and the contact area | region 15 in the upper surface of the 1st mesa part 71-1 and the 2nd mesa part 71-2. It is a figure which shows the other example of arrangement | positioning of the emitter area | region 12 and the contact area | region 15 in the upper surface of the 1st mesa part 71-1 and the 2nd mesa part 71-2. FIG. 6 is a view showing an arrangement example of a storage area 16; FIG. 16 is a diagram showing an example of a method of manufacturing the semiconductor device 100.

  Hereinafter, the present invention will be described through the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Moreover, not all combinations of features described in the embodiments are essential to the solution of the invention.

  In the present specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as “upper”, and the other side is referred to as “lower”. Of the two main surfaces of the substrate, layer or other member, one surface is referred to as the upper surface, and the other surface is referred to as the lower surface. The directions of “upper” and “lower” are not limited to the direction of gravity or the mounting direction to a substrate or the like at the time of mounting of the semiconductor device. In this specification, technical matters may be described using orthogonal coordinate axes of the X axis, the Y axis, and the Z axis. The depth direction of the semiconductor substrate is taken as the Z axis. Further, the orthogonal coordinate system is a so-called right hand system in this example.

  Although the terms "emitter" and "collector" are used herein, the semiconductor device is not limited to the IGBT. "Source" and "drain" in a transistor such as a MOSFET may also be included within the scope of the terms "emitter" and "collector" herein.

  In each embodiment, an example in which the first conductivity type is N-type and the second conductivity type is P-type is shown, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region and the like in the respective embodiments have opposite polarities. In the present specification, when comparing doping concentrations between regions, peak concentrations in the respective regions may be used.

  In the present specification, the term “identical” may also include an error due to manufacturing variations and the like. The error is, for example, within 10%.

  FIG. 1 is a view partially showing an upper surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 in this example is a semiconductor chip including a transistor such as an IGBT. In FIG. 1, the top surface of the chip around the chip end is shown, and the other regions are omitted.

  Although FIG. 1 shows the active region of the semiconductor substrate in the semiconductor device 100, the semiconductor device 100 may have an edge termination portion surrounding the active region. The active region indicates a region through which current flows when the semiconductor device 100 is controlled to be in an on state. The edge termination alleviates the concentration of the electric field on the upper surface side of the semiconductor substrate. The edge end has, for example, a guard ring, a field plate, a resurf, and a combination of these.

  The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, a first well region 13 and a second well region 11 provided inside a semiconductor substrate. Prepare. In addition, the semiconductor device 100 of the present example includes the emitter electrode 52 and the gate electrode 46 provided above the upper surface of the semiconductor substrate. Emitter electrode 52 and gate electrode 46 are provided separately from each other.

  An interlayer insulating film is provided between the emitter electrode 52 and the gate electrode 46 and the upper surface of the semiconductor substrate, but is omitted in FIG. A contact hole 54, a contact hole 55, and a contact hole 56 are provided in the interlayer insulating film of this example so as to penetrate the interlayer insulating film.

  Emitter electrode 52 is in contact with emitter region 12, contact region 15, base region 14 and first well region 13 on the upper surface of the semiconductor substrate through contact hole 54. The contact holes 54 in this example are provided between the respective trench portions. Further, emitter electrode 52 is connected to the dummy conductive portion in dummy trench portion 30 through contact hole 56. Between the emitter electrode 52 and the dummy conductive portion, a connection portion 57 formed of a conductive material such as polysilicon doped with an impurity may be provided. The connection portion 57 is provided on the upper surface of the semiconductor substrate with an insulating film such as a thermal oxide film interposed therebetween. In the present example, the contact hole 56 is disposed at the tip of the dummy trench portion 30 in the X-axis direction.

  Gate electrode 46 is in contact with gate interconnection 45 through contact hole 55. Gate interconnection 45 is formed of polysilicon or the like doped with an impurity. An insulating film such as a thermal oxide film is provided between the gate wiring 45 and the semiconductor substrate. Gate interconnection 45 is connected to the gate conductive portion in gate trench portion 40 on the upper surface of the semiconductor substrate. Gate interconnection 45 is not connected to the dummy conductive portion in dummy trench portion 30. The gate wiring 45 in this example is provided from below the contact hole 55 to the tip 43 of the gate trench portion 40. The gate conductive portion is exposed at the top surface of the semiconductor substrate at the tip portion 43 of the gate trench portion 40 and is in contact with the gate wiring 45.

  Emitter electrode 52 and gate electrode 46 are formed of a material containing metal. For example, at least a partial region of each electrode is formed of aluminum or aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium, a titanium compound, or the like below the region formed of aluminum or the like. Furthermore, in the contact hole, a plug formed by embedding tungsten or the like so as to be in contact with the barrier metal and aluminum or the like may be provided.

  The one or more gate trench portions 40 and the one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (short direction) on the upper surface of the semiconductor substrate. The arrangement direction in FIG. 1 is the Y-axis direction.

  In the gate trench portion 40 of this example, two extending portions 41 extending in a linear shape along the extending direction (longitudinal direction of the trench, in this example, the X-axis direction) perpendicular to the arrangement direction It may have a tip 43 connecting the two extension parts 41. Preferably, at least a part of the tip portion 43 is formed in a curved shape on the upper surface of the semiconductor substrate. By connecting the tips of the two extension parts 41 of the gate trench part 40 with the tip part 43, electric field concentration at the end of the extension part 41 can be alleviated. In the present specification, two extension portions 41 connected by the tip portion 43 may be treated as two gate trench portions 40.

  One or more dummy trench portions 30 are provided between the extension portions 41 of the gate trench portions 40. Similar to the gate trench portion 40, the dummy trench portion 30 may have a tip portion 33 connecting the tips of the two extension portions 31. In the present example, a dummy trench portion 30 having two extension portions 31 and a tip portion 33 is provided between the extension portions 41 of the gate trench portion 40. The dummy trench portion 30 of another example may have a linear shape without the tip portion 33. The dummy trench portion 30 is provided at a position not overlapping the gate wiring 45. In the present specification, the two extension portions 31 connected by the tip end portion 33 may be treated as two dummy trench portions 30.

  Emitter electrode 52 is provided above gate trench portion 40, dummy trench portion 30, first well region 13, second well region 11, emitter region 12, base region 14 and contact region 15. The second well region 11 is provided in a predetermined range away from the longitudinal end of the contact hole 54 in the direction toward the gate electrode 46. The diffusion depth of the second well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 on the gate electrode 46 side is provided in the second well region 11. The bottom in the extending direction of the dummy trench portion 30 and the tip end may be covered by the second well region 11.

  In this example, the region of the semiconductor substrate sandwiched between the trench portions is referred to as a mesa portion 71. However, a region of the semiconductor substrate sandwiched by two dummy trench portions 30 (or two extension portions 31) is referred to as a dummy mesa portion 72. The mesa portion 71 and the dummy mesa portion 72 are regions on the upper surface side of the deepest bottom portion of the trench portion in the region of the semiconductor substrate sandwiched between the trench portions.

  In the mesa portion 71, a base region 14 is provided. The second well region 11 is of the second conductivity type. The base region 14 is P− type having a doping concentration lower than that of the second well region 11, and the second well region 11 is P + type.

  On the upper surface of the base region 14 of the mesa portion 71, a P + -type contact region 15 having a higher doping concentration than the base region 14 is provided. The second well region 11 is provided in the direction of the gate electrode 46 away from the contact region 15 disposed at the end of the contact region 15 in the active region in the extending direction of the trench portion. Further, an N + -type emitter region 12 having a doping concentration higher than that of the semiconductor substrate is selectively formed on the upper surface of the base region 14.

  Each of contact region 15 and emitter region 12 is provided from one adjacent trench in the Y-axis direction to the other trench. The contact regions 15 and the emitter regions 12 are provided so as to be alternately exposed on the upper surface of the semiconductor substrate along the extending direction (X-axis direction) of the trench portion. The contact region 15 and the emitter region 12 may be provided on the upper surface of the mesa portion 71 in a region sandwiched by the base regions 14 exposed at both ends in the X-axis direction.

  In the mesa portion 71 of another example, the contact region 15 and the emitter region 12 may be provided in a stripe shape along the extending direction (X-axis direction). For example, the emitter region 12 is provided in the region adjacent to the trench portion, and the contact region 15 is provided in the region sandwiched by the emitter regions 12.

  The dummy mesa portion 72 is provided with a first well region 13 of the second conductivity type having a doping concentration higher than that of the base region 14. The first well region 13 of this example is of P + type. The doping concentration of the first well region 13 may be the same as or different from the doping concentration of the second well region 11. The doping concentration of the first well region 13 may be 5 times or more or 10 times or more the doping concentration of the base region 14.

  The first well region 13 is provided so as to be exposed on the upper surface of the dummy mesa portion 72. The first well region 13 in this example is provided in a range facing the emitter region 12 and the contact region 15 in the mesa 71 adjacent in the Y-axis direction. The first well region 13 is continuously provided in the Y-axis direction from the position in contact with one dummy trench portion 30 to the position in contact with the other dummy trench portion 30 on the upper surface of the dummy mesa portion 72. The first well region 13 may be provided continuously on the upper surface of the dummy mesa portion 72 in a region sandwiched by the base regions 14 exposed at both ends in the X-axis direction.

  A contact hole 54 provided in the mesa portion 71 is provided above each of the contact region 15 and the emitter region 12. The contact hole 54 provided in the dummy mesa portion 72 is provided above the first well region 13. The contact hole 54 is not provided in the region corresponding to the base region 14 and the second well region 11. The emitter region may not be provided on the upper surface of the dummy mesa portion 72. The contact region 15 may be provided on the upper surface of the dummy mesa 72 at least in the region where the contact hole 54 is to be formed.

  FIG. 2A is a view showing an example of an aa cross section in FIG. The aa cross section of this example is a YZ plane passing through the emitter region 12. The semiconductor device 100 of this example has the semiconductor substrate 10, the interlayer insulating film 26, the emitter electrode 52, and the collector electrode 58 in the cross section. The interlayer insulating film 26 is, for example, silicate glass to which an impurity such as boron and phosphorus is added. Interlayer insulating film 26 is selectively formed on upper surface 21 of semiconductor substrate 10. Emitter electrode 52 is provided on upper surface 21 of semiconductor substrate 10 and interlayer insulating film 26. The collector electrode 58 is provided on the lower surface 23 of the semiconductor substrate 10. The collector electrode 58 may be provided on the entire lower surface 23 of the semiconductor substrate 10.

  The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 of this example is a silicon substrate.

  Inside the semiconductor substrate 10, an N− type drift region 18 is provided. The drift region 18 in the cross section is a region of the semiconductor substrate 10 where the emitter region 12, the base region 14, the first well region 13, the buffer region 20, and the collector region 22 are not formed.

  In the region of the semiconductor substrate 10 adjacent to any one of the gate trench portions 40, a P − -type base region is provided between the upper surface 21 of the semiconductor substrate 10 and the drift region 18. In this example, each mesa portion 71 is provided with a P-type base region. The base region 14 may be formed by implanting P-type impurities such as boron from the upper surface of the semiconductor substrate 10.

  In the mesa portion 71, an N + -type emitter region 12 is provided on the upper surface of the base region 14. Emitter region 12 may be formed by implanting an N-type impurity such as phosphorus or arsenic from the upper surface of semiconductor substrate 10.

  A first well region 13 is provided between the top surface 21 of the semiconductor substrate 10 and the drift region 18 in the region of the semiconductor substrate 10 adjacent to any of the dummy trench portions 30. The first well region 13 is provided from the upper surface 21 of the semiconductor substrate 10 to a position deeper than the lower end of the dummy trench portion 30. In the cross section shown in FIG. 2A, the first well region 13 is provided in the entire dummy mesa portion 72 and the region under the dummy mesa portion 72.

  The lower end of the first well region 13 may be determined based on the doping concentration distribution in the depth direction (Z-axis direction) of the first well region 13 and the drift region 18. As used herein, doping concentration refers to the concentration of a donor or acceptorized impurity (dopant). The depth position at which the concentration difference (net doping concentration) distribution of the donor and the acceptor has a minimum value, which is measured by the spread resistance (SR) method or the like, may be the lower end of the first well region 13.

  Gate trench portion 40 is formed from upper surface 21 of semiconductor substrate 10 to the inside of semiconductor substrate 10, and is in contact with emitter region 12 and base region 14 on the side wall. The gate trench portion 40 of this example is not in contact with the first well region 13. The gate trench portion 40 of this example is provided to penetrate the emitter region 12 and the base region 14 from the upper surface 21 of the semiconductor substrate 10.

  The dummy trench portion 30 is formed from the upper surface 21 of the semiconductor substrate 10 to the inside of the semiconductor substrate 10 and is in contact with the first well region 13 on the side wall. Of the side walls of the dummy trench portion 30, the side wall facing the gate trench portion 40 may be in contact with the emitter region 12 and the base region 14. Gate trench portion 40 and dummy trench portion 30 may be provided to the same depth position Z1 in the Z-axis direction.

  The bottom of the gate trench portion 40 in this example is disposed in the drift region 18. The bottom of the dummy trench portion 30 may be disposed in the drift region 18 and may be covered by the first well region 13. In addition, that a trench part penetrates each doping area | region is not limited to what was manufactured in order of forming a trench part after forming a doping area | region. After forming the trench portion, those in which the doping region is formed between the trench portions are also included in those in which the trench portion penetrates the doping region.

  The buffer region 20 is formed on the lower surface side of the drift region 18. The doping concentration of buffer region 20 is higher than the doping concentration of drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the P + -type collector region 22. On the lower surface side of the buffer region 20, a P + -type collector region 22 is formed.

  The gate trench portion 40 has a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is covered with the gate insulating film 42 inside the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

  Gate conductive portion 44 includes a region facing at least adjacent base region 14 with gate insulating film 42 interposed therebetween in the depth direction. The gate trench portion 40 in the cross section is covered with the interlayer insulating film 26 on the upper surface of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel of the inversion layer of electrons is formed in the surface layer of the interface in contact with the gate trench portion 40 in the base region 14.

  The dummy trench portion 30 in the present example has a dummy insulating film 32 and a dummy conductive portion 34. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench portion 30 and is covered with the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. The dummy trench portion 30 in the cross section is covered with the interlayer insulating film 26 on the upper surface of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved downward (curved in cross section).

The width of the mesa 71 and the width of the dummy mesa 72 may be equal. The width of the mesa portion 71 is typically 1.0 μm and may be 0.1 μm or more and 3.0 μm or less. The width W _GT of the gate trench portion and the width W _DT of the dummy trench portion 30 may be equal to or different from each other. In this example, they are equal. Further, the width C of the mesa portion 71 may be equal to the width D of the dummy mesa portion 72.

  The width in the Y-axis direction of the contact hole 54 may be equal between the mesa 71 and the dummy mesa 72. The width of the contact hole 54 is typically 0.6 μm, and may be 0.05 μm or more and 2.0 μm or less within the range not exceeding the mesa width or the dummy mesa width.

  By providing the dummy trench portion 30, the carrier accumulation effect can be enhanced to promote conductivity modulation, and the on voltage can be reduced. Further, by adjusting the ratio of the dummy trench portion 30 to the gate trench portion 40, the switching speed of the semiconductor device 100 can be adjusted.

  When the semiconductor device 100 is turned off, carriers accumulated near the bottom of the trench in the drift region 18 are extracted to the emitter electrode 52 via the region of the second conductivity type. If the carrier extraction speed at turn-off time is slow relative to the accumulated carrier concentration, the semiconductor device 100 has a reduced tolerance. The carrier extraction rate refers to the amount of carriers such as holes extracted from the drift region 18 to the emitter electrode 52 or the like per unit time when the semiconductor device 100 is turned off.

  In the semiconductor device 100, by providing the first well region 13 formed deeper than the dummy trench portion 30, carriers such as holes accumulated in the vicinity of the bottom of the trench can be efficiently extracted. Therefore, the reduction of the on voltage of the semiconductor device 100 and the maintenance of the withstand voltage of the semiconductor device 100 can be easily achieved at the same time.

  FIG. 2B is a view showing an example of an aa cross section in FIG. In the semiconductor device 100 of the present example, the contact width of the contact for connecting to the semiconductor substrate 10 is different from the case of FIG. 2A. In this example, the contact width B of the contact formed on the first well region 13 is different from the contact width A of the contact formed on the emitter region 12. The contact width B in this example may be larger or smaller than the contact width A. In this example, the contact width B is larger than the contact width A. That is, by making the contact width B between the dummy trench portions 30 larger than the contact width A between the dummy trench portion 30 and the gate trench portion 40, the turn-off tolerance of the semiconductor device 100 can be improved.

  The ratio (A / B) of the contact width A to the contact width B may be 0.2 or more and 2.0 or less. When the contact width B is larger than the contact width A, the ratio (A / B) may be 0.2 or more and less than 1.0, and may be 0.4 or more and 0.7 or less. On the other hand, when the contact width B is smaller than the contact width A, the ratio (A / B) may be greater than 1.0 and 2.0 or less, and further 1.3 or more and 1.7 or less.

  FIG. 2C is a view showing an example of an aa cross section in FIG. The semiconductor device 100 of this example is different from the case of FIG. 2A in that the width in the Y-axis direction of the dummy mesa portion 72 is different from the width in the Y-axis direction of the mesa portion 71. In this example, the width D of the dummy mesa 72 is different from the width C of the mesa 71 between the dummy trench 30 and the gate trench 40. The width D of the dummy mesa 72 in this example may be larger than the width C of the mesa 71. By making the width D of the dummy mesa portion 72 larger than the widths C of the other mesa portions 71, the turn-off tolerance of the semiconductor device 100 can be improved.

  The ratio (D / C) of the width C of the mesa 71 to the width D of the dummy mesa 72 may be greater than 0.2 and 5.0 or less. When the width D of the dummy mesa portion 72 is smaller than the width C of the mesa portion 71, the ratio (D / C) may be 0.2 or more and less than 1.0, and further 0.4 or more and 0.7 or less. On the other hand, when the width D of the dummy mesa portion 72 is larger than the width C of the mesa portion 71, the ratio (D / C) is greater than 1.0 and 5.0 or less, and is 2.0 or more and 4.0 or less Good.

  FIG. 2D is an example of a distribution diagram of doping concentrations when the c-c cross section and the d-d cross section in FIG. 2A are cut. In the c-c cross section, the emitter region 12, the base region 14, and the drift region 18 are disposed in this order from the upper surface side of the semiconductor substrate 10. In the d-d cross section, the doping concentration distribution of the first well region 13 may have a Gaussian distribution from the top surface of the semiconductor substrate 10. The Gaussian distribution is a profile when the dopant introduced to the upper surface of the semiconductor substrate 10 is diffused by thermal diffusion.

  The depth from the upper surface of the pn junction between the base region 14 and the drift region 18, that is, the depth of the base region 14 is deeper than the lower end position Z1 of the trench portion. On the other hand, the depth of the pn junction between the first well region 13 and the drift region 18, that is, the depth of the first well region 13 may be deeper than the lower end position Z1 of the trench portion. The depth of the base region 14 is typically 3.0 μm and may be 0.5 μm or more and 5.0 μm or less. The depth of the first well region 13 is typically 7.0 μm, and may be 2.0 μm or more and 10 μm or less.

  FIG. 2E is another example of the distribution diagram of the doping concentration when the c-c cross section and the d-d cross section in FIG. 2A are cut. The doping concentration distribution in the c-c cross section of this example is the same as the doping concentration distribution in the c-c cross section in FIG. 2D. In this example, the doping concentration distribution on the d-d cross section is different from the case of FIG. 2D. The first well region 13 of this example has four peaks of the first well region 13-1 to the first well region 13-4. For example, in the d-d cross section, the doping concentration distribution of the first well region 13 has a concentration peak at a first step to lower the contact resistance, a second step of the doping concentration distribution substantially the same as the base region 14 and a deeper position than the base region 14 It comprises the fourth stage which has a concentration peak at a deeper position than the third stage and the third stage.

  The number and depth of peak positions of the first well region 13 are not limited to this example. The fourth stage of the first well region 13 is in contact with the drift region 18 and has a pn junction. The minimum concentration of the valley portion between each concentration peak may be higher than the doping concentration of the drift region 18. The peak concentration of the third and fourth rows of the first well region 13 of FIG. 2E may be higher than the peak concentration of the base region 14 and may be lower than the base region 14.

  Also, the peak position of the third stage may be deeper than the position of the pn junction between the base region 14 and the drift region 18. Further, the peak position of the fourth row may be shallower than the lower end position Z1 of the trench portion.

  FIG. 3 is a view showing another example of the top surface of the semiconductor device 100. As shown in FIG. The semiconductor device 100 of this example further includes a storage region 16 in addition to the configuration of the semiconductor device 100 described with reference to FIGS. 1 and 2A. The accumulation region 16 is a region of the first conductivity type having a doping concentration higher than that of the drift region 18. The storage area 16 of this example is N + type.

  The storage region 16 is not exposed on the top surface of the semiconductor substrate 10. The accumulation region 16 may be formed between the drift region 18 and the base region 14. In FIG. 3, a region where the accumulation region 16 is provided in the XY plane parallel to the upper surface 21 of the semiconductor substrate 10 is indicated by a broken line. In this example, a plurality of storage areas 16 separated from each other in the plane are provided.

  A storage region 16 is provided in a region of at least a part of the mesa portion 71 sandwiched between two trench portions, at least one of which is the gate trench portion 40. The storage region 16 of this example is provided at least below the emitter region 12. The storage region 16 may also be provided below the contact region 15. The storage region 16 of this example is provided on the entire mesa portion 71 in the width direction (Y-axis direction). The storage region 16 may not be provided below the base region 14 exposed on the top surface of the mesa 71. On the other hand, the dummy mesa portion 72 is not provided with the storage region 16 having a doping concentration higher than that of the base region 14.

  FIG. 4A is a view showing an example of an aa cross section in FIG. The aa cross section of this example is a YZ plane passing through the emitter region 12. The semiconductor device 100 of this example further includes a storage region 16 in addition to the configuration of the semiconductor device 100 shown in FIG. 2A. The storage region 16 is provided between the base region 14 and the drift region 18 in each of the mesas 71. The storage region 16 in this example is provided in each mesa 71 from the region adjacent to one trench to the region adjacent to the other trench.

  The accumulation region 16 is an N + -type region having a doping concentration higher than that of the drift region 18. For example, between the drift region 18 and the base region 14, a region having a doping concentration ten times or more higher than the average value of the doping concentration of the drift region 18 may be used as the storage region 16. The doping concentration of the accumulation region 16 may be 50 times or more or 100 times or more the doping concentration of the drift region 18. The accumulation region 16 may be formed by implanting an N-type impurity such as phosphorus or proton from the upper surface 21 of the semiconductor substrate 10.

  By providing the accumulation region 16, the carrier concentration accumulated below the accumulation region 16 can be further increased. Therefore, the on voltage of the semiconductor device 100 can be reduced. Further, by providing the first well region 13, carriers accumulated by the accumulation region 16 can be efficiently extracted. Therefore, even if the storage region 16 is provided, the withstand voltage of the semiconductor device 100 can be maintained.

  FIG. 4B is a view showing an example of an aa cross section in FIG. 3. The semiconductor device 100 of this example is different from the case of FIG. 4A in that the dummy mesa portion 72 has the storage region 16. The storage region 16 of this example includes a storage region 16-1 formed in the mesa portion 71 and a storage region 16-2 formed in the dummy mesa portion 72. The storage area 16-1 and the storage area 16-2 may be formed simultaneously in the same process. Also, storage region 16-1 and storage region 16-2 may be formed with different dopant concentrations by different processes.

  The storage region 16-2 is formed by being sandwiched by the dummy trench portion 30 in the dummy mesa portion 72. That is, the upper end and the lower end of the accumulation region 16-2 are provided in contact with the first well region 13. The accumulation region 16-2 is a region of the first conductivity type having a doping concentration higher than that of the drift region 18. In the semiconductor device 100 of this example, by providing the storage region 16-2 in the dummy mesa portion 72, extraction of carriers through the P-type inversion layer at the bottom of the dummy trench portion 30 at turn-on is suppressed to reduce turn-on loss. it can.

  FIG. 4C is an example of a distribution diagram of doping concentrations when the c-c cross section and the d-d cross section in FIG. 4B are cut. In the c-c cross section, the emitter region 12, the base region 14, and the drift region 18 are disposed in this order from the upper surface side of the semiconductor substrate 10. In the d-d cross section, the doping concentration distribution of the first well region 13 may have a Gaussian distribution from the top surface of the semiconductor substrate 10. The Gaussian distribution is a profile when the dopant introduced to the upper surface of the semiconductor substrate 10 is diffused by thermal diffusion.

  The depth from the upper surface of the semiconductor substrate 10 to the peak position of the doping concentration of the storage region 16 may be deeper than the depth from the peak position to the lower end position Z1 of the trench portion. The peak position of the accumulation region 16 is typically 4.0 μm, and may be 1.0 μm or more and 6.0 μm or less.

  FIG. 4D is another example of the distribution diagram of the doping concentration when the c-c cross section and the d-d cross section in FIG. 4B are cut. The doping concentration distribution on the d-d cross section is different from the case of FIG. 2D. The first well region 13 of this example has three peaks of the first well region 13-1 to the first well region 13-3. For example, in the d-d cross section, the doping concentration distribution corresponds to the first step of the first well region 13 for reducing the contact resistance, the second step of the first well region 13 having substantially the same distribution as the base region 14, the storage region 16-2, It consists of the third stage of the first well region 13 having a concentration peak at a position deeper than the accumulation region 16-2. The peak concentration at the third stage of the first well region 13 of FIG. 4D may be higher than the peak concentration of the accumulation region 16-2, and may be lower than the accumulation region 16-2. In this example, the peak concentration at the third stage of the first well region 13 is higher than the peak concentration of the accumulation region 16-2.

  FIG. 4E is a view showing an example of an aa cross section in FIG. 3. The semiconductor device 100 of this example is different from the case of FIG. 4A in that the film thickness d1 of the dummy insulating film 32 and the film thickness d2 of the gate insulating film 42 are different. The film thickness d1 of the dummy insulating film 32 in this example is larger than the film thickness d2 of the gate insulating film 42. Thus, it is possible to suppress carrier extraction via the P-type inversion layer at the bottom of the dummy trench portion 30 at turn-on, and reduce the turn-on loss. The film thickness d2 is typically 0.1 μm, and may be 0.05 μm or more and 0.3 μm or less. The film thickness d1 is typically 0.2 μm, and may be 0.1 μm or more and 1.0 μm or less in a range thicker than the film thickness d2. Thus, it is possible to suppress carrier extraction via the P-type inversion layer at the bottom of the dummy trench portion 30 at turn-on, and reduce the turn-on loss.

  In this example, since the width in the Y-axis direction of the dummy trench portion 30 and the gate trench portion 40 is the same, and the film thickness d1 of the dummy insulating film 32 is large, the width in the Y-axis direction of the dummy conductive portion 34 is the gate conductive portion. It becomes smaller than the width of 44 in the Y-axis direction. The thickness d1 of the dummy insulating film 32 is larger than the thickness d2 of the gate insulating film 42 by making the width of the dummy trench 30 in the Y-axis direction larger than the width of the gate trench 40 in the Y-axis direction. You may

  FIG. 5 is a view showing another example of the top surface of the semiconductor device 100. As shown in FIG. The semiconductor device 100 of this example differs from the configuration of the semiconductor device 100 shown in FIGS. 3 and 4A in the arrangement of the storage region 16. The other configuration is the same as that of the semiconductor device 100 shown in FIGS. 3 and 4A.

  The storage region 16 of this example is not provided in a region adjacent to at least one trench portion in at least a part of the mesa portion 71. In the example of FIG. 5, the storage region 16 is in contact with the gate trench portion 40 in each of the mesa portions 71 and is not in contact with the dummy trench portion 30. Further, the accumulation region 16 is not provided in the dummy mesa portion 72.

  FIG. 6 is a view showing an example of an aa cross section in FIG. The aa cross section of this example is a YZ plane passing through the emitter region 12. The semiconductor device 100 of this example differs from the configuration of the semiconductor device 100 shown in FIG. 4A in the arrangement of the storage region 16. The other configuration is the same as that of the semiconductor device 100 shown in FIG. 4A.

  The storage region 16 of this example is provided in a region adjacent to the gate trench portion 40 inside the semiconductor substrate 10. The accumulation region 16 may be provided in contact with the base region 14 or may be provided apart from the base region 14. However, it is preferable that the storage region 16 be provided inside the mesa portion 71 (that is, a region from the upper surface 21 of the semiconductor substrate 10 to the lower end of the trench portion).

  In each of the mesa portions 71, the N-type doping concentration of the region 17 adjacent to the dummy trench portion 30 inside the semiconductor substrate 10 and at the same depth position as the storage region 16 is lower than that of the storage region 16. Region 17 in this example has the same doping concentration as drift region 18. The accumulation region 16 may be provided in a region equal to or less than half of the width of the mesa portion 71 in the Y-axis direction, or may be provided in a region equal to or more than half.

  With such a structure, carriers can be accumulated in the vicinity of the lower end of the gate trench portion 40, and carriers such as holes can also be extracted from the mesa portion 71 at turn-off. For example, carriers which have passed near the dummy trench portion 30 are drawn to the emitter electrode 52 through the base region 14 and the contact region 15.

  FIG. 7 is a view showing another example of the cross section aa in FIG. The semiconductor device 100 of this example differs from the configuration of the semiconductor device 100 shown in FIG. 6 in the arrangement of the storage region 16 in the Z-axis direction. The other configuration is the same as that of the semiconductor device 100 shown in FIG.

  The storage area 16 of this example is disposed apart from the base area 14. A drift region 18 may be provided between the storage region 16 and the base region 14. Incidentally, the storage region 16 is in contact with the gate trench portion 40 and not in contact with the dummy trench portion 30. The partial region of the storage region 16 may be provided below the lower end of the gate trench portion 40.

  The bottom of the gate trench portion 40 in this example has a curved surface shape convex downward. The accumulation region 16 may cover a part of the curved surface at the bottom of the gate trench portion 40. With such a structure as well, carriers can be accumulated in the vicinity of the lower end of the gate trench portion 40, and carriers such as holes can also be extracted from the mesa portion 71 at turn-off.

  FIG. 8 is a view showing another example of the cross section aa in FIG. The semiconductor device 100 of this example differs from the configuration of the semiconductor device 100 shown in FIG. 6 in the arrangement of the storage region 16. The other configuration is the same as that of the semiconductor device 100 shown in FIG.

  The semiconductor device 100 of this example has a first storage region 16-1 and a second storage region 16-2 in each of the mesa portions 71. The first accumulation area 16-1 is the same as the accumulation area 16 shown in FIG. 6, and the second accumulation area 16-2 is the same as the accumulation area 16 shown in FIG.

  The first accumulation region 16-1 and the second accumulation region 16-2 may have the same doping concentration or different doping concentrations. As viewed in the Z-axis direction, at least a part of the first accumulation area 16-1 and at least a part of the second accumulation area 16-2 are disposed so as to overlap with each other.

  The first accumulation area 16-1 and the second accumulation area 16-2 may be provided separately in the Z-axis direction. In this case, a drift region 18 may be provided between the first accumulation region 16-1 and the second accumulation region 16-2. The first accumulation area 16-1 and the second accumulation area 16-2 may be provided continuously in the Z-axis direction. In this case, the doping concentration distribution in the depth direction of the first accumulation region 16-1 and the second accumulation region 16-2 is the same as that of each of the first accumulation region 16-1 and the second accumulation region 16-2. It may have a peak in the region. The doping concentration between the peaks is greater than the doping concentration of the drift region 18.

  With such a structure as well, carriers can be accumulated in the vicinity of the lower end of the gate trench portion 40, and carriers such as holes can also be extracted from the mesa portion 71 at turn-off.

  FIG. 9 is a view showing another example of the cross section aa in FIG. The semiconductor device 100 of this example differs from the configuration of the semiconductor device 100 shown in FIG. 4A in the arrangement of the storage region 16. The other configuration is the same as that of the semiconductor device 100 shown in FIG. 4A.

  The semiconductor device 100 of this example has a first storage region 16-1 and a second storage region 16-2 in each of the mesa portions 71. The first accumulation area 16-1 is the same as the accumulation area 16 shown in FIG. 4A. The second accumulation region 16-2 is provided below the first accumulation region 16-1 inside the mesa portion 71. The second storage region 16-2 may have the same doping concentration as the first storage region 16-1, or may have a different doping concentration. The semiconductor device 100 may include storage regions 16 provided in three or more stages in the depth direction inside the mesa portion 71.

  Similar to the first storage region 16-1, the second storage region 16-2 is provided from the region in contact with one trench portion to the region in contact with the other trench portion in the Y-axis direction. The first accumulation area 16-1 and the second accumulation area 16-2 may be provided separately in the Z-axis direction or may be provided continuously. Such a structure can further enhance the carrier accumulation effect.

  Note that by providing the storage region 16 in multiple stages in the depth direction, the electron current that has passed through the channel formed in the vicinity of the interface between the base region 14 and the gate trench portion 40 during turn-on It becomes easy to flow near the center in the direction.

  The main current at the initial stage of turn-on is electron current, not hole current. The initial stage is a period from immediately before the gate voltage Vge reaches the threshold voltage to before the mirror period in which Vge becomes constant at the value of the threshold voltage. As Vge approaches the threshold voltage, the channel opens and injection of electrons into the drift region 18 begins.

  Electrons directed downward from the channel may flow once in the first accumulation region 16-1 in the arrangement direction (the Y-axis direction or the direction from the vicinity of the gate trench 40 toward the center of the mesa 71). When the second storage region 16-2 is not provided, in the drift region 18 below the first storage region 16-1, an electron storage layer is already formed in the vicinity of the gate trench portion 40. Because of this (the threshold voltage at which the electron accumulation layer of the N-type region is formed is much smaller than the threshold voltage of the inversion layer of the P-type region), the impedance is lower than that of the drift region 18. Therefore, the electron current mainly flows in the vicinity of the gate trench portion 40.

When the electrons reach the back side collector region 22, hole injection starts from the collector region 22 to the buffer region 20 and the drift region 18. Thereby, holes are accumulated in the vicinity of the lower end of the trench portion. As an example, holes are present in the order of 1.0 × 10 ¹⁶ [cm ⁻³ ] from the vicinity of the lower end of gate trench portion 40 to the side portion of dummy trench portion 30 below first storage region 16. .

  The holes gather at the lower end of the gate trench portion 40 and the lower end of the dummy trench portion 30. In particular, since the dummy conductive portion 34 has the same potential as the emitter electrode 52, a hole inversion layer is likely to be formed on the side wall of the dummy trench portion 30. Holes injected from the collector region 22 gather in the vicinity of the hole inversion layer. The holes are distributed continuously from the dummy trench portion 30 to the lower end of the gate trench portion 40. Due to the distribution of holes, a large displacement current may flow near the lower end of the gate trench portion 40 at turn-on.

  The semiconductor device 100 of the present example further includes a second storage region 16-2. In this case, the impedance for the electron current is higher than the path flowing from the vicinity of the center of the first accumulation region 16-1 to the vicinity of the gate trench portion 40 and flowing to the second accumulation region 16-2. The path flowing directly from -1 to the second accumulation area 16-2 is lower.

  Holes are likely to be accumulated in the hole high concentration region adjacent to the gate trench portion 40 below the respective accumulation regions. Further, when the electron current flows not in the vicinity of the gate trench portion 40 but in the vicinity of the center of the mesa portion 71, accumulation of holes in the hole high concentration region is promoted. Therefore, the electron current is promoted to flow near the center of the mesa portion 71.

  By providing the storage region 16 in multiple stages in the depth direction, the electron current can easily travel downward in the vicinity of the center of the mesa portion 71. When the electron current flows in the vicinity of the center of the mesa 71, the hole distribution in the vicinity of the bottom of the mesa 71 is divided in the vicinity of the center of the mesa 71 by the electron current. Therefore, the holes on the dummy trench portion 30 side than the path of the electron current do not flow to the gate trench portion 40 side. The division of the hole distribution at the central portion of the mesa portion 71 suppresses the accumulation of holes at the lower end of the gate trench portion 40. Thus, the displacement current can be reduced. Since the displacement current can be reduced, charging of the gate conductive portion 44 is also reduced, and an instantaneous increase of the gate electrode Vge is also suppressed. Thereby, the voltage decrease rate (dV / dt) of the voltage between the collector and the emitter can also be suppressed.

  FIG. 10 is a view showing another example of the cross section aa in FIG. The semiconductor device 100 of this example differs in the shape of the first well region 13 from the semiconductor device 100 of any of the aspects described in FIGS. 1 to 9. The other configuration is the same as any of the semiconductor devices 100 described in FIGS. 1 to 9. FIG. 10 shows an example in which the shape of the first well region 13 is changed in the semiconductor device 100 shown in FIG.

  The first well region 13 of this example has a recess 73 in which the width in the Y-axis direction is minimized in the YZ plane. In addition, the first well region 13 may have a plurality of depressions 73 having different positions in the Z-axis direction. The at least one recess 73 may be provided below the lower end of the dummy trench 30. The first well region 13 has peaks of doping concentration on the upper side and the lower side of the recess 73, respectively.

  The first well region 13 of this example can be formed by implanting a P-type impurity a plurality of times while changing the implantation depth. By changing the implantation depth of the impurity, the first well region 13 can be formed to a deeper position. That is, it is possible to easily form the first well region 13 in which the width in the Y-axis direction is relatively small and the depth in the Z-axis direction is large. By forming the first well region 13 deep, carriers such as holes can be easily extracted.

  As an example, the first well region 13 may be formed 20% or more deeper than the dummy trench portion 30 or 50% or more deeper. Further, the difference in depth between the first well region 13 and the dummy trench portion 30 may be larger than the width of the dummy mesa portion 72 in the Y-axis direction. The first well region 13 may be formed deeper than the second well region 11.

  FIG. 11 is a cross-sectional view in which the vicinity of the first well region 13 is enlarged. The dummy trench portion 30 in the present example has a first dummy sidewall 38, a second dummy sidewall 37, and a bottom portion 35 in the YZ plane. The first dummy sidewall 38 contacts the first well region 13. The second dummy side wall 37 is a side opposite to the first dummy side wall 38 in the YZ plane.

  The first well region 13 of this example covers at least a part of the bottom 35 of the dummy trench portion 30. The bottom portion 35 in this example has a curved surface shape projecting downward from the lower ends of the first dummy side wall 38 and the second dummy side wall 37. The lower end position Z2 of the first well region 13 is disposed below the lower end position Z1 of the dummy trench portion 30.

  A region having the same inclination as the portion in contact with the base region 14 in the side wall of the dummy trench portion 30 may be used as the second dummy side wall 37. The first dummy side wall 38 is a side wall opposite to the second dummy side wall 37, and is a side wall in the same depth range as the second dummy side wall 37. The bottom portion 35 may indicate a region having a smaller inclination with respect to the upper surface 21 of the semiconductor substrate 10 than the first dummy sidewall 38 and the second dummy sidewall 37. As the first well region 13 covers at least a part of the bottom 35 of the dummy trench portion 30, the carrier extraction speed can be further improved.

  The first well region 13 covers at least a part of the region between the center Y 1 in the width direction (Y-axis direction) and the first dummy sidewall 38 at the bottom portion 35 of the dummy trench portion 30. That is, the position Y 2 of the end 36 in the Y-axis direction of the first well region 13 covering the bottom 35 is disposed between the central position Y 1 of the bottom 35 and the first dummy sidewall 38. Such a structure can further improve the carrier withdrawal speed.

  FIG. 12 is a cross-sectional view showing an example in which the position of the end 36 of the first well region 13 covering the bottom 35 is changed in the structure shown in FIG. The first well region 13 of this example covers the bottom 35 to the side of the second dummy sidewall 37 more than the center Y1 of the bottom 35. That is, the position Y 2 of the end 36 of the first well region 13 is disposed between the central position Y 1 of the bottom 35 and the second dummy sidewall 37. Such a structure can further improve the carrier withdrawal speed.

  FIG. 13 is a cross-sectional view showing an example in which the position of the end 36 of the first well region 13 covering the bottom 35 is changed in the structure shown in FIG. The first well region 13 of this example covers the entire bottom 35. That is, the position Y 2 of the end portion 36 of the first well region 13 is disposed closer to the center of the mesa portion 71 than the second dummy sidewall 37. In this case, the first well region 13 is provided to the lower side of the mesa portion 71. Such a structure can further improve the carrier withdrawal speed.

  In the trench portion in contact with the mesa portion 71, the length from the side wall of the trench portion on the mesa portion 71 side to Y2 may be shorter or longer than the length from the side wall of the trench portion to Y1. In this example, in the trench portion in contact with the mesa portion 71, the length from the trench portion sidewall to the mesa portion 71 to Y2 is shorter than the length from the trench portion sidewall to Y1.

  FIG. 14 shows another example of dummy trench portion 30 and gate trench portion 40. Referring to FIG. The dummy trench portion 30 in this example is formed deeper than the gate trench portion 40 when viewed from the upper surface 21 of the semiconductor substrate 10. That is, the lower end position Z3 of the dummy trench portion 30 is disposed below the lower end position Z1 of the gate trench portion 40. When viewed from the upper surface 21 of the semiconductor substrate 10, the dummy trench portion 30 may be formed 10% or more deeper than the gate trench portion 40, or 20% or more. Such a structure can further improve the carrier withdrawal speed.

  FIG. 15 is a diagram showing another example of the first well region 13. In the semiconductor device 100 of this example, three or more dummy trench portions 30 are continuously arranged in the Y-axis direction. Three or more dummy trench portions 30 may be sandwiched by the gate trench portion 40 in the Y-axis direction. In this example, the first well regions 13 provided in the two or more dummy mesa portions 72 are connected to each other.

  In the present embodiment, the entire bottom portion of the dummy trench portions 30 other than the dummy trench portions 30 arranged at both ends in the Y-axis direction among the plurality of dummy trench portions 30 arranged continuously is covered with the first well region 13. You may be The relationship between the dummy trench portions 30 arranged at both ends in the Y-axis direction and the first well region 13 is the same as any one of the modes described in FIGS. Such a structure can further improve the carrier withdrawal speed.

  FIG. 16 is a view showing another example of the cross section aa of the semiconductor device 100. As shown in FIG. The semiconductor device 100 of this example is different from the semiconductor device 100 described in FIGS. 1 to 15 in that a lower surface side region 28 is further provided. The other configuration is the same as that of the semiconductor device 100 according to any one of the embodiments described in FIGS.

  The lower surface side region 28 is provided at the same depth position as the collector region 22 in at least a partial region below the dummy mesa portion 72. The lower surface side area 28 is an N-type area. The lower surface side region 28 may have a higher doping concentration than the drift region 18. The lower surface side region 28 may have a doping concentration higher than that of the buffer region 20.

  The lower surface side region 28 may have the same width as that of the dummy mesa portion 72 in the Y-axis direction. The lower surface side region 28 may have a smaller width than the dummy mesa portion 72 in the Y-axis direction, and may have a larger width. The lower surface side region 28 may be formed below the dummy trench portion 30 and may also be formed at a partial region below the mesa portion 71.

  By providing the lower surface side region 28, carrier accumulation of the second conductivity type below the dummy mesa portion 72 can be suppressed. The carrier concentration below the dummy mesa portion 72 has little influence on the on voltage of the semiconductor device 100. Therefore, it is possible to facilitate carrier extraction at the time of turn-off or the like while reducing the on-voltage.

  FIG. 17 is a view showing an example of the bb cross section shown in FIG. 3. However, the structure shown in FIG. 17 is also applicable to the semiconductor device 100 shown in FIG. The b-b cross section is the XZ plane passing through the contact hole 54 in the dummy mesa portion 72.

  In the semiconductor device 100 of this example, the collector regions 22 and the lower surface side regions 28 are alternately arranged in the longitudinal direction of the dummy trench portion 30 below the dummy mesa portion 72. With such a structure, the area ratio of the collector region 22 to the lower surface side region 28 can be easily adjusted. The width of one collector region 22 in the X-axis direction and the width of one lower surface region 28 may be the same. The width of one collector region 22 may be larger than the width of one lower surface side region 28 in the X-axis direction, and the width of one lower surface side region 28 may be larger than the width of one collector region 22.

  The range in which the collector region 22 is provided in the X-axis direction may at least partially overlap the range in which the emitter region 12 is provided in the X-axis direction. The range in which the collector region 22 is provided in the X axis direction may coincide with the range in which the emitter region 12 is provided in the X axis direction. The range where the collector region 22 is provided in the X axis direction may be included in the range where the emitter region 12 is provided in the X axis direction, and the range where the emitter region 12 is provided in the X axis direction is the collector region 22 in the X axis direction. May be included in the range provided.

Collector region 22 sandwiched in the X-axis direction into two lower surface side region 28, the length L _p of the X-axis direction may be longer than the length L _n of the lower surface area 28 may be shorter. In this example, they are equal. The length L _p in the X-axis direction of the collector region 22 is typically 10 μm, and may be 5 μm or more and 15 μm or less. The length L _n of the lower surface side region 28 is typically 5 μm, and may be 5 μm to 15 μm.

  FIG. 18 is a diagram partially showing the top surface of a semiconductor device 200 according to another embodiment of the present invention. The semiconductor device 200 differs from the semiconductor device 100 described in FIGS. 1 to 17 in the arrangement of the emitter region 12, the contact region 15, and the storage region 16. The other configuration may be the same as any of the semiconductor devices 100 described in FIGS. 1 to 17.

  In the present example, the extension portion 41 of the gate trench portion 40 has a long side and a short side on the upper surface of the semiconductor substrate 10. In the example of FIG. 18, the extension part 41 has a length in the X-axis direction and a short in the Y-axis direction.

  The gate trench portion 40 has a first gate sidewall 74 along the longitudinal direction and a second gate sidewall 75 opposite to the first gate sidewall 74. The first gate sidewall 74 and the second gate sidewall 75 are disposed to face each other in the semiconductor substrate 10.

  In this example, in the mesa 71, the mesa 71 adjacent to the first gate sidewall 74 is the first mesa 71-1, and the mesa 71 adjacent to the second gate sidewall 75 is the second mesa 71-2. I assume. That is, one mesa 71 disposed across the gate trench 40 is referred to as a first mesa 71-1, and the other mesa 71 is referred to as a second mesa 71-2.

  Emitter regions 12 and contact regions 15 are disposed alternately on the upper surfaces of the first mesa portion 71-1 and the second mesa portion 71-2 along the X-axis direction. In the semiconductor device 100 of the present example, at least a partial region of at least one emitter region 12 in the first mesa portion 71-1 is disposed at a position facing the contact region 15 in the second mesa portion 71-2. There is. That is, at least a part of the range in the X-axis direction in which at least one emitter region 12 in the first mesa portion 71-1 is provided is the range in the X-axis direction in which the contact region 15 in the second mesa portion 71-2 is provided. overlapping.

  In the example of FIG. 18, the whole of all the emitter regions 12 in the first mesa portion 71-1 is disposed at a position opposed to any one of the contact regions 15 in the second mesa portion 71-2. The width in the X axis direction of the emitter region 12 in the first mesa portion 71-1 may be the same as the width in the X axis direction of the contact region 15 in the second mesa portion 71-2.

  In addition, at least a partial region of at least one contact region 15 in the first mesa portion 71-1 is disposed at a position facing the emitter region 12 in the second mesa portion 71-2. That is, at least a part of the range in the X axis direction in which at least one contact region 15 in the first mesa portion 71-1 is provided is the range in the X axis direction in which the emitter region 12 in the second mesa portion 71-2 is provided. overlapping.

  In the example of FIG. 18, the whole of each contact region 15 in the first mesa portion 71-1 is disposed at a position opposed to any of the emitter regions 12 in the second mesa portion 71-2. The width in the X-axis direction of the contact region 15 in the first mesa portion 71-1 may be the same as the width in the X-axis direction of the emitter region 12 in the second mesa portion 71-2. However, of the contact regions 15 in the first mesa portion 71-1, the contact regions 15 provided at both ends in the X-axis direction face both the emitter region 12 and the contact region 15 of the second mesa portion 71-2. Are arranged. That is, in both of the first mesa portion 71-1 and the second mesa portion 71-2, the contact region 15 is disposed adjacent to the base region 14 provided at both ends in the X-axis direction. Thereby, the carriers under the base region 14 provided at both ends in the X-axis direction can be efficiently extracted. The width in the X-axis direction of the contact region 15 in the first mesa portion 71-1 may be equal to the sum of the widths in the X-axis direction of the emitter region 12 and the contact region 15 of the second mesa portion 71-2.

  In the two mesa portions 71 adjacent to each other with the gate trench portion 40 interposed therebetween, the emitter regions 12 and the contact regions 15 are arranged in a staggered manner in the X-axis direction, thereby distributing the contact regions 15 contributing to the extraction of holes. can do. Therefore, in the XY plane, holes can be drawn without deviation, and the tolerance of the semiconductor device 100 at turn-off can be improved.

  In the semiconductor device 200 of this embodiment, the contact region 15 is exposed on the upper surface of the dummy mesa portion 72. Below the contact region 15, a base region 14 may be formed. Further, in the semiconductor device 200 of the present example, the storage region 16 is formed in the mesa portion 71 and the dummy mesa portion 72.

  Further, in the first mesa portion 71-1 and the second mesa portion 71-2, in the region where the emitter region 12 or the contact region 15 is formed, the gate trench portion 40 extends in the lateral direction (Y-axis direction). The trench portion is not formed. That is, in the region where emitter region 12 and contact region 15 are regularly arranged, gate trench portion 40 does not have a branch or branch extending inside mesa portion 71. In addition, the dummy trench portion 30 is not provided in the region. With such a structure, carriers such as holes can be effectively extracted through the dispersedly arranged contact regions 15 without being blocked by the trench portion.

  FIG. 19 is a view showing an example of an aa cross section in FIG. The aa cross section of this example is a YZ plane passing through the contact region 15 of the first mesa portion 71-1 and the emitter region 12 of the second mesa portion 71-2.

  As described above, the contact region 15 of the first mesa portion 71-1 and the contact region 15 of the second mesa portion 71-2 are arranged to be shifted in the X-axis direction. Therefore, in the cross section shown in FIG. 19, the contact region 15 is provided in the first mesa portion 71-1, and the emitter region 12 is provided in the second mesa portion 71-2. With such an arrangement, holes can be drawn without bias.

  In the dummy mesa portion 72 of this example, the contact region 15, the base region 14 and the storage region 16 are provided in order from the upper surface 21 side of the semiconductor substrate 10. In another example, the dummy mesa portion 72 may not be provided with the storage region 16. Further, similarly to the semiconductor device 100 shown in FIG. 1 and FIG. 2A, the storage region 16 may not be provided in the mesa portion 71.

  FIG. 20 is a view showing another example of the cross section aa in FIG. In the semiconductor device 200 of this example, the structure of the dummy mesa portion 72 is similar to that of the semiconductor device 100 described in FIGS. That is, the semiconductor device 200 of this example has the first well region 13 in the dummy mesa portion 72. Such a structure allows the carrier to be pulled out more easily. In addition, the structure of the storage region 16 in the semiconductor device 200 may be similar to that of the storage region 16 of the semiconductor device 100. The semiconductor device 200 may also include the lower surface side region 28 shown in FIGS. 16 and 17.

  FIG. 21 is a view showing an arrangement example of the emitter region 12 and the contact region 15 on the top surfaces of the first mesa portion 71-1 and the second mesa portion 71-2. In this example, the emitter region 12 and the contact region 15 in each mesa portion 71 have the same length in the X-axis direction. The contact region 15 in the first mesa portion 71-1 is disposed at a position facing the emitter region 12 of the second mesa portion 71-2, and the emitter region 12 in the first mesa portion 71-1 is a second mesa. It is arrange | positioned in the position facing the contact area | region 15 of the part 71-2.

  FIG. 22 is a view showing another arrangement example of the emitter region 12 and the contact region 15 on the upper surfaces of the first mesa portion 71-1 and the second mesa portion 71-2. In this example, in the first mesa portion 71-1 and the second mesa portion 71-2, the contact region 15 is formed longer in the X-axis direction than the emitter region 12. The length of the contact region 15 may be twice or more the length of the emitter region 12.

  The range in the X-axis direction in which the emitter region 12 of the first mesa portion 71-1 is provided is included in the range in the X-axis direction in which the contact region 15 of the second mesa portion 71-2 is provided. The range in the X-axis direction in which the emitter region 12 of the second mesa portion 71-2 is provided is included in the range in the X-axis direction in which the contact region 15 of the first mesa portion 71-1 is provided. Such a structure can improve the carrier extraction speed.

  FIG. 23 is a view showing another arrangement example of the emitter region 12 and the contact region 15 on the upper surfaces of the first mesa portion 71-1 and the second mesa portion 71-2. In this example, the emitter region 12 is formed longer in the X-axis direction than the contact region 15 in the first mesa portion 71-1 and the second mesa portion 71-2. The length of the emitter region 12 may be twice or more the length of the contact region 15.

  The range in the X-axis direction in which the contact region 15 of the first mesa portion 71-1 is provided is included in the range in the X-axis direction in which the emitter region 12 of the second mesa portion 71-2 is provided. The range in the X-axis direction in which the contact region 15 of the second mesa portion 71-2 is provided is included in the range in the X-axis direction in which the emitter region 12 of the first mesa portion 71-1 is provided. Such a structure can improve channel density.

  FIG. 24 is a view showing an arrangement example of the storage area 16. The storage region 16 in this example has an opening 92 in the XY plane. Inside the opening 92, a drift region 18 may be provided. The opening 92 may be arranged to overlap the contact region 15 in the first mesa portion 71-1 and the second mesa portion 71-2. With such a structure, carriers can be drawn out in the first mesa portion 71-1 and the second mesa portion 71-2. The area of the opening 92 in the XY plane may be the same as or smaller than the area of the contact region 15. The area of the opening 92 may be half or less of the area of the contact region 15.

  FIG. 25 is a diagram showing an example of a method of manufacturing the semiconductor device 100. As shown in FIG. The semiconductor device 200 may also be manufactured by the same method. In step S250, the base region 14 is formed in the semiconductor substrate 10 in which the gate trench portion 40 and the dummy trench portion 30 are provided. The base region 14 may be formed by implanting a P-type impurity such as boron from the upper surface side of the semiconductor substrate 10.

  In step S252, the accumulation region 16 is formed. The storage region 16 may be formed by implanting an N-type impurity such as phosphorus from the upper surface side of the semiconductor substrate 10 using a mask such as a photoresist.

  In step S254, the first well region 13 is formed. The first well region 13 may be formed by implanting a P-type impurity such as boron from the upper surface side of the semiconductor substrate 10 using a mask such as a photoresist. The P-type impurity may be implanted at different depths in multiple times by changing the acceleration voltage.

  In step S256, the contact region 15 is formed. The contact region 15 may be formed by implanting a P-type impurity such as boron from the upper surface side of the semiconductor substrate 10 using a mask such as a photoresist.

  In step S258, the structure on the lower surface side of the semiconductor substrate 10 is formed. For example, the collector region 22 is formed.

  In step S260, the semiconductor substrate 10 is annealed under predetermined conditions. Thus, the impurity implanted in steps S250 to S258 is made donor or acceptor to form each region.

  In step S262, emitter region 12 is formed. The emitter region 12 may be formed by implanting an N-type impurity such as arsenic from the upper surface side of the semiconductor substrate 10 using a mask such as a photoresist.

  In step S264, the semiconductor substrate 10 is annealed under predetermined conditions. Thus, the impurity implanted in step S262 is donated to form the emitter region 12.

  After step S264, the interlayer insulating film 26, the contact hole 54, the emitter electrode 52, and the like are formed. Thus, the semiconductor device 100 can be manufactured.

  Step S254 may be performed after step S264. In this case, an annealing step may be included after step S254. In this case, since the number of times of annealing after forming the first well region 13 can be reduced, the depth of the first well region 13 can be accurately controlled.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It is apparent to those skilled in the art that various changes or modifications can be added to the above embodiment. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the present invention.

  The order of execution of the respective processes in the methods shown in the claims, the specification and the drawings is not particularly marked as "before", "before", etc., and the result of the preceding process It should be noted that it can be realized in any order, as long as it is not used in later processing. With regard to the flow of operations in the claims, the specification and the drawings, even if it is described using “first,” “next,” etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

Reference Signs List 10 semiconductor substrate 11 second well region 12 emitter region 13 first well region 14 base region 15 contact region 16 Storage region 17 region 18 drift region 20 buffer region 21 top surface 22 collector region 23 bottom surface 26 interlayer dielectric film 28: lower surface side region 30, 30: dummy trench portion 31, 31: extended portion, 32: dummy insulating film, 33: tip portion, 34: dummy conductive portion, 35: Bottom part 36: End part 37: Second dummy side wall 38: First dummy side wall 40: Gate trench part 41: Stretched part 42: Gate insulating film 43 · · · tip portion, 44 · · · gate conductive portion, 45 · · · gate wiring, 46 · Gate electrode 52 Emitter electrode 54 55 56 Contact hole 57 Connection portion 58 Collector electrode 71 Mesa portion 72 Dummy mesa portion 73: recessed portion 74: first gate sidewall 75: second gate sidewall 92: opening 100: semiconductor device 200: semiconductor device

Claims (24)

A semiconductor substrate,
A drift region of the first conductivity type provided inside the semiconductor substrate;
A plurality of gate trench portions provided from the upper surface of the semiconductor substrate to the drift region;
A dummy trench portion provided between two gate trench portions and provided from the upper surface of the semiconductor substrate to the drift region;
A second conductivity type base region provided between the top surface of the semiconductor substrate and the drift region in a region of the semiconductor substrate adjacent to any one of the gate trench portions;
A semiconductor of a second conductivity type provided in a region of the semiconductor substrate adjacent to the dummy trench portion to a position deeper than a lower end of the dummy trench portion and having a doping concentration higher than that of the base region; apparatus. Two or more dummy trench portions are provided between the two gate trench portions,
A dummy mesa portion is formed between the two dummy trench portions inside the semiconductor substrate,
The semiconductor device according to claim 1, wherein the first well region is provided in the dummy mesa portion. The semiconductor device according to claim 2, wherein the first well region is provided in contact with both of the two dummy trench portions. The semiconductor device according to any one of claims 1 to 3, wherein the first well region covers at least a part of a bottom of the dummy trench portion. The dummy trench portion has a first dummy sidewall adjacent to the first well region,
5. The semiconductor device according to claim 4, wherein the first well region covers at least a part of a region between a center in the width direction and the first dummy sidewall at a bottom portion of the dummy trench portion. The dummy trench portion has a second dummy sidewall opposite to the first dummy sidewall.
6. The semiconductor device according to claim 5, wherein the first well region covers the bottom of the dummy trench portion to a side closer to the second dummy sidewall than the center in the width direction of the bottom portion of the dummy trench portion. The semiconductor device according to any one of claims 1 to 6, wherein the dummy trench portion and the gate trench portion are formed to the same depth. The semiconductor device according to any one of claims 1 to 6, wherein the dummy trench portion is formed deeper than the gate trench portion. A collector region of a second conductivity type provided between the lower surface of the semiconductor substrate and the drift region;
The semiconductor device according to claim 2, further comprising: a lower surface side region of the first conductivity type provided at the same depth position as the collector region in at least a partial region below the dummy mesa portion. The dummy trench portion has a long side and a short side on the upper surface of the semiconductor substrate,
10. The semiconductor device according to claim 9, wherein the collector region and the lower surface side region are alternately arranged in the longitudinal direction of the dummy trench portion below the dummy mesa portion. A storage region having a doping concentration higher than that of the drift region is provided in a region adjacent to the gate trench in the semiconductor substrate,
The semiconductor according to claim 2, wherein a doping concentration of the first conductivity type in a region adjacent to the dummy trench portion inside the semiconductor substrate and at the same depth position as the storage region is lower than the storage region. apparatus. In a mesa portion at least one of which is sandwiched between two trench portions which are the gate trench portion, the doping concentration is higher than that of the drift region from a position in contact with one of the trench portions to a position in contact with the other trench portion. An accumulation area is provided,
The semiconductor device according to claim 2, wherein the storage region is not provided in the dummy mesa portion. The storage region is provided in contact with the gate trench portion and not in contact with the dummy trench portion in a mesa portion sandwiched by the adjacent gate trench portion and the dummy trench portion. The semiconductor device of description. The gate trench portion has a long side and a short side on the upper surface of the semiconductor substrate,
The gate trench portion has a first gate sidewall along a longitudinal direction of the gate trench portion inside the semiconductor substrate, and a second gate sidewall opposite to the first gate sidewall.
In the semiconductor substrate, a first mesa portion adjacent to the first gate sidewall of the gate trench portion and a second mesa portion adjacent to the second gate sidewall of the gate trench portion are provided.
An emitter region of the first conductivity type and a contact region of the second conductivity type are alternately exposed along the longitudinal direction of the gate trench portion on the upper surfaces of the first mesa portion and the second mesa portion. Placed
The region according to any one of claims 1 to 13, wherein at least a partial region of at least one of the emitter regions in the first mesa portion is disposed at a position facing the contact region in the second mesa portion. Semiconductor devices. The semiconductor device further comprises an emitter region of a first conductivity type provided on the top surface of the semiconductor substrate adjacent to the gate trench portion,
The semiconductor device according to any one of claims 1 to 14, wherein a contact width of a contact formed on the first well region is larger than a contact width of a contact formed on the emitter region. The mesa width of the mesa portion between the dummy trench portions is larger than the mesa width of the mesa portion sandwiched by two trench portions, at least one of which is the gate trench portion. The semiconductor device of description. The semiconductor device according to claim 2, wherein a storage region having a doping concentration higher than that of the drift region is provided in the dummy mesa portion. The semiconductor device according to any one of claims 1 to 17, wherein a film thickness of the dummy insulating film in the dummy trench portion is thicker than a film thickness of the gate insulating film in the gate trench portion. A semiconductor substrate,
A first gate sidewall is provided from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate, has a longitudinal and a short on the upper surface of the semiconductor substrate, and a first gate sidewall along the longitudinal direction in the semiconductor substrate; A gate trench portion having a second gate sidewall opposite to the gate sidewall;
The semiconductor device further includes: a first mesa portion adjacent to the first gate sidewall of the gate trench portion; and a second mesa portion adjacent to the second gate sidewall of the gate trench portion inside the semiconductor substrate;
Emitter regions of the first conductivity type and contact regions of the second conductivity type are alternately exposed along the longitudinal direction of the gate trench on the top surfaces of the first mesa and the second mesa. Arranged as
The semiconductor device according to claim 1, wherein at least a part of at least one of the emitter regions in the first mesa portion is disposed at a position facing the contact region in the second mesa portion. 20. The semiconductor device according to claim 19, wherein at least a partial region of at least one of the contact regions in the first mesa portion is disposed at a position facing the emitter region in the second mesa portion. The semiconductor device according to claim 19, wherein the emitter region is formed longer in the longitudinal direction of the gate trench portion than the contact region in the first mesa portion. 21. The semiconductor device according to claim 19, wherein the contact region is formed longer in the longitudinal direction of the gate trench portion than the emitter region in the first mesa portion. The semiconductor device according to claim 19, wherein lengths of the emitter region and the contact region in the longitudinal direction of the gate trench portion are the same in the first mesa portion. The trench portion extending in the short direction of the gate trench portion is not formed in the first mesa portion in a region where the emitter region or the contact region is formed. The semiconductor device according to claim 1.

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