JP7056031B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device.

Conventionally, power semiconductor devices such as gate-insulated bipolar transistors (IGBTs) are known (see, for example, Patent Document 1). In a semiconductor element such as an IGBT, the on-voltage can be lowered by accumulating carriers such as holes in the drift region.
Patent Document 1 Japanese Patent Application Laid-Open No. 2015-72950

If the carrier is not sufficiently pulled out at the time of turn-off of the semiconductor device with respect to the concentration of the carrier accumulated in the drift region, the withstand capacity of the semiconductor device is lowered.

In the first aspect of the present invention, a semiconductor device including a semiconductor substrate is provided. The semiconductor device may include a first conductive type drift region provided inside the semiconductor substrate. The semiconductor device may include a plurality of gate trench portions provided from the upper surface of the semiconductor substrate to the drift region. The semiconductor device may include a dummy trench portion provided between the two gate trench portions and provided from the upper surface of the semiconductor substrate to the drift region. The semiconductor device may include a second conductive type base region provided between the upper surface of the semiconductor substrate and the drift region in the region of the semiconductor substrate adjacent to any gate trench portion. The semiconductor device may be provided in a region of the semiconductor substrate adjacent to the dummy trench portion to a position deeper than the lower end of the dummy trench portion, and may include a second conductive type first well region having a higher doping concentration than the base region. ..

Two or more dummy trench portions may be provided between the two gate trench portions. Inside the semiconductor substrate, a dummy mesa portion may be formed between the two dummy trench portions. A first well region may be provided in the dummy mesa portion. The first well region may be provided in contact with both of the two dummy trench portions.

The first well region may cover at least a portion of the bottom of the dummy trench portion. The dummy trench portion may have a first dummy side wall adjacent to the first well region. At the bottom of the dummy trench portion, the first well region may cover at least a part of the region between the center in the width direction and the first dummy side wall. The dummy trench portion may have a second dummy side wall opposite to the first dummy side wall. The first well region may cover the bottom of the dummy trench portion from the center in the width direction of the bottom of the dummy trench portion to the side of the second dummy side wall.

The dummy trench portion and the gate trench portion may be formed to the same depth. The dummy trench portion may be formed deeper than the gate trench portion.

The semiconductor device may include a second conductive type collector region provided between the lower surface of the semiconductor substrate and the drift region. The semiconductor device may include a first conductive type lower surface side region provided at the same depth position as the collector region in at least a part region below the dummy mesa portion.

The dummy trench portion may have a length and a short side on the upper surface of the semiconductor substrate. Below the dummy mesa portion, collector regions and lower surface side regions may be alternately arranged along the longitudinal direction of the dummy trench portion.

A storage region having a higher doping concentration than the drift region may be provided in the region adjacent to the gate trench portion inside the semiconductor substrate. The doping concentration of the first conductive type in the region adjacent to the dummy trench portion inside the semiconductor substrate and at the same depth position as the storage region may be lower than that in the storage region.

The storage region may be continuously provided from a position in contact with one trench portion to a position in contact with the other trench portion in a mesa portion sandwiched between two trench portions, one of which is a gate trench portion. The dummy mesa portion does not have to be provided with a storage area.

The storage region may be in contact with the gate trench portion in the mesa portion sandwiched between the adjacent gate trench portion and the dummy trench portion. The storage area may be provided so as not to be in contact with the dummy trench portion.

The gate trench portion may have a length and a short side on the upper surface of the semiconductor substrate. The gate trench portion may have a first gate side wall along the longitudinal direction of the gate trench portion inside the semiconductor substrate, and a second gate side wall opposite to the first gate side wall. Inside the semiconductor substrate, a first mesa portion adjacent to the first gate side wall of the gate trench portion and a second mesa portion adjacent to the second gate side wall of the gate trench portion may be provided. The first conductive type emitter region and the second conductive type contact region are arranged on the upper surfaces of the first mesa portion and the second mesa portion so as to be alternately exposed along the longitudinal direction of the gate trench portion. good. At least a part of the region of at least one emitter in the first mesa portion may be arranged at a position facing the contact region in the second mesa portion.

The semiconductor device may further include a first conductive type emitter region provided on the upper surface of the semiconductor substrate adjacent to the gate trench portion. The contact width of the contact formed on the first well region may be larger than the contact width of the contact formed on the emitter region.

The mesa width of the mesa portion between the dummy trench portions may be larger than the mesa width of the mesa portion sandwiched between the two trench portions having at least one of the gate trench portions.

In the dummy mesa portion, an accumulation region having a higher doping concentration than the drift region may be provided.

The film thickness of the dummy insulating film in the dummy trench portion may be thicker than the film thickness of the gate insulating film in the gate trench portion.

In the second aspect of the present invention, a semiconductor device including a semiconductor substrate is provided. The semiconductor device may be provided from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate, and may include a gate trench portion having a length and a short side on the upper surface of the semiconductor substrate and having a first gate side wall and a second gate side wall. The first gate side wall may be provided along the longitudinal direction inside the semiconductor substrate. The second gate side wall may be a second gate side wall opposite to the first gate side wall. The semiconductor device may include a first mesa portion adjacent to the first gate side wall of the gate trench portion inside the semiconductor substrate. The semiconductor device may include a second mesa portion adjacent to the second gate side wall of the gate trench portion. The first conductive type emitter region and the second conductive type contact region are arranged on the upper surfaces of the first mesa portion and the second mesa portion so as to be alternately exposed along the longitudinal direction of the gate trench portion. May be done. At least a part of the region of at least one emitter in the first mesa portion may be arranged at a position facing the contact region in the second mesa portion.

At least a part of the at least one contact region in the first mesa portion may be arranged at a position facing the emitter region in the second mesa portion. In the first mesa portion, the emitter region may be formed longer in the longitudinal direction of the gate trench portion than in the contact region. In the first mesa portion, the contact region may be formed longer in the longitudinal direction of the gate trench portion than in the emitter region.

In the first mesa portion, the lengths of the emitter region and the contact region in the longitudinal direction of the gate trench portion may be the same. In the region where the emitter region or the contact region is formed in the first mesa portion, the trench portion extending in the lateral direction of the gate trench portion may not be formed.

The outline of the above invention is not a list of all the features of the present invention. A subcombination of these feature groups can also be an invention.

It is a figure which partially shows the upper surface of the semiconductor device 100 which concerns on embodiment of this invention. It is a figure which shows an example of the aa cross section in FIG. It is a figure which shows an example of the aa cross section in FIG. It is a figure which shows an example of the aa cross section in FIG. It is an example of the distribution map of the doping concentration when the cc cross section and the dd cross section of FIG. 2A are cut. It is another example of the distribution map of the doping concentration when the cc cross section and the dd cross section of FIG. 2A are cut. It is a figure which shows another example of the upper surface of a semiconductor device 100. It is a figure which shows an example of the aa cross section in FIG. It is a figure which shows an example of the aa cross section in FIG. It is an example of the distribution map of the doping concentration when the cc cross section and the dd cross section of FIG. 4B are cut. It is another example of the distribution map of the doping concentration when the cc cross section and the dd cross section of FIG. 4B are cut. It is a figure which shows an example of the aa cross section in FIG. It is a figure which shows another example of the upper surface of a semiconductor device 100. It is a figure which shows an example of the aa cross section in FIG. It is a figure which shows the other example of the aa cross section in FIG. It is a figure which shows the other example of the aa cross section in FIG. It is a figure which shows the other example of the aa cross section in FIG. It is a figure which shows the other example of the aa cross section in FIG. It is a cross-sectional view which expanded the vicinity of the 1st well region 13. 11 is a cross-sectional view showing an example in which the position of the end portion 36 of the first well region 13 covering the bottom portion 35 is changed in the structure shown in FIG. 11 is a cross-sectional view showing an example in which the position of the end portion 36 of the first well region 13 covering the bottom portion 35 is changed in the structure shown in FIG. It is a figure which shows another example of a dummy trench part 30 and a gate trench part 40. It is a figure which shows another example of the 1st well area 13. It is a figure which shows the other example of the aa cross section of the semiconductor device 100. It is a figure which shows an example of the bb cross section shown in FIG. It is a figure which partially shows the upper surface of the semiconductor device 200 which concerns on other embodiment of this invention. It is a figure which shows an example of the aa cross section in FIG. It is a figure which shows the other example of the aa cross section in FIG. It is a figure which shows the arrangement example of the emitter region 12 and the contact region 15 on the upper surface of the 1st mesa part 71-1 and the 2nd mesa part 71-2. It is a figure which shows the other arrangement example of the emitter region 12 and the contact region 15 on the upper surface of the 1st mesa part 71-1 and the 2nd mesa part 71-2. It is a figure which shows the other arrangement example of the emitter region 12 and the contact region 15 on the upper surface of the 1st mesa part 71-1 and the 2nd mesa part 71-2. It is a figure which shows the arrangement example of the storage area 16. It is a figure which shows an example of the manufacturing method of a semiconductor device 100.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention within the scope of the claims. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

In the present specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The "up" and "down" directions are not limited to the gravity direction or the mounting direction to the substrate or the like at the time of mounting the semiconductor device. In the present specification, technical matters may be described using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The depth direction of the semiconductor substrate is the Z axis. The Cartesian coordinate system is a so-called right-handed system in this example.

Although the terms "emitter" and "collector" are used in the present specification, the semiconductor device is not limited to the IGBT. "Source" and "drain" in transistors such as MOSFETs may also be included within the scope of the terms "emitter" and "collector" herein.

In each embodiment, an example in which the first conductive type is N-type and the second conductive type is P-type is shown, but the first conductive type may be P-type and the second conductive type may be N-type. In this case, the conductive types such as the substrate, the layer, and the region in each embodiment have opposite polarities. When comparing the doping concentrations between regions in the present specification, the peak concentration in each region may be used.

When referred to as "identical" in the present specification, it may include a case where there is an error due to manufacturing variation or the like. The error is, for example, within 10%.

FIG. 1 is a diagram partially showing the upper surface of the semiconductor device 100 according to the embodiment of the present invention. The semiconductor device 100 of this example is a semiconductor chip including a transistor such as an IGBT. In FIG. 1, the upper surface of the chip around the end of the chip is shown, and other regions are omitted.

Further, although FIG. 1 shows the active region of the semiconductor substrate in the semiconductor device 100, the semiconductor device 100 may have an edge termination portion surrounding the active region. The active region refers to a region in which a current flows when the semiconductor device 100 is controlled to be in the ON state. The edge termination portion relaxes the electric field concentration on the upper surface side of the semiconductor substrate. The edge termination has, for example, a guard ring, a field plate, a resurf, and a combined structure thereof.

The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, a first well region 13 and a second well region 11 provided inside a semiconductor substrate. Be prepared. Further, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate electrode 46 provided above the upper surface of the semiconductor substrate. The emitter electrode 52 and the gate electrode 46 are provided separately from each other.

An interlayer insulating film is provided between the emitter electrode 52 and the gate electrode 46 and the upper surface of the semiconductor substrate, but this is omitted in FIG. 1. The interlayer insulating film of this example is provided with a contact hole 54, a contact hole 55, and a contact hole 56 penetrating the interlayer insulating film.

The emitter electrode 52 passes through the contact hole 54 and comes into contact with the emitter region 12, the contact region 15, the base region 14, and the first well region 13 on the upper surface of the semiconductor substrate. The contact hole 54 of this example is provided between the respective trench portions. Further, the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through the contact hole 56. A connecting portion 57 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connecting portion 57 is provided on the upper surface of the semiconductor substrate with an insulating film such as a thermal oxide film interposed therebetween. In this example, the contact hole 56 is arranged at the tip of the dummy trench portion 30 in the X-axis direction.

The gate electrode 46 passes through the contact hole 55 and comes into contact with the gate wiring 45. The gate wiring 45 is formed of polysilicon or the like doped with impurities. An insulating film such as a thermal oxide film is provided between the gate wiring 45 and the semiconductor substrate. The gate wiring 45 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate. The gate wiring 45 is not connected to the dummy conductive portion in the dummy trench portion 30. The gate wiring 45 of this example is provided from below the contact hole 55 to the tip portion 43 of the gate trench portion 40. At the tip 43 of the gate trench 40, the gate conductive portion is exposed on the upper surface of the semiconductor substrate and comes into contact with the gate wiring 45.

The emitter electrode 52 and the gate electrode 46 are made of a material containing metal. For example, at least a portion of each electrode is formed of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium, a titanium compound, or the like in the lower layer of the region formed of aluminum or the like. Further, the contact hole may have a plug formed by embedding tungsten or the like so as to be in contact with the barrier metal and aluminum or the like.

The one or more gate trench portions 40 and the one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (short direction) on the upper surface of the semiconductor substrate. The arrangement direction in FIG. 1 is the Y-axis direction.

The gate trench portion 40 of this example is formed at two extending portions 41 extending linearly along an extending direction (longitudinal direction of the trench, X-axis direction in this example) perpendicular to the arrangement direction, and at the tip of the extending portion 41. It may have a tip 43 connecting the two stretches 41. It is preferable that at least a part of the tip portion 43 is formed in a curved shape on the upper surface of the semiconductor substrate. By connecting the tips of the two stretched portions 41 of the gate trench portion 40 with the tip portion 43, the electric field concentration at the end portion of the stretched portion 41 can be relaxed. In the present specification, the two extension portions 41 connected by the tip portion 43 may be treated as two gate trench portions 40.

One or more dummy trench portions 30 are provided between the respective extension portions 41 of the gate trench portion 40. The dummy trench portion 30 may have a tip portion 33 connecting the tips of the two extension portions 31, similarly to the gate trench portion 40. In this example, a dummy trench portion 30 having two extending portions 31 and a tip portion 33 is provided between each extending portion 41 of the gate trench portion 40. The dummy trench portion 30 of another example may have a linear shape without having the tip portion 33. The dummy trench portion 30 is provided at a position that does not overlap with the gate wiring 45. In the present specification, the two extension portions 31 connected by the tip portion 33 may be treated as two dummy trench portions 30.

The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the first well region 13, the second well region 11, the emitter region 12, the base region 14, and the contact region 15. The second well region 11 is provided in a predetermined range away from the longitudinal end of the contact hole 54 in the direction toward the gate electrode 46. The diffusion depth of the second well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. A part of the gate trench portion 40 and the dummy trench portion 30 on the gate electrode 46 side is provided in the second well region 11. The end of the dummy trench portion 30 in the stretching direction and the bottom of the tip portion may be covered with the second well region 11.

In this example, the region of the semiconductor substrate sandwiched between the trench portions is referred to as a mesa portion 71. However, the region of the semiconductor substrate sandwiched between the two dummy trench portions 30 (or the two stretched portions 31) is referred to as a dummy mesa portion 72. The mesa portion 71 and the dummy mesa portion 72 are regions on the upper surface side of the deepest bottom portion of the trench portion in the region of the semiconductor substrate sandwiched between the trench portions.

The mesa portion 71 is provided with a base region 14. The second well region 11 is a second conductive type. The base region 14 is a P-type having a lower doping concentration than the second well region 11, and the second well region 11 is a P + type.

On the upper surface of the base region 14 of the mesa portion 71, a P + type contact region 15 having a higher doping concentration than the base region 14 is provided. The second well region 11 is provided apart from the contact region 15 arranged at the end of the contact region 15 in the active region in the extending direction of the trench portion in the direction of the gate electrode 46. Further, an N + type emitter region 12 having a higher doping concentration than the semiconductor substrate is selectively formed on the upper surface of the base region 14.

Each of the contact region 15 and the emitter region 12 is provided from one trench portion adjacent to each other in the Y-axis direction to the other trench portion. The contact region 15 and the emitter region 12 are provided so as to be alternately exposed on the upper surface of the semiconductor substrate along the stretching direction (X-axis direction) of the trench portion. The contact region 15 and the emitter region 12 may be provided on the upper surface of the mesa portion 71 in a region sandwiched between exposed base regions 14 at both ends in the X-axis direction.

In the mesa portion 71 of another example, the contact region 15 and the emitter region 12 may be provided in a stripe shape along the stretching direction (X-axis direction). For example, an emitter region 12 is provided in a region adjacent to the trench portion, and a contact region 15 is provided in a region sandwiched between the emitter regions 12.

The dummy mesa portion 72 is provided with a second conductive type first well region 13 having a doping concentration higher than that of the base region 14. The first well region 13 of this example is P + type. The doping concentration of the first well region 13 may be the same as or different from the doping concentration of the second well region 11. The doping concentration of the first well region 13 may be 5 times or more of the doping concentration of the base region 14, and may be 10 times or more.

The first well region 13 is provided so as to be exposed on the upper surface of the dummy mesa portion 72. The first well region 13 of this example is provided in a range facing the emitter region 12 and the contact region 15 in the adjacent mesa portion 71 in the Y-axis direction. The first well region 13 is continuously provided in the Y-axis direction from a position in contact with one dummy trench portion 30 to a position in contact with the other dummy trench portion 30 on the upper surface of the dummy mesa portion 72. The first well region 13 may be continuously provided on the upper surface of the dummy mesa portion 72 in a region sandwiched between exposed base regions 14 at both ends in the X-axis direction.

The contact hole 54 provided in the mesa portion 71 is provided above each region of the contact region 15 and the emitter region 12. The contact hole 54 provided in the dummy mesa portion 72 is provided above the first well region 13. The contact hole 54 is not provided in the region corresponding to the base region 14 and the second well region 11. The emitter region may not be provided on the upper surface of the dummy mesa portion 72. The contact region 15 may be provided on the upper surface of the dummy mesa portion 72 at least in the region where the contact hole 54 is formed.

FIG. 2A is a diagram showing an example of a cross section in FIG. 1. The aa cross section of this example is a YZ plane passing through the emitter region 12. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 26, an emitter electrode 52, and a collector electrode 58 in the cross section. The interlayer insulating film 26 is a silicate glass to which impurities such as boron and phosphorus are added. The interlayer insulating film 26 is selectively formed on the upper surface 21 of the semiconductor substrate 10. The emitter electrode 52 is provided on the upper surface 21 of the semiconductor substrate 10 and the interlayer insulating film 26. The collector electrode 58 is provided on the lower surface 23 of the semiconductor substrate 10. The collector electrode 58 may be provided on the entire lower surface 23 of the semiconductor substrate 10.

The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or the like. The semiconductor substrate 10 of this example is a silicon substrate.

An N-type drift region 18 is provided inside the semiconductor substrate 10. The drift region 18 in the cross section is a region of the semiconductor substrate 10 in which the emitter region 12, the base region 14, the first well region 13, the buffer region 20 and the collector region 22 remain without being formed.

In the region of the semiconductor substrate 10 adjacent to any of the gate trench portions 40, a P-type base region is provided between the upper surface 21 of the semiconductor substrate 10 and the drift region 18. In this example, a P-shaped base region is provided in each mesa portion 71. The base region 14 may be formed by injecting a P-type impurity such as boron from the upper surface of the semiconductor substrate 10.

In the mesa portion 71, an N + type emitter region 12 is provided on the upper surface of the base region 14. The emitter region 12 may be formed by injecting N-type impurities such as phosphorus and arsenic from the upper surface of the semiconductor substrate 10.

In the region of the semiconductor substrate 10 adjacent to any of the dummy trench portions 30, a first well region 13 is provided between the upper surface 21 of the semiconductor substrate 10 and the drift region 18. The first well region 13 is provided from the upper surface 21 of the semiconductor substrate 10 to a position deeper than the lower end of the dummy trench portion 30. In the cross section shown in FIG. 2A, the first well region 13 is provided in the entire dummy mesa portion 72 and in the region below the dummy mesa portion 72.

The lower end of the first well region 13 may be determined based on the doping concentration distribution in the depth direction (Z-axis direction) of the first well region 13 and the drift region 18. As used herein, the doping concentration refers to the concentration of a donor or an acceptorized impurity (dopant). The depth position where the concentration difference (net doping concentration) distribution between the donor and the acceptor measured by the spreading resistance (SR) method or the like becomes the minimum value may be the lower end of the first well region 13.

The gate trench portion 40 is formed from the upper surface 21 of the semiconductor substrate 10 to the inside of the semiconductor substrate 10 and is in contact with the emitter region 12 and the base region 14 on the side wall. The gate trench portion 40 of this example is not in contact with the first well region 13. The gate trench portion 40 of this example is provided so as to penetrate the emitter region 12 and the base region 14 from the upper surface 21 of the semiconductor substrate 10.

The dummy trench portion 30 is formed from the upper surface 21 of the semiconductor substrate 10 to the inside of the semiconductor substrate 10 and is in contact with the first well region 13 on the side wall. Of the side walls of the dummy trench portion 30, the side wall facing the gate trench portion 40 may be in contact with the emitter region 12 and the base region 14. The gate trench portion 40 and the dummy trench portion 30 may be provided up to the same depth position Z1 in the Z-axis direction.

The bottom of the gate trench portion 40 of this example is arranged in the drift region 18. The bottom of the dummy trench portion 30 may be arranged in the drift region 18 and may be covered by the first well region 13. It should be noted that the fact that the trench portion penetrates each doping region is not limited to those manufactured in the order of forming the doping region and then forming the trench portion. Those in which the doping region is formed between the trench portions after the trench portion is formed are also included in those in which the trench portion penetrates the doping region.

The buffer region 20 is formed on the lower surface side of the drift region 18. The doping concentration in the buffer region 20 is higher than the doping concentration in the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the P + type collector region 22. A P + type collector region 22 is formed on the lower surface side of the buffer region 20.

The gate trench portion 40 has a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is formed so as to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is covered with a gate insulating film 42 inside the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

The gate conductive portion 44 includes a region facing at least the adjacent base region 14 with the gate insulating film 42 interposed therebetween in the depth direction. The gate trench portion 40 in the cross section is covered with the interlayer insulating film 26 on the upper surface of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel due to an electron inversion layer is formed on the surface layer of the interface of the base region 14 in contact with the gate trench portion 40.

The dummy trench portion 30 of this example has a dummy insulating film 32 and a dummy conductive portion 34. The dummy insulating film 32 is formed so as to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench portion 30 and is covered with the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. The dummy trench portion 30 in the cross section is covered with the interlayer insulating film 26 on the upper surface of the semiconductor substrate 10. The bottom of the dummy trench portion 30 and the gate trench portion 40 may be curved downward (curved in cross section).

The width of the mesa portion 71 and the width of the dummy mesa portion 72 may be equal. The width of the mesa portion 71 is typically 1.0 μm, and may be 0.1 μm or more and 3.0 μm or less. The width _WGT of the gate trench portion and the width _WDT of the dummy trench portion 30 may be equal or different. In this example, they are equal. Further, the width C of the mesa portion 71 may be equal to the width D of the dummy mesa portion 72.

The width of the contact hole 54 in the Y-axis direction may be the same for the mesa portion 71 and the dummy mesa portion 72. The width of the contact hole 54 is typically 0.6 μm, and may be 0.05 μm or more and 2.0 μm or less within a range not exceeding the mesa width or the dummy mesa width.

By providing the dummy trench portion 30, it is possible to enhance the carrier accumulation effect, promote the conductivity modulation, and reduce the on-voltage. Further, the switching speed of the semiconductor device 100 can be adjusted by adjusting the ratio of the dummy trench portion 30 to the gate trench portion 40.

At the time of turn-off of the semiconductor device 100, the carriers accumulated in the vicinity of the bottom of the trench in the drift region 18 are pulled out to the emitter electrode 52 via the second conductive type region. If the carrier withdrawal speed at turn-off is slower than the concentration of the accumulated carriers, the withstand capacity of the semiconductor device 100 will decrease. The carrier extraction speed refers to the amount of carriers such as holes extracted from the drift region 18 to the emitter electrode 52 and the like per unit time at the time of turn-off of the semiconductor device 100.

In the semiconductor device 100, by providing the first well region 13 formed deeper than the dummy trench portion 30, carriers such as holes accumulated in the vicinity of the bottom of the trench can be efficiently extracted. Therefore, it is possible to easily reduce the on-voltage of the semiconductor device 100 and maintain the withstand voltage of the semiconductor device 100 at the same time.

FIG. 2B is a diagram showing an example of a cross section in FIG. 1. In the semiconductor device 100 of this example, the contact width of the contact for connecting to the semiconductor substrate 10 is different from that in FIG. 2A. In this example, the contact width B of the contact formed on the first well region 13 is different from the contact width A of the contact formed on the emitter region 12. The contact width B of this example may be larger or smaller than the contact width A. In this example, the contact width B is larger than the contact width A. That is, by making the contact width B between the dummy trench portions 30 larger than the contact width A between the dummy trench portions 30 and the gate trench portion 40, the turn-off resistance of the semiconductor device 100 can be improved.

The ratio (A / B) of the contact width A to the contact width B may be 0.2 or more and 2.0 or less. When the contact width B is larger than the contact width A, the ratio (A / B) may be 0.2 or more and less than 1.0, and further 0.4 or more and 0.7 or less. On the other hand, when the contact width B is smaller than the contact width A, the ratio (A / B) may be larger than 1.0 and 2.0 or less, and further 1.3 or more and 1.7 or less.

FIG. 2C is a diagram showing an example of a cross section in FIG. 1. The semiconductor device 100 of this example differs from the case of FIG. 2A in that the width of the dummy mesa portion 72 in the Y-axis direction is different from the width of the mesa portion 71 in the Y-axis direction. In this example, the width D of the dummy mesa portion 72 is different from the width C of the mesa portion 71 between the dummy trench portion 30 and the gate trench portion 40. The width D of the dummy mesa portion 72 of this example may be larger than the width C of the mesa portion 71. By making the width D of the dummy mesa portion 72 larger than the width C of the other mesa portions 71, the turn-off withstand capability of the semiconductor device 100 can be improved.

The ratio (D / C) of the width C of the mesa portion 71 to the width D of the dummy mesa portion 72 may be larger than 0.2 and 5.0 or less. When the width D of the dummy mesa portion 72 is smaller than the width C of the mesa portion 71, the ratio (D / C) may be 0.2 or more and less than 1.0, and further 0.4 or more and 0.7 or less. On the other hand, when the width D of the dummy mesa portion 72 is larger than the width C of the mesa portion 71, the ratio (D / C) is larger than 1.0 and 5.0 or less, and further 2.0 or more and 4.0 or less. good.

FIG. 2D is an example of a distribution diagram of the doping concentration when the cc cross section and the dd cross section of FIG. 2A are cut. In the cc cross section, the emitter region 12, the base region 14, and the drift region 18 are arranged in this order from the upper surface side of the semiconductor substrate 10. In the dd cross section, the doping concentration distribution of the first well region 13 may be Gaussian distribution from the upper surface of the semiconductor substrate 10. The Gaussian distribution is a profile when the dopant introduced on the upper surface of the semiconductor substrate 10 is diffused by thermal diffusion.

The depth from the upper surface of the pn junction between the base region 14 and the drift region 18, that is, the depth of the base region 14, is deeper than the lower end position Z1 of the trench portion. On the other hand, the depth of the pn junction between the first well region 13 and the drift region 18, that is, the depth of the first well region 13 may be deeper than the lower end position Z1 of the trench portion. The depth of the base region 14 is typically 3.0 μm and may be 0.5 μm or more and 5.0 μm or less. The depth of the first well region 13 is typically 7.0 μm and may be 2.0 μm or more and 10 μm or less.

FIG. 2E is another example of the distribution map of the doping concentration when the cc cross section and the dd cross section of FIG. 2A are cut. The doping concentration distribution in the cc cross section of this example is the same as the doping concentration distribution in the cc cross section in FIG. 2D. In this example, the doping concentration distribution in the dd cross section is different from that in FIG. 2D. The first well region 13 of this example has four peaks of the first well region 13-1 to the first well region 13-4. For example, in the dd cross section, the doping concentration distribution of the first well region 13 has a concentration peak at a position deeper than the first stage of lowering the contact resistance, the second stage of the doping concentration distribution almost the same as that of the base region 14, and the base region 14. It consists of the third stage to be provided and the fourth stage to have a concentration peak at a position deeper than the third stage.

The number and depth of peak positions in the first well region 13 are not limited to this example. The fourth stage of the first well region 13 is in contact with the drift region 18 and has a pn junction. The minimum concentration of the valley portion between each concentration peak may be higher than the doping concentration of the drift region 18. The peak concentrations of the third and fourth stages of the first well region 13 in FIG. 2E may be higher than the peak concentration of the base region 14 and may be lower than the base region 14.

Further, the peak position of the third stage may be deeper than the position of the pn junction between the base region 14 and the drift region 18. Further, the peak position of the fourth stage may be shallower than the lower end position Z1 of the trench portion.

FIG. 3 is a diagram showing another example of the upper surface of the semiconductor device 100. The semiconductor device 100 of this example further includes a storage region 16 in addition to the configuration of the semiconductor device 100 described in FIGS. 1 and 2A. The storage region 16 is a first conductive type region having a higher doping concentration than the drift region 18. The storage area 16 of this example is N + type.

The storage region 16 is not exposed on the upper surface of the semiconductor substrate 10. The storage region 16 may be formed between the drift region 18 and the base region 14. In FIG. 3, a region in which the storage region 16 is provided in the XY plane parallel to the upper surface 21 of the semiconductor substrate 10 is shown by a broken line. In this example, a plurality of storage regions 16 separated from each other in the plane are provided.

A storage region 16 is provided in at least a part of the mesa portion 71 sandwiched between the two trench portions, one of which is the gate trench portion 40. The storage region 16 of this example is provided at least below the emitter region 12. The storage area 16 may also be provided below the contact area 15. The storage area 16 of this example is provided on the entire mesa portion 71 in the width direction (Y-axis direction). The storage region 16 does not have to be provided below the base region 14 exposed on the upper surface of the mesa portion 71. On the other hand, the dummy mesa portion 72 is not provided with the accumulation region 16 having a higher doping concentration than the base region 14.

FIG. 4A is a diagram showing an example of the aa cross section in FIG. The aa cross section of this example is a YZ plane passing through the emitter region 12. The semiconductor device 100 of this example further includes a storage region 16 in addition to the configuration of the semiconductor device 100 shown in FIG. 2A. The storage region 16 is provided between the base region 14 and the drift region 18 in each mesa portion 71. The storage area 16 of this example is provided in each mesa portion 71 from a region adjacent to one trench portion to a region adjacent to the other trench portion.

The accumulation region 16 is an N + type region having a higher doping concentration than the drift region 18. For example, between the drift region 18 and the base region 14, a region having a doping concentration 10 times or more higher than the average value of the doping concentration of the drift region 18 may be designated as the accumulation region 16. The doping concentration of the accumulation region 16 may be 50 times or more, or 100 times or more, the doping concentration of the drift region 18. The storage region 16 may be formed by injecting an N-type impurity such as phosphorus or proton from the upper surface 21 of the semiconductor substrate 10.

By providing the storage region 16, the carrier concentration accumulated below the storage region 16 can be further increased. Therefore, the on-voltage of the semiconductor device 100 can be reduced. Further, by providing the first well region 13, the carriers accumulated in the accumulation region 16 can be efficiently extracted. Therefore, even if the storage region 16 is provided, the withstand capacity of the semiconductor device 100 can be maintained.

FIG. 4B is a diagram showing an example of the aa cross section in FIG. The semiconductor device 100 of this example is different from the case of FIG. 4A in that the dummy mesa portion 72 has the storage region 16. The storage region 16 of this example includes a storage region 16-1 formed in the mesa portion 71 and a storage region 16-2 formed in the dummy mesa portion 72. The storage area 16-1 and the storage area 16-2 may be formed simultaneously by the same process. Further, the storage region 16-1 and the storage region 16-2 may be formed by different processes at different dopant concentrations.

The storage region 16-2 is formed by being sandwiched between the dummy trench portions 30 in the dummy mesa portion 72. That is, the upper end and the lower end of the storage region 16-2 are provided in contact with the first well region 13. The storage region 16-2 is a first conductive type region having a higher doping concentration than the drift region 18. In the semiconductor device 100 of this example, by providing the storage region 16-2 in the dummy mesa portion 72, the pulling out of the carrier via the P-type inversion layer at the bottom of the dummy trench portion 30 at the time of turn-on is suppressed, and the turn-on loss is reduced. can.

FIG. 4C is an example of a distribution diagram of the doping concentration when the cc cross section and the dd cross section of FIG. 4B are cut. In the cc cross section, the emitter region 12, the base region 14, and the drift region 18 are arranged in this order from the upper surface side of the semiconductor substrate 10. In the dd cross section, the doping concentration distribution of the first well region 13 may be Gaussian distribution from the upper surface of the semiconductor substrate 10. The Gaussian distribution is a profile when the dopant introduced on the upper surface of the semiconductor substrate 10 is diffused by thermal diffusion.

The depth from the upper surface of the semiconductor substrate 10 to the peak position of the doping concentration in the storage region 16 may be deeper than the depth from the peak position to the lower end position Z1 of the trench portion. The peak position of the storage region 16 is typically 4.0 μm and may be 1.0 μm or more and 6.0 μm or less.

FIG. 4D is another example of the distribution map of the doping concentration when the cc cross section and the dd cross section of FIG. 4B are cut. The doping concentration distribution in the dd cross section is different from that in FIG. 2D. The first well region 13 of this example has three peaks of the first well region 13-1 to the first well region 13-3. For example, in the dd cross section, the doping concentration distribution is the first stage of the first well region 13 that lowers the contact resistance, the second stage of the first well region 13 having almost the same distribution as the base region 14, and the accumulation region 16-2. It consists of the third stage of the first well region 13 having a concentration peak at a position deeper than the accumulation region 16-2. The peak concentration of the third stage of the first well region 13 in FIG. 4D may be higher than the peak concentration of the storage region 16-2 and may be lower than the peak concentration of the storage region 16-2. In this example, the peak concentration of the third stage of the first well region 13 is higher than the peak concentration of the accumulation region 16-2.

FIG. 4E is a diagram showing an example of the aa cross section in FIG. The semiconductor device 100 of this example is different from the case of FIG. 4A in that the film thickness d1 of the dummy insulating film 32 and the film thickness d2 of the gate insulating film 42 are different. The film thickness d1 of the dummy insulating film 32 of this example is thicker than the film thickness d2 of the gate insulating film 42. As a result, it is possible to suppress the pulling out of the carrier via the P-type inversion layer at the bottom of the dummy trench portion 30 at the time of turn-on, and reduce the turn-on loss. The film thickness d2 is typically 0.1 μm, and may be 0.05 μm or more and 0.3 μm or less. The film thickness d1 is typically 0.2 μm, and may be 0.1 μm or more and 1.0 μm or less in a range thicker than the film thickness d2. As a result, it is possible to suppress the pulling out of the carrier via the P-type inversion layer at the bottom of the dummy trench portion 30 at the time of turn-on, and reduce the turn-on loss.

In this example, the width of the dummy trench portion 30 and the gate trench portion 40 in the Y-axis direction are the same, and the film thickness d1 of the dummy insulating film 32 becomes thicker. Therefore, the width of the dummy conductive portion 34 in the Y-axis direction is the width of the gate conductive portion. It is smaller than the width of 44 in the Y-axis direction. By making the width of the dummy trench portion 30 in the Y-axis direction larger than the width of the gate trench portion 40 in the Y-axis direction, the film thickness d1 of the dummy insulating film 32 is larger than the film thickness d2 of the gate insulating film 42. You may.

FIG. 5 is a diagram showing another example of the upper surface of the semiconductor device 100. In the semiconductor device 100 of this example, the arrangement of the storage region 16 is different from the configuration of the semiconductor device 100 shown in FIGS. 3 and 4A. Other configurations are the same as the semiconductor device 100 shown in FIGS. 3 and 4A.

The storage region 16 of this example is not provided in at least a part of the mesa portion 71 in a region adjacent to at least one trench portion. In the example of FIG. 5, the storage region 16 is in contact with the gate trench portion 40 and not with the dummy trench portion 30 in each mesa portion 71. Further, the storage area 16 is not provided in the dummy mesa portion 72.

FIG. 6 is a diagram showing an example of the aa cross section in FIG. The aa cross section of this example is a YZ plane passing through the emitter region 12. In the semiconductor device 100 of this example, the arrangement of the storage region 16 is different from the configuration of the semiconductor device 100 shown in FIG. 4A. Other configurations are the same as the semiconductor device 100 shown in FIG. 4A.

The storage region 16 of this example is provided in a region adjacent to the gate trench portion 40 inside the semiconductor substrate 10. The storage region 16 may be provided in contact with the base region 14, or may be provided apart from the base region 14. However, it is preferable that the storage region 16 is provided inside the mesa portion 71 (that is, a region from the upper surface 21 of the semiconductor substrate 10 to the lower end of the trench portion).

In each mesa portion 71, the N-type doping concentration of the region 17 adjacent to the dummy trench portion 30 inside the semiconductor substrate 10 and at the same depth as the storage region 16 is lower than that of the storage region 16. The region 17 of this example has the same doping concentration as the drift region 18. The storage region 16 may be provided in a region of half or less of the width of the mesa portion 71 in the Y-axis direction, or may be provided in a region of half or more.

With such a structure, carriers can be accumulated near the lower end of the gate trench portion 40, and carriers such as holes can be extracted from the mesa portion 71 at the time of turn-off. For example, the carrier that has passed in the vicinity of the dummy trench portion 30 is pulled out to the emitter electrode 52 through the base region 14 and the contact region 15.

FIG. 7 is a diagram showing another example of the aa cross section in FIG. In the semiconductor device 100 of this example, the arrangement of the storage region 16 in the Z-axis direction is different from the configuration of the semiconductor device 100 shown in FIG. Other configurations are the same as those of the semiconductor device 100 shown in FIG.

The storage area 16 of this example is arranged apart from the base area 14. A drift region 18 may be provided between the storage region 16 and the base region 14. The storage region 16 is in contact with the gate trench portion 40 and is not in contact with the dummy trench portion 30. A part of the storage area 16 may be provided below the lower end of the gate trench portion 40.

The bottom of the gate trench portion 40 of this example has a curved surface shape that is convex downward. The storage region 16 may cover a part of the curved surface at the bottom of the gate trench portion 40. With such a structure, carriers can be accumulated near the lower end of the gate trench portion 40, and carriers such as holes can be extracted from the mesa portion 71 at the time of turn-off.

FIG. 8 is a diagram showing another example of the aa cross section in FIG. In the semiconductor device 100 of this example, the arrangement of the storage region 16 is different from the configuration of the semiconductor device 100 shown in FIG. Other configurations are the same as those of the semiconductor device 100 shown in FIG.

The semiconductor device 100 of this example has a first storage region 16-1 and a second storage region 16-2 in each mesa portion 71. The first storage area 16-1 is the same as the storage area 16 shown in FIG. 6, and the second storage area 16-2 is the same as the storage area 16 shown in FIG. 7.

The first storage region 16-1 and the second storage region 16-2 may have the same doping concentration or may have different doping concentrations. When viewed from the Z-axis direction, at least a part of the first storage area 16-1 and at least a part of the second storage area 16-2 are arranged so as to overlap each other.

The first storage area 16-1 and the second storage area 16-2 may be provided apart in the Z-axis direction. In this case, a drift region 18 may be provided between the first storage region 16-1 and the second storage region 16-2. The first storage region 16-1 and the second storage region 16-2 may be continuously provided in the Z-axis direction. In this case, the doping concentration distribution in the depth direction of the first storage region 16-1 and the second storage region 16-2 is the respective of the first storage region 16-1 and the second storage region 16-2. It may have a peak in the region. The doping concentration between the peaks is higher than the doping concentration in the drift region 18.

With such a structure, carriers can be accumulated near the lower end of the gate trench portion 40, and carriers such as holes can be extracted from the mesa portion 71 at the time of turn-off.

FIG. 9 is a diagram showing another example of the aa cross section in FIG. In the semiconductor device 100 of this example, the arrangement of the storage region 16 is different from the configuration of the semiconductor device 100 shown in FIG. 4A. Other configurations are the same as the semiconductor device 100 shown in FIG. 4A.

The semiconductor device 100 of this example has a first storage region 16-1 and a second storage region 16-2 in each mesa portion 71. The first storage area 16-1 is the same as the storage area 16 shown in FIG. 4A. The second storage region 16-2 is provided inside the mesa portion 71 below the first storage region 16-1. The second storage region 16-2 may have the same doping concentration as the first storage region 16-1, or may have a different doping concentration. The semiconductor device 100 may include a storage region 16 provided in three or more stages in the depth direction inside the mesa portion 71.

Similar to the first storage region 16-1, the second storage region 16-2 is provided from a region in contact with one trench portion to a region in contact with the other trench portion in the Y-axis direction. The first storage area 16-1 and the second storage area 16-2 may be provided apart from each other in the Z-axis direction, or may be provided continuously. With such a structure, the carrier accumulation effect can be further enhanced.

By providing the storage regions 16 in multiple stages in the depth direction, the electron current that has passed through the channel formed near the interface with the gate trench portion 40 of the base region 14 at the time of turn-on is the Y-axis of the mesa portion 71. It becomes easy to flow near the center in the direction.

The main source of current at the initial stage of turn-on is not a hole current but an electron current. The initial period is a period from immediately before the gate voltage Vge reaches the threshold voltage to before entering the mirror period in which the Vge becomes constant at the value of the threshold voltage. When Vge approaches the threshold voltage, the channel is about to open and the injection of electrons into the drift region 18 begins.

Electrons heading downward from the channel may once flow in the arrangement direction (Y-axis direction or direction from the vicinity of the gate trench portion 40 toward the center of the mesa portion 71) in the first storage region 16-1. When the second storage region 16-2 is not provided, in the drift region 18 below the first storage region 16-1, an electron storage layer is already formed in the vicinity of the gate trench portion 40. Therefore (the threshold voltage at which the electron storage layer in the N-type region is formed is much smaller than the threshold voltage of the inversion layer in the P-type region), the impedance is lower than that in the drift region 18. Therefore, the electron current mainly flows in the vicinity of the gate trench portion 40.

When the electrons reach the collector region 22 on the back surface, hole injection starts from the collector region 22 to the buffer region 20 and the drift region 18. As a result, holes are accumulated near the lower end of the trench portion. As an example, holes exist on the order of 1.0 × 10 ¹⁶ [cm ^-3 ] from the vicinity of the lower end of the gate trench portion 40 to the side portion of the dummy trench portion 30 below the first storage region 16. ..

The holes collect at the lower end of the gate trench portion 40 and the lower end of the dummy trench portion 30. In particular, since the dummy conductive portion 34 has the same potential as the emitter electrode 52, a hole inversion layer is likely to be formed on the side wall of the dummy trench portion 30. The holes injected from the collector region 22 collect in the vicinity of the inversion layer of the holes. The holes are continuously distributed from the dummy trench portion 30 to the lower end of the gate trench portion 40. Due to this hole distribution, a large displacement current may flow near the lower end of the gate trench portion 40 at the time of turn-on.

The semiconductor device 100 of this example further includes a second storage region 16-2. In this case, the impedance for the electron current is the first storage region 16 rather than the path that returns from the vicinity of the center of the first storage region 16-1 to the vicinity of the gate trench portion 40 and flows into the second storage region 16-2. The route that flows directly from -1 to the second storage region 16-2 is lower.

Holes are likely to be accumulated in the hole high concentration region adjacent to the gate trench portion 40 in the lower part of each storage region. Further, since the electron current flows not in the vicinity of the gate trench portion 40 but in the vicinity of the center of the mesa portion 71, the accumulation of holes in the hole high concentration region is promoted. Therefore, it is promoted that the electron current flows near the center of the mesa portion 71.

By providing the storage regions 16 in multiple stages in the depth direction, the electron current can easily travel downward near the center of the mesa portion 71. When the electron current flows near the center of the mesa portion 71, the hole distribution near the bottom of the mesa portion 71 is divided near the center of the mesa portion 71 by the electron current. Therefore, the holes on the dummy trench portion 30 side of the electron current path do not flow to the gate trench portion 40 side. The division of the hole distribution in the central portion of the mesa portion 71 suppresses the accumulation of holes at the lower end of the gate trench portion 40. Therefore, the displacement current can be reduced. Since the displacement current can be reduced, the charge of the gate conductive portion 44 is also reduced, and the momentary increase in the gate electrode Vge is suppressed. As a result, the voltage reduction rate (dV / dt) of the collector-emitter voltage can also be suppressed.

FIG. 10 is a diagram showing another example of the aa cross section in FIG. The semiconductor device 100 of this example has a different shape of the first well region 13 from the semiconductor device 100 of any of the embodiments described with reference to FIGS. 1 to 9. Other configurations are the same as any of the semiconductor devices 100 described with reference to FIGS. 1 to 9. FIG. 10 shows an example in which the shape of the first well region 13 is changed in the semiconductor device 100 shown in FIG.

The first well region 13 of this example has a recessed portion 73 having a minimum width in the Y-axis direction on the YZ plane. Further, the first well region 13 may have a plurality of recesses 73 having different positions in the Z-axis direction. At least one recess 73 may be provided below the lower end of the dummy trench 30. The first well region 13 has peak doping concentrations on the upper side and the lower side of the recess 73, respectively.

The first well region 13 of this example can be formed by injecting P-type impurities a plurality of times at different injection depths. By changing the injection depth of impurities, the first well region 13 can be formed to a deeper position. That is, the first well region 13 having a relatively small width in the Y-axis direction and a large depth in the Z-axis direction can be easily formed. By forming the first well region 13 deeply, carriers such as holes can be easily extracted.

As an example, the first well region 13 may be formed 20% or more deeper than the dummy trench portion 30, and may be formed 50% or more deeper. Further, the difference in depth between the first well region 13 and the dummy trench portion 30 may be larger than the width of the dummy mesa portion 72 in the Y-axis direction. The first well region 13 may be formed deeper than the second well region 11.

FIG. 11 is an enlarged cross-sectional view of the vicinity of the first well region 13. The dummy trench portion 30 of this example has a first dummy side wall 38, a second dummy side wall 37, and a bottom portion 35 on the YZ surface. The first dummy side wall 38 is in contact with the first well region 13. The second dummy side wall 37 is a side wall on the YZ surface opposite to the first dummy side wall 38.

The first well region 13 of this example covers at least a part of the bottom portion 35 of the dummy trench portion 30. The bottom portion 35 of this example has a curved surface shape protruding downward from the lower ends of the first dummy side wall 38 and the second dummy side wall 37. The lower end position Z2 of the first well region 13 is arranged below the lower end position Z1 of the dummy trench portion 30.

Of the side walls of the dummy trench portion 30, a region having the same inclination as the portion in contact with the base region 14 may be used as the second dummy side wall 37. The first dummy side wall 38 is a side wall opposite to the second dummy side wall 37, and is a side wall having the same depth range as the second dummy side wall 37. The bottom portion 35 may refer to a region where the inclination of the semiconductor substrate 10 with respect to the upper surface 21 is smaller than that of the first dummy side wall 38 and the second dummy side wall 37. By covering at least a part of the bottom portion 35 of the dummy trench portion 30, the first well region 13 can further improve the pulling speed of the carrier.

The first well region 13 covers at least a part of the region between the central Y1 in the width direction (Y-axis direction) and the first dummy side wall 38 in the bottom portion 35 of the dummy trench portion 30. That is, the position Y2 of the end portion 36 of the first well region 13 covering the bottom portion 35 in the Y-axis direction is arranged between the central position Y1 of the bottom portion 35 and the first dummy side wall 38. With such a structure, the pull-out speed of the carrier can be further improved.

FIG. 12 is a cross-sectional view showing an example in which the position of the end portion 36 of the first well region 13 covering the bottom portion 35 is changed in the structure shown in FIG. The first well region 13 of this example covers the bottom portion 35 from the center Y1 of the bottom portion 35 to the side of the second dummy side wall 37. That is, the position Y2 of the end portion 36 of the first well region 13 is arranged between the central position Y1 of the bottom portion 35 and the second dummy side wall 37. With such a structure, the pull-out speed of the carrier can be further improved.

FIG. 13 is a cross-sectional view showing an example in which the position of the end portion 36 of the first well region 13 covering the bottom portion 35 is changed in the structure shown in FIG. The first well region 13 of this example covers the entire bottom 35. That is, the position Y2 of the end portion 36 of the first well region 13 is arranged on the center side of the mesa portion 71 with respect to the second dummy side wall 37. In this case, the first well region 13 is provided down to the lower part of the mesa portion 71. With such a structure, the pull-out speed of the carrier can be further improved.

In the trench portion in contact with the mesa portion 71, the length from the side wall of the trench portion on the mesa portion 71 side to Y2 may be shorter or longer than the length from the side wall of the trench portion to Y1. In this example, in the trench portion in contact with the mesa portion 71, the length from the side wall of the trench portion on the mesa portion 71 side to Y2 is shorter than the length from the side wall of the trench portion to Y1.

FIG. 14 is a diagram showing another example of the dummy trench portion 30 and the gate trench portion 40. The dummy trench portion 30 of this example is formed deeper than the gate trench portion 40 when viewed from the upper surface 21 of the semiconductor substrate 10. That is, the lower end position Z3 of the dummy trench portion 30 is arranged below the lower end position Z1 of the gate trench portion 40. When viewed from the upper surface 21 of the semiconductor substrate 10, the dummy trench portion 30 may be formed 10% or more deeper than the gate trench portion 40, or may be formed 20% or more. With such a structure, the pull-out speed of the carrier can be further improved.

FIG. 15 is a diagram showing another example of the first well region 13. In the semiconductor device 100 of this example, three or more dummy trench portions 30 are continuously arranged in the Y-axis direction. The three or more dummy trench portions 30 may be sandwiched between the gate trench portions 40 in the Y-axis direction. In this example, the first well regions 13 provided in the two or more dummy mesa portions 72 are connected to each other.

In this example, among the plurality of dummy trench portions 30 arranged continuously, the entire bottom of the dummy trench portions 30 other than the dummy trench portions 30 arranged at both ends in the Y-axis direction is covered with the first well region 13. You may be broken. The relationship between the dummy trench portions 30 arranged at both ends in the Y-axis direction and the first well region 13 is the same as any of the embodiments described with reference to FIGS. 1 to 14. With such a structure, the pull-out speed of the carrier can be further improved.

FIG. 16 is a diagram showing another example of the aa cross section of the semiconductor device 100. The semiconductor device 100 of this example is different from the semiconductor device 100 described with reference to FIGS. 1 to 15 in that it further includes a lower surface side region 28. Other configurations are the same as the semiconductor device 100 of any aspect described with reference to FIGS. 1 to 15.

The lower surface side region 28 is provided at the same depth as the collector region 22 in at least a part of the region below the dummy mesa portion 72. The lower surface side region 28 is an N-shaped region. The lower surface side region 28 may have a higher doping concentration than the drift region 18. The lower surface side region 28 may have a higher doping concentration than the buffer region 20.

The lower surface side region 28 may have the same width as the dummy mesa portion 72 in the Y-axis direction. The lower surface side region 28 may have a width smaller than that of the dummy mesa portion 72 in the Y-axis direction, and may have a large width. The lower surface side region 28 may be formed below the dummy trench portion 30, and may also be formed in a part of the region below the mesa portion 71.

By providing the lower surface side region 28, it is possible to suppress the carrier accumulation of the second conductive type below the dummy mesa portion 72. The carrier concentration below the dummy mesa portion 72 has a small effect on the on-voltage of the semiconductor device 100. Therefore, it is possible to easily pull out the carrier at the time of turn-off or the like while reducing the on-voltage.

FIG. 17 is a diagram showing an example of the bb cross section shown in FIG. However, the structure shown in FIG. 17 can be applied to the semiconductor device 100 shown in other than FIG. The bb cross section is an XZ plane that passes through the contact hole 54 in the dummy mesa portion 72.

In the semiconductor device 100 of this example, the collector region 22 and the lower surface side region 28 are alternately arranged below the dummy mesa portion 72 along the longitudinal direction of the dummy trench portion 30. With such a structure, the area ratio of the collector region 22 and the lower surface side region 28 can be easily adjusted. The width of one collector region 22 in the X-axis direction and the width of one lower surface side region 28 may be the same. In the X-axis direction, the width of one collector region 22 may be larger than the width of one lower surface side region 28, and the width of one lower surface side region 28 may be larger than the width of one collector region 22.

Further, the range in which the collector region 22 is provided in the X-axis direction may overlap with the range in which the emitter region 12 is provided in the X-axis direction at least in part. The range in which the collector region 22 is provided in the X-axis direction may coincide with the range in which the emitter region 12 is provided in the X-axis direction. The range in which the collector region 22 is provided in the X-axis direction may be included in the range in which the emitter region 12 is provided in the X-axis direction, and the range in which the emitter region 12 is provided in the X-axis direction is the collector region 22 in the X-axis direction. May be included in the range provided.

The length L _p of the collector region 22 sandwiched between the two lower surface side regions 28 in the X-axis direction may be longer or shorter than the length L _n of the lower surface side region 28. Equal in this example. The length L _p of the collector region 22 in the X-axis direction is typically 10 μm, and may be 5 μm or more and 15 μm or less. The length L _n of the lower surface side region 28 is typically 5 μm, and may be 5 μm or more and 15 μm or less.

FIG. 18 is a diagram partially showing the upper surface of the semiconductor device 200 according to another embodiment of the present invention. The semiconductor device 200 has a different arrangement of the emitter region 12, the contact region 15, and the storage region 16 from the semiconductor device 100 described with reference to FIGS. 1 to 17. Other configurations may be the same as any of the semiconductor devices 100 described with reference to FIGS. 1 to 17.

In this example, the stretched portion 41 of the gate trench portion 40 has a length and a short side on the upper surface of the semiconductor substrate 10. In the example of FIG. 18, the stretched portion 41 has a longitudinal length in the X-axis direction and a short hand in the Y-axis direction.

The gate trench portion 40 has a first gate side wall 74 along the longitudinal direction and a second gate side wall 75 opposite to the first gate side wall 74. The first gate side wall 74 and the second gate side wall 75 are arranged so as to face each other inside the semiconductor substrate 10.

In this example, among the mesa portions 71, the mesa portion 71 adjacent to the first gate side wall 74 is referred to as the first mesa portion 71-1, and the mesa portion 71 adjacent to the second gate side wall 75 is referred to as the second mesa portion 71-2. And. That is, one mesa portion 71 arranged across the gate trench portion 40 is referred to as a first mesa portion 71-1, and the other mesa portion 71 is referred to as a second mesa portion 71-2.

Emitter regions 12 and contact regions 15 are arranged on the upper surfaces of the first mesa portion 71-1 and the second mesa portion 71-2 so as to be alternately exposed along the X-axis direction. In the semiconductor device 100 of this example, at least a part of the at least one emitter region 12 in the first mesa section 71-1 is arranged at a position facing the contact region 15 in the second mesa section 71-2. There is. That is, at least a part of the range in the X-axis direction in which at least one emitter region 12 is provided in the first mesa portion 71-1 is the range in the X-axis direction in which the contact region 15 in the second mesa portion 71-2 is provided. overlapping.

In the example of FIG. 18, the entire emitter region 12 in the first mesa portion 71-1 is arranged at a position facing any contact region 15 in the second mesa portion 71-2. The width of the emitter region 12 in the first mesa portion 71-1 in the X-axis direction may be the same as the width of the contact region 15 in the second mesa portion 71-2 in the X-axis direction.

Further, at least a part of the at least one contact region 15 in the first mesa portion 71-1 is arranged at a position facing the emitter region 12 in the second mesa portion 71-2. That is, at least a part of the range in the X-axis direction in which at least one contact region 15 is provided in the first mesa portion 71-1 is the range in the X-axis direction in which the emitter region 12 in the second mesa portion 71-2 is provided. overlapping.

In the example of FIG. 18, the entire contact region 15 in the first mesa portion 71-1 is arranged at a position facing any emitter region 12 in the second mesa portion 71-2. The width of the contact region 15 in the first mesa portion 71-1 in the X-axis direction may be the same as the width of the emitter region 12 in the second mesa portion 71-2 in the X-axis direction. However, of the contact regions 15 in the first mesa portion 71-1, the contact regions 15 provided at both ends in the X-axis direction face both the emitter region 12 and the contact region 15 of the second mesa portion 71-2. Are arranged. That is, in both the first mesa portion 71-1 and the second mesa portion 71-2, the contact region 15 is arranged adjacent to the base regions 14 provided at both ends in the X-axis direction. As a result, the carriers below the base region 14 provided at both ends in the X-axis direction can be efficiently pulled out. The width of the contact region 15 in the first mesa portion 71-1 in the X-axis direction may be the same as the sum of the widths of the emitter region 12 and the contact region 15 of the second mesa portion 71-2 in the X-axis direction.

In two mesa portions 71 adjacent to each other with the gate trench portion 40 interposed therebetween, the emitter region 12 and the contact region 15 are arranged so as to be offset in the X-axis direction, so that the contact region 15 that contributes to the extraction of holes is dispersedly arranged. can do. Therefore, holes can be extracted without bias on the XY surface, and the withstand capacity at the time of turn-off of the semiconductor device 100 can be improved.

In the semiconductor device 200 of this example, the contact region 15 is exposed on the upper surface of the dummy mesa portion 72. A base region 14 may be formed below the contact region 15. Further, in the semiconductor device 200 of this example, the storage region 16 is formed in the mesa portion 71 and the dummy mesa portion 72.

Further, in the first mesa portion 71-1 and the second mesa portion 71-2, the region where the emitter region 12 or the contact region 15 is formed extends in the lateral direction (Y-axis direction) of the gate trench portion 40. The trench portion is not formed. That is, in the region where the emitter region 12 and the contact region 15 are regularly arranged, the gate trench portion 40 does not have a branch portion or a branch portion extending inward of the mesa portion 71. Further, the dummy trench portion 30 is not provided in the area. With such a structure, carriers such as holes can be effectively extracted through the contact regions 15 dispersed and arranged without being hindered by the trench portion.

FIG. 19 is a diagram showing an example of the aa cross section in FIG. The aa cross section of this example is a YZ plane that passes through the contact region 15 of the first mesa portion 71-1 and the emitter region 12 of the second mesa portion 71-2.

As described above, the contact region 15 of the first mesa portion 71-1 and the contact region 15 of the second mesa portion 71-2 are arranged so as to be offset in the X-axis direction. Therefore, in the cross section shown in FIG. 19, the contact region 15 is provided in the first mesa portion 71-1 and the emitter region 12 is provided in the second mesa portion 71-2. With such an arrangement, holes can be extracted without bias.

The dummy mesa portion 72 of this example is provided with a contact region 15, a base region 14, and a storage region 16 in order from the upper surface 21 side of the semiconductor substrate 10. In another example, the dummy mesa portion 72 may not be provided with the storage region 16. Further, similarly to the semiconductor device 100 shown in FIGS. 1 and 2A, the mesa portion 71 does not have to be provided with the storage region 16.

FIG. 20 is a diagram showing another example of the aa cross section in FIG. In the semiconductor device 200 of this example, the structure of the dummy mesa portion 72 is the same as that of the semiconductor device 100 described with reference to FIGS. 1 to 17. That is, the semiconductor device 200 of this example has a first well region 13 in the dummy mesa portion 72. With such a structure, the carrier can be pulled out more easily. Further, the structure of the storage region 16 in the semiconductor device 200 may be the same as that of the storage region 16 of the semiconductor device 100. Further, the semiconductor device 200 may include a lower surface side region 28 shown in FIGS. 16 and 17.

FIG. 21 is a diagram showing an example of arrangement of the emitter region 12 and the contact region 15 on the upper surfaces of the first mesa portion 71-1 and the second mesa portion 71-2. In this example, the emitter region 12 and the contact region 15 in each mesa portion 71 have the same length in the X-axis direction. The contact region 15 in the first mesa portion 71-1 is arranged at a position facing the emitter region 12 of the second mesa portion 71-2, and the emitter region 12 in the first mesa portion 71-1 is the second mesa. It is arranged at a position facing the contact area 15 of the unit 71-2.

FIG. 22 is a diagram showing another arrangement example of the emitter region 12 and the contact region 15 on the upper surfaces of the first mesa portion 71-1 and the second mesa portion 71-2. In this example, in the first mesa portion 71-1 and the second mesa portion 71-2, the contact region 15 is formed longer in the X-axis direction than the emitter region 12. The length of the contact region 15 may be at least twice the length of the emitter region 12.

The range in the X-axis direction in which the emitter region 12 of the first mesa portion 71-1 is provided is included in the range in the X-axis direction in which the contact region 15 of the second mesa portion 71-2 is provided. The range in the X-axis direction in which the emitter region 12 of the second mesa portion 71-2 is provided is included in the range in the X-axis direction in which the contact region 15 of the first mesa portion 71-1 is provided. With such a structure, the pulling speed of the carrier can be improved.

FIG. 23 is a diagram showing another arrangement example of the emitter region 12 and the contact region 15 on the upper surfaces of the first mesa portion 71-1 and the second mesa portion 71-2. In this example, in the first mesa portion 71-1 and the second mesa portion 71-2, the emitter region 12 is formed longer than the contact region 15 in the X-axis direction. The length of the emitter region 12 may be at least twice the length of the contact region 15.

The range in the X-axis direction in which the contact region 15 of the first mesa portion 71-1 is provided is included in the range in the X-axis direction in which the emitter region 12 of the second mesa portion 71-2 is provided. The range in the X-axis direction in which the contact region 15 of the second mesa portion 71-2 is provided is included in the range in the X-axis direction in which the emitter region 12 of the first mesa portion 71-1 is provided. With such a structure, the channel density can be improved.

FIG. 24 is a diagram showing an arrangement example of the storage area 16. The storage area 16 of this example has an opening 92 on the XY plane. A drift region 18 may be provided inside the opening 92. The opening 92 may be arranged so as to overlap the contact region 15 in the first mesa portion 71-1 and the second mesa portion 71-2. With such a structure, the carrier can be pulled out in the first mesa part 71-1 and the second mesa part 71-2. The area of the opening 92 on the XY plane may be the same as the area of the contact region 15 or may be small. The area of the opening 92 may be less than half the area of the contact area 15.

FIG. 25 is a diagram showing an example of a manufacturing method of the semiconductor device 100. The semiconductor device 200 may also be manufactured by the same method. In step S250, the base region 14 is formed on the semiconductor substrate 10 provided with the gate trench portion 40 and the dummy trench portion 30. The base region 14 may be formed by injecting a P-type impurity such as boron from the upper surface side of the semiconductor substrate 10.

In step S252, the storage area 16 is formed. The storage region 16 may be formed by injecting an N-type impurity such as phosphorus from the upper surface side of the semiconductor substrate 10 using a mask such as a photoresist.

In step S254, the first well region 13 is formed. The first well region 13 may be formed by injecting a P-type impurity such as boron from the upper surface side of the semiconductor substrate 10 using a mask such as a photoresist. P-type impurities may be injected at different depths in multiple batches by varying the acceleration voltage.

In step S256, the contact region 15 is formed. The contact region 15 may be formed by injecting a P-type impurity such as boron from the upper surface side of the semiconductor substrate 10 using a mask such as a photoresist.

In step S258, the structure on the lower surface side of the semiconductor substrate 10 is formed. For example, the collector region 22 is formed.

In step S260, the semiconductor substrate 10 is annealed under predetermined conditions. As a result, the impurities injected in steps S250 to S258 are made into donors or acceptors to form each region.

In step S262, the emitter region 12 is formed. The emitter region 12 may be formed by injecting N-type impurities such as arsenic from the upper surface side of the semiconductor substrate 10 using a mask such as a photoresist.

In step S264, the semiconductor substrate 10 is annealed under predetermined conditions. As a result, the impurities injected in step S262 are made into donors to form the emitter region 12.

After step S264, an interlayer insulating film 26, a contact hole 54, an emitter electrode 52, and the like are formed. As a result, the semiconductor device 100 can be manufactured.

Note that step S254 may be performed after step S264. In this case, an annealing step may be provided after step S254. In this case, since the number of annealings after forming the first well region 13 can be reduced, the depth of the first well region 13 can be controlled accurately.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that the form with such changes or improvements may be included in the technical scope of the present invention.

The order of execution of each process in the claims, the specification, and the method shown in the drawings is not specified as "before", "prior", etc., and is the result of the previous process. It should be noted that this can be achieved in any order unless is used in a later process. Even if the scope of claims, the specification, and the operation flow in the drawings are explained using "first", "next", etc. for convenience, it means that it is essential to carry out in this order. It's not a thing.

10 ... Semiconductor substrate, 11 ... Second well region, 12 ... Emitter region, 13 ... First well region, 14 ... Base region, 15 ... Contact region, 16 ... Storage region, 17 ... region, 18 ... drift region, 20 ... buffer region, 21 ... top surface, 22 ... collector region, 23 ... bottom surface, 26 ... interlayer insulating film, 28 ... Bottom side region, 30 ... Dummy trench portion, 31 ... Stretched portion, 32 ... Dummy insulating film, 33 ... Tip portion, 34 ... Dummy conductive portion, 35 ... Bottom, 36 ... end, 37 ... second dummy side wall, 38 ... first dummy side wall, 40 ... gate trench part, 41 ... extension part, 42 ... gate insulating film, 43 ... tip part, 44 ... gate conductive part, 45 ... gate wiring, 46 ... gate electrode, 52 ... emitter electrode, 54, 55, 56 ... contact hole, 57 ... -Connection part, 58 ... collector electrode, 71 ... mesa part, 72 ... dummy mesa part, 73 ... recessed part, 74 ... first gate side wall, 75 ... second gate side wall, 92 ... Opening, 100 ... Semiconductor device, 200 ... Semiconductor device

Claims (24)

With a semiconductor substrate,
The first conductive type drift region provided inside the semiconductor substrate and
A plurality of gate trench portions provided from the upper surface of the semiconductor substrate to the drift region, and
A dummy trench portion provided between the two gate trench portions and provided from the upper surface of the semiconductor substrate to the drift region, and a dummy trench portion.
In the region of the semiconductor substrate adjacent to any of the gate trench portions, a second conductive type base region provided between the upper surface of the semiconductor substrate and the drift region, and
In the region of the semiconductor substrate adjacent to the dummy trench portion, a second conductive type first well region provided to a position deeper than the lower end of the dummy trench portion and having a higher doping concentration than the base region,
It is provided with an emitter electrode provided above the semiconductor substrate.
The first well region is a semiconductor device electrically connected to the emitter electrode. Two or more dummy trench portions are provided between the two gate trench portions.
Inside the semiconductor substrate, a dummy mesa portion is formed between the two dummy trench portions.
The semiconductor device according to claim 1, wherein the first well region is provided in the dummy mesa portion. The semiconductor device according to claim 2, wherein the first well region is provided in contact with both of the two dummy trench portions. The semiconductor device according to any one of claims 1 to 3, wherein the first well region covers at least a part of the bottom portion of the dummy trench portion. The dummy trench portion has a first dummy side wall adjacent to the first well region.
The semiconductor device according to claim 4, wherein at least a part of the region between the center in the width direction and the first dummy side wall at the bottom of the dummy trench portion is covered by the first well region. The dummy trench portion has a second dummy side wall opposite to the first dummy side wall.
The semiconductor device according to claim 5, wherein the first well region covers the bottom of the dummy trench portion from the center of the bottom of the dummy trench portion in the width direction to the side of the second dummy side wall. The semiconductor device according to any one of claims 1 to 6, wherein the dummy trench portion and the gate trench portion are formed to the same depth. The semiconductor device according to any one of claims 1 to 6, wherein the dummy trench portion is formed deeper than the gate trench portion. A second conductive type collector region provided between the lower surface of the semiconductor substrate and the drift region,
The semiconductor device according to claim 2 or 3, further comprising a first conductive type lower surface side region provided at the same depth as the collector region in at least a part of the region below the dummy mesa portion. The dummy trench portion has a length and a short side on the upper surface of the semiconductor substrate, and has a length and a short side.
The semiconductor device according to claim 9, wherein the collector region and the lower surface side region are alternately arranged below the dummy mesa portion along the longitudinal direction of the dummy trench portion. In the region adjacent to the gate trench portion inside the semiconductor substrate, a storage region having a higher doping concentration than the drift region is provided.
The semiconductor according to claim 2, wherein the doping concentration of the first conductive type in a region adjacent to the dummy trench portion inside the semiconductor substrate and at the same depth position as the storage region is lower than that in the storage region. Device. In the mesa portion sandwiched between two trench portions, one of which is the gate trench portion, the doping concentration is higher than that of the drift region from the position in contact with the one trench portion to the position in contact with the other trench portion. A storage area is provided,
The semiconductor device according to claim 2, wherein the dummy mesa portion is not provided with the storage area. 13. The semiconductor device described. The gate trench portion has a length and a short side on the upper surface of the semiconductor substrate, and has a length and a short side.
The gate trench portion has a first gate side wall along the longitudinal direction of the gate trench portion inside the semiconductor substrate, and a second gate side wall opposite to the first gate side wall.
Inside the semiconductor substrate, a first mesa portion adjacent to the first gate side wall of the gate trench portion and a second mesa portion adjacent to the second gate side wall of the gate trench portion are provided.
The first conductive type emitter region and the second conductive type contact region are alternately exposed along the longitudinal direction of the gate trench portion on the upper surfaces of the first mesa portion and the second mesa portion. Placed,
13. Semiconductor device. Further, a first conductive type emitter region provided on the upper surface of the semiconductor substrate adjacent to the gate trench portion is provided.
The semiconductor device according to any one of claims 1 to 13 , wherein the contact width of the contact formed on the first well region is larger than the contact width of the contact formed on the emitter region. The contact width of the contact formed on the first well region is larger than the contact width of the contact formed on the emitter region.
The semiconductor device according to claim 14. The semiconductor device according to claim 2 , wherein the mesa width of the dummy mesa portion is larger than the mesa width of the mesa portion sandwiched between two trench portions, one of which is the gate trench portion. In the dummy mesa portion, an accumulation region having a higher doping concentration than the drift region is provided.
The semiconductor device according to claim 2, wherein the storage region is sandwiched between the first well regions in the depth direction of the semiconductor substrate, and upper and lower ends of the storage region are in contact with the first well region. The semiconductor device according to any one of claims 1 to 18 , wherein the film thickness of the dummy insulating film in the dummy trench portion is thicker than the film thickness of the gate insulating film in the gate trench portion. The semiconductor device according to claim 14, wherein at least a part of at least one of the contact regions in the first mesa portion is arranged at a position facing the emitter region in the second mesa portion. The semiconductor device according to claim 14 or 20 , wherein in the first mesa portion, the emitter region is formed longer than the contact region in the longitudinal direction of the gate trench portion. The semiconductor device according to claim 14 or 20 , wherein in the first mesa portion, the contact region is formed longer in the longitudinal direction of the gate trench portion than the emitter region. The semiconductor device according to claim 14 or 20 , wherein in the first mesa portion, the lengths of the emitter region and the contact region in the longitudinal direction of the gate trench portion are the same. Any of claims 14 or 20 to 23 , wherein in the first mesa portion, a trench portion extending in the lateral direction of the gate trench portion is not formed in the region where the emitter region or the contact region is formed. The semiconductor device according to paragraph 1.

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