CN116577643A - Automatic testing system and method for semiconductor chip - Google Patents
Automatic testing system and method for semiconductor chip Download PDFInfo
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- CN116577643A CN116577643A CN202310842069.8A CN202310842069A CN116577643A CN 116577643 A CN116577643 A CN 116577643A CN 202310842069 A CN202310842069 A CN 202310842069A CN 116577643 A CN116577643 A CN 116577643A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 204
- 238000012360 testing method Methods 0.000 title claims abstract description 114
- 238000000034 method Methods 0.000 title claims abstract description 9
- 230000007246 mechanism Effects 0.000 claims abstract description 45
- 238000005286 illumination Methods 0.000 claims abstract description 42
- 230000001105 regulatory effect Effects 0.000 claims description 31
- 230000001276 controlling effect Effects 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 9
- 238000004088 simulation Methods 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 3
- 230000005855 radiation Effects 0.000 claims description 3
- 238000010998 test method Methods 0.000 claims description 2
- 230000006872 improvement Effects 0.000 description 8
- 206010034972 Photosensitivity reaction Diseases 0.000 description 5
- 230000036211 photosensitivity Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000000523 sample Substances 0.000 description 4
- 206010057040 Temperature intolerance Diseases 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008543 heat sensitivity Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008542 thermal sensitivity Effects 0.000 description 2
- 206010034960 Photophobia Diseases 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 208000013469 light sensitivity Diseases 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
- G01R31/2875—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to heating
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2881—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to environmental aspects other than temperature, e.g. humidity or vibrations
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Abstract
The invention relates to the technical field of semiconductor chip testing, in particular to an automatic testing system and method for semiconductor chips. The test control mechanism comprises a test bench and a test control mechanism arranged on the test bench, wherein a photosensitive component is arranged above the test bench, a thermosensitive component is further arranged on the test bench, the photosensitive component and the thermosensitive component are both used for simulating application environments for semiconductor chips, a state regulation component is arranged between the test bench and the photosensitive component, a positioning mechanism is arranged below the state regulation component and used for controlling the semiconductor chips to be in different temperature environments, and the test mechanism is arranged on the test bench. The invention controls the intensity and the range of the irradiation light of the irradiation hole through the outer regulation plate and the inner regulation plate, so that the semiconductor chip is in different illumination states and temperature states, thereby simulating the specific states of the semiconductor chip in different application environments.
Description
Technical Field
The invention relates to the technical field of semiconductor chip testing, in particular to an automatic testing system and method for semiconductor chips.
Background
In the manufacture of semiconductor chips, electrical performance of the semiconductor chips needs to be tested by a testing mechanism, and current testing methods are usually implemented by using probes to contact the semiconductor chips.
Chinese patent publication No. CN215768881U discloses a semiconductor chip conductive test bench, including platen and the support frame of setting in the platen bottom, still include: the stabilizing component is arranged on the bedplate and used for fixing the semiconductor chip to be tested; the light-shielding control temperature component is covered at the top of the stable component and is used for providing constant temperature and light-shielding testing environments for the semiconductor chip to be tested.
Because the semiconductor chip has the specificity of heat sensitivity and photosensitivity, the conduction performance of the semiconductor chip under the condition that the semiconductor chip is not in the state of illumination and temperature abnormality can be tested through the scheme, but the applied scene and environment of the semiconductor chip are wider, and when the semiconductor chip is applied to some special or extreme environments, such as the influence of illumination and temperature, the conduction performance of the semiconductor chip under the environment can not be obtained by adopting the technical scheme.
Disclosure of Invention
The invention aims to provide an automatic test system and method for semiconductor chips, which are used for solving the problems in the background technology.
In order to achieve the above object, one of the objects of the present invention is to provide an automated test system for semiconductor chips, comprising a base and a test control mechanism mounted on the base, wherein the test control mechanism comprises a test bench for receiving semiconductor chips, a photosensitive component for simulating illumination conditions is disposed above the test bench, a thermal component for simulating temperature conditions is further disposed on the test bench, the photosensitive component and the thermal component are both used for simulating application environments for the semiconductor chips, a state control component for controlling the semiconductor chips to receive different illumination ranges is disposed between the test bench and the photosensitive component, a positioning mechanism is mounted below the state control component, and the positioning mechanism is used for controlling the semiconductor chips to be in different temperature environments, wherein:
the state control assembly and the positioning mechanism are used for controlling illumination and temperature to simulate states of the semiconductor chip in different application environments, and the test mechanism for testing the semiconductor chip in different environments is further arranged on the base station.
By placing the semiconductor chip in the test bench, since the semiconductor chip has a certain photosensitivity, it is therefore: the light-sensitive component is started, the state regulation and control component regulates and controls the illumination state of the light-sensitive component, the condition of different illumination intensities of the semiconductor chip under the light-sensitive component is simulated, then the semiconductor chip is subjected to contact test through the test mechanism, and the electrical performance of the semiconductor chip under the environment is accurately tested; since the semiconductor chip has a certain thermal sensitivity, it is: the temperature sensing assembly is started, the positioning mechanism controls the semiconductor chip to be in different temperature states, so that the semiconductor chip is heated to different degrees, then the semiconductor chip is tested by the testing mechanism, the electrical performance of the semiconductor chip in the environment can be tested, and the photosensitivity and the thermosensitive independent test of the semiconductor chip are realized; the semiconductor chip is controlled to be in different illumination intensities at a set temperature through the photosensitive component and the thermosensitive component, bidirectional simulation of illumination and temperature is realized, and the test mechanism is used for testing the electrical performance of the semiconductor chip, so that the specific state of the electrical performance of the semiconductor chip in the practical application process is conveniently tested.
As a further improvement of the technical scheme, the state regulation and control assembly comprises a plurality of support plates, wherein fixing plates are arranged on the support plates, an outer regulation and control disc and an inner regulation and control disc are arranged at the central positions of the plurality of fixing plates, one fixing plate is rotationally connected with the outer regulation and control disc, irradiation holes for enabling light to pass through are formed in the outer regulation and control disc and the inner regulation and control disc, and the state that the semiconductor chip is subjected to different light intensity is regulated and controlled through the outer regulation and control disc and the inner regulation and control disc.
As the further improvement of this technical scheme, interior regulation and control dish rotates the inside that sets up at outer regulation and control dish, and interior regulation and control dish passes through the motor drive of positioning, wherein, when photosensitive assembly opens, include the following state:
half way environment: the irradiation holes of the inner control disc are controlled to be incompletely corresponding to the irradiation holes on the outer control disc through rotation of the inner control disc, and application environments when the surface of the semiconductor chip is subjected to different illumination states are simulated;
local path environment: the irradiation holes of the inner control disc are controlled not to correspond to the irradiation holes on the outer control disc through rotation of the inner control disc, and the application environment of the semiconductor chip in the local illumination state is simulated.
As a further improvement of the technical scheme, when the thermosensitive assembly is opened:
and simulating the thermosensitive environment of the semiconductor chip in the state according to the half-way environment and the local path environment. The semiconductor chip is heated by the thermosensitive assembly in the semi-directional passage environment and the local passage environment respectively so as to simulate the state of the semiconductor chip when the semiconductor chip is influenced by temperature in the semi-directional passage environment or the local passage environment, and the testing mechanism performs the testing operation of the electrical performance of the semiconductor chip.
As a further improvement of the technical scheme, the photosensitive assembly comprises a positioning plate rotatably mounted on the supporting plate, the positioning plate is driven by a fixed motor, and the positioning restriction is carried out on the semiconductor chip by the positioning plate.
As a further improvement of the technical scheme, the test bench is provided with a limiting groove for enabling the positioning plate to slide, and when the positioning plate gradually rotates to leave the limiting groove, the positioning plate lifts the semiconductor chip off the surface of the test bench to simulate the non-contact heated state of the semiconductor chip.
As a further improvement of the technical scheme, the bottom surface of the fixing plate is provided with a fixing part, the fixing part is connected with a positioning arm, the positioning arm is connected with an outer positioning arm in a sliding manner, the outer positioning arm is connected with the positioning arm through an elastic piece, and the outer positioning arm is used for positioning the semiconductor chip.
As a further improvement of the technical scheme, when the positioning plate lifts the semiconductor chip, the positioning plate forms partial blocking on the bottom of the semiconductor chip, so that the semiconductor chip is in a partial heated state.
As a further improvement of the technical scheme, when the positioning plate controls the semiconductor chip to be in a horizontal state, the distance between the semiconductor chip and the irradiation hole is changed, and the application environment of the semiconductor chip surface under multi-point illumination is simulated.
Another object of the present invention is to provide a testing method generated by the automated testing system for semiconductor chips, comprising the following steps:
step one: the outer regulating disc is controlled to be in an opened state through the fixing plate, so that the semiconductor chip is placed in the test bench;
step two: the photosensitive component and the thermosensitive component are used for running, the outer regulating and controlling disc and the inner regulating and controlling disc are in different connection states, so that light rays can show different illumination radiation through illuminating Kong Duiban semiconductor chips, and the thermosensitive component is used for applying a heated environment to the semiconductor chips so as to simulate the conditions of the semiconductor chips in different application environments;
step three: according to the condition of the semiconductor chip under the application environment, the test mechanism is used for testing the electrical performance of the semiconductor chip.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the automatic testing system and the automatic testing method for the semiconductor chip, the intensity and the range of irradiation light rays of the irradiation holes are controlled through the outer regulation disc and the inner regulation disc, so that the semiconductor chip is in different illumination states and temperature states, the specific states of the semiconductor chip in different application environments are simulated, the semiconductor chip is tested in the environments, and the heat sensitivity and the light sensitivity of the semiconductor chip in different application environments can be accurately tested.
2. In the automatic testing system and method for the semiconductor chip, when the semiconductor chip is positioned by the positioning plate, the semiconductor chip is controlled to be in a non-contact heated state between the thermosensitive components, the application environment of the semiconductor chip under the non-contact condition of a heat source is simulated, and the accurate conductivity test is carried out on the semiconductor chip.
3. According to the automatic test system and the automatic test method for the semiconductor chip, the semiconductor chip is close to the outer regulation disc and the inner regulation disc, so that the semiconductor chip is in an application environment under local single-point illumination, and the illumination intensity of the semiconductor chip is increased at the moment, so that the situation when the semiconductor chip is locally subjected to single-point illumination is simulated.
Drawings
FIG. 1 is a schematic diagram of the overall structure of the present invention;
FIG. 2 is a second schematic diagram of the overall structure of the present invention;
FIG. 3 is a top view of the test control mechanism of the present invention;
FIG. 4 is a schematic diagram of a test control mechanism according to the present invention;
FIG. 5 is a schematic view of the structure of FIG. 1A according to the present invention;
FIG. 6 is a schematic diagram of an outer tuning pad according to the present invention;
fig. 7 is a front view of the test control mechanism of the present invention.
The meaning of each reference sign in the figure is:
10. a base station;
20. a test control mechanism;
210. a test bench; 211. a limiting groove;
220. a photosensitive component; 221. a bracket; 222. a lamp holder;
230. a heat sensitive component;
240. a status regulating component; 241. an outer regulation plate; 242. an inner regulating plate; 243. an irradiation hole; 244. a support plate; 245. a fixing plate; 246. a drive motor; 247. a position-adjusting motor; 248. a receiving plate;
250. a positioning mechanism; 251. a positioning plate; 252. a fixing part; 253. an inner positioning arm; 254. an outer positioning arm;
30. a testing mechanism;
310. a testing machine; 320. and (3) a probe.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 1-7, the present embodiment provides an automated semiconductor chip testing system, which includes a base 10 and a testing control mechanism 20 mounted on the base 10, wherein the testing control mechanism 20 includes a testing table 210 for receiving a semiconductor chip, a photosensitive component 220 for simulating an illumination state is disposed above the testing table 210, a thermal component 230 for simulating a temperature state is further disposed on the testing table 210, the photosensitive component 220 and the thermal component 230 are both used for simulating an application environment for the semiconductor chip, a state regulation component 240 for controlling the semiconductor chip to receive different illumination ranges is disposed between the testing table 210 and the photosensitive component 220, a positioning mechanism 250 is mounted below the state regulation component 240, and the positioning mechanism 250 is used for controlling the semiconductor chip to be in different temperature environments, wherein:
the state control assembly 240 and the positioning mechanism 250 are used for controlling illumination and temperature to simulate states of the semiconductor chip under different application environments, and the test mechanism 30 for testing the semiconductor chip under different environments is also arranged on the base station 10; in this embodiment, the semiconductor chip is placed in the test bench 210, and thus the semiconductor chip has a certain photosensitivity: by starting the photosensitive assembly 220, regulating the illumination state of the photosensitive assembly 220 by the state regulating assembly 240, simulating the conditions of different illumination intensities of the semiconductor chip under the photosensitive assembly 220, then performing contact test on the semiconductor chip by the test mechanism 30, analyzing whether the resistivity of the semiconductor chip is changed and the degree of change caused by the irradiation of light with specific wavelength when the semiconductor chip is illuminated, and accurately testing the electrical performance of the semiconductor chip under the environment;
since the semiconductor chip has a certain thermal sensitivity, it is: the temperature sensing assembly 230 is started, the positioning mechanism 250 controls the semiconductor chip to be in different temperature states, so that the semiconductor chip is heated to different degrees, then the semiconductor chip is tested by the testing mechanism 30, whether the resistivity of the semiconductor chip changes and the degree of the change are analyzed when the semiconductor chip is affected by the temperature, and the independent testing of the photosensitivity and the thermosensitive property of the semiconductor chip is realized;
the photosensitive component 220 and the thermosensitive component 230 are simultaneously started, the semiconductor chip is controlled to be in different illumination intensities at a given temperature by the state regulating component 240, the bidirectional simulation of illumination and temperature is realized, and the test mechanism 30 is used for testing the electrical performance of the semiconductor chip, so that the specific state of the electrical performance of the semiconductor chip in the actual application process is conveniently tested.
Based on the above technical scheme, the scheme is explained in detail as follows:
the state regulating assembly 240 comprises a plurality of supporting plates 244, a fixed plate 245 is arranged on the supporting plates 244, an outer regulating plate 241 and an inner regulating plate 242 are arranged in the center of the plurality of fixed plates 245, one fixed plate 245 is rotationally connected with the outer regulating plate 241, irradiation holes 243 for allowing light to pass through are formed in the outer regulating plate 241 and the inner regulating plate 242, and the state of the semiconductor chip under different light intensity is regulated by the outer regulating plate 241 and the inner regulating plate 242; the fixing plate 245 rotationally connected with the outer regulation and control disc 241 is driven by the transmission motor 246, when a semiconductor chip is placed, the fixing plate 245 is controlled by the transmission motor 246 to rotate upwards, so that the fixing plate 245 controls the outer regulation and control disc 241 and the inner regulation and control disc 242 to turn upwards and away from the test board 210, the semiconductor chip can be placed in the test board 210 at the moment, then the outer regulation and control disc 241 and the inner regulation and control disc 242 are reset, the inner regulation and control disc 242 is in a disc structure, therefore, light rays emitted by the photosensitive assemblies 220 can be irradiated onto the semiconductor chip through the irradiation holes 243 in a one-to-one correspondence manner, and then the semiconductor chip can be contacted with the test mechanism 30 to form a convenient environment test.
According to the above: the inner regulating disc 242 is rotatably disposed inside the outer regulating disc 241, and the inner regulating disc 242 is driven by the positioning motor 247, wherein when the photosensitive assembly 220 is turned on, the following states are included:
half way environment: the irradiation holes 243 of the inner control disc 242 are controlled to be incompletely corresponding to the irradiation holes 243 on the outer control disc 241, so that the application environment when the surface of the semiconductor chip is in different illumination states is simulated, the incompletely corresponding means that only half of the irradiation holes 243 on the inner control disc 242 and the irradiation holes 243 on the outer control disc 241 can pass through the hole paths of light rays, but the outer control disc 241 is of a half ring structure, at the moment, the part of the inner control disc 242 far away from the irradiation holes 243 on the outer control disc 241 is not influenced, at the moment, the area of the surface of the semiconductor chip affected by illumination is different, and the electric performance of the semiconductor chip in use under the application environment is simulated;
local path environment: the irradiation holes 243 of the inner control disc 242 are controlled not to correspond to the irradiation holes 243 on the outer control disc 241 in a rotating manner, so that the application environment of the semiconductor chip in a local illumination state is simulated, and the irradiation holes 243 on the outer control disc 241 and the inner control disc 242 are in a mutually blocking and sealing state, so that the surface of the semiconductor chip only has light rays irradiated by the irradiation holes 243 on the local inner control disc 242, the application environment of the surface of the semiconductor chip only influenced by illumination of a half area is simulated, and the electrical performance test of the semiconductor chip in different application environments is realized through the test mechanism 30;
wherein, the fixed plates 245 which are not connected with the outer regulation and control disc 241 in a rotating way are all provided with a bearing plate 248 for bearing the outer regulation and control disc 241, thus improving the stability of the outer regulation and control disc 241 and the inner regulation and control disc 242 when in use.
Then, when the thermosensitive assembly 230 is turned on:
according to the above-described half-way environment and partial-way environment, the thermal environment of the semiconductor chip in this state is simulated, and the semiconductor chip is heated by the thermal module 230 in the half-way environment and partial-way environment, respectively, so as to simulate the state of the semiconductor chip when the semiconductor chip is affected by temperature in the half-way environment or partial-way environment, and thus the test operation of the electrical performance of the semiconductor chip is performed by the test mechanism 30. The thermal sensitive component 230 can adopt an electrothermal tube structure, and can generate heat energy through the electrothermal tube to perform heat treatment on the semiconductor chip, and can avoid damage to the semiconductor chip caused by the electrothermal tube in a high-temperature state by controlling the heating temperature of the electrothermal tube.
The light-sensitive assembly 220 includes a positioning plate 251 rotatably mounted on the support plate 244, and the positioning plate 251 is driven by a fixed motor, and positions and limits the semiconductor chip by the positioning plate 251, and the light-sensitive assembly 220 includes a bracket 221 mounted on the support plate 244, and one end of the bracket 221 is connected with a lamp holder 222, and the lamp holder 222 emits light to irradiate the semiconductor chip, and simulates the condition that the semiconductor chip is irradiated by light, and the positioning plate 251 is driven to rotate by the fixed motor, so that the positioning plate 251 positions and limits the semiconductor chip, and thus the semiconductor chip can be accurately tested for electrical properties.
Example 2
The test bench 210 is provided with a limiting groove 211 for sliding the positioning plate 251, when the positioning plate 251 gradually rotates away from the limiting groove 211, the positioning plate 251 lifts the semiconductor chip off the surface of the test bench 210, and simulates the non-contact heating state of the semiconductor chip, at this time, the semiconductor chip is converted from direct heating to indirect heating, so that the heating state of the semiconductor chip under a close heat source can be simulated, the environment is non-contact heating, and the simulated application environment is different from the above, so that the situation of the semiconductor chip under different environments can be accurately simulated.
Wherein, the bottom surface of the fixing plate 245 is provided with a fixing part 252, the fixing part 252 is connected with a positioning arm 253, the positioning arm 253 is connected with an outer positioning arm 254 in a sliding way, the outer positioning arm 254 is connected with the positioning arm 253 through an elastic piece, and the outer positioning arm 254 is used for positioning the semiconductor chip; the elastic member may be an elastic element such as a spring or an elastic sheet, and when the positioning plate 251 lifts the semiconductor chip, the positioning plate 251 does not limit the semiconductor chip, so that the outer positioning arm 254 and the inner positioning arm 253 gradually rotate horizontally to position and clamp the semiconductor chip on the positioning plate 251 along with the positioning plate 251 being in a state of being prone to horizontally pressing the outer positioning arm 254, so that the semiconductor chip can be accurately tested in electrical performance.
Example 3
When the positioning plate 251 lifts the semiconductor chip, the positioning plate 251 forms a local barrier on the bottom of the semiconductor chip, so that the semiconductor chip is in a local heated state, the bottom of the semiconductor chip is formed into a local barrier through the positioning plate 251, the heated state of the semiconductor chip when blocked by other devices is simulated, the difference characteristic with the semiconductor chip when heated comprehensively can be tested through the local heating of the semiconductor chip, and the subsequent study and analysis of the electrical performance of the semiconductor chip are facilitated.
Example 4
When the positioning plate 251 controls the semiconductor chip to be in a horizontal state, the distance between the semiconductor chip and the irradiation hole 243 is changed, the application environment of multi-point illumination on the surface of the semiconductor chip is simulated, when the semiconductor chip is far away from the irradiation hole 243, light rays are irradiated on the surface of the semiconductor chip through the irradiation hole 243 and spread, and the semiconductor chip is in a comprehensive irradiation state; according to the above, when the semiconductor chip is closer to the irradiation hole 243, the diffusion degree of the light irradiated on the surface of the semiconductor chip through the irradiation hole 243 is reduced, and the irradiation intensity is increased, so that the state of the semiconductor chip surface irradiated by the single point of light and having a certain irradiation intensity can be simulated, and the semiconductor chip is tested for electrical performance in this state; the test mechanism 30 includes a test body 310 mounted on the base 10, and the test body 310 is connected with a probe 320 through a wire, and the probe 320 is in direct contact with the semiconductor chip to perform a test of electrical performance.
The second object of the present invention is to provide a testing method generated by an automated testing system for semiconductor chips, comprising the following steps:
step one: the outer regulation plate 241 is controlled to be in an opened state by the fixing plate 245, so that the semiconductor chip is placed in the test bench 210;
step two: the photosensitive assembly 220 and the thermosensitive assembly 230 are operated, the outer regulating disc 241 and the inner regulating disc 242 are in different connection states, so that light rays can present different illumination radiation to the semiconductor chip through the illumination holes 243, and the thermosensitive assembly 230 is used for applying a heated environment to the semiconductor chip to simulate the conditions of the semiconductor chip under different application environments;
step three: the test mechanism 30 is used to test the electrical performance of the semiconductor chip, depending on the condition of the semiconductor chip in the above application environment.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments, and that the above-described embodiments and descriptions are only preferred embodiments of the present invention, and are not intended to limit the invention, and that various changes and modifications may be made therein without departing from the spirit and scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. The utility model provides an automatic test system of semiconductor chip, includes base station (10) and installs test control mechanism (20) on base station (10), test control mechanism (20) are including being used for accepting test bench (210) of semiconductor chip, the top of test bench (210) is provided with photosensitive assembly (220) of simulation illumination state, still be provided with on test bench (210) and be used for the thermal subassembly (230) of simulation temperature state, photosensitive assembly (220) and thermal subassembly (230) all are used for the semiconductor chip simulation application environment, its characterized in that: a state regulation and control component (240) for controlling the semiconductor chip to receive different illumination ranges is arranged between the test bench (210) and the photosensitive component (220), a positioning mechanism (250) is arranged below the state regulation and control component (240), and the positioning mechanism (250) is used for controlling the semiconductor chip to be in different temperature environments, wherein:
the state control assembly (240) and the positioning mechanism (250) are used for controlling illumination and temperature to simulate states of the semiconductor chip in different application environments, and the base station (10) is also provided with a testing mechanism (30) for testing the semiconductor chip in different environments.
2. The automated semiconductor chip testing system of claim 1, wherein: the state regulation and control assembly (240) comprises a plurality of support plates (244), wherein fixing plates (245) are arranged on the support plates (244), an outer regulation and control disc (241) and an inner regulation and control disc (242) are arranged at the central positions of the plurality of fixing plates (245), one fixing plate (245) is rotationally connected with the outer regulation and control disc (241), irradiation holes (243) for enabling illumination to pass through are formed in the outer regulation and control disc (241) and the inner regulation and control disc (242), and the states of the semiconductor chips, which are different in illumination intensity, are regulated and controlled through the outer regulation and control disc (241) and the inner regulation and control disc (242).
3. The automated semiconductor chip testing system of claim 2, wherein: the inner regulating disc (242) is rotatably arranged in the outer regulating disc (241), and the inner regulating disc (242) is driven by a positioning motor (247), wherein when the photosensitive assembly (220) is started, the inner regulating disc comprises the following states:
half way environment: the irradiation holes (243) of the inner control disc (242) are controlled to be incompletely corresponding to the irradiation holes (243) on the outer control disc (241) through rotation of the inner control disc, and the application environment when the surface of the semiconductor chip is subjected to different illumination states is simulated;
local path environment: the irradiation holes (243) of the inner control disc (242) are controlled not to correspond to the irradiation holes (243) on the outer control disc (241) through rotation of the inner control disc, and the application environment of the semiconductor chip in the local illumination state is simulated.
4. The automated semiconductor chip testing system of claim 3, wherein: -when the heat sensitive assembly (230) is open:
and simulating the thermosensitive environment of the semiconductor chip in the state according to the half-way environment and the local path environment.
5. The automated semiconductor chip testing system of claim 2, wherein: the photosensitive assembly (220) comprises a positioning plate (251) rotatably mounted on the support plate (244), and the positioning plate (251) is driven by a fixed motor to perform positioning restriction on the semiconductor chip by the positioning plate (251).
6. The automated semiconductor chip testing system of claim 5, wherein: the test bench (210) is provided with a limiting groove (211) for enabling the locating plate (251) to slide, and when the locating plate (251) gradually rotates to leave the limiting groove (211), the locating plate (251) lifts the semiconductor chip off the surface of the test bench (210) to simulate the non-contact heated state of the semiconductor chip.
7. The automated semiconductor chip testing system of claim 6, wherein: the bottom surface of fixed plate (245) is installed fixed part (252), and is connected with interior position arm (253) on fixed part (252), interior position arm (253) is last to be connected with outer positioning arm (254), is connected through the elastic component between outer positioning arm (254) and the interior positioning arm (253), and outer positioning arm (254) are used for carrying out the location to the semiconductor chip.
8. The automated semiconductor chip testing system of claim 7, wherein: when the positioning plate (251) lifts the semiconductor chip, the positioning plate (251) forms a local barrier to the bottom of the semiconductor chip, so that the semiconductor chip is in a local heated state.
9. The automated semiconductor chip testing system of claim 7, wherein: when the positioning plate (251) controls the semiconductor chip to be in a horizontal state, the space between the semiconductor chip and the irradiation hole (243) is changed, and the application environment of the semiconductor chip surface under multi-point illumination is simulated.
10. A test method generated by the automated test system for semiconductor chips according to any one of claims 2-9, wherein: the method comprises the following steps:
step one: the outer regulating disc (241) is controlled to be in an opened state through the fixing plate (245), so that the semiconductor chip is placed in the test table (210);
step two: the photosensitive assembly (220) and the thermosensitive assembly (230) are operated, the outer regulating disc (241) and the inner regulating disc (242) are in different connection states, so that light rays can present different illumination radiation to the semiconductor chip through the illumination holes (243), and the thermosensitive assembly (230) is used for applying a heating environment to the semiconductor chip to simulate the situation of the semiconductor chip under different application environments;
step three: the semiconductor chip is tested for electrical properties with a test mechanism (30) depending on the situation of the semiconductor chip in the application environment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310842069.8A CN116577643B (en) | 2023-07-11 | 2023-07-11 | Automatic testing system and method for semiconductor chip |
Applications Claiming Priority (1)
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106847722A (en) * | 2016-12-26 | 2017-06-13 | 东莞市蓉工自动化科技有限公司 | A kind of full-automatic detector of semiconductor chip |
| CN111751708A (en) * | 2020-06-29 | 2020-10-09 | 苏州猎奇智能设备有限公司 | Chip temperature control test bench and temperature control test method thereof |
| CN214953943U (en) * | 2021-06-28 | 2021-11-30 | 厦门欣艾博电力科技有限公司 | Semiconductor chip test bench |
| CN215575532U (en) * | 2021-09-23 | 2022-01-18 | 广东宝驰电子科技有限公司 | Automatic aging test system |
| CN215768881U (en) * | 2021-08-10 | 2022-02-08 | 徐州汉通电子科技有限公司 | Conductive test bench for semiconductor chip |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106847722A (en) * | 2016-12-26 | 2017-06-13 | 东莞市蓉工自动化科技有限公司 | A kind of full-automatic detector of semiconductor chip |
| CN111751708A (en) * | 2020-06-29 | 2020-10-09 | 苏州猎奇智能设备有限公司 | Chip temperature control test bench and temperature control test method thereof |
| CN214953943U (en) * | 2021-06-28 | 2021-11-30 | 厦门欣艾博电力科技有限公司 | Semiconductor chip test bench |
| CN215768881U (en) * | 2021-08-10 | 2022-02-08 | 徐州汉通电子科技有限公司 | Conductive test bench for semiconductor chip |
| CN215575532U (en) * | 2021-09-23 | 2022-01-18 | 广东宝驰电子科技有限公司 | Automatic aging test system |
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