CN116523012A - Memristor self-learning circuit based on generation countermeasure neural network - Google Patents
Memristor self-learning circuit based on generation countermeasure neural network Download PDFInfo
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Abstract
The invention discloses a memristor self-learning circuit based on a generation countermeasure neural network, which is formed by combining a discrimination network circuit and a generation network circuit, wherein the discrimination network circuit and the generation network circuit both comprise an input layer, an error calculation layer and a self-learning signal release layer. The judging network circuit carries out self-learning under the guidance of a correct sample, and the generating network circuit realizes self-learning under the competition game of the self-output voltage and the output voltage of the judging network circuit. The specific cases are as follows: the output voltage of the judging network circuit gradually approaches to the correct sample value in the self-learning process, and when the difference value between the output voltage of the judging network circuit and the correct sample is smaller than the acceptable error value, the self-learning of the judging network circuit is finished; meanwhile, the generating network circuit and the judging network circuit perform competition game, the output voltage of the generating network circuit gradually approaches to the output voltage of the judging network circuit, and when the difference value of the two voltages is smaller than the acceptable error value, the generating network circuit stops self-learning.
Description
Technical Field
The invention relates to the field of memristor self-learning circuit design, in particular to a memristor self-learning circuit based on an antagonistic neural network.
Background
As the most complex and efficient information processing system at present, the information processing manner of the biological neural network is widely studied, and the implementation of an artificial neural network by constructing a mathematical model based on the principle of the biological neural network is gradually becoming a big research hotspot.
The implementation of the artificial neural network can be divided into two modes of software and hardware, and although the software implementation is still a main mode of the artificial neural network at present, with the increase of data explosion, the problem of a storage wall existing in the traditional von neumann computer architecture severely limits the information processing speed of the artificial neural network. Therefore, the realization of the artificial neural network by the hardware circuit becomes a feasible path.
Similar to the structure of the front and rear neurons in the biological neural network connected by synapses, the variable connection weights in the artificial neural network correspond to the changes in the synaptic weights in the biological neural network.
As a fourth basic electronic element in circuit theory, memristors with resistance plasticity have become core elements for hardware circuit implementation in artificial neural networks. The resistance plasticity of the memristor means that the resistance of the memristor changes when a specific external electric field is applied to the memristor; in addition, the memristor has directivity in resistance plasticity, that is, the applied electric field with opposite directions can generate opposite resistance change results. This property of memristors well embodies the plasticity of biological synaptic weights, so memristors will play a significant role in the hardware circuit implementation of artificial neural networks.
Besides the biological synapse-like property, the memristor has the advantages of low power consumption, nano size, compatibility with MOS tubes and the like, and the advantages enable research of adopting the memristor to realize an artificial neural network hardware circuit to have good development prospect.
Currently, generating an antagonistic neural network is a deep learning model that generates a more desirable output through competing game-type learning rules between an internal generation network and a discrimination network. The generation of the countermeasure neural network mainly comprises a generation network and a discrimination network, wherein the input of the discrimination network is a correct sample, and the input of the generation network is noise. The discrimination network can output the correct sample through learning, and can also use the correct sample as a competing object to prompt the generation network to continuously learn and improve the similarity between the output of the generation network and the correct sample.
With the development of memristors, memristor neural network self-learning circuits have been widely studied, but most memristor self-learning circuits are based on a software-hardware combination method at present, which means that the self-learning speed of the designed circuit is limited by a von neumann architecture, so that the energy consumption is larger and the speed is slower. Based on the memristor resistance plasticity, the invention provides a memristor self-learning circuit based on the generation of an antagonistic neural network, and the circuit adopts a method realized by a full hardware circuit, which is beneficial to solving the problems of high energy consumption, low speed and the like in the prior research. Based on the competition game type learning rule between the generation network and the discrimination network in the circuit, the full-hardware memristor self-learning circuit provided by the invention can improve the self-learning accuracy in a shorter time.
Disclosure of Invention
The generation of the countermeasure neural network is a neural network employing unsupervised learning, which completes self-learning through a game between an internal generation network and a discrimination network.
Based on the competition game type learning rule for generating the countermeasure neural network, the invention provides a memristor self-learning circuit based on generating the countermeasure neural network. The memristor self-learning circuit is built by using the resistance plasticity of the memristor of the novel two-end device, and the generation of the countermeasure neural network is realized, so that the accuracy of the self-learning of the circuit is improved by generating a game learning algorithm of the countermeasure neural network.
The invention is realized by the following technical scheme: a memristor self-learning circuit based on a generation countermeasure neural network comprises a discrimination network circuit module and a generation network circuit module. The judging network circuit module and the generating network circuit module are composed of an input layer, an error calculation layer and a self-learning signal release layer. The judging network circuit module can output an output signal which is infinitely close to the correct sample value under the guidance of the correct sample after receiving the external input; judging the output signal of the network circuit module to be used as a game object for generating the network circuit module, and gradually approaching to a correct sample value infinitely under the competition game learning rule.
In the discrimination network circuit, the input layer is formed by a switch G D1 -G Dm Memristor M 11 -M m1 And M 12 -M m2 Two summing circuits and one differencing circuit. The two summing circuits are respectively composed of an operational amplifier A1 and a resistor R8, and an operational amplifier A2 and a resistor R9; the difference circuit is composed of an operational amplifier A3 and resistors R10-R13. Switch G Dn From NMOS tube N Dn And PMOS tube P Dn Constitution, N Dn Source electrode and P of (2) Dn Is connected with the drain electrode of the switch and is used as the output end of the switch, N Dn And P Dn Is connected to the voltage Vc and is used to control N Dn And P Dn Is turned on. External input signal V D1 -V Dm Respectively with switch G D1 -G Dm Middle PMOS tube P D1 -P Dm Is connected with the source electrode of the self-learning signal V DL Respectively with switch G D1 -G Dm Middle NMOS tube N D1 -N Dm Is connected with the drain electrode of the transistor; switch G Dn Respectively with memristor M n2 Positive electrode of (a) and memristor M n1 Is connected to the negative electrode of the battery. Wherein, in the first half period of Vc, switch G Dn PMOS tube P in Dn Is turned on and externally inputs a signal V D1 -V Dm Through memristor M 12 -M m2 Converted into a current signal and connected to the inverting input end of the operational amplifier A1, the summation circuit taking A1 as the main body sums the input current signal and converts the total current into voltage and then passes through the output end of A1And outputting. Similarly, an external input signal V D1 -V Dm Through memristor M 11 -M m1 The current signal is converted into a current signal and is connected to the inverting input end of the operational amplifier A2, the summation circuit taking A2 as a main body sums the input current signal, and the total current is converted into voltage and is output through the output end of A2. The difference solving circuit taking A3 as a main body solves the difference between the outputs of A1 and A2 to obtain voltage output, and the voltage output is an output signal for judging an input layer in the network circuit.
In the discrimination network circuit, the error calculation layer consists of a sample holder LF398a and a correct sample V T And a difference circuit composed of a resistor R 14 -R 17 And an operational amplifier A4. The logic control signal of LF398a is composed of digital periodic signal V DI Providing, wherein V DI Is composed of high and low levels each taking 10 ms. LF398a will sample the output of operational amplifier A3, and the sampled signal from LF398a is regarded as the output signal V of the discrimination network circuit D . Then V is arranged D The correct sample V is connected to the inverting input end of the difference solving circuit A4 T Is connected to the non-inverting input terminal of the difference circuit A4. In this case, the difference circuit A4 can calculate the output of LF398a and the correct sample V T And outputs the difference as a learning error signal E.
In the discrimination network circuit, the self-learning signal release layer comprises a self-learning signal generation circuit, a sample holder LF398b, a control signal Vc1 and an NMOS tube N 1 The composition is formed. The self-learning signal generating circuit is composed of a first branch and a second branch which are connected in parallel and are respectively used for processing the learning error signal E>E 1 And learning error signal E<E 2 In the case of (2), E 1 >0 and E 2 <0. Branch one is composed of NMOS tube N 2 PMOS tube P 2 Operational amplifier A5 and resistor R 18 、R 20 、R 22 And R is 24 Constructing; branch two by PMOS tube P 1 NMOS tube N 3 Operational amplifier A6 and resistor R 19 、R 21 、R 23 And R is 25 The composition is formed. Here, E 1 And N 2 Is set at a threshold voltage V of TH Corresponding E 2 And P 1 Is set at a threshold voltage V of TH Corresponding to each other. When learning error signal E>E 1 NMOS tube N 2 Turn on and make PMOS tube P 2 Is grounded at the gate electrode of P 2 Thus will be in a conductive state, DC power supply V L1 The voltage signal provided will pass through P 2 And go through R 22 、R 24 And A5 to form a self-learning signal. Similarly, when learning the error signal E<E 2 During the process, PMOS tube P 1 Turn on and make NMOS transistor N 3 Is grounded to the gate of N 3 Thus will be in a conductive state, DC power supply V L2 The voltage signal provided will pass through N 3 And go through R 23 、R 25 And A6 to form another self-learning signal. It should be noted that the learning error signal E is respectively connected to N via the drain of N1 2 And P 1 Is connected with the grid electrode of the power supply; NMOS tube N 1 The gate voltage of (2) is provided by a control signal Vc1, and the NMOS tube is in an off state and an on state respectively in the first half period and the second half period of Vc 1. Since Vc1 can be applied to N 1 Is controlled by the conduction of N in the first half period 1 The learning error signals E and N are disconnected 2 And P 1 The grid electrode of the self-learning signal generating circuit is connected to influence the self-learning signal generating circuit; in the second half period, N 1 The output end of the A4 is connected with the ground, and the self-learning signal generating circuit is not influenced by E. In addition, the logic control signal of LF398b is also composed of a digital periodic signal V DI Providing. When the self-learning signal is sampled and held by LF398b, an output signal V is generated DL This signal is on switch G Dn Memristor M in input layer in second half period of Vc 12 -M m2 And M 21 -M m1 And (5) performing weight adjustment.
One period of the control signal Vc is a self-learning period of the network circuit. With continuous self-learning, the output signal of the discrimination network circuit gradually approaches to the correct sample V T The value of the learning error signal E will also be toward E 1 Or E is 2 Approximation, when meeting E<E 1 Or E is>E 2 After that, the self-learning process of discriminating the network circuit will be stopped.
In the network generation circuit, an input layer is formed by a PMOS tube P G1 -P Gm Memristor M 1 -M m A summing circuit and an inverter. Wherein the control signal V c Will be P G1 -P Gm The gate voltage of the m PMOS transistors is controlled to be turned on and off; the summing circuit consists of a resistor R1 and an operational amplifier A7, and the inverter consists of a resistor R 2 、R 3 And an operational amplifier A8. External input signal V G1 -V Gm Respectively connected to P G1 -P Gm Source, P of (2) G1 -P Gm The drains of the (a) are respectively connected with the memristor M 1 -M m Is a positive electrode of (a). In the first half period of Vc, P G1 -P Gm In the on state, externally input signal V G1 -V Gm In the process of M 1 -M m And then converted into a current signal, the current signal is summed by a summing circuit, a voltage signal with the polarity opposite to the total current is obtained at the output end of A7, then the output voltage signal of A7 is inverted by an inverter formed by A8, and the voltage signal with the polarity identical to the total current is obtained at the output end of A8, and the voltage signal is the output signal of an input layer in a generation network circuit.
In the generation network circuit, the error calculation layer is composed of a sample holder LF398c, a difference calculation circuit, and a voltage follower. The difference circuit consists of a resistor R 4 -R 7 And an operational amplifier A9, the voltage follower is composed of an operational amplifier A10, and the logic control signal of LF398c is composed of a digital periodic signal V DI Providing. LF398c at V DI Sampling the output signal of the input layer in the first half period of (a) and obtaining the output signal V of the network circuit G . Then V is arranged G The non-inverting input end of the difference solving circuit A9 is connected; output signal V of discrimination network circuit D As a competition game object of the network circuit, the competition game object is input to an inverting input terminal of the A9 through a voltage follower A10; the difference between the two can be calculated by a difference circuit, and the difference is taken as a learning error signal E G And input to self-learningA signal release layer.
In the generating network circuit, the self-learning signal release layer is composed of two transmission gates corresponding to the third branch and the fourth branch, and the two transmission gates are respectively used for processing the learning error signal E G >E 3 And learning error signal E G <E 4 In the case of (2), E 3 >0 and E 4 <0. The transmission gate corresponding to the branch III is composed of an NMOS tube N 4 PMOS tube P 3 And DC power supply V L3 Composition, wherein V L3 <0; the transmission gate corresponding to the branch four is composed of an NMOS tube N 5 PMOS tube P 4 And DC power supply V L4 Composition, wherein V L4 >0. Here, E 3 And N 4 Is set at a threshold voltage V of TH Corresponding to E 4 And P 4 Is set at a threshold voltage V of TH Corresponding to each other. In order to learn the error signal E G As the conduction control signals of the two transmission gates, the outputs of the error calculation layer are respectively connected to N 4 And P 4 Is formed on the substrate. When E is G Greater than E 3 When the transmission gate corresponding to branch III is turned on, V L3 The self-learning signal is provided through the NMOS tube N G Reach M 1 -M m Thereby enabling M in the input layer 1 -M m The resistance of (c) increases. While when E G Less than E 4 When the transmission gate corresponding to the branch four is turned on, V L4 The self-learning signal is provided through the NMOS tube N G Reach M 1 -M m Thereby making M 1 -M m The resistance of (c) decreases. Notably, N G In an on-state only during the second half period of Vc, which means that the self-learning signal provided by the self-learning signal release layer is only applied to M in the input layer during the second half period of Vc 1 -M m 。
Wherein a self-learning period of the network circuit, i.e. a period of the control signal Vc, is generated. M with continuous self-learning of network circuit generation 1 -M m Will be directed to E G Approach E 3 Or E is 4 In the direction of (c) when meeting E G <E 3 Or E is G >E 4 The self-learning process of generating the network circuit is then stopped.
The self-learning process of the discrimination network circuit and the generation network circuit can be divided into two stages of feedforward calculation and feedback adjustment, wherein the feedforward calculation stage of the above circuit corresponds to the first half period of Vc and the feedback adjustment stage corresponds to the second half period of Vc. For the discrimination network circuit, vc causes P in the feedforward calculation stage Dn Conducting to make the external input V D1 -V Dm Can act on the circuit, at V D1 -V Dm The error calculation layer generates an output signal V for discriminating the network circuit D And can calculate the output signal and correct sample V T And error E between them. As a reference for determining the self-learning of the network circuit, the error E determines whether the self-learning signal release layer can generate the self-learning signal, when E>E 1 When the first branch in the self-learning signal release layer is in the on state and the second branch is in the off state, the self-learning signal generated by the self-learning signal release layer will reduce the memristive weight in the input layer during the feedback adjustment stage, thereby reducing E, when 0<E<E 1 When the branch is disconnected, the self-learning is finished; while when E<E 2 When the second branch in the self-learning signal release layer is in the on state and the first branch is in the off state, the self-learning signal generated by the self-learning signal release layer will increase the memristive weight in the input layer during the feedback adjustment stage, thereby increasing E, and when E is 2 <E<And when the first branch is 0, the second branch is disconnected, and the self-learning is finished.
Similarly, for the generation network circuit, vc causes P in the feed forward calculation phase G1 -P Gm Conducting to make the external input V G1 -V Gm Can act on the circuit, at V G1 -V Gm The error calculation layer generates an output signal V for generating a network circuit G And can calculate the output signal and judge the output signal V of the network circuit D Error E between G . Error E as a benchmark for generating self-learning of network circuits G Determining whether the self-learning signal release layer can generate the self-learning signal when E>E 3 Self-learning signal release layerThe third branch is in a conducting state and the fourth branch is in a disconnecting state, at this time, the self-learning signal generated by the self-learning signal release layer can reduce the memristive weight in the input layer in the feedback adjustment stage, so as to reduce E, when 0<E<E 3 When the third branch is disconnected, the self-learning is finished; while when E<E 4 When the third branch is in the on state and the fourth branch is in the off state, the self-learning signal generated by the self-learning signal release layer will increase the memristive weight in the input layer during the feedback adjustment stage, thereby increasing E, and when E 4 <E<And when the number is 0, the branch IV is disconnected, and the self-learning is finished.
Drawings
Fig. 1 is a diagram showing the construction of an antagonistic neural network.
FIG. 2 is a diagram of a memristor self-learning circuit based on generation of an antagonistic neural network.
FIG. 3 shows an input layer switch G in a discrimination network circuit Dn Is a structural diagram of (a).
FIG. 4 is a diagram illustrating the variation of the resistance of the first group of memristors M11 and M12 in a circuit of the discrimination network.
FIG. 5 is a graph showing the variation of a first set of synaptic weights in a discrimination network circuit.
FIG. 6 is a diagram illustrating the variation of the resistance of the second group of memristors M21 and M22 in a discrimination network.
FIG. 7 is a diagram illustrating the variation of the second set of synaptic weights in a network circuit.
Fig. 8 shows the output signal of the discrimination network circuit.
FIG. 9 is a diagram of a change in resistance of memristors M1 and M2 in a generation network circuit.
Fig. 10 is a diagram of an output signal from a generation network circuit.
Detailed Description
In order to make the technical scheme, the purpose and the advantages of the invention clearer and more clear, the invention is further described in detail below with reference to the accompanying drawings.
As shown in fig. 1 and 2, the present invention provides a memristor self-learning circuit based on a generation countermeasure neural network, which comprises a discrimination network circuit module and a generation network circuit module, and each module comprises an input layer, an error calculation layer and a self-learning signal release layer.
As shown in fig. 2, the input layer of the discrimination network circuit is inputted with the external input V D1 -V Dm Switch G D1 -G Dm Memristor M 11 -M m1 And M 12 -M m2 Resistance R 8 -R 13 Operational amplifiers A1-A3; FIG. 3 shows a switch G Dn Is a schematic structural diagram of the (c). Switch G Dn Middle PMOS tube P Dn Gate and NMOS transistor N Dn The grid of (a) is connected with the periodic signal Vc, P Dn Drain and N of (2) Dn Is connected to switch G Dn An output terminal of (a); external input V D1 -V Dm Respectively with switch G D1 -G Dm Middle P D1 -P Dn Source connection of switch G D1 -G Dm The output ends of the (1) are respectively connected with the memristor M through nodes 1, 2, 3 and 4 11 -M m1 Is of (1) and memristor M 12 -M m2 Is connected to the positive electrode of the battery. M is M 11 -M m1 The positive electrode of the (A) and the inverting input terminal of the operational amplifier A2 are connected to the node 5, the resistor R 9 Intersecting the inverting input and output of A2 at node 5 and node 8, respectively; m is M 12 -M m2 Is connected to node 6 with the negative electrode of the operational amplifier A1 and resistor R 8 Intersecting the inverting input and output of A1 at node 6 and node 7, respectively; the non-inverting inputs of the operational amplifiers A1 and A2 are grounded. At the same time, node 8 passes through resistor R 12 Is connected with the non-inverting input end R of the operational amplifier A3 12 And R is R 13 Crossing at node 10 and connected to the non-inverting input of A3, R 13 The other end of the first electrode is grounded; node 7 is connected to the resistor R 10 An inverting input terminal of A3 is connected, R 11 Intersecting the inverting input and output of A3 at node 9 and node 11, respectively.
As shown in fig. 2, the error calculation layer of the discrimination network circuit is composed of a sample holder LF398a, an operational amplifier A4 and a resistor R 14 -R 17 The composition is formed. Wherein the output signal of the input layer is connected to the input end of LF398a via node 11 and generates a sampling signal V via node 12 at its output end D The method comprisesSample signal V D The non-inverting input of A10 is connected to the non-inverting input of A10 via node 12, the inverting input of A10 intersects the output thereof at node 36 and the output signal of the discrimination network circuit is connected to the error calculation layer of the generation network circuit via node 36. At the same time, node 12 passes through resistor R 15 Connected to the same-directional input terminal R of the operational amplifier A4 15 And R is R 16 Crossing at node 14 and connected to the co-directional input of A4, R 16 The other end of the first electrode is grounded; correct sample V T Through resistance R 14 Connected to the inverting input of A4, node 13, resistor R 17 Intersecting the inverting input and output of A4 at nodes 13 and 15, respectively; in this connection, node 15 is the output signal of the error calculation layer.
As shown in FIG. 2, the self-learning signal release layer of the discrimination network circuit is composed of NMOS transistor N 1 ~N 3 PMOS tube P 1 、P 2 Resistance R 18 ~R 25 Operational amplifiers A5, A6 and a sample holder LF398 b. Wherein, the output end of A4 is connected with the drain electrode of NMOS tube N1 through node 15 and is respectively connected with N 2 And P 1 Is formed on the substrate. In branch one, N 2 Is grounded at the source of N 2 Is connected to P through node 16 2 Is connected to the node 16 via a resistor R 18 Is connected with a DC power supply; DC power supply V L1 Positive and negative electrodes of (a) are respectively connected with P 2 Is connected to ground, P 2 The drain of (2) is connected to resistor R through node 18 20 Connection, resistance R 20 The other end of which is grounded. The node 20, which is the inverting input terminal of the operational amplifier A5, passes through the resistor R 22 And P 2 Drain electrode connection of resistor R 24 The inverting input terminal of A5 is connected with the output terminal of A5, and the output terminal of A5, namely the node 21 is connected with the input terminal of LF398 b. On the other hand, in branch two, P 1 Is grounded at the source of P 1 Is connected to N through node 17 3 Gate of (d), node 17 is connected to a resistor R 19 Is connected with a DC power supply; DC power supply V L2 Positive and negative electrodes of (a) are respectively connected with N 3 Is connected to ground, N 3 The drain of (2) is connected to resistor R through node 19 21 Connection, resistance R 21 Is connected with the other end of (a)And (3) ground. The node 22, which is the inverting input terminal of the operational amplifier A6, passes through the resistor R 23 And N 3 Drain electrode connection of resistor R 25 The inverting input terminal of A6 is connected with the output terminal of A6, and the output terminal of A6, namely the node 23 is connected with the input terminal of LF398 b. LF398b samples the accessed self-learning signal and generates a sampling signal V at its output DL And connect it in parallel to G D1 -G Dm Middle N D1 -N Dm A source of (a); in the second half period of Vc, N D1 -N Dm Turned on at this time V DL The memristor is accessed and its memristance is adjusted.
As shown in fig. 2, the input layer of the network circuit is generated by external input V G1 ~V Gm Timing control signal Vc, PMOS tube P G1 ~P Gm Memristor M 1 Mm, resistance R 1 -R 3 And operational amplifiers A7 and A8. Wherein R is 1 Forms a summation circuit with A7, R 2 、R 3 And an inverter circuit is formed by the circuit A8. External input V G1 -V Gm And PMOS tube P G1 -P Gm Is connected with the source electrode of the (V), and the time sequence control signal Vc is connected with P G1 -P Gm A gate electrode of (a); in the first half period of Vc, V G1 -V Gm Through P G1 -P Gm Drain access memristor M 1 -M m And intersect at nodes 24 through 27, respectively. Memristor M 1 -M m The negative electrode of which is connected in parallel with the inverting input terminal of A7, namely a node 28; resistor R 1 Intersecting the inverting input and output of A7 at node 28 and node 29, respectively, the non-inverting input of A7 is grounded. Resistor R 2 Between the output node 29 of the switch A7 and the inverting input node 30 of the switch A8, the resistor R 3 The inverting input and the output of A8 are intersected at a node 30 and a node 31 respectively, and the non-inverting input of A8 is grounded.
As shown in fig. 2, the error calculation layer of the generated network circuit is composed of LF398c, operational amplifiers A9, a10, and a resistor R 4 -R 7 Constructing; wherein A10 forms a voltage follower, resistor R 4 -R 7 And A9 forms a difference circuit. The output signal of the input layer is represented by node 31Is connected to the input of LF398c, and the output signal V of the network circuit is obtained at node 32 after the LF398c samples the signal G LF398c will signal V G Through resistance R 5 、R 6 Is connected to the same-direction input end of A9. Resistor R 6 Is intersected with the same-directional input end of A9 at a node 34, and a resistor R 6 The other end of the first electrode is grounded; resistor R 5 Between the output node 32 of LF398c and the co-directional input node 34 of A9. Discriminating the output signal V of the network circuit D By the output node 36 of A10 through resistor R 4 The resistor R7 is introduced into the inverting input end node 33 of the A9, intersects with the inverting input end and the output end of the A9 respectively at the node 33 and the node 35, and the output end node 35 of the A9 is connected into the next self-learning signal release layer.
As shown in FIG. 2, the self-learning signal release layer of the network circuit is formed by NMOS transistor N 4 、N 5 、N G PMOS tube P 3 、P 4 And DC power supply V L3 、V L4 The composition is formed. Wherein is composed of N 4 、P 3 And DC power supply V L3 Composed transmission gate for processing E G >E 3 Branch three of (2), from N 5 、P 4 And DC power supply V L4 Composed transmission gate for processing E G <E 4 Branch four of (2). In the transmission gate corresponding to branch three, the output signal of the error calculation layer is connected to N by node 35 4 Gate electrode of P 3 Is connected to ground, DC power supply V L3 Access to N via nodes 37, respectively 4 And P 3 Source, N of (2) 4 And P 3 And the drain of (c) intersects at node 39. In the transmission gate corresponding to the branch four, the output signal of the error calculation layer is connected to P by the node 35 4 Gate of (2), N 5 Is connected to ground, DC power supply V L4 Access to N via nodes 38, respectively 5 And P 4 Source, N of (2) 5 And P 4 And the drain of (c) intersects at node 39. The output signals of the third branch and the fourth branch are led out from the node 39 and then are connected to N G Drain of (2), N G The gate of (2) is connected with the control signal Vc, and is N G In the second half period of Vc, the self-learning signal is derived from N G Respectively connected with M 1 -M m And intersect nodes 24 through 27, respectively.
In the memristor self-learning circuit simulation example, two input signals V are arranged at an input layer in a discrimination network circuit D1 And V is equal to D2 ，V D1 And V is equal to D2 Are respectively connected with a corresponding group of memristors, wherein V D1 The corresponding first group of memristors is M 11 And M 12 ，V D2 The corresponding second group of memristors is M 21 And M 22 . V is also arranged in the generating network circuit G1 And V is equal to G2 Two input signals, where V G1 And M is as follows 1 Connection, V G2 And M is as follows 2 And (5) connection. In addition, the correct sample V in the network circuit will be discriminated T Set to 0.55V.
Fig. 4 is a diagram showing the resistance change of the first group of memristors M11 and M12 in the discrimination network circuit, and fig. 6 is a diagram showing the resistance change of the second group of memristors M21 and M22 in the discrimination network circuit. As can be seen from FIGS. 4 and 6, M 11 Is 5kΩ, M 12 Is 5.8kΩ, M 21 Is 7kΩ, M 22 Is 8kΩ. Discriminating the network circuit in the correct sample V T Is guided to self-learn to distinguish the output signal V of the network circuit D Toward the correct sample V T Approach, M 11 、M 12 、M 21 And M 22 The resistance of the two groups of memristors is continuously adjusted in the self-learning process of the circuit, as shown in fig. 4 and 6, until the resistance of the two groups of memristors stops changing after 180ms, which indicates that the self-learning process is finished. FIGS. 5 and 7 correspond to the determination of the change in the two sets of synaptic weights of the input layer in the network circuit, the first set of synaptic weights being W 1 The second group of synapses has a weight of W 2 W is then 1 =1/M 11 -1/M 12 ，W 2 =1/M 21 -1/M 22 Similar to the change in memristance, the two sets of synaptic weights also stop changing at 180 ms.
Fig. 8 is a diagram showing the variation of the output signal of the discrimination network circuit. Discriminating the network circuit in the correct sample V T Is guided to self-learn by the circuit itselfOutput signal V of (2) D Will be continuously directed to the correct sample V T Approaching, when the synaptic weight of the input layer of the network circuit is judged to stop changing, V D And V is equal to T The difference E between the two is reduced to be within an acceptable error range, wherein the acceptable error range can be adjusted according to actual conditions; v (V) D The change is stopped, and the self-learning process of the discrimination network circuit is ended at this time.
FIG. 9 shows memristor resistance M in input layer of generation network circuit 1 And M 2 Is a variation graph of (a). Output signal V of AND discrimination network circuit D M in the competition gaming process 1 And M 2 Will be directed to generate the network circuit output signal V G To V D An approximated direction change; when V is G And V is equal to D Difference E between G When the error is reduced to be within an acceptable error range, the acceptable error range can be adjusted according to actual conditions; m is M 1 And M 2 The change will stop. FIG. 10 is a graph showing the change of the output signal of the network circuit, V at 320ms according to the change of the memristor resistance in FIG. 9 G And V is equal to D Difference E between G The self-learning process of generating the network circuit ends at this point, which is reduced to within an acceptable error range.
Claims (7)
1. The memristor self-learning circuit based on the generation countermeasure neural network is characterized by comprising a discrimination network circuit module and a generation network circuit module, wherein each circuit module comprises an input layer, an error calculation layer and a self-learning signal release layer; wherein, the network circuit is judged to be in a correct sample V T Under the guidance of (1) to self-learn when it outputs signal V D And correct sample V T When the difference E between the two voltages does not reach an acceptable error range, judging that a self-learning signal generated by a self-learning signal release layer in a network circuit adjusts the resistance value of a memristor of an input layer until the difference E reaches the acceptable error range; meanwhile, based on the competition game type learning rule for generating the antagonism neural network, the output signal V of the network circuit is judged D Will be used as the object of competition game of the generated network circuit to further causeGenerating an output voltage V of a network circuit G In V form D As learning target, self-learning is performed when V G And V is equal to D Difference E between G When the acceptable error range is not reached, the self-learning signal generated by the self-learning signal release layer in the generated network circuit adjusts the resistance value of the memristor in the input layer until the difference E is obtained G To within acceptable error limits; the above two self-learning processes of discriminating the network circuit and generating the network circuit are performed in parallel only when the differences E and E are different G And after the self-learning circuit reaches the corresponding acceptable error range, the self-learning process of the memristor is completely finished.
2. The memristor self-learning circuit based on generation of antagonistic neural network according to claim 1, wherein the input layer of the discrimination network circuit is externally input with V D1 -V Dm Switch G D1 -G Dm Memristor M 11 -M m1 And M 12 -M m2 Resistance R 8 -R 13 Operational amplifiers A1-A3; switch G Dn Middle PMOS tube P Dn Gate and NMOS transistor N Dn The grid of (a) is connected with the periodic signal Vc, P Dn Drain and N of (2) Dn Is connected to switch G Dn An output terminal of (a); external input V D1 -V Dm Respectively with switch G D1 -G Dm Middle P D1 -P Dn Source connection of switch G D1 -G Dm The output end of the (C) is respectively connected with the memristor M through the first node to the fourth node 11 -M m1 Is of (1) and memristor M 12 -M m2 Is connected with the positive electrode of the battery; m is M 11 -M m1 The positive electrode of the (A) and the inverting input terminal of the operational amplifier A2 are connected to the fifth node, the resistor R 9 Intersecting the inverting input and output of A2 at a fifth node and an eighth node, respectively; m is M 12 -M m2 Is connected to the negative electrode of the operational amplifier A1 and the inverting input terminal of the sixth node, resistor R 8 Intersecting the inverting input and output of A1 at a sixth node and a seventh node, respectively; non-inverting inputs of operational amplifiers A1 and A2Grounding; at the same time, the eighth node passes through the resistor R 12 Is connected with the non-inverting input end R of the operational amplifier A3 12 And R is R 13 Intersecting at the tenth node and connected to the non-inverting input of A3, R 13 The other end of the first electrode is grounded; the seventh node passes through the resistor R 10 An inverting input terminal of A3 is connected, R 11 Intersecting the inverting input and output of A3 at the ninth node and the eleventh node, respectively.
3. The memristor self-learning circuit based on generation of antagonistic neural network according to claim 1, wherein the error calculation layer of the discrimination network circuit is composed of a sample holder LF398a, an operational amplifier A4 and a resistor R 14 -R 17 Constructing; wherein the output signal of the input layer is connected to the input end of the LF398a through the eleventh node and generates a sampling signal V at the output end thereof through the twelfth node D The sampling signal V D The non-inverting input end of the A10 is accessed through a twelfth node, the inverting input end of the A10 is intersected with the output end of the A10 to a thirty-sixth node, and the output signal of the judging network circuit is connected to an error calculation layer of the generating network circuit through the thirty-sixth node; at the same time, the twelfth node passes through the resistor R 15 Connected to the same-directional input terminal R of the operational amplifier A4 15 And R is R 16 Intersecting at the fourteenth node and connected to the same-directional input terminal of A4, R 16 The other end of the first electrode is grounded; correct sample V T Through resistance R 14 A thirteenth node connected to the inverting input of A4, a resistor R 17 Intersecting the inverting input and output of A4 at thirteenth and fifteenth nodes, respectively; in this connection, the fifteenth node is an output signal of the error calculation layer.
4. The memristor self-learning circuit based on generation of antagonistic neural network according to claim 1, wherein the self-learning signal release layer of the discrimination network circuit is composed of an NMOS transistor N 1 ~N 3 PMOS tube P 1 、P 2 Resistance R 18 ~R 25 Operational amplifiers A5, A6 and a sample holder LF398 b; wherein the output of A4The end is connected with the drain electrode of the NMOS tube N1 through a fifteenth node and is respectively connected with N 2 And P 1 A gate electrode of (a); in branch one, N 2 Is grounded at the source of N 2 Access P through sixteenth node 2 A sixteenth node through a resistor R 18 Is connected with a DC power supply; DC power supply V L1 Positive and negative electrodes of (a) are respectively connected with P 2 Is connected to ground, P 2 Through the eighteenth node and the resistor R 20 Connection, resistance R 20 The other end of the first electrode is grounded; the twentieth node, which is the inverting input terminal of the operational amplifier A5, passes through the resistor R 22 And P 2 Drain electrode connection of resistor R 24 The input end of the second node is connected with the input end of the second node, and the output end of the second node is connected with the input end of the LF398 b; on the other hand, in branch two, P 1 Is grounded at the source of P 1 Is connected to N through seventeenth node 3 A seventeenth node through a resistor R 19 Is connected with a DC power supply; DC power supply V L2 Positive and negative electrodes of (a) are respectively connected with N 3 Is connected to ground, N 3 The drain of (2) passes through the nineteenth node and the resistor R 21 Connection, resistance R 21 The other end of the first electrode is grounded; the twenty-second node, which is the inverting input terminal of the operational amplifier A6, passes through the resistor R 23 And N 3 Drain electrode connection of resistor R 25 The inverting input end of the first node is connected with the output end of the second node A6, and the output end of the second node A6 is connected with the input end of the LF398 b; LF398b samples the accessed self-learning signal and generates a sampling signal V at its output DL And connect it in parallel to G D1 -G Dm Middle N D1 -N Dm A source of (a); in the second half period of Vc, N D1 -N Dm Turned on at this time V DL The memristor is accessed and its memristance is adjusted.
5. The memristor self-learning circuit based on generation of antagonistic neural network of claim 1, wherein the input layer of the generation network circuit is externally input with V G1 ~V Gm Timing control signal Vc, PMOSPipe P G1 ~P Gm Memristor M 1 Mm, resistance R 1 -R 3 And operational amplifiers A7 and A8; wherein R is 1 Forms a summation circuit with A7, R 2 、R 3 An inverter circuit is formed by the first and the second circuits A8; external input V G1 -V Gm And PMOS tube P G1 -P Gm Is connected with the source electrode of the (V), and the time sequence control signal Vc is connected with P G1 -P Gm A gate electrode of (a); in the first half period of Vc, V G1 -V Gm Through P G1 -P Gm Drain access memristor M 1 -M m And intersect at the twenty-fourth node to the twenty-seventh node, respectively; memristor M 1 -M m The negative electrode of the capacitor is connected into the inverting input end of A7 in parallel, namely a twenty-eighth node; resistor R 1 Intersecting the inverting input end and the output end of A7 at a twenty-eighth node and a twenty-ninth node respectively, wherein the non-inverting input end of A7 is grounded; resistor R 2 A resistor R is connected between the twenty-ninth node of the output end of the A7 and the thirty-second node of the inverting input end of the A8 3 Intersecting the inverting input and output of A8 at the thirty-th node and the thirty-th node, respectively, the non-inverting input of A8 is grounded.
6. The memristor self-learning circuit based on generation countermeasure neural network of claim 1, wherein the error calculation layer of the generation network circuit is composed of LF398c, operational amplifiers A9, a10 and a resistor R 4 -R 7 Constructing; wherein A10 forms a voltage follower, resistor R 4 -R 7 A difference circuit is formed by the A9; the output signal of the input layer is connected to the input end of the LF398c by the thirty-second node, and the output signal V of the generated network circuit is obtained at the thirty-second node after the LF398c samples the signal G LF398c will signal V G Through resistance R 5 、R 6 A same-direction input end connected to A9; resistor R 6 Is intersected with the same-direction input end of A9 at a thirty-fourth node, and a resistor R 6 The other end of the first electrode is grounded; resistor R 5 The third node is positioned between the thirty-second node of the output end of the LF398c and the thirty-fourth node of the homodromous input end of the A9; discriminating the output of a network circuitSignal V D A thirty-sixth node at the output end of A10 passes through a resistor R 4 The third node is introduced to the inverting input end of A9, the resistor R7 is intersected with the inverting input end and the output end of A9 respectively at the third node and the thirty-fifth node, and the thirty-fifth node of the output end of A9 is connected into the self-learning signal release layer of the next stage.
7. The memristor self-learning circuit based on generation countermeasure neural network of claim 1, wherein the self-learning signal release layer of the generation network circuit is composed of an NMOS tube N 4 、N 5 And N G PMOS tube P 3 、P 4 And DC power supply V L3 、V L4 Constructing; wherein branch three is composed of N 4 、P 3 And DC power supply V L3 The transmission gate consists of four branches consisting of N 5 、P 4 And DC power supply V L4 A transmission gate; in the transmission gate corresponding to the third branch, the output signal of the error calculation layer is connected to N by the thirty-fifth node 4 Gate electrode of P 3 Is connected to ground, DC power supply V L3 Accessing N through thirty-seventh nodes respectively 4 And P 3 Source, N of (2) 4 And P 3 Is intersected at the thirty-ninth node; in the transmission gate corresponding to the branch four, the output signal of the error calculation layer is accessed to P by the thirty-fifth node 4 Gate of (2), N 5 Is connected to ground, DC power supply V L4 Accessing N through thirty-eighth nodes respectively 5 And P 4 Source, N of (2) 5 And P 4 Is intersected at the thirty-ninth node; the output signals of the third branch and the fourth branch are led out from the thirty-ninth node and then are connected to N G Drain of (2), N G The gate of (2) is connected with the control signal Vc, and is N G In the second half period of Vc, the self-learning signal is derived from N G Respectively connected with M 1 -M m And intersect the positive electrodes of the twenty-fourth to twenty-seventh nodes, respectively.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006180128A (en) * | 2004-12-21 | 2006-07-06 | Rohm Co Ltd | Input/output switching circuit, and semiconductor integrated circuit device mounted with the same |
| CN103246904A (en) * | 2013-05-24 | 2013-08-14 | 北京大学 | Resistance-adjustable-memristor-based time-related learning neuron circuit and implementation method thereof |
| US9336870B1 (en) * | 2013-08-16 | 2016-05-10 | Sandia Corporation | Methods for resistive switching of memristors |
| CN109002647A (en) * | 2018-08-17 | 2018-12-14 | 郑州轻工业学院 | A kind of memristor associative memory neural network circuit with delay learning functionality |
| CN110443168A (en) * | 2019-07-23 | 2019-11-12 | 华中科技大学 | A kind of Neural Network for Face Recognition system based on memristor |
| WO2022105890A1 (en) * | 2020-11-20 | 2022-05-27 | 唯捷创芯(天津)电子技术股份有限公司 | Voltage bias circuit with adjustable output, and chip and communication terminal |
| CN114723025A (en) * | 2022-03-25 | 2022-07-08 | 武汉工程大学 | Memristor back propagation neural network circuit and control method thereof |
| US20220261661A1 (en) * | 2019-08-07 | 2022-08-18 | Intel Corporation | Methods, systems, articles of manufacture and apparatus to improve job scheduling efficiency |
| CN114970850A (en) * | 2022-06-28 | 2022-08-30 | 郑州轻工业大学 | Emotional habituation neural network circuit with situation dependence and generalization |
| CN114997387A (en) * | 2022-06-28 | 2022-09-02 | 郑州轻工业大学 | Visual-evoked emotional habituation characteristic neural network circuit |
| CN115577758A (en) * | 2022-03-16 | 2023-01-06 | 郑州轻工业大学 | Multi-mode generalization and differentiation association memory neural network circuit based on memristor |
| CN115630693A (en) * | 2022-12-21 | 2023-01-20 | 湖南师范大学 | Memristor self-learning circuit based on Elman neural network learning algorithm |
-
2023
- 2023-07-03 CN CN202310804507.1A patent/CN116523012B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006180128A (en) * | 2004-12-21 | 2006-07-06 | Rohm Co Ltd | Input/output switching circuit, and semiconductor integrated circuit device mounted with the same |
| CN103246904A (en) * | 2013-05-24 | 2013-08-14 | 北京大学 | Resistance-adjustable-memristor-based time-related learning neuron circuit and implementation method thereof |
| US9336870B1 (en) * | 2013-08-16 | 2016-05-10 | Sandia Corporation | Methods for resistive switching of memristors |
| CN109002647A (en) * | 2018-08-17 | 2018-12-14 | 郑州轻工业学院 | A kind of memristor associative memory neural network circuit with delay learning functionality |
| CN110443168A (en) * | 2019-07-23 | 2019-11-12 | 华中科技大学 | A kind of Neural Network for Face Recognition system based on memristor |
| US20220261661A1 (en) * | 2019-08-07 | 2022-08-18 | Intel Corporation | Methods, systems, articles of manufacture and apparatus to improve job scheduling efficiency |
| WO2022105890A1 (en) * | 2020-11-20 | 2022-05-27 | 唯捷创芯(天津)电子技术股份有限公司 | Voltage bias circuit with adjustable output, and chip and communication terminal |
| CN115577758A (en) * | 2022-03-16 | 2023-01-06 | 郑州轻工业大学 | Multi-mode generalization and differentiation association memory neural network circuit based on memristor |
| CN114723025A (en) * | 2022-03-25 | 2022-07-08 | 武汉工程大学 | Memristor back propagation neural network circuit and control method thereof |
| CN114970850A (en) * | 2022-06-28 | 2022-08-30 | 郑州轻工业大学 | Emotional habituation neural network circuit with situation dependence and generalization |
| CN114997387A (en) * | 2022-06-28 | 2022-09-02 | 郑州轻工业大学 | Visual-evoked emotional habituation characteristic neural network circuit |
| CN115630693A (en) * | 2022-12-21 | 2023-01-20 | 湖南师范大学 | Memristor self-learning circuit based on Elman neural network learning algorithm |
Non-Patent Citations (2)
| Title |
|---|
| ENVER SOLAN等: "Wave Digital Emulation of General Memristors", 《INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS》, pages 1 - 17 * |
| 洪庆辉: "忆阻神经网络的全电路设计及其应用", 《中国博士学位论文全文数据库信息科技辑》, no. 1, pages 140 - 37 * |
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| Publication number | Publication date |
|---|---|
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