CN115630693A - Memristor self-learning circuit based on Elman neural network learning algorithm - Google Patents

Memristor self-learning circuit based on Elman neural network learning algorithm Download PDF

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CN115630693A
CN115630693A CN202211644728.9A CN202211644728A CN115630693A CN 115630693 A CN115630693 A CN 115630693A CN 202211644728 A CN202211644728 A CN 202211644728A CN 115630693 A CN115630693 A CN 115630693A
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万求真
刘炯
杨巧
孙坤亮
陈思邈
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Hunan Normal University
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Abstract

The invention discloses a memristor self-learning circuit based on an Elman neural network learning algorithm. Based on the learning rule and the network structure of the Elman neural network, the memristor self-learning circuit provided by the invention comprises a positive signal input channel and a negative signal input channel, and each signal input channel comprises an input layer, a carrying layer and an output layer. The input layer can identify the positive and negative polarities of the input voltage signal values, and then input signals with different positive and negative polarities are processed through different input channels. The output of the receiving layer can be used as an input signal of the output layer and can also be used as a local feedback signal to jointly act on the input layer with an external input signal at the next moment. The self-learning signal output by the output layer can adjust the resistance value of the memristor between the input layer and the bearing layer and finally realize the self-learning function. The memristor self-learning circuit can accelerate the self-learning process of the circuit, shorten the self-learning time and further improve the self-learning efficiency of the circuit.

Description

Memristor self-learning circuit based on Elman neural network learning algorithm
Technical Field
The invention relates to the field of memristor self-learning circuit design, in particular to a memristor self-learning circuit based on an Elman neural network learning algorithm.
Background
As early as the advent of the computer, human beings have begun exploring the intelligence of the human brain. Artificial neural network based technology is one of the ways in which humans currently study artificial intelligence. An artificial neural network is a mathematical model description of the human brain system, and can be implemented either by electronic circuitry or by a computer program.
The network structure of the artificial neural network is formed by a plurality of layers together, different layers are connected by weight, the structure corresponds to the internal structure of the biological neural network, and the layers which are connected with each other in front and back correspond to the neurons which are connected in front and back; the weight values connected between different levels correspond to synapses of the neurons before and after connection, and the change of the weight values corresponds to the change of the strength of synapse connection.
Currently, as a fourth circuit element of the circuit theory, a memristor has become a core element for constructing an artificial neural network electronic circuit. The resistance value of the memristor can change under a specific external electric field, in addition, the resistance value change of the memristor has directionality, and the external electric fields in opposite directions can obtain opposite resistance value change results. The change of the resistance value of the memristor corresponds to the change of the weight value in the artificial neural network and the change of the synaptic connection strength in the biological neural network. Therefore, the resistance plasticity and the resistance variation directionality of the memristor play a significant role in the electronic circuit implementation of the artificial neural network.
Except for the resistance plasticity and the direction of resistance change, the memristor has the characteristics of low power consumption, small size, compatibility with an MOS (metal oxide semiconductor) transistor and the like, and the advantages of low power consumption and high integration degree of a neural network circuit built by taking the memristor as a core element are determined. Therefore, the field of realizing the neural network circuit by adopting hardware elements such as memristors has a good development prospect.
The Elman neural network is a recurrent neural network with local memory units and local feedback connections. Compared with the traditional BP neural network structure, the network structure of the Elman neural network learning algorithm is additionally provided with a carrying layer, and the carrying layer is characterized in that the output of the carrying layer can be used as the input of an output layer and can also be used as a feedback signal to act on the input layer together with an external input signal at the next time point, so that the Elman neural network has a memory function.
At present, learning algorithms such as 'winner is king', hebbian and weighted sum with disturbance at the same time can be realized by memristor circuits, and an Elman neural network learning algorithm cannot be realized by the circuits. Therefore, the invention provides a memristor self-learning circuit based on an Elman neural network learning algorithm on the basis of utilizing the plasticity of the resistance value of the memristor. Based on the characteristic that the Elman neural network carrying layer can realize local negative feedback, the memristor self-learning circuit provided by the invention can accelerate the self-learning process, shorten the self-learning time and further improve the whole self-learning efficiency of the circuit.
Disclosure of Invention
The Elman neural network is a typical local regression network, which can implement local memory and local feedback. The Elman neural network is additionally provided with a carrying layer on the basis of a BP neural network structure; the receiving layer is characterized in that the receiving layer can realize local feedback, and a local feedback signal of the receiving layer and an external input signal at the next moment act on the input layer together. A structure diagram of an improved Elman neural network learning algorithm is shown in fig. 1.
Based on the learning rule and the network structure of the Elman neural network, the invention provides a memristor self-learning circuit based on an Elman neural network learning algorithm. The resistance plasticity of the novel two-end device memristor is used for building a memristor self-learning circuit and realizing an Elman neural network learning algorithm, and then the self-learning speed of the circuit is accelerated through the self-learning rule of the algorithm.
The invention is realized by the following technical scheme: a memristor self-learning circuit based on an Elman neural network learning algorithm comprises a positive signal input channel and a negative signal input channel, wherein each signal input channel comprises an input layer module, a receiving layer module and an output layer module, and is shown in figure 2.
In the negative signal input channel, the input layer module is composed of an NMOS tube Q 1 -Q m+1 And memristor M 11 -M 1m+1 Composition, signal V 1 -V m+1 Respectively connected into Q 1 -Q m+1 Source electrode of, Q 1 -Q m+1 The drain electrodes of the two-way resistor are respectively connected with a memristor M 11 -M 1m+1 Positive electrode of (2), external input signal V 1 -V m+1 Memory resistor M 11 -M 1m+1 Converted into a current signal and output as an input layer module as shown in fig. 3.
The receiving layer is controlled by a time sequence control signal V ct1 Resistance N a1 -N a8 Operational amplifier A 1 -A 3 And MOS transistor D 3 -D 8 And (4) forming. Wherein, the resistance N a2 And operational amplifier a 1 Forming a voltage converter; resistance N 13 And N 14 And operational amplifier a 2 Forming an inverter; operational amplifier A 3 Reference voltage V p1 (V p1 <0) And a resistor N a5 -N a8 Forming a voltage differentiator; resistance N a1 MOS transistor D 3 -D 8 And timing control signal V ct1 A feedback network is constructed. The output of the last-time receiving layer feedback network is connected with the resistor N a1 And converting the current feedback signal into a current feedback signal, wherein the feedback signal and an output signal of the input layer module are jointly used as the input of the next moment of the receiving layer and are connected to the inverting input end of the operational amplifier A1. The current input signal of the bearing layer is converted into a voltage signal after being processed by A1, the voltage signal is processed by an inverter to obtain a voltage signal in the same phase with the input signal, the output of the inverter is used as the input of a voltage differentiator and is connected to the in-phase input end of A3, and then is compared with a reference voltage V p1 The difference value Δ V is used as the output of the voltage differentiator, and Δ V is also the output signal of the receiving layer. When the initial time | Δ V | is larger, the output Δ V will turn on the corresponding transmission gate in the feedback network according to the positive or negative of its own value to output the corresponding feedback signal (the feedback signal is from the dc power supply V) f+ And V f- And providing), the | Δ V | is gradually reduced along with the self-learning, and when the | Δ V | is reduced to a specific value, the transmission gate which is turned on at the initial moment in the feedback network is turned off. In addition, the feedback net can be determined by the size of the DeltaV |Whether or not the transmission gate in the network is turned on is determined by a timing control signal V ct1 To decide. The time period requiring feedback in the first 1/2 cycle, V ct1 Do not satisfy D 7 、D 8 The feedback signal is connected to the input terminal of the receiving layer; and the time period without feedback in the last 1/2 period, V ct1 Satisfies D 7 、D 8 The output signals of the two transmission gates pass through the NMOS transistor D directly 7 、D 8 Ground and therefore no feedback signal is coupled into the input of the receiving layer during this time period, as shown in fig. 3.
Two transmission gates included in the feedback network of the receiving layer are respectively connected with a DC power supply V f+ And V f- And the feedback network can enable the corresponding transmission gate to be conducted according to the positive and negative of the self value of the delta V so as to output a feedback signal provided by the direct-current power supply. If Δ V<0, it means that the external negative input signal is less than the reference voltage V p1 At this time, with V f+ The connected transmission gate is conducted and the DC power supply V is connected f+ The supplied voltage is connected to the input end of the receiving layer through the transmission gate and used as a feedback signal to suppress the negative input signal. In the same way, if Δ V>0, it means that the external negative input signal is greater than the reference voltage V p1 At this time with V f- The connected transmission gate is conducted, and the DC power supply V is connected f- The voltage provided will be coupled through the transmission gate and as a feedback signal to the input of the receiving layer and boost the negative input signal as shown in fig. 3.
The output layer is composed of an operational amplifier A 4 Resistance N a9 -N a11 And a fixed capacitor C a1 、C a2 MOS transistor D 9 -D n+1 And sample and hold devices LF398a, LF398b and an auxiliary timing signal. Wherein, the DC power supply V L1 、D 9 And N a9 Forming a self-learning signal generator; operational amplifier A 4 And a resistance N a10 And N a11 Forming an inverter; MOS tube D 10 -D n+1 And forming a self-learning signal parallel transmission channel in a parallel connection mode. The output of the take-up layer being the input of the output layer and being connected to the sample-and-hold unit LF398aControl signal V of input terminal LF398a c For digital control pulse, the output of LF398a is summed with the auxiliary timing signal and connected to NMOS transistor D 9 When the gate voltage satisfies D 9 After the on condition of (2), the DC power supply V L1 The supplied voltage passes through D 9 To A 4 The output signal obtained after LF398b sampling is connected to the M in the input layer through a self-learning signal parallel transmission channel 11 -M 1m+1 As shown in fig. 3.
D 9 The conduction of (1) is also influenced by the delta V, and the | delta V | is gradually reduced along with the self-learning, so when the | delta V | is reduced to no longer satisfy the D 9 In the on condition of (A) 4 The inverting input terminal of the self-learning signal parallel transmission channel becomes grounded, and no feedback signal passes through any more at this moment.
In the positive signal input channel, the input layer module is composed of PMOS pipe P 1 -P m+1 And memristor M 21 -M 2m+1 Composition, signal V 1 -V m+1 Separately accessing P 1 -P m+1 Source of (2), P 1 -P m+1 The drain electrodes of the two-way resistor are respectively connected with a memristor M 21 -M 2m+1 Positive electrode of (2), external input signal V 1 -V m+1 Memory resistor M 21 -M 2m+1 Converted into a current signal and output as an input layer module as shown in fig. 4.
The receiving layer is controlled by a time sequence control signal V ct4 Resistance N b1 -N b8 Operational amplifier A 5 -A 7 And MOS tube H 3 -H 8 And (4) forming. Wherein, the resistance N b2 And operational amplifier a 5 Forming a voltage converter; resistance N b3 And N b4 And operational amplifier a 6 Forming an inverter; operational amplifier A 7 Reference voltage V p2 (V p2 >0) And a resistance N b5 -N b8 Forming a voltage difference calculator; resistance N b1 MOS tube H 3 -H 8 And timing control signal V ct4 A feedback network is constructed. The output of the last-time receiving layer feedback network is connected with the resistor N b1 Is converted into a current feedback signal, the feedbackThe signal and the output signal of the input layer module are jointly used as the input of the next moment of the receiving layer and are connected into the operational amplifier A 5 The inverting input terminal of (1). The current input signal of the receiving layer passes through an operational amplifier A 5 The processed voltage signal is converted into a voltage signal, the voltage signal is processed by an inverter to obtain a voltage signal in the same phase as the input voltage, the output of the inverter is used as the input of a voltage differentiator and is connected to A 7 Is then connected to a reference voltage V p2 The difference value Δ V is used as the output of the voltage differentiator, and Δ V is also the output signal of the receiving layer. When the initial time is larger than the initial time, the output delta V can conduct the corresponding transmission gate in the feedback network according to the positive and negative of the value of the output delta V, and then outputs the corresponding feedback signal (the feedback signal is provided by the direct current power supply V) f+ And V f- Provided), but as the self-learning proceeds, | Δ V | gradually decreases, and after decreasing to a specific value, the transmission gate turned on at the initial time in the feedback network becomes an off state. In addition, it is controlled by timing control signal V, besides the magnitude of DeltaV can determine whether the transmission gate in feedback network is conducted or not ct4 To determine. The time period requiring feedback in the first 1/2 cycle, V ct4 Do not satisfy H 7 、H 8 The feedback signal is connected to the input end of the receiving layer; and the time period without feedback in the last 1/2 period, V ct4 Satisfy H 7 、H 8 The output of the two transmission gates will pass through the NMOS transistor H directly 7 、H 8 Ground and therefore no feedback signal is coupled into the input of the receiving layer during this time period, as shown in fig. 4.
Two transmission gates included in the feedback network of the receiving layer are respectively connected with a DC power supply V f+ And V f- And the feedback network can enable the corresponding transmission gate to be conducted according to the positive and negative of the self value of the delta V so as to output a feedback signal provided by the direct-current power supply. If Δ V<0, it means that the external positive input signal is less than the reference voltage V p2 At this time, with V f+ The connected transmission gate is conducted and the DC power supply V is connected f+ The voltage provided will be connected to the input of the receiving layer through the transmission gate and used as a feedback signal, and will enhance the positive input signal.In the same way, if Δ V>0, it means that the external positive input signal is greater than the reference voltage V p2 At this time with V f- The connected transmission gate is conducted and the DC power supply V is connected f- The voltage provided will pass through the transmission gate and be coupled as a feedback signal to the input of the receiving layer and suppress the positive input signal, as shown in fig. 4.
The output layer is composed of an operational amplifier A 8 Resistance N b9 -N b12 And a fixed capacitor C b1 MOS transistor H 9 -H n+1 And a sample holder LF398 c. Wherein, DC power supply, H 9 、H 10 And N b9 、N b10 Forming a self-learning signal generator; operational amplifier A 8 And a resistance N b11 And N b12 Forming an inverter; MOS tube H 11 -H n+1 And forming self-learning signal parallel transmission channels in a parallel connection mode. The output of the receiving layer is connected to H as the input of the output layer 9 When the gate voltage satisfies H 9 After the on condition of (1), H 10 Gate voltage of 9 Supply of drain-connected DC power, H 9 Turn on (or off) of (2) will make H 10 Is turned off (or on) to generate a self-learning signal pulse having a high level amplitude equal to the DC power source V L2 The magnitude of the voltage provided. Self-learning signal pulse connection to A 8 LF398c to A 8 The output signal obtained after sampling is connected to the M in the input layer through the self-learning signal parallel transmission channel 21 -M 2m+1 As shown in fig. 4.
H 9 The conduction of the self-learning circuit is also influenced by the delta V, and the delta V is gradually reduced along with the self-learning, so that the self-learning circuit can not meet the requirement of H when the delta V is reduced to the value 9 In the on condition of (A) 8 The inverting input terminal of the self-learning signal parallel transmission channel becomes grounded, and no feedback signal passes through any more at this moment.
The self-learning mentioned in the invention is based on the resistance plasticity of the memristor and also takes the reference voltage as a learning target. The resistance plasticity is that when a certain external electric field is applied to the memristor, the resistance of the memristor can be changed, the memristor has a positive threshold voltage and a negative threshold voltage, and when the voltage at the two ends of the memristor is larger than the positive threshold voltage or smaller than the negative threshold voltage, the resistance of the memristor can be reduced or increased. Meanwhile, when the external input voltage signal is smaller than the positive threshold voltage of the memristor or larger than the negative threshold voltage of the memristor, the resistance value of the memristor is not changed along with the external input. Therefore, when the difference between the input weighted sum of the input layer and the reference voltage is large at the initial moment, the magnitude of Δ V obtained by the voltage differentiator (the magnitude of Δ V can be set by itself) is enough to enable the output layer to transmit the self-learning signal to the input layer, and the self-learning signal is set to be greater than the positive threshold voltage or less than the negative threshold voltage, and the self-learning signal adjusts the resistance value of the memristor in the input layer. And as the resistance value of the memristor is reduced or increased, the difference value delta V between the input weighted sum and the reference voltage is gradually reduced, when the delta V is reduced to a value which is not enough for the output layer to transmit the self-learning signal to the input layer, the self-learning is ended, and the resistance value of the memristor stops changing.
Drawings
Fig. 1 is a structural diagram of an improved Elman neural network learning algorithm.
FIG. 2 is a memristor self-learning circuit based on an Elman neural network learning algorithm.
FIG. 3 is a schematic diagram of a memristor self-learning circuit of a negative signal input channel.
FIG. 4 is a schematic diagram of a memristor self-learning circuit of a positive signal input channel.
FIG. 5 is a diagram of the circuit simulation results when the negative signal input channel has a receiving layer.
FIG. 6 is a diagram of the circuit simulation results when the negative signal input channel has no receiving layer.
FIG. 7 is a diagram of the results of a circuit simulation with a receiving layer for the positive signal input channel.
FIG. 8 is a diagram of the circuit simulation results when the positive signal input channel has no receiving layer.
Detailed Description
In order to make the technical scheme, the purpose and the advantages of the invention clearer and clearer, the invention is further described in detail with reference to the accompanying drawings.
As shown in FIG. 2, the invention provides a memristor self-learning circuit based on an Elman neural network learning algorithm, which comprises a positive signal input channel and a negative signal input channel. Wherein each signal input channel includes an input layer, a receiving layer, and an output layer.
FIG. 3 is a schematic diagram of a memristor self-learning circuit of a negative signal input channel. In the NMOS transistor Q 1 -Q m+1 AND memristor M 11 -M 1m+1 In the input layer module, an external input V 1 -V m+1 Are respectively connected with NMOS tube Q 1 -Q m+1 Source connection of Q 1 -Q m+1 Drain and memristor M 11 -M 1m+1 In addition, an NMOS tube Q 1 -Q m+1 Drain and memristor M 11 -M 1m+1 The connecting line between the positive electrodes and the output layer intersect at the fifteenth node 15 to the eighteenth node 18, respectively, and the self-learning signal from the output layer passes through the fifteenth node 15 to the eighteenth node 18 and M 11 -M 1m+1 Is connected to the positive electrode. M +1 external input and self-learning signals pass through M 11 -M 1m+1 And then meets the feedback current signal from the receiving layer feedback network at the first node 1.
In FIG. 3, the receiving layer module is controlled by the timing control signal V ct1 Resistance N a1 -N a8 Operational amplifier A 1 -A 3 And MOS transistor D 3 -D 8 And (4) forming. Wherein, the resistance N a2 And operational amplifier a 1 Forming a voltage converter; resistance N a3 And N a4 And operational amplifier a 2 Forming an inverter; operational amplifier A 3 Reference voltage V p1 (V p1 <0) And a resistor N a5 -N a8 Forming a voltage difference calculator; resistance N a1 MOS transistor D 3 -D 8 And timing control signal V ct1 A feedback network is constructed. The first node 1 is connected to the operational amplifier A 1 The reverse input terminal of (1), resistor N a2 Is positioned between the first node 1 and the second node 2 and is connected with A 1 Is connected to the second node 2. Resistance N a3 At the second sectionBetween the point 2 and the third node 3 and through the third node 3 and A 2 Is connected with the inverting input terminal of the resistor N a4 Between the third node 3 and the fourth node 4, N a4 And A 2 And the output terminal of which is connected to the fourth node 4. Resistance N a5 A resistor N between the fourth node 4 and the fifth node 5 a6 Between the fifth node 5 and ground, a resistor N a5 And a resistance N a6 Intersects the fifth node 5 and is a 3 Is connected with the non-inverting input terminal of the resistor N a7 、N a8 And a reference voltage V p1 The whole formed is accessed into A through the sixth node 6 3 The inverting input terminal of (3), the resistor N a7 Between the sixth node 6 and the seventh node 7 and A 3 And an output terminal thereof is connected to a seventh node 7. A. The 3 Acting in parallel on the input of LF398a and also on D in the feedback network 3 、D 6 A gate electrode of (1). In a feedback network, D 3 、D 4 Transmission gates connected to form a transmission positive feedback signal, D 5 、D 6 Transmission gates connected to form a transmission negative feedback signal, D 3 Drain electrode of (1) and (D) 4 Intersects the tenth node 10, D 3 Source and D of 4 Intersects the eighth node 8 and positively feeds back a signal V f+ Between the eighth node 8 and ground; d 5 Drain electrode of (1) and D 6 Intersects the tenth node 10, D 5 Source and D of 6 Intersects the ninth node 9, and a negative feedback signal V f- Between the ninth node 9 and ground; d 7 And the output of the positive feedback signal transmission gate intersects tenth node 10 8 Intersects the output of the negative feedback signal transmission gate at a tenth node 10 7 Source and D of 8 Are connected to ground, D 4 And D 5 The grid electrodes of the two-way resistor are all grounded, and the resistor N a1 Between the first node 1 and the tenth node 10, D 7 And D 8 Is controlled by a timing control signal V ct1 Provided is a method.
In FIG. 3, the output layer is composed of an operational amplifier A 4 Resistance N a9 -N a11 And a fixed capacitor C a1 And C a2 MOS transistor D 9 -D n+1 Two sample holders LF398a and LF398b and an auxiliary timing signal. Wherein, the DC power supply V L1 、D 9 And N a9 Forming a self-learning signal generator; operational amplifier A 4 And a resistance N a10 And N a11 Forming an inverter; MOS tube D 10 -D n+1 And forming a self-learning signal parallel transmission channel in a parallel connection mode. The output of LF398a summed with the auxiliary timing signal is applied to D 9 Grid of, N a9 Through the eleventh node 11 and D 9 Is connected to the drain of N a9 At D 9 Between the drain of (1) and ground, self-learning signal DC power supply V L1 At D 9 Between the source of (1) and ground, N a10 To a through a twelfth node 12 4 Between the eleventh node 11 and the twelfth node 12, N a11 Through the thirteenth node 13 and A 4 Is located between a twelfth node 12 and a thirteenth node 13, A 4 Is connected via a thirteenth node 13 to an input of LF398b, the output of LF398b being connected in parallel to the self-learning signal transmission channel D 10 -D n+1 Intersects the fourteenth node 14, D 10 -D n+1 Respectively with Q 1 -Q m+1 Cross at the fifteenth node 15 to the eighteenth node 18, the timing control signal V ct2 And D 10 -D n+1 Are connected.
FIG. 4 is a schematic diagram of a memristor self-learning circuit of a positive signal input channel. In the PMOS transistor P 1 -P m+1 AND memristor M 21 -M 2m+1 In the input layer module, an external input V 1 -V m+1 Respectively connected with PMOS transistor P 1 -P m+1 Source connection of P 1 -P m+1 Drain and memristor M 21 -M 2m+1 Is connected to the positive pole of (1), and in addition, a PMOS tube P 1 -P m+1 Drain and memristor M 21 -M 2m+1 The connecting line between the positive electrodes and the output layer are respectively intersected at the thirty-fourth node 34 to the thirty-seventh node 37, and the self-learning signal from the output layer also passes through the thirty-fourth node34 to thirty-seventh nodes 37 and M 21 -M 2m+1 Is connected. M +1 external input or self-learning signals pass through M 21 -M 2m+1 Meets the feedback current signal from the acceptor layer feedback network at a nineteenth node 19.
In FIG. 4, the receiving layer module is controlled by the timing control signal V ct4 Resistance N b1 -N b8 Operational amplifier A 5 -A 7 And MOS transistor H 3 -H 8 And (4) forming. Wherein, the resistance N b2 And operational amplifier a 5 Forming a voltage converter; resistance N b3 And N b4 And operational amplifier a 6 Forming an inverter; operational amplifier A 5 Reference voltage V p2 (V p2 >0) And a resistance N b5 -N b8 Forming a voltage difference calculator; resistance N b1 MOS transistor H 3 -H 8 And timing control signal V ct4 A feedback network is constructed. Nineteenth node 19 has access to A 5 The inverting input terminal of (3), the resistor N b2 Between the nineteenth node 19 and the twentieth node 20 and with A 5 Is connected to the twentieth node 20. Resistance N b3 Between the twentieth node 20 and the twenty-first node 21 and through the twenty-first node 21 and A 6 Is connected to the inverting input terminal of the resistor N b4 Between twenty-first and twenty- second nodes 21, 22, N b4 And A 6 Intersects the twenty-second node 22. Resistance N b5 A resistor N between the twenty-second node 22 and the twenty-third node 23 b6 Between the twentieth node 23 and ground, a resistor N b5 And a resistance N b6 Intersect the twenty-third node 23 and all pass through the twenty-third node 23 and A 7 Is connected with the non-inverting input terminal of the resistor N b8 And a reference voltage V p2 The whole body is positioned between the twenty-fourth node 24 and the ground and accesses A through the twenty-fourth node 24 7 The inverting input terminal of (3), the resistor N b7 Between the twenty-fourth node 24 and the twenty-fifth node 25 and with A 7 Intersects the twenty-fifth node 25. A. The 7 Act on H in parallel 9 Also acts onH in feedback network 3 、H 6 A gate electrode of (1). In the feedback network, H 3 、H 4 Transmission gate connected to form a transmission positive feedback signal, H 5 、H 6 Transmission gates connected to form a transmission negative feedback signal, H 3 Drain electrode of (1) and H 4 Intersects the twenty-eighth node 28, h 3 Source and H 4 Crosses the twenty sixth node 26 and positively feeds back the signal V f+ Between the twenty-sixth node 26 and ground; h 5 Drain electrode of (1) and H 6 Intersects the twenty-eighth node 28, h 5 Source and H 6 Cross over the twenty-seventh node 27 and negatively feeds back the signal V f- Between the twenty-seventh node 27 and ground. H 7 And the output of the positive feedback signal transmission gate intersects at a twenty-eighth node 28 8 Intersects the output of the negative feedback signal transmission gate at a twenty-eighth node 28; h 7 Source and H 8 Is connected to ground, H 4 And H 5 The grid electrodes of the resistors are all grounded, and the resistors N b1 Between the nineteenth node 19 and the twenty-eighth node 28, H 7 And H 8 Is controlled by a timing control signal V ct4 Provided is a method.
In FIG. 4, the output layer is composed of an operational amplifier A 8 Resistance N b9 -N b12 And a fixed capacitor C b1 MOS transistor H 9 -H n+1 And sample and hold unit LF398c and an auxiliary timing signal. Wherein, the DC power supply V L2 、H 9 、H 10 、N b9 And N b10 Forming a self-learning signal generator; operational amplifier A 8 And a resistance N b11 And N b12 Forming an inverter; MOS tube H 10 -H n+1 And forming a self-learning signal parallel transmission channel in a parallel connection mode. Output of the receiving layer acting on H 9 Grid of, N b9 Through the twenty-ninth node 29 and H 9 Is connected to the drain of N b9 At H 9 Between the drain of (1) and ground, H 9 Through a twenty-ninth node 29 and H 10 Are connected to the gate of, N b10 Connected to H through the thirtieth node 30 10 Between the thirtieth node 30 and ground, N b11 Between the thirtieth node 30 and the thirty-first node 31, N b11 To a via a thirty-first node 31 8 Of the inverting input terminal, N b12 Is located between the thirty-first node 31 and the thirty-second node 32 and passes through the thirty-second node 32 and A 8 Are connected to the output terminal of A 8 Is connected via a third twelve-node 32 to the input of the LF398c, the output of the LF398c being connected in parallel to the self-learning signal transmission channel H 10 -H n+1 Cross the thirty-third node 33, H 10 -H n+1 Respectively with P 1 -P m+1 Intersects the nodes thirty-fourth to thirty-seventh nodes 34 to 37, and a timing control signal V ct3 And H 10 -H n+1 Are connected.
FIG. 5 is a diagram of circuit simulation results for a negative signal input channel with a receiving layer, and FIG. 6 is a diagram of circuit simulation results for a negative signal input channel without a receiving layer; FIG. 7 is a diagram showing the simulation results of the circuit when the positive signal input channel has the receiving layer, and FIG. 8 is a diagram showing the simulation results of the circuit when the positive signal input channel does not have the receiving layer. In fig. 5 to 8, 5 memristors are selected as examples for the number of memristors in the input layers of two signal input channels. Comparing fig. 5 with fig. 6, the learning time is 40ms when there is a receptive layer in the negative signal input channel and 50ms when there is no receptive layer; on the one hand, when the receiving layer is present, the output of the negative signal input channel approaches the reference voltage V more quickly p1 On the other hand, the resistance values of 5 memristors in the input layer can be reduced in a shorter time till the output is approximately equal to V p1 The value required. It should be noted that "approximately equal" here indicates that the output and V after the learning of the circuit are completed p1 There will still be an error between them, and the setting of this target error can be adjusted by itself, so the invention is not limited to the specific magnitude of the error. Similarly, comparing fig. 7 with fig. 8, the learning time of the positive signal input channel is 70ms when there is a connected layer, and the learning time is 80ms when there is no connected layer; on the one hand, when the receiving layer exists, the output of the negative signal input channel is fasterGround approaches the reference voltage V p2 On the other hand, the resistance values of 5 memristors in the input layer can be reduced to be approximately equal to V at the output in shorter time p2 The value required.

Claims (7)

1. A memristor self-learning circuit based on an Elman neural network learning algorithm is characterized by comprising a negative signal input channel and a positive signal input channel, wherein each signal input channel comprises an input layer, a carrying layer and an output layer; the memristor self-learning circuit can judge the positive polarity and the negative polarity of an external input signal, further introduce the external input signal with different positive polarities and negative polarities into different input channels, and simultaneously determine whether self-learning is needed or not according to the input weighting of the input layer and the difference value of the reference voltage of the bearing layer; when the self-learning memristor is in an initial moment, the difference value delta V between the input weighted sum of the input layer and the reference voltage of the bearing layer is large, the obtained delta V enables the output layer to transmit a self-learning signal to the input layer, and the self-learning signal can adjust the resistance value of the memristor in the input layer; and as the resistance value of the memristor is reduced or increased, the difference value delta V between the input weighted sum and the reference voltage is gradually reduced, when the delta V is reduced to be insufficient to enable the output layer to transmit the self-learning signal to the input layer, the resistance value of the memristor stops changing, and the self-learning process is ended.
2. The memristor self-learning circuit based on Elman neural network learning algorithm as claimed in claim 1, wherein the input layer of the negative signal input channel is composed of NMOS transistor Q 1 -Q m+1 And memristor M 11 -M 1m+1 Composition, external input V 1 -V m+1 Are respectively connected with NMOS tube Q 1 -Q m+1 Source connection of Q 1 -Q m+1 Drain and memristor M 11 -M 1m+1 In addition, an NMOS tube Q 1 -Q m+1 Drain and memristor M 11 -M 1m+1 The connecting line between the positive electrodes and the output layer respectively intersect at a fifteenth node (15) to an eighteenth node (18), and self-learning signals from the output layer also pass through the fifteenth node (15) to the tenth nodeEight nodes (18) and M 11 -M 1m+1 M +1 external input and self-learning signals pass through M 11 -M 1m+1 Then, the signal is converged with a feedback current signal from a receiving layer feedback network at a first node (1).
3. The self-learning circuit of memristor based on Elman neural network learning algorithm as claimed in claim 1, wherein the accepting layer of the negative signal input channel is controlled by timing control signal V ct1 Resistance N a1 -N a8 Operational amplifier A 1 -A 3 And MOS transistor D 3 -D 8 Forming; wherein, the resistance N a2 And operational amplifier a 1 Forming a voltage converter; resistance N a3 And N a4 And operational amplifier a 2 Forming an inverter; operational amplifier A 3 Reference voltage V p1 (V p1 <0) And a resistance N a5 -N a8 Forming a voltage difference calculator; resistance N a1 MOS transistor D 3 -D 8 And timing control signal V ct1 Forming a feedback network; the first node (1) is connected to an operational amplifier A 1 The reverse input terminal of (1), resistor N a2 Is positioned between the first node (1) and the second node (2) and is connected with A 1 The output end of which is connected to the second node (2); resistance N a3 Is positioned between the second node (2) and the third node (3) and passes through the third node (3) and A 2 Is connected to the inverting input terminal of the resistor N a4 Is positioned between the third node (3) and the fourth node (4), N a4 And A 2 Is connected to the fourth node (4); resistance N a5 A resistor N between the fourth node (4) and the fifth node (5) a6 Between the fifth node (5) and ground, a resistor N a5 And a resistance N a6 Intersects the fifth node (5) and is connected with A 3 Is connected with the non-inverting input terminal of the resistor N a7 、N a8 And a reference voltage V p1 The formed whole is accessed into A through a sixth node (6) 3 The inverting input terminal of (1), the resistor N a7 Is positioned between the sixth node (6) and the seventh node (7) and is connected with A 3 Is connected to a seventh node (7); a. The 3 In parallel with the output ofThe input terminals acting in the form of LF398a also act on D in the feedback network 3 、D 6 A gate of (2); in a feedback network, D 3 、D 4 Transmission gates connected to form a transmission positive feedback signal, D 5 、D 6 Coupled to form transmission gates for transmitting negative feedback signals, D 3 Drain electrode of (1) and D 4 Intersects the tenth node (10), D 3 Source and D of 4 Intersects the eighth node (8) and positively feeds back a signal V f+ Is positioned between the eighth node (8) and ground; d 5 Drain electrode of (1) and (D) 6 Intersects the tenth node (10), D 5 Source and D of 6 Intersects the ninth node (9), and a negative feedback signal V f- Between the ninth node (9) and ground; d 7 Intersects the output of the positive feedback signal transmission gate at a tenth node (10), D 8 Intersects the output of the negative feedback signal transmission gate at a tenth node (10), D 7 Source and D of 8 Are connected to ground, D 4 And D 5 The grid electrodes of the two-way resistor are all grounded, and the resistor N a1 Between the first node (1) and the tenth node (10), D 7 And D 8 Is controlled by a timing control signal V ct1 Provided is a method.
4. The memristor self-learning circuit based on Elman neural network learning algorithm as claimed in claim 1, wherein the output layer of the negative signal input channel is composed of operational amplifier A 4 Resistance N a9 -N a11 And a fixed capacitor C a1 、C a2 MOS transistor D 9 -D n+1 And sample and hold devices LF398a, LF398b and an auxiliary timing signal; wherein, the DC power supply V L1 、D 9 And N a9 Forming a self-learning signal generator; operational amplifier A 4 And a resistor N a10 And N a11 Forming an inverter; MOS tube D 10 -D n+1 Forming a self-learning signal parallel transmission channel in a parallel connection mode; the output of LF398a summed with the auxiliary timing signal is applied to D 9 Grid of, N a9 Through the eleventh node (11) and D 9 Of the drain electrodeTo each other, N a9 At D 9 Between the drain of (1) and ground, self-learning signal DC power supply V L1 At D 9 Between the source of (1) and ground, N a10 Is connected to A through a twelfth node (12) 4 Is located between an eleventh node (11) and a twelfth node (12), N a11 Through a thirteenth node (13) and A 4 Is connected and is located between a twelfth node (12) and a thirteenth node (13), A 4 Is connected via a thirteenth node (13) to an input of the LF398b, the output of the LF398b being connected in parallel to the self-learning signal transmission channel D 10 -D n+1 Intersects a fourteenth node (14), D 10 -D n+1 Respectively with Q 1 -Q m+1 Intersects at a fifteenth node (15) to an eighteenth node (18), a timing control signal V ct2 And D 10 -D n+1 Are connected.
5. The memristor self-learning circuit based on Elman neural network learning algorithm as claimed in claim 1, wherein the input layer of the positive signal input channel is composed of PMOS tube P 1 -P m+1 And memristor M 21 -M 2m+1 Composition, external input V 1 -V m+1 Respectively connected with PMOS transistor P 1 -P m+1 Source connection of (2), P 1 -P m+1 Drain and memristor M 21 -M 2m+1 Is connected to the positive pole of (1), and in addition, a PMOS tube P 1 -P m+1 Drain and memristor M 21 -M 2m+1 The connecting line between the positive electrodes and the output layer are respectively intersected at the thirty-fourth node (34) to the thirty-seventh node (37), and the self-learning signal from the output layer also passes through the thirty-fourth node (34) to the thirty-seventh node (37) and the M 21 -M 2m+1 The positive electrode of (1) is connected; m +1 external input or self-learning signals pass through M 21 -M 2m+1 And a feedback current signal from the receiving layer feedback network is converged at a nineteenth node (19).
6. Memristor based on Elman neural network learning algorithm according to claim 1The self-learning circuit is characterized in that the receiving layer of the positive signal input channel is controlled by a time sequence control signal V ct4 Resistance N b1 -N b8 Operational amplifier A 5 -A 7 And MOS tube H 3 -H 8 Forming; wherein, the resistance N b2 And operational amplifier a 5 Forming a voltage converter; resistance N b3 And N b4 And operational amplifier a 6 Forming an inverter; operational amplifier A 5 Reference voltage V p2 ((V p2 >0) And resistance N) b5 -N b8 Forming a voltage difference calculator; resistance N b1 MOS transistor H 3 -H 8 And timing control signal V ct4 Forming a feedback network; nineteenth node (19) access A 5 The inverting input terminal of (1), the resistor N b2 Is positioned between the nineteenth node (19) and the twentieth node (20) and is connected with A 5 Is connected to the twentieth node (20); resistance N b3 Is positioned between the twentieth node (20) and the twenty-first node (21) and passes through the twenty-first node (21) and A 6 Is connected to the inverting input terminal of the resistor N b4 Between twenty-first (21) and twenty-second (22) nodes, N b4 And A 6 Intersects the twenty-second node (22); resistance N b5 Is positioned between the twenty-second node (22) and the twenty-third node (23), and a resistor N b6 A resistor N between the twenty-third node (23) and ground b5 And a resistance N b6 Intersect at the twenty-third node (23) and pass through the twenty-third node (23) and A 7 Is connected with the non-inverting input terminal of the resistor N b8 And a reference voltage V p2 The whole body is positioned between the twenty-fourth node (24) and the ground and accesses A through the twenty-fourth node (24) 7 The inverting input terminal of (1), the resistor N b7 Is positioned between the twenty-fourth node (24) and the twenty-fifth node (25) and is connected with A 7 Intersects the twenty-fifth node (25); a. The 7 Act on H in parallel 9 Is also applied to H in the feedback network 3 、H 6 A gate electrode of (1); in the feedback network, H 3 、H 4 Connected to form a transmission gate for transmitting a positive feedback signal, H 5 、H 6 Transmission gates connected to form a transmission negative feedback signal, H 3 Drain electrode of (1) and H 4 Intersects the twenty-eighth node (28), H 3 Source and H 4 Intersects the twenty-sixth node (26) and positively feeds back a signal V f+ Between the twenty-sixth node (26) and ground; h 5 Drain electrode of (1) and H 6 Intersects at a twenty-eighth node (28), H 5 Source and H 6 Intersects the twenty-seventh node (27), and a negative feedback signal V f- Between the twenty-seventh node (27) and ground; h 7 Intersects the output of the positive feedback signal transmission gate at a twenty-eighth node (28), H 8 Intersects the output of the negative feedback signal transmission gate at a twenty-eighth node (28); h 7 Source and H 8 Are connected to ground, H 4 And H 5 The grid electrodes of the two-way resistor are all grounded, and the resistor N b1 Between the nineteenth node (19) and the twenty-eighth node (28), H 7 And H 8 Is controlled by a timing control signal V ct4 Provided is a method.
7. The memristor self-learning circuit based on Elman neural network learning algorithm as claimed in claim 1, wherein the output layer of the positive signal input channel is composed of an operational amplifier A 8 Resistance N b9 -N b12 And a fixed capacitor C b1 MOS transistor H 9 -H n+1 And a sample-and-hold unit LF398c and an auxiliary timing signal; wherein, the DC power supply V L2 、H 9 、H 10 、N b9 And N b10 Forming a self-learning signal generator; operational amplifier A 8 And a resistance N b11 And N b12 Forming an inverter; MOS tube H 10 -H n+1 Forming a self-learning signal parallel transmission channel in a parallel connection mode; output of the receiving layer acting on H 9 Grid of (2), N b9 Through twenty-ninth node (29) and H 9 Is connected to the drain of N b9 Is located at H 9 Between the drain of (1) and ground, H 9 Through a twenty-ninth node (29) and H 10 Are connected to the gate of, N b10 Through the thirdTen nodes (30) are connected to H 10 And between the thirtieth node (30) and ground, N b11 Between the thirtieth node (30) and the thirty-first node (31), N b11 Is connected to A through a thirty-first node (31) 8 Of the inverting input terminal, N b12 Is positioned between the thirty-first node (31) and the thirty-second node (32) and passes through the thirty-second node (32) and A 8 Are connected to the output terminal of A 8 Is connected via a third twelfth node (32) to an input of the LF398c, the output of the LF398c being connected in parallel to the self-learning signal transmission channel H 10 -H n+1 Is intersected at a thirty-third node (33), H 10 -H n+1 Respectively with P 1 -P m+1 Intersects the nodes thirty-fourth (34) to thirty-seventh (37), a timing control signal V ct3 And H 10 -H n+1 Are connected.
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