CN110059816B - Memristor-based neural network unit circuit - Google Patents
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Abstract
The invention discloses a neural network unit circuit based on a memristor in the technical field of neural networks, and aims to solve the problems of low speed and high power consumption of the existing neural network operation process based on hardware devices such as a traditional CPU (Central processing Unit), a GPU (graphics processing Unit), an FPGA (field programmable Gate array), an ASIC (application specific Integrated Circuit) and the like. The neural network unit circuit based on the memristor comprises a memristor processing circuit, a subtracter circuit and a weight operation circuit; the memristor processing circuit performs weighting operation on the transmitted voltage signal and outputs the weighted voltage signal; the subtractor circuit performs subtraction operation on the weighted information elements of the memristor processing circuit and sends the obtained effective information elements to the weight operation circuit; the weight arithmetic circuit adds the information elements processed by the subtracter circuit and transmits the information elements to the next-stage unit circuit. Compared with a transistor, the memristor device has a simpler two-terminal structure, is convenient to integrate, has higher conversion speed and lower power consumption, and can be compatible with a traditional CMOS device.
Description
Technical Field
The invention belongs to the technical field of neural networks, and particularly relates to a neural network unit circuit based on a memristor.
Background
A memristor is a nonlinear two-terminal device that represents the relationship between magnetic flux and charge, having the dimension of resistance, but the resistance is determined by the amount of charge flowing through it, and thus has the effect of memorizing the amount of charge flowing through. The memristor serving as a novel electronic device has a simpler two-end structure compared with a traditional CMOS (complementary metal oxide semiconductor) process, so that the memristor has stronger expandability and 3D stacking capacity to a certain extent, and can realize high-density storage by adopting a cross array structure. Due to the small size of the memristor, electrons in the memristor have higher speed and lower power consumption and can be compatible with the traditional CMOS device. Meanwhile, the memristors have abundant specific resistance values which are very similar to those of nerve synapses, and synaptic plasticity refers to that the connection strength of synapses is gradually strengthened or weakened along with the migration of ions in presynaptic membranes to postsynaptic membranes or the backflow of ions to presynaptic membranes caused by different stimuli. Similarly, the resistance value of the memristor can be gradually tuned under external stimulation due to the directional migration of internal ions under voltage, and the memristor has great similarity with the plasticity of biological protrusions, so that the memristor has a great application prospect in the aspect of neural networks. Due to the characteristics of synapse similarity, nonvolatility, expandability, nanoscale size, low power consumption and the like of the memristor, the memristor is expected to become a novel artificial electronic synapse and plays a role in construction of a bionic neural network, and therefore the problem that the memristor resistor is difficult to integrate into the neural network due to the fact that the memristor resistor cannot present a negative resistance state also becomes a problem which needs to be solved urgently.
The artificial neural network is used for processing a neural network algorithm by utilizing a special hardware circuit. At present, hardware implementation of the neural network depends on traditional hardware devices such as a CPU, a GPU, an FPGA, an ASIC and the like, however, the speed of the neural network of the hardware devices is low in the operation process, the power consumption is high, and more large-scale artificial neural networks put forward more strict requirements on hardware and performance of the hardware devices.
Disclosure of Invention
The invention aims to provide a neural network unit circuit based on a memristor, and aims to solve the problems that in the prior art, the speed of a neural network operation process based on hardware devices such as a traditional CPU (Central processing Unit), a GPU (graphics processing Unit), an FPGA (field programmable Gate array), an ASIC (application specific Integrated Circuit) and the like is low, and the power consumption is high.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows: a neural network unit circuit based on a memristor comprises a memristor processing circuit, a subtracter circuit and a weight operation circuit; the memristor processing circuit performs weighting operation on the transmitted voltage signal and outputs the weighted voltage signal; the subtractor circuit calculates the voltage signal weighted by the memristor processing circuit and sends the obtained effective information element to the weight calculation circuit; and the weight calculation circuit adds the information elements processed by the subtractor circuit and transmits the information elements to the next-stage unit circuit.
The memristor processing circuit comprises a plurality of memristor resistors, and positive resistance states and negative resistance states of the memristor resistors correspond to positive values and negative values of weights.
The current generated by the voltage input end in the memristor processing circuit is respectively connected with two memristor branches with opposite polarities, and each branch is respectively connected with a memristor with opposite polarity to the memristor of the branch close to the voltage input end and then grounded, so that the voltage values of the two memristors connected with the grounding end are output.
The voltage value output by the memristor processing circuit is the voltage of each added term obtained by weighting.
The weight value corresponding to the memristor processing circuit is (-1, 1).
The effective information element is a weight unit which is obtained by the operation of a subtracter and contains positive and negative terms.
The weight computing circuit is an in-phase adder or a reverse-phase adder.
Compared with the prior art, the invention has the following beneficial effects:
(1) compared with a transistor, the memristor device has a simpler two-end structure, is convenient to integrate, has higher conversion speed and lower power consumption, and can be compatible with a traditional CMOS device;
(2) the memristor adopted in the invention is used as a novel two-end resistive device, the resistance of the memristor can be continuously modulated by voltage, so that the resistance value can continuously change along with the change of the voltage when receiving stimulation, and the synaptic plasticity shown by the current response influenced by the accumulated charges can show that different stimulation is obtained to different voltage values in the circuit;
(3) the unit circuit can be modulated to different weight states under different stimuli due to the modulation effect of the resistance value of the internal memristor, and compared with a traditional binary neural network, the unit circuit can obtain richer response, so that the information processing is carried out more efficiently;
(4) the invention provides a circuit connection mode of a memristor capable of presenting a negative resistance state, and solves the problem that the memristor resistance is difficult to integrate into a neural network because the memristor resistance cannot present the negative resistance state.
Drawings
FIG. 1 is a memristor processing circuit schematic diagram of a memristor-based neural network cell circuit provided by an embodiment of the present invention;
FIG. 2 is a subtractor schematic diagram of a memristor-based neural network cell circuit provided by an embodiment of the present invention;
FIG. 3 is a schematic diagram of a weight calculation circuit of a memristor-based neural network unit circuit according to an embodiment of the present disclosure;
FIG. 4 is a circuit schematic diagram of a memristor-based neural network cell provided by an embodiment of the present invention;
FIG. 5 is a schematic diagram of a neural network model composed of memristor-based neural network unit circuits according to an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
As shown in fig. 4, the neural network unit circuit based on the memristor includes a memristor processing circuit, a subtractor circuit, and a weight operation circuit; the memristor processing circuit performs weighting operation on the transmitted voltage signal and outputs the weighted voltage signal; the subtractor circuit calculates the voltage signal weighted by the memristor processing circuit and sends the obtained effective information element to the weight calculation circuit; the weight calculation circuit 3 adds the information elements processed by the subtractor circuit and transmits the added information elements to the next stage unit circuit.
As shown in fig. 1, the memristor processing circuit is formed by connecting a certain number of memristors with each other, and the resistance values of the memristors can be modulated by voltage signals applied to both ends of the memristors. In the neural network circuit, because the weights in the neural network have positive and negative weights, according to the principle of memristor resistance modulation, the current generated by the control voltage input end in the circuit is dividedThe positive and negative problems of the weight are solved by connecting two memristor branches with opposite polarities, respectively connecting one memristor with the opposite polarity to the memristor of the branch close to the voltage input end to be grounded on each branch, and outputting the voltage values of the two memristors connected with the ground terminal. As shown in fig. 1, in this embodiment, the memristors M1 and M5 are two memristors with opposite polarities, while the memristors M2 and M1 are opposite polarities, the memristors M4 and M5 are opposite polarities, and the memristor M3 is a memristor connected in parallel with the two memristors at the near-ground end, and outputs a voltage across the two memristors. When the input is a positive voltage V in When M5 is in low resistance state, the potential between M4 and M5 is positive; m1 is high impedance, so the potential between M1 and M2 is zero, and the output is negative. The circuit connection mode effectively solves the problem that the memristor resistance cannot present a negative resistance state and is difficult to integrate into a neural network. When the signal begins to be applied, the resistance values of memristors M1 and M4 are at low resistance (R) on ) State, the resistance of memristors M2 and M5 is at high resistance (R) off ) State when the input stimulation signal is V in The memristor processing circuit can obtain corresponding processing information elements
V o 1＝+u 1 (1)
Or V o 1＝-u 1 (2)
In the formula, V o 1 is the output signal of the memristor processing circuit, + u 1 Represents a positive voltage signal output by the memristor processing circuit in the actual circuit; -u 1 A positive or negative voltage signal representing the output of the memristor processing circuit in the actual circuit; u. of 1 Is given by the stimulus signal V in And determining the modulation resistance state of the memristor to realize the weighting of the information elements in the neural network. Similarly, the output signal V of the memristor processing circuit can be obtained through the method o 2。
As shown in fig. 2, the subtractor circuit is located at the output end of the memristor processing circuit, and the voltage value input to the memristor network port, i.e., the stimulation signal, is subjected to weighting processing by the memristor processing circuit and is sent to the subtractor for operation, so that the voltage value at the output end of the memristor processing circuit is obtained, and subsequent neural network addition operation is facilitated.
From V 0 1 input signal with amplification factor R 3 /R 1 And is connected with the output terminal u o Are in opposite phases, so
u o ＝-R 3 /R 1 ×V 0 1 (3)
In the formula u o Representing the output signal of a subtractor, V 0 1 represents the potential signal at the lower end of M3 in the memristor processing circuit, R 3 Representing the feedback resistance of the subtractor part, R 1 Is represented in an input signal V 0 1 branch resistance.
From V 0 2 input signal with amplification factor of
And is connected with the output terminal u o The phases are the same, so
In the formula u o Representing the output signal of a subtractor, V 0 2 represents a potential signal at the upper end of M3 in the memristor processing circuit, R 4 Representing the resistance to ground of the non-inverting input, R 2 Is represented in an input signal V 0 Resistance of 2 branches, R 3 Representing the feedback resistance of the subtractor part, R 1 Is represented in an input signal V 0 1 branch resistance.
When R is 1 ＝R 2 ＝R 3 ＝R 4 When the temperature of the water is higher than the set temperature,
u o ＝V 0 2-V 0 1 (5)
in the formula u o Representing the output signal of a subtractor, V 0 1 represents the voltage signal at the lower end of M3 in the memristor processing circuit, V 0 2 denotes a potential signal of the upper end of M3 in the memristor processing circuit.
As shown in fig. 3, the weight computing circuit is located at the next stage of the subtractor circuit, and is used for connecting the output ends of different subtractor circuits, and adding the weighted current stimulation signals input to the neural network and outputting the added current stimulation signals. The weight calculation circuit can adopt an in-phase adder or an anti-phase adder, and the embodiment adopts an in-phase adder.
For an adder circuit:
from the "virtual open circuit" we can get:
in the formula u - The voltage of the inverting input end of the operational amplifier is represented, R1 is the grounding resistance of the inverting input end, u is the output signal of the adder, and R3 is the feedback resistance of the adder.
Namely:
also for u + Then there are:
finishing to obtain:
in the formula u + The voltage of the non-inverting input end of the adder is shown, V1 and V2 respectively show different voltage signal values obtained by weighting of the adder, and R2 and R4 respectively show resistances of input signals V1 and V2 branches.
According to the principle of "virtual short circuit". u + ＝u - 。
It is possible to obtain:
when R1 ═ R2 ═ R3 ═ R4, then
u＝V1+V2 (11)。
The overall structure of the neural network unit circuit based on the memristor is shown in fig. 4, the leftmost end is a memristor processing circuit which is responsible for weighting stimulation signals input by the neural network, and the output voltage value is the voltage of each added term obtained through weighting. The middle part is a subtracter circuit which calculates the voltage difference between two ends of the memristor, and the output result is a weighted weight unit containing positive and negative terms. The rightmost end is a weight operation circuit which is mainly used for adding weighted information and carrying out effective integration to realize the processing of multi-channel signals.
Based on the above proposed neural network unit circuit structure based on the memristor, the following explains the specific operation mode and the obtained effect of the neural network unit circuit based on the memristor by taking a neural network of a weight matrix of 2 × 2 as an example.
The 2 x 2 weight matrix comprises 4 memristor weight circuits, each memristor weight circuit corresponds to one weight in the weight matrix, and the weight range corresponding to the memristor weight circuit is (-1,1) according to the characteristics of the memristor.
The four-bit stimulation signal is input into the memristor processing circuit, the signal can be subjected to weighting operation after processing, and two voltage values can be output at two ends of the memristor processing circuit network due to the high-low resistance state and the directivity of the memristor. Further output to the subtractor circuit of the next stage.
The voltage values output by the 4 subtracter circuits are all connected to the weight processing circuit, the input 4 weighted voltage signals are added, and the added result is output.
The neural network unit circuit based on the memristor can realize the construction of a multilayer neural network model in a cascading mode as shown in fig. 5.
The memristor processing circuit can weight different voltage signals corresponding to different weights in the neural network and transmit the weighted voltage signals to the next-stage unit circuit; the signal output by the subtracter circuit is an information element weighted by the memristor network and is sent to a weight operation circuit of the next stage; the weight calculation circuit can add the processed information elements for effective integration, thereby realizing the processing of the multi-channel signals. The processing function of the neural network on the information can be completely realized through the cascade connection.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, it is possible to make various improvements and modifications without departing from the technical principle of the present invention, and those improvements and modifications should be considered as the protection scope of the present invention.
Claims (5)
1. A neural network unit circuit based on a memristor is characterized by comprising a memristor processing circuit, a subtracter circuit and a weight operation circuit;
the memristor processing circuit performs weighting operation on the transmitted voltage signal and outputs the weighted voltage signal;
the subtractor circuit calculates the voltage signal weighted by the memristor processing circuit and sends the obtained effective information element to the weight calculation circuit;
the weight calculation circuit adds the information elements processed by the subtracter circuit and transmits the information elements to the next-stage unit circuit;
the memristor processing circuit comprises a plurality of memristor resistors, and positive resistance states and negative resistance states of the memristor resistors correspond to positive values and negative values of weights;
the current generated by the voltage input end in the memristor processing circuit is respectively connected with two memristor branches with opposite polarities, and each branch is respectively connected with a memristor with opposite polarity to the memristor of the branch close to the voltage input end and then grounded, so that the voltage values of the two memristors connected with the grounding end are output.
2. The memristor-based neural network cell circuit of claim 1, wherein the voltage value output by the memristor processing circuit is the voltage of each of the summed terms resulting from the weighting.
3. The memristor-based neural network cell circuit of claim 1, wherein the weight value corresponding to the memristor processing circuit is (-1, 1).
4. The memristor-based neural network cell circuit as claimed in claim 1, wherein the effective information elements are weight cells containing positive and negative terms obtained by a subtractor operation.
5. The memristor-based neural network cell circuit of claim 1, wherein the weight arithmetic circuit is an in-phase adder or an anti-phase adder.
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| CN109460818A (en) * | 2018-09-25 | 2019-03-12 | 电子科技大学 | A kind of multilayer neural network design method based on memristor bridge and array |
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| CN106845634A (en) * | 2016-12-28 | 2017-06-13 | 华中科技大学 | A kind of neuron circuit based on memory resistor |
| CN109460818A (en) * | 2018-09-25 | 2019-03-12 | 电子科技大学 | A kind of multilayer neural network design method based on memristor bridge and array |
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