CN114997387A - Visual-evoked emotional habituation characteristic neural network circuit - Google Patents

Visual-evoked emotional habituation characteristic neural network circuit Download PDF

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CN114997387A
CN114997387A CN202210751267.9A CN202210751267A CN114997387A CN 114997387 A CN114997387 A CN 114997387A CN 202210751267 A CN202210751267 A CN 202210751267A CN 114997387 A CN114997387 A CN 114997387A
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habituation
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孙军伟
王妍
赵阳
徐远鹏
赵麟豪
陈振
孙策
李闯闯
张静宜
刘鹏
王英聪
凌丹
王延峰
刘娜
雷霆
方洁
余培照
黄春
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Zhengzhou University of Light Industry
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Abstract

The invention provides a vision-induced emotion habituation characteristic neural network circuit which comprises an input signal source, an input module, a logic control module, a habituation module, a strengthening module and a spontaneous recovery module, wherein the input signal source is respectively connected with the input module and the logic control module, the input module is connected with the logic control module, the logic control module is respectively connected with the habituation module, the strengthening module and the spontaneous recovery module, the strengthening module is respectively connected with the habituation module and the spontaneous recovery module, the spontaneous recovery module is connected with the habituation module, and the habituation module outputs fear or happy emotion signals. The invention realizes the habituation of the habituation stimulation under different stimulations, the habituation of the habituation stimulation under the emotional habituation state, and the second emotional habituation and spontaneous recovery after the first emotional habituation and spontaneous recovery. The invention is more consistent with biological characteristics and is beneficial to constructing a more intelligent neural network circuit.

Description

Visual-evoked emotional habituation characteristic neural network circuit
Technical Field
The invention relates to the technical field of neural network circuits, in particular to a visual-evoked emotional habituation characteristic neural network circuit.
Background
Memristors (Memristor), originally proposed in 1971 by professor zeia stubbon, berkeley, university of california, he considered that resistance, capacitance, and inductance represent the relationship between 4 important elements of voltage, current, charge, and magnetic flux in electronics, but an element representing the relationship between charge and magnetic flux is not yet present, and thus named memristors. The hewlett-packard (HP) in 2007 announced that a solid-state memristor was successfully developed by the team leading from Richard Stanley Williams, which formed a two-layer film from inorganic titanium dioxide as the starting material. The memristor can still "remember" the passing charge after power failure, and the similarity between the characteristic and the nerve synapse makes the memristor have the potential of acquiring the autonomous learning function.
Behavioral plasticity establishes a link between information and appropriate behavioral responses, enabling an organism to adjust its own behavior in response to stimuli from the external environment. Habituation is the basic and common form of behavioral plasticity. In neuroscience, a general description of habituation is: "assuming a particular stimulus elicits a response, repeated use of the stimulus results in a decrease in response". In addition, the habituation exhibited 9 parameter features including negative exponential behavior of habituation, spontaneous recovery, stimulation intensity and frequency dependence, habituation removal, habituation below zero, generalization of habituated stimulation, habituation removal.
Habituation of emotional response has an important role in survival and adaptation of individuals. It was found that the positive stimuli-induced emotional responses of any intensity exhibited significant habituation effects, whereas the negative stimuli-induced emotional responses of various intensities exhibited no habituation effects. In addition, research experiments on habituation of the knee flexion reflex and stimulation intensity relationship show that the habituation effect of the low-intensity stimulation is more significant than that of the high-intensity stimulation.
Disclosure of Invention
Aiming at the technical problems that the functions realized by the conventional habituation neural network circuit are single and are not combined with vision and emotion, the invention provides the emotion habituation characteristic neural network circuit induced by vision, which leads to emotion habituation through picture stimulation with different polarities and intensities, realizes habituation and spontaneous recovery, habituation removal and secondary emotion habituation and spontaneous recovery under different stimulation and realizes the emotion habituation characteristic with more comprehensive functions.
In order to achieve the purpose, the technical scheme of the invention is realized as follows: a vision-induced emotion habituation characteristic neural network circuit comprises an input signal source, an input module, a logic control module, a habituation module, a reinforcement module and a spontaneous recovery module, wherein the input signal source is respectively connected with the input module and the logic control module; the input module converts the amplitude and the effective level of an input signal source; the logic control module respectively generates control signals for controlling the habituation module, the strengthening module and the spontaneous recovery module according to the output of the input signal source and the output of the input module; the habituation module realizes the functions of habituation formation, recovery and output; the strengthening module outputs habituation and spontaneous recovery feedback signals according to the received stimulation; the spontaneous recovery module recovers the habituation that has formed when no stimulus is applied.
Preferably, the input signal sources include a positive strong stimulation habituation signal source N1, a positive weak stimulation habituation signal source N2, a positive medium stimulation habituation signal source N3, a negative weak stimulation habituation signal source N4 and a negative medium stimulation habituation signal source N5; the positive strong stimulation habituation signal source N1, the positive weak stimulation habituation signal source N2, the positive medium stimulation habituation signal source N3, the negative weak stimulation habituation signal source N4 and the negative medium stimulation habituation signal source N5 are all connected with the input module, and the positive strong stimulation habituation signal source N1, the positive weak stimulation habituation signal source N2, the positive medium stimulation habituation signal source N3, the negative weak stimulation habituation signal source N4 and the negative medium stimulation habituation signal source N5 are all connected with the logic control module;
the input module comprises a positive strong stimulation habituation removal signal receiving and processing unit, a positive weak stimulation habituation signal receiving and processing unit, a positive medium stimulation habituation signal receiving and processing unit, a negative weak stimulation habituation signal receiving and processing unit and a negative medium stimulation habituation signal receiving and processing unit, wherein a positive strong stimulation habituation removal signal source N1 is connected with the input end of the positive strong stimulation habituation removal signal receiving and processing unit, and the output end of the positive strong stimulation habituation removal signal receiving and processing unit is connected with the logic control module; the positive and weak stimulation habituation signal source N2 is connected with the input end of the positive and weak stimulation habituation signal receiving and processing unit, and the output end of the positive and weak stimulation habituation signal receiving and processing unit is connected with the logic control module; the positive medium stimulation habituation signal source N3 is connected with the input end of the positive medium stimulation habituation signal receiving and processing unit, and the output end of the positive medium stimulation habituation signal receiving and processing unit is connected with the logic control module; the negative weak stimulation habituation signal source N4 is connected with the input end of the negative weak stimulation habituation signal receiving and processing unit, and the output end of the negative weak stimulation habituation signal receiving and processing unit is connected with the logic control module; the negative medium stimulation habituation signal source N5 is connected with the input end of the negative medium stimulation habituation signal receiving and processing unit, and the output end of the negative medium stimulation habituation signal receiving and processing unit is connected with the logic control module;
the positive strong stimulation habituation removal signal receiving and processing unit comprises a first voltage control unit and a same logic gate D1, wherein a positive strong stimulation habituation removal signal source N1 is connected with the input end of the first voltage control unit, the output end of the first voltage control unit is connected with the input end of the same logic gate D1, and the output end of the same logic gate D1 is connected with a logic control module; the positive weak stimulation habituation signal receiving and processing unit comprises a second voltage control unit and a same logic gate D2, wherein a positive weak stimulation habituation signal source N2 is connected with the input end of the second voltage control unit, the output end of the second voltage control unit is connected with the input end of the same logic gate D2, and the output end of the same logic gate D2 is connected with a logic control module; the positive and medium stimulation habituation signal receiving and processing unit comprises a third voltage control unit and a same logic gate D3, wherein a positive and medium stimulation habituation signal source N3 is connected with the input end of the third voltage control unit, the output end of the third voltage control unit is connected with the input end of the same logic gate D3, and the output end of the same logic gate D3 is connected with a logic control module; the negative weak stimulation habituation signal receiving and processing unit comprises a fourth voltage control unit and a same logic gate D4, wherein a negative weak stimulation habituation signal source N4 is connected with the input end of the fourth voltage control unit, the output end of the fourth voltage control unit is connected with the input end of the same logic gate D4, and the output end of the same logic gate D4 is connected with a logic control module; the negative medium stimulation habituation signal receiving and processing module comprises a fifth voltage control unit and a same logic gate D5, wherein a negative medium stimulation habituation signal source N5 is connected with the input end of the fifth voltage control unit, the output end of the fifth voltage control unit is connected with the input end of the same logic gate D5, and the output end of the same logic gate D5 is connected with the logic control module.
Preferably, the logic control module comprises a summation module, a habit removal control module and a reinforcement and recovery control module, wherein the output end of the input module is respectively connected with the input ends of the summation module and the habit removal control module, and the input signal source is respectively connected with the input ends of the summation module and the reinforcement and recovery control module; the positive strong stimulation habituation removing signal source N1 is connected with the input end of the spontaneous recovery module, and the positive weak stimulation habituation signal source N2, the positive medium stimulation habituation signal source N3, the negative weak stimulation habituation signal source N4 and the negative medium stimulation habituation signal source N5 are connected with the input end of the summation module; the input end of the habituation removal control module is connected with the output end of the positive strong stimulation habituation removal signal receiving and processing unit of the input module, the output ends of the positive weak stimulation habituation signal receiving and processing unit, the positive medium stimulation habituation signal receiving and processing unit, the negative weak stimulation habituation signal receiving and processing unit and the negative medium stimulation habituation signal receiving and processing unit of the input module are connected with the input end of the summation module, and the output end of the summation module is connected with the input ends of the habituation control module and the habituation control module respectively; the output ends of the habituation removal control module and the habituation control module are connected with the input end of the habituation module, and the output ends of the reinforcement and recovery control module are respectively connected with the input ends of the reinforcement module and the spontaneous recovery module.
Preferably, the habit removing control module comprises a same logic gate D6, a same logic gate D7 and a voltage control switch S6, the input voltages of the input ends of the same logic gate D6 and the same gate D7 and the controlled voltage side of the voltage control switch S6 are all connected with the output end of the positive strong stimulation habit removing signal receiving processing unit of the input module, the output ends of the same logic gate D6, the same logic gate D7 and the voltage control switch S6 are all connected with the input end of the habit removing module, the output end of the same logic gate D7 is connected with the positive input end of the voltage control switch S6, and the negative input end of the voltage control switch S6 is grounded;
the system comprises a plurality of habituation control modules and a plurality of habituation control modules, wherein each habituation control module comprises a first summing module and a second summing module, the input end of the first summing module is respectively connected with the output ends of a positive weak stimulation habituation signal receiving and processing unit and a positive medium stimulation habituation signal receiving and processing unit of an input module, the input end of the second summing module is respectively connected with the output ends of a negative weak stimulation habituation signal receiving and processing unit and a negative medium stimulation habituation signal receiving and processing unit of the input module, the output ends of the first summing module and the second summing module are respectively connected with a sixth summing module, the output end of the sixth summing module is respectively connected with a habituation control module and a strengthening module, and the output ends of the second summing module and the first summing module are respectively connected with the habituation module;
the habitual control module comprises an identity logic gate D10, an identity logic gate D12, an AND gate D13, a NOT gate D14, a voltage-controlled switch S7 and a seventh summing module, wherein the output end of the sixth summing module is respectively connected with the input ends of an identity logic gate D10, an identity logic gate D12 and one input end of the seventh summing module, the output end of the reinforced and recovery control module is connected with the input end of a NAND gate D14 of an AND gate D16, the output ends of the identity logic gate D12 and the NOT gate D14 are both connected with the input ends of a AND gate D13, the positive input end of the voltage-controlled switch S7 is connected with the output end of the AND gate D13, and the negative input end of the voltage-controlled switch S7 is grounded; the other input end of the seventh summing module is connected with the output end of the strengthening module, the output end of the seventh summing module is connected with the input end of the controlled voltage side of the voltage-controlled switch S7, the input end of the same logic gate D9 is connected with the output end of the first summing module, and the output ends of the same logic gate D9, the same logic gate D10 and the controlled voltage side of the voltage-controlled switch S7 are connected with the habituation module;
the positive weak stimulation habituation signal source N2 is connected with one input end of a third summing module, the other input end of the third summing module is connected with a positive medium stimulation habituation signal source N3, a negative weak stimulation habituation signal source N4 is connected with one input end of a fourth summing module, the other input end of the fourth summing module is connected with a negative medium stimulation habituation signal source N5, the output end of the third summing module is connected with one input end of a fifth summing module, the other input end of the fifth summing module is connected with the output end of the fourth summing module, and the output end of the fifth summing module is connected with the input end of a same logic gate D19 in the strengthening and restoring control module;
the strengthening and recovering control module comprises a third summing module, a fourth summing module, a fifth summing module, a NOT gate D15, a NOT gate D17, a NOT gate D20, a NOT gate D22, a same logic gate D19, a same logic gate D21, an AND gate D16, an AND gate D18, a D flip-flop DFF1 and a sixth voltage control unit, a positive strong stimulation habituation signal source N1 is respectively connected with the CLK end of the D flip-flop DFF1 and the input end of the NOT gate D15, and the D end of the D flip-flop DFF1 is connected with the D end of the D flip-flop DFF1
Figure DEST_PATH_IMAGE001
The end is connected, the input end of the NOT gate D17 is connected with the Q end of the D trigger, and the output end of the NOT gate D17 is connected with the input end of the AND gate D18; the output end of the fifth summation module is connected with the input end of a same logic gate D19, the output end of the same logic gate D19 is connected with the input end of a NAND gate D20, the output end of a not gate D20 is connected with the input end of an AND gate D18, the output ends of the not gate D15 and the AND gate D18 are connected with the input end of an AND gate D16, the output end of the AND gate D16 is respectively connected with the input end of a sixth voltage control unit, the input end of a not gate D14 in the habituation control module, the input end of the same logic gate D21, the reinforcement module and the spontaneous recovery module, and the output end of the fifth summation module is connected with the input end of a sixth voltage control unit, the input end of a not gate D14 in the habituation control module, the input end of a reinforcement module and the spontaneous recovery moduleThe input end and the output end of the controlled voltage side of the six voltage control unit are connected with the spontaneous recovery module, the output end of the fourth summation module is connected with the input end of the NAND gate D22, and the output ends of the NOT gate D22 and the same logic gate D21 are connected with the input end of the reinforcement module.
Preferably, the habituation module comprises a habituation synapse module and a habituation output module, the output ends of the habituation removal control module and the habituation control module in the logic control module are both connected with the habituation synapse module, the output ends of the habituation removal control module and the habituation control module are both connected with the habituation output module, the habituation synapse module is connected with the habituation output module, and the habituation output module outputs the fear signal N6 or the happy emotion signal N7.
Preferably, the habituation synapse module comprises a memristor M1, an NMOS transistor T1, an NMOS transistor T2 and a first proportion module, an output terminal of a controlled voltage side of a voltage-controlled switch S6 of the habituation-removing control module is connected with a positive terminal of the memristor M1 and a drain of the NMOS transistor T2 respectively, an output terminal of a same logic gate D6 is connected with a gate of the NMOS transistor T1, an output terminal of the same logic gate D10 of the habituation-removing control module is connected with a gate of the NMOS transistor T2, an output terminal of the voltage-controlled switch S7 of the habituation-removing control module is connected with a negative terminal of the memristor M1, a positive terminal of the memristor M1 is connected with a drain of the NMOS transistor T2, a negative terminal of the NMOS transistor M1 is connected with a drain of the NMOS transistor T1, a source of the NMOS transistor T1 is connected with the first proportion module, and a resistor R35 is connected in parallel with a capacitor C1; the source electrode of the NMOS tube T2 is connected with the first proportional module;
the habituation output module comprises a voltage-controlled switch S9, a voltage-controlled switch S11, a seventh voltage-controlled unit, an eighth summation module, a first difference module, a second difference module and a second proportion module, wherein the output end of a same logic gate D7 of the habituation removal control module is respectively connected with the positive input end of the voltage-controlled switch S9 and the input end of the seventh voltage-controlled unit, the output end of the same logic gate D9 of the habituation control module is connected with the positive input end of the voltage-controlled switch S11, the negative input ends of the voltage-controlled switch S9 and the voltage-controlled switch S11 are both grounded, the input ends of the controlled voltage sides of the voltage-controlled switch S9 and the voltage-controlled switch S11 are both connected with the output end of the first proportion module of the habituation synapse module, the output end of the voltage-controlled switch S9 is respectively connected with one end of a resistor R40 and one input end of the first difference module, the output end of the controlled voltage-controlled voltage side of the voltage-controlled switch S11 is connected with one end of a resistor R41 and one input end of the second proportion module, the other ends of the resistor R40 and the resistor R41 are both grounded; the output end of the seventh voltage control unit is connected with the other input end of the first difference module, the input end of the eighth summing module is respectively connected with the output ends of the first difference module and the second proportion module, the output end of the eighth summing module is connected with one input end of the second difference module, the other input end of the second difference module is connected with the output end of the third proportion module in the reinforcement module, and the output end of the second difference module is a happy emotion signal N7; the input end of the eighth voltage control unit is connected with the output end of the same logic gate D8 in the habituation control module, the input end of the controlled voltage side of the eighth voltage control unit is connected with the output end of the first proportion module in the habituation synapse module, and the output end of the controlled voltage side of the eighth voltage control unit is a fear emotion signal N6.
Preferably, the strengthening module comprises a rate change module, a habituation feedback module and a spontaneous recovery feedback module, an input end of the rate change module is connected with an output end of the recovery control module of the strengthening and logic control module, an output end of the rate change module is respectively connected with input ends of the habituation feedback module and the spontaneous recovery feedback module, an output end of the habituation feedback module is connected with an input end of the habituation control module of the logic control module, and an output end of the spontaneous recovery feedback module is connected with the spontaneous recovery module. The rate change module outputs a feedback signal according to the habituated stimulation signal applied before; the habituation feedback module amplifies the output of the rate change module and feeds the output back to the habituation signal source; the spontaneous recovery feedback module amplifies the output of the rate change module and feeds back the amplified output to the spontaneous recovery module to be used as a spontaneous recovery signal source;
the spontaneous recovery module comprises a voltage comparison module, a starting module and a recovery voltage module, the voltage comparison module is connected with the logic control module and the habituation module, the starting module is connected with the logic control module, and the recovery voltage module is respectively connected with the voltage comparison module, the starting module, the logic control module and the reinforcement module. The voltage comparison module stops outputting signals to the recovery voltage module when the resistance value of the memristor M1 of the habituation synapse module of the habituation module is recovered to the initial value 1K; the starting module generates a 0.09S pulse signal at the spontaneous recovery starting moment to enable the voltage comparison module to function at the spontaneous recovery starting moment; the recovery voltage module applies a spontaneous recovery voltage to the habituation module.
Preferably, the rate change module includes a ninth voltage control unit, a tenth voltage control unit, a ninth summation module, a third difference module and an NMOS transistor T3, an output terminal of the not gate D22 of the logic control module is connected to the positive input terminals of the ninth voltage control unit and the tenth voltage control unit, respectively, an output terminal of the same logic gate D19 of the reinforcement and recovery control module is connected to the input terminal of the controlled voltage side of the ninth voltage control unit, an output terminal of the same logic gate D21 of the reinforcement and recovery control module is connected to one input terminal of the ninth summation module and the input terminal of the controlled voltage side of the tenth voltage control unit, respectively, an output terminal of the controlled voltage side of the ninth voltage control unit is connected to the other input terminal of the ninth summation module, an output terminal of the controlled voltage side of the tenth voltage control unit is connected to the gate of the NMOS transistor T3, and an output terminal of the ninth summation module is connected to one input terminal of the third difference module, the other input end of the third difference calculating module is connected with the positive pole of a power supply V7, and the negative pole of the power supply V7 is grounded; the output end of the third difference finding module is connected with the drain electrode of an NMOS tube T3, the source electrode of the NMOS tube T3 is respectively connected with the input ends of the habituation feedback module and the spontaneous recovery feedback module and one end of a capacitor C3, and the other end of the capacitor C3 is grounded;
the habituation feedback module comprises a voltage control switch S13 and a third proportion module, wherein the output of a habituation control module of the logic control module, which is the same as a logic gate D11, is connected with the positive input end of a voltage control switch S13, the negative input end of the voltage control switch S13 is grounded, the source of an NMOS (N-channel metal oxide semiconductor) tube T3 is connected with the input end of the controlled voltage side of a voltage control switch S13, the output end of the voltage control switch S13 is connected with the input end of the third proportion module, and the output end of the third proportion module is connected with the other input end of a seventh summation module in the habituation control module;
the spontaneous recovery feedback module comprises a voltage control switch S14 and a fourth proportion module, the output end of an AND gate D16 in the strengthening and recovery control module is connected with the positive input end of a voltage control switch S14, the negative input end of the voltage control switch S14 is grounded, the source electrode of an NMOS (N-channel metal oxide semiconductor) tube T3 is connected with the input end of the controlled voltage side of the voltage control switch S14, the output end of the controlled voltage side of the voltage control switch S14 is connected with the input end of the fourth proportion module, and the output end of the fourth proportion module is connected with the spontaneous recovery module.
Preferably, the voltage comparison module includes a voltage-controlled switch S17, a diode, a fifth proportion module, a fourth difference module, a tenth summation module, an NMOS transistor T4, a PMOS transistor T5, and a same logic gate D23, an output terminal of the and gate D16 of the logic control module is connected to a positive input terminal of the voltage-controlled switch S17, a negative terminal of a memristor M1 in the habitual synapse module of the habitual module is connected to an input terminal of the voltage-controlled switch S17 on a controlled voltage side, and an output terminal and a negative input terminal of the voltage-controlled switch S17 on the controlled voltage side are both grounded; the output end of a controlled voltage side of a voltage-controlled switch S6 of a sixth voltage-controlled unit of the strengthening and recovering control module is respectively connected with the input end of a diode and one end of a resistor R77, the output end of the diode is connected with the input end of a fifth proportion module, the other end of the resistor R77 is respectively connected with the positive electrode end of a memristor M1 and the grid electrode of an NMOS tube T4 in the habituation module, the output end of the fifth proportion module is respectively connected with one input end of a fourth differencing module, one input end of a tenth summing module and one end of a resistor R86, the other input end of the fourth differencing module is connected with the positive electrode of a power supply V8, the other input end of the tenth summing module is connected with the positive electrode of a power supply V9, and the negative electrodes of the power supply V8 and the power supply V9 are both grounded; the output end of the fourth difference calculating module is connected with the source electrode of an NMOS transistor T4, the output end of the tenth difference calculating module is connected with the source electrode of a PMOS transistor T5, the drain electrode of the NMOS transistor T4 is connected with the other end of a resistor R86 and the grid electrode of the PMOS transistor T5, the drain electrode of the PMOS transistor T5 is connected with one end of a resistor R87 and the input end of a logic gate D23, and the other end of the resistor R87 is grounded; the output end of the same logic gate D23 is connected with the input end of the recovery voltage module;
the starting module comprises an eleventh voltage control unit and a fifth difference module, the output end of an AND gate D16 of the strengthening and recovering control module is respectively connected with the input end and the positive input end of the controlled voltage side of the eleventh voltage control unit and one input end of the fifth difference module, the output end of the controlled voltage side of the eleventh voltage control unit is connected with the other input end of the fifth difference module, and the output end of the fifth difference module is connected with the input end of the recovering voltage module;
the recovery voltage module includes a voltage controlled switch S19, an output end of a same logic gate D23 of the voltage comparison module is connected with one input end of the eleventh summation module, an output end of a fifth difference-finding module of the starting module is connected with the other input end of the eleventh summation module, an output end of the eleventh summation module is connected with a positive input end of a voltage-controlled switch S19, a negative input end of the voltage-controlled switch S19 is grounded, an output end of a controlled voltage side of the voltage-controlled switch S19 is connected with an input end of a controlled voltage side of a sixth voltage-controlled unit of the strengthening and restoring control module, one input end of the twelfth summation module is connected with an output end of a fourth proportion module in the spontaneous restoring feedback module of the strengthening module, the other input end of the twelfth summation module is connected with a positive electrode of a power supply V10, and a negative electrode of the power supply V10 is grounded; the output end of the twelfth summing module is connected with the input end of the controlled voltage side of the voltage-controlled switch S19.
Preferably, the output end of the first summation module is connected with the input end of a same logic gate D8, and the output end of a same logic gate D8 is connected with the habituation module; the output end of the second summation module is connected with a same logic gate D9, and the same logic gate D9 is connected with a habituation module;
the source electrode of the NMOS transistor T1 is respectively connected with one end of a resistor R35 and one end of a capacitor C1, and the resistor R36 is connected with the capacitor C2 in parallel; the source electrode of the NMOS tube T2 is respectively connected with one end of a resistor R36 and one end of a capacitor C2, and the other ends of the resistor R35, the capacitor C1, the resistor R36 and the capacitor C2 are all grounded;
the first voltage control unit, the second voltage control unit, the third voltage control unit, the fourth voltage control unit, the fifth voltage control unit and the seventh voltage control unit respectively comprise a first voltage control switch, the positive input end of the first voltage control switch is connected with an input signal, the negative input end of the first voltage control switch is grounded, the controlled voltage side input end of the first voltage control switch is connected with a first power supply, and the controlled voltage side output end of the first voltage control switch is respectively connected with a first resistor and an output signal;
the sixth voltage control unit, the eighth voltage control unit, the ninth voltage control unit, the tenth voltage control unit and the eleventh voltage control unit respectively comprise a second voltage control switch and a second resistor, wherein the positive input end of the second voltage control switch is connected with an input signal, the negative input end of the second voltage control switch is grounded, the controlled voltage side input end of the second voltage control switch is connected with one end of the second resistor, the other end of the second resistor is grounded, and the controlled voltage side output end of the second voltage control switch is connected with an output signal;
the first summing module, the second summing module, the third summing module, the fourth summing module, the fifth summing module, the sixth summing module, the seventh summing module, the eighth summing module, the ninth summing module, the tenth summing module, the eleventh summing module and the twelfth summing module respectively comprise a first operational amplifier, the non-inverting input end of the first operational amplifier is respectively connected with a third resistor and a fourth resistor, the third resistor and the fourth resistor are respectively connected with two input signals, the inverting input end of the first operational amplifier is respectively connected with a fifth resistor and a sixth resistor, the fifth resistor is grounded, the sixth resistor is connected with the output end of the first operational amplifier, and the output end of the first operational amplifier outputs the summed signals;
the first proportion module comprises a second operational amplifier, a third operational amplifier, an NMOS tube T1 and a memristor M1, wherein the positive end of the memristor M1 is the input end of the first proportion module, the drain electrode of the NMOS tube T1 is connected with the negative end of the memristor M1, the source electrode of the NMOS tube T1 is respectively connected with the inverting input end and a seventh resistor of the second operational amplifier, the seventh resistor is connected with the output end of the second operational amplifier, and the non-inverting input end of the second operational amplifier is grounded; the output end of the second operational amplifier is connected with an eighth resistor, the eighth resistor is respectively connected with the inverting input end and a tenth resistor of the third operational amplifier, the tenth resistor is connected with the output end of the third operational amplifier, the non-inverting input end of the third operational amplifier is grounded, and the output of the third operational amplifier is the output of the first proportional module;
the second proportion module and the third proportion module, the fourth proportional module and the fifth proportional module respectively comprise a fourth operational amplifier and a fifth operational amplifier, the inverting input end of the fourth operational amplifier is connected with one end of an eleventh resistor, one end of a first resistor is the input end of the second proportional module, the inverting input end of the fourth operational amplifier is connected with the output end of the fourth operational amplifier through a twelfth resistor, the non-inverting input end of the fourth operational amplifier is grounded, the output end of the fourth operational amplifier is connected with one end of a thirteenth resistor, the other end of the thirteenth resistor is respectively connected with the inverting input end of the fifth operational amplifier and the fourteenth resistor, the fourteenth resistor is connected with the output end of the fifth operational amplifier, the non-inverting input end of the fifth operational amplifier is grounded, and the output of the fifth operational amplifier is the output of the second proportional module;
the first difference module, the second difference module, the fourth difference module and the fifth difference module respectively comprise a sixth operational amplifier, the non-inverting input end of the sixth operational amplifier is connected with one end of a fifteenth resistor, the inverting input end of the sixth operational amplifier is connected with the other end of a sixteenth resistor, one ends of the fifteenth resistor and the sixteenth resistor are two input ends of the fifteenth resistor and the sixteenth resistor respectively, and the non-inverting input end of the sixth operational amplifier is grounded through a seventeenth resistor; the inverting input end of the sixth operational amplifier is connected with the output end of the sixth operational amplifier through an eighteenth resistor, and the output of the sixth operational amplifier is the output of the sixth operational amplifier;
the third difference calculating module comprises a seventh operational amplifier, the non-inverting input end of the seventh operational amplifier is connected with one end of a memristor M2, the inverting input end of the seventh operational amplifier is connected with one end of a nineteenth resistor, the other ends of the memristor M2 and the nineteenth resistor are two input ends of the memristor, and the non-inverting input end of the seventh operational amplifier is grounded through a twentieth resistor; and the inverting input end of the sixth operational amplifier is connected with the output end of the seventh operational amplifier through a twenty-first resistor, and the output of the seventh operational amplifier is the output of the seventh operational amplifier.
Compared with the prior art, the invention has the following beneficial effects:
1) by applying pictures of different intensities of positive or negative stimuli, emotional habituation caused by different stimuli is achieved. Positive stimulation generates remarkable happy emotion habituation, and negative stimulation does not generate fear emotion habituation. In addition, the weaker the homopolar stimulation intensity, the more emotional habituation is easy to occur, so that the stimulation is more diverse, and the circuit is more consistent with biological characteristics.
2) In the case of habituation of a person, the habituation feeling that has been formed can be restored by applying a high-intensity habituation-removal stimulus signal, and the person who has been habituated can be gradually habituated by continuing to apply the habituation-removal stimulus signal.
3) After the habituation of emotion is formed and no other stimulation signals are provided, the formed habituated emotion is gradually restored to the state before habituation is not formed, and the habituation spontaneous restoration process is realized. If habituation stimulation is applied again after spontaneous recovery is complete, habituation enters a phase of reinforcement. After strengthening, habituation forms faster and spontaneous recovery is slower.
According to the invention, through the connection between the visual neurons and the emotional neurons, the circuit is used for realizing the emotional habituation characteristic induced under the stimulation of pictures with different polarities and intensities; the habituation of the habituation stimulation under the emotional habituation state and the second emotional habituation and spontaneous recovery after the first emotional habituation and spontaneous recovery are realized. The emotion habituation characteristic circuit provided by the invention is more consistent with biological characteristics, and is beneficial to constructing a more intelligent neural network circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of the present invention.
Fig. 2 is a circuit diagram of the input module and the logic control module of fig. 1.
FIG. 3 is a circuit diagram of the habituation module in FIG. 1.
Fig. 4 is a circuit diagram of the enhancement module of fig. 1.
Fig. 5 is a circuit diagram of the spontaneous recovery module of fig. 1.
FIG. 6 is a diagram showing the results of the emotional habituation and spontaneous recovery simulation under positive and negative stimuli, wherein (a) is the input of a positive weak stimulus habituation signal source, (b) is the input of a positive medium stimulus habituation signal source, and (c) is the input of a negative weak stimulus habituation signal source and a negative medium stimulus habituation signal source.
FIG. 7 is a graph of habituation simulation results of a de-habituation stimulus in accordance with the present invention, wherein (a) is under a positive low stimulus habituation condition and (b) is under a positive medium stimulus habituation condition.
FIG. 8 is a diagram of simulation results of secondary habituation and spontaneous recovery according to the present invention, wherein (a) is under the positive weak stimulus signal source, and (b) is under the positive medium stimulus signal source.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art based on the embodiments of the present invention without inventive step, are within the scope of the present invention.
As shown in fig. 1, a visual-induced emotion habituation characteristic neural network circuit includes an input signal source, an input module, a logic control module, a habituation module, a reinforcement module and a spontaneous recovery module, wherein the input signal source is respectively connected with the input module and the logic control module, the input module is connected with the logic control module, the logic control module is respectively connected with the habituation module, the reinforcement module and the spontaneous recovery module, the reinforcement module is respectively connected with the habituation module and the spontaneous recovery module, the spontaneous recovery module is connected with the habituation module, and the habituation module outputs fear/happy emotion signals. The input module carries out amplitude and effective level conversion on an input signal source; the logic control module is used for generating control signals for controlling the habituation module, the strengthening module and the spontaneous recovery module according to the input signal source and the output of the input module; the habituation module realizes the functions of habituation formation, recovery and output; the strengthening module outputs habituation and spontaneous recovery feedback signals according to the received stimulation; the spontaneous recovery module recovers the habituation that has formed when no stimulus is applied.
The input signal sources comprise a 10V positive strong stimulation habituation signal source N1, a 2V positive weak stimulation habituation signal source N2, a 4V positive medium stimulation habituation signal source N3, a 6V negative weak stimulation habituation signal source N4 and an 8V negative medium stimulation habituation signal source N5. In the specific implementation, the input end inputs the picture stimulation signal voltage, and the output end outputs the induced fear/happy emotion signal. The signal N6 output by the habituation module represents a fear emotion signal and the signal N7 represents a happy emotion signal. The positive strong stimulation habituation signal source N1, the positive weak stimulation habituation signal source N2, the positive medium stimulation habituation signal source N3, the negative weak stimulation habituation signal source N4 and the negative medium stimulation habituation signal source N5 are respectively connected with the input module, and the positive strong stimulation habituation signal source N1, the positive weak stimulation habituation signal source N2, the positive medium stimulation habituation signal source N3, the negative weak stimulation habituation signal source N4 and the negative medium stimulation habituation signal source N5 are respectively connected with the logic control module.
As shown in fig. 2, the input module includes a positive strong stimulation habituation removal signal receiving and processing unit, a positive weak stimulation habituation signal receiving and processing unit, a positive medium stimulation habituation signal receiving and processing unit, a negative weak stimulation habituation signal receiving and processing unit, and a negative medium stimulation habituation signal receiving and processing unit, wherein the positive strong stimulation habituation removal signal source N1 is connected with the input end of the positive strong stimulation habituation removal signal receiving and processing unit, and the output end of the positive strong stimulation habituation removal signal receiving and processing unit is connected with the logic control module; the positive and weak stimulation habituation signal source N2 is connected with the input end of the positive and weak stimulation habituation signal receiving and processing unit, and the output end of the positive and weak stimulation habituation signal receiving and processing unit is connected with the logic control module. The positive medium stimulation habituation signal source N3 is connected with the input end of the positive medium stimulation habituation signal receiving and processing unit, and the output end of the positive medium stimulation habituation signal receiving and processing unit is connected with the logic control module. The negative weak stimulation habituation signal source N4 is connected with the input end of the negative weak stimulation habituation signal receiving and processing unit, and the output end of the negative weak stimulation habituation signal receiving and processing unit is connected with the logic control module; the negative medium stimulation habituation signal source N5 is connected with the input end of the negative medium stimulation habituation signal receiving and processing unit, and the output end of the negative medium stimulation habituation signal receiving and processing unit is connected with the logic control module. The positive strong stimulation habituation removing signal receiving and processing unit, the positive weak stimulation habituation signal receiving and processing unit, the positive medium stimulation habituation signal receiving and processing unit, the negative weak stimulation habituation signal receiving and processing unit and the negative medium stimulation habituation signal receiving and processing unit all carry out amplitude and effective level conversion on respective input signal sources.
The positive strong stimulation habituation removal signal receiving and processing unit comprises a first voltage control unit and a same logic gate D1, a positive strong stimulation habituation removal signal source N1 is connected with the input end of the first voltage control unit, the output end of the first voltage control unit is connected with the input end of the same logic gate D1, the same logic gate D1 carries out amplitude conversion on input high-level voltage, and the output of the same logic gate D1 is an output signal of the positive strong stimulation habituation removal signal receiving and processing module. The positive weak stimulation habituation signal receiving and processing unit comprises a second voltage control unit and a same logic gate D2, wherein the positive weak stimulation habituation signal source N2 is connected with the input end of the second voltage control unit, the output end of the second voltage control unit is connected with the input end of the same logic gate D2, and the same logic gate D2 performs amplitude conversion on the input high-level voltage. The output of the same logic gate D2 is the output signal of the positive and weak stimulation habituation signal receiving and processing unit. The positive and medium stimulation habituation signal receiving and processing unit comprises a third voltage control unit and a same logic gate D3, a positive and medium stimulation habituation signal source N3 is connected with the input end of the third voltage control unit, the output end of the third voltage control unit is connected with the input end of the same logic gate D3, the same logic gate D3 carries out amplitude conversion on input high-level voltage, and the output of the same logic gate D3 is an output signal of the positive and medium stimulation habituation signal receiving and processing unit. The negative weak stimulation habituation signal receiving and processing unit comprises a fourth voltage control unit and a same logic gate D4, a negative weak stimulation habituation signal source N4 is connected with the input end of the fourth voltage control unit, the output end of the fourth voltage control unit is connected with the input end of the same logic gate D4, the same logic gate D4 carries out amplitude conversion on input high-level voltage, and the output of the same logic gate D4 is an output signal of the negative weak stimulation habituation signal receiving and processing module. The negative medium stimulation habituation signal receiving and processing module comprises a fifth voltage control unit and a same logic gate D5, wherein a negative medium stimulation habituation signal source N5 is connected with the input end of the fifth voltage control unit, the output end of the fifth voltage control unit is connected with the input end of the same logic gate D5, the same logic gate D5 carries out amplitude conversion on input high-level voltage, and the output of the same logic gate D5 is an output signal of the negative medium stimulation habituation signal receiving and processing unit.
The first voltage control unit comprises a voltage control switch S1, the positive input end of the voltage control switch S1 is connected with a positive strong stimulation habituation removal signal source N1, the reverse input end of the voltage control switch S1 is grounded, the output end of the voltage control switch S1 is connected with a power supply V1, the output end of the voltage control switch S1 is connected with one end of a resistor R1 and the input end of a logic gate D1 respectively, and the other end of a resistor R1 is grounded. The second voltage control unit comprises a voltage control switch S2, the positive input end of the voltage control switch S2 is connected with the positive strong stimulation habituation removal signal source N2, the reverse input end of the voltage control switch S2 is grounded, the input end of the voltage control switch S2 is connected with the power supply V2, the output end of the voltage control switch S2 is respectively connected with one end of a resistor R2 and the input end of the logic gate D2, and the other end of the resistor R2 is grounded. The second voltage control unit comprises a voltage control switch S2, the positive input end of the voltage control switch S2 is connected with the positive strong stimulation habituation removal signal source N2, the reverse input end of the voltage control switch S2 is grounded, the input end of the voltage control switch S2 is connected with the power supply V2, the output end of the voltage control switch S2 is respectively connected with one end of a resistor R2 and the input end of the logic gate D2, and the other end of the resistor R2 is grounded. The third voltage control unit comprises a voltage control switch S3, the positive input end of the voltage control switch S3 is connected with the positive strong stimulation habituation removal signal source N3, the reverse input end of the voltage control switch S3 is grounded, the input end of the voltage control switch S3 is connected with the power supply V3, the output end of the voltage control switch S3 is respectively connected with one end of a resistor R3 and the input end of the logic gate D3, and the other end of the resistor R3 is grounded. The fourth voltage control unit comprises a voltage control switch S4, the positive input end of the voltage control switch S4 is connected with the positive strong stimulation habituation removal signal source N4, the reverse input end of the voltage control switch S4 is grounded, the input end of the voltage control switch S4 is connected with the power supply V4, the output end of the voltage control switch S4 is respectively connected with one end of a resistor R4 and the input end of the logic gate D4, and the other end of the resistor R4 is grounded. The fifth voltage control unit comprises a voltage control switch S5, the positive input end of the voltage control switch S5 is connected with the positive strong stimulation habituation removing signal source N5, the reverse input end of the voltage control switch S5 is grounded, the input voltage of the controlled voltage side of the voltage control switch S5 is a power supply V5, the output voltage of the controlled voltage side of the voltage control switch S5 is connected with one end of a resistor R5 and the input end of a logic gate D5, and the other end of the resistor R5 is grounded. When the input ends of the first voltage control unit, the second voltage control unit, the third voltage control unit, the fourth voltage control unit and the fifth voltage control unit exceed the threshold value of the first voltage control unit, the controlled voltage side of each voltage control unit is conducted, and the voltage of power supplies V1-V5 is output respectively, wherein the power supplies V1-V5 are all 3V high-level periodic square wave signals with the period of 1s and the effective level of 0.5 s.
As shown in fig. 2, the logic control module includes a summation module, a de-habituation control module, a habituation control module, and a reinforcement and recovery control module, wherein an output terminal of the input module is connected to input terminals of the summation module and the de-habituation control module, respectively, and an input signal source is connected to input terminals of the summation module and the reinforcement and recovery control module, respectively; the positive strong stimulation habituation signal source N1 is connected with the input end of the spontaneous recovery module, and the positive weak stimulation habituation signal source N2, the positive medium stimulation habituation signal source N3, the negative weak stimulation habituation signal source N4 and the negative medium stimulation habituation signal source N5 are connected with the input end of the summation module. The output end of the positive strong stimulation habituation removal signal receiving and processing unit is connected with the input end of the habituation removal control module, the output ends of the positive weak stimulation habituation signal receiving and processing unit, the positive medium stimulation habituation signal receiving and processing unit, the negative weak stimulation habituation signal receiving and processing unit and the negative medium stimulation habituation signal receiving and processing unit are connected with the input end of the summation module, and the output end of the summation module is respectively connected with the input ends of the habituation control module and the habituation control module; the output ends of the habituation removal control module and the habituation control module are connected with the input end of the habituation module, and the output ends of the reinforcement and recovery control module are respectively connected with the input ends of the reinforcement module and the spontaneous recovery module. The summation module is used for carrying out addition operation on the two inputs; the habituation removal control module is used for carrying out logic control on the habituation removal signal source; the habituation control module is used for carrying out logic control on the habituation signal source; the strengthening and restoring control module is used for carrying out logic control on the strengthening module and the restoring module.
The habituation removal control module comprises a same logic gate D6, a same logic gate D7 and a voltage control switch S6, wherein the input ends of the same logic gate D6 and the same logic gate D7 and the input voltage of a voltage control switch S6 are connected with the output end of the positive strong stimulation habituation removal signal receiving processing unit, the output ends of the same logic gate D6, the same logic gate D7 and the voltage control switch S6 are connected with the input end of the habituation module, the output end of the same logic gate D7 is connected with the positive input end of the voltage control switch S6, and the negative input end of the voltage control switch S6 is grounded. When the positive strong stimulation habituation removal signal source N1 is input, the signal N1 outputs a signal D1 after passing through the positive strong stimulation habituation removal signal receiving and processing unit, when the signal D1 is at a high level, the same logic gate D6 outputs a high-level voltage signal to control the conduction of an NMOS tube T1 in the habituation module, the habituation removal circuit is conducted after the T1 is conducted, the same logic gate D7 also outputs a high-level voltage signal to control the conduction of the voltage-controlled switch S6, the habituation removal voltage signal D1 is output to the habituation module after the voltage-controlled switch S6 is conducted, and in addition, the same logic gate D7 also controls the voltage-controlled switch S9 to enable the controlled voltage side of the same logic gate to only output a habituation removal voltage.
The summation module comprises a first summation module and a second summation module, wherein the input end of the first summation module is respectively connected with the output ends of the positive weak stimulation habituation signal receiving and processing unit and the positive medium stimulation habituation signal receiving and processing unit, the input end of the second summation module is respectively connected with the output ends of the negative weak stimulation habituation signal receiving and processing unit and the negative medium stimulation habituation signal receiving and processing unit, the output ends of the first summation module and the second summation module are respectively connected with a sixth summation module, the output end of the sixth summation module is connected with the habituation control module and the reinforcement module, the second summation module and the first summation module are also connected with the habituation module, the output end of the second summation module is connected with the input end of the same logic gate D8, and the output end of the same logic gate D8 is connected with the habituation module. When the negative stimulation voltage signal is input, the high level signal input by the logic gate D8 outputs a logic control signal to the voltage-controlled switches S12 and S12 in the habituation module to control the output of the voltage signal N6 for fear emotion. The output end of the second summation module is connected with a same logic gate D9, the same logic gate D9 is connected with the positive input end of the voltage control switch S11 in the habituation module, and the same logic gate D9 controls the voltage control switch S11 to output only habituation voltage on the controlled voltage side. The first summation module is to add the outputs of the AND gate D2 and the AND gate D3 as the output of the first summation module, the second summation module is to add the outputs of the AND gate D4 and the AND gate D5 as the output of the second summation module, and the sixth summation module is to add the outputs of the first summation module and the second summation module as the output of the sixth summation module. The first summing module comprises resistors R6-R9 and an operational amplifier OP1, the second summing module comprises resistors R10-13 and an operational amplifier OP2, and the sixth summing module comprises resistors R26-R29 and an operational amplifier OP 6.
The first summing module, the second summing module, the third summing module, the fourth summing module, the fifth summing module, the sixth summing module, the seventh summing module, the eighth summing module, the ninth summing module, the tenth summing module, the eleventh summing module and the twelfth summing module are all first operational amplifiers, the non-inverting input end of each first operational amplifier is connected with a third resistor and a fourth resistor respectively, the third resistor and the fourth resistor are connected with two input signals respectively, the inverting input end of each first operational amplifier is connected with a fifth resistor and a sixth resistor respectively, the fifth resistor is grounded, the sixth resistor is connected with the output end of each first operational amplifier, and the output end of each first operational amplifier outputs summed signals.
The habitual control module comprises an XNOR logic gate D9, an XNOR logic gate D10, an XNOR logic gate D12, an AND gate D13, an NOT gate D14, a voltage control switch S7 and a seventh summation module, wherein the output of the sixth summation module is respectively connected with the input ends of the XNOR logic gate D10, the XNOR logic gate D12 and one input end of the seventh summation module, the input end of the NOT gate D14 is connected with the output end of an AND gate D16 in the strengthening and restoring control module, the output ends of the XNOR logic gate D12 and the NOT gate D14 are connected with the input end of the AND gate D13, the positive input end of the voltage control switch S7 is connected with the output end of the AND gate D13, and the negative input end of the voltage control switch S7 is grounded; the other input end of the seventh summing module is connected with the output end of the strengthening module, the output end of the seventh summing module is connected with the output end of the voltage-controlled switch S7, the input end of the same logic gate D9 is connected with the output end of the first summing module, the output ends of the same logic gate D9, the same logic gate D10 and the voltage-controlled switch S7 are connected with the input end of the habituation module, and the seventh summing module sums the outputs of the sixth summing module and the third proportion module of the strengthening module to serve as the output of the seventh summing module. The output of the seventh summing module is connected to the input of a voltage controlled switch S7. The seventh summing module includes resistors R30-R33 and an operational amplifier OP 7. The same logic gate D10 outputs a logic signal according to the habituation signal output by the sixth summation module, and the output logic signal controls the on and off of the NMOS transistor T2 on the habituation circuit; the same logic gate D12 inputs a habituation logic control signal, the signal of the same logic gate D12 and the NOT gate D14 are input to the AND gate D13, the high-level output signal of the AND gate D13 controls the voltage-controlled switch S7 to be opened, and the habituation voltage is input to the habituation module after the voltage-controlled switch S7 is opened.
One input end of the third summing module is connected with a positive weak stimulation habituation signal source N2, the other input end of the third summing module is connected with a positive medium stimulation habituation signal source N3, one input end of the fourth summing module is connected with a negative weak stimulation habituation signal source N4, the other input end of the fourth summing module is connected with a negative medium stimulation habituation signal source N5, one input end of the fifth summing module is connected with the output of the third summing module, the input 2 end of the fifth summing module is connected with the output of the fourth summing module, and the output of the fifth summing module is connected with the input end of a gate D19 in the strengthening and restoring control module. The third summation module is used for adding the positive weak stimulus signal source N2 and the positive medium stimulus signal source N3 as the output of the third summation module; the fourth summation module adds the negative weak stimulus signal source N4 and the negative medium stimulus signal source N5 as the output of the fourth summation module; the fifth summation module is to add the outputs of the third summation module and the fourth summation module as the output of the fifth summation module. The third summing module comprises an operational amplifier OP3 and resistors R14-R17, the fourth summing module comprises an operational amplifier OP4 and resistors R18-R21, and the fifth summing module comprises an operational amplifier OP5 and resistors R22-R25.
The strengthening and recovering control module comprises a third summing module, a fourth summing module, a fifth summing module, a NOT gate D15, a NOT gate D17, a NOT gate D20, a NOT gate D22, a same logic gate D19, a same logic gate D21, an AND gate D16, an AND gate D18, a D trigger DFF1 and a sixth voltage control unit, wherein the positive strong stimulation habituation removal signal source N1 and the D trigger DFF are respectively connected with one anotherThe CLK terminal of 1 is connected to the input terminal of the NOT gate D15, and the D terminal of the D flip-flop DFF1 is connected to
Figure 65879DEST_PATH_IMAGE001
The ends are connected, and the input end of the NOT gate D17 is connected with the Q end of the D trigger DFF 1. The D flip-flop DFF1 outputs a logic signal for controlling the spontaneous recovery voltage to be turned off when the habituation removal signal is input, the Q end of the D flip-flop DFF1 outputs a high level signal when receiving a rising edge signal, and the Q end outputs a low level signal if the habituation removal signal is not input. The output end of the NOT gate D17 is connected with the input end of the AND gate D18; the input end of the same logic gate D19 is connected with the output end of the fifth summation module, the output end of the same logic gate D19 is respectively connected with the input end of the NAND gate D20 and the reinforcement module, the output end of the not gate D20 is connected with the input end of the AND gate D18, the output ends of the not gate D15 and the AND gate D18 are respectively connected with the input end of the AND gate D16, the output end of the AND gate D16 is respectively connected with the input end of the sixth voltage control unit, the input end of the not gate D14 in the habitual control module, the input end of the same logic gate D21, the reinforcement module and the input end of the spontaneous recovery module, the input end and the output end of the sixth voltage control unit on the controlled voltage side are both connected with the spontaneous recovery module, the output end of the fourth summation module is connected with the input end of the NAND gate D22, and the output ends of the not gate D22 and the same logic gate D21 are both connected with the input end of the reinforcement module. When the input end of the sixth voltage control unit exceeds the set 3.5V threshold voltage VT, the controlled voltage side of the voltage control unit is conducted. The input of a not gate D22 in the strengthening and restoring control module is connected with a positive habituated voltage signal output by an operational amplifier OP4, a logic signal output by a not gate D22 controls a voltage-controlled switch S15 and a voltage-controlled switch S16 in the strengthening module, under the condition that a not gate D22 outputs high level, a same logic gate D19 outputs a logic control voltage signal according to the input habituated voltage signal to change the resistance value of a memristor M2, and when the same logic gate D21 inputs a variable feedback voltage signal in a spontaneous restoring period; the AND gate D16 in the ENR/RESTORE control module outputs a high-level logic control signal to control the voltage control switch S8 to turn on, the controlled voltage side of the voltage control switch S8 outputs an AFR signal, and the AND gate D16 outputs a low level signal when the spontaneous recovery is completed, and the output of the and gate D16 is also input to the voltage controlled switch S18 in the spontaneous recovery block, and the voltage controlled switch S18 makes the voltage comparison block in the spontaneous recovery block function the first time the spontaneous recovery voltage signal is input.
As shown in fig. 3, the habituation module includes a habituation synapse module and a habituation output module, wherein the output ends of the habituation removal control module and the habituation control module in the logic control module are both connected to the habituation synapse module, the output ends of the habituation removal control module and the habituation control module are both connected to the habituation output module, the habituation synapse module is connected to the habituation output module, and the habituation output module outputs a fear emotion signal N6 or a happy emotion signal N7. The habituation synapse module realizes the change of the resistance value of the memristor M1 according to the positive and negative voltages of the input; the habituation output module generates an emotional habit output signal according to the input habituation stimulation signal and the de-habituation stimulation signal.
The habituation synapse module comprises a memristor M1, an NMOS tube T1, an NMOS tube T2, a capacitor C1, a capacitor C2, a resistor R35, a resistor R36 and a first proportion module (comprising a memristor M1), an output end of a controlled voltage side of a voltage-controlled switch S6 in the habituation control module is respectively connected with a positive electrode end of the memristor M1 and a drain electrode of the NMOS tube T2, an output end of a logic gate D6 is connected with a gate electrode of the NMOS tube T1, an output end of the logic gate D10 in the habituation control module is connected with a gate electrode of the NMOS tube T2, an output end of the voltage-controlled switch S7 of the habituation control module is connected with a negative electrode 737373737373737373 1, a positive electrode end of the memristor M1 is connected with a drain electrode of the NMOS tube T2, a negative electrode end of the memristor M1 is connected with a drain electrode of the NMOS tube T1, a source electrode of the NMOS tube T1 is respectively connected with one end of the resistor R35, one end of the capacitor C1 and the first proportion module, a resistor R33 are connected in parallel connection, a filter function of the resistor C1 is realized, the other ends of the resistor R35 and the capacitor C1 are grounded, the source of the NMOS transistor T2 is connected with one end of the resistor R36 and one end of the capacitor C2 and the first proportional module respectively, the resistor R36 and the capacitor C2 are connected in parallel to achieve a filtering effect, and the other ends of the resistor R36 and the capacitor C2 are grounded. The first proportion module is used for carrying out proportion operation; the positive voltage and the back voltage applied to the memristor M1 can be realized by turning on and off the NMOS transistor T1 and the NMOS transistor T2.
The habituation output module comprises a voltage control switch S9, a voltage control switch S11, a resistor R40, a resistor R41, a seventh voltage control unit, an eighth summation module, a first difference module, a second difference module and a second proportion module, wherein the output end of a same logic gate D7 in the habituation removal control module is respectively connected with the positive input end of the voltage control switch S9 and the input end of the seventh voltage control unit, the output end of a same logic gate D9 in the habituation control module is connected with the positive input end of the voltage control switch S11, the negative input ends of the voltage control switch S9 and the voltage control switch S11 are grounded, the input ends of the voltage control switch S9 and the voltage control switch S11 on controlled voltage sides are respectively connected with the output end of the first proportion module in the habituation synapse module, the output end of the voltage control switch S9 is respectively connected with one end of the resistor R40 and one input end of the first difference module, the output voltage control switch S11 on controlled voltage side is connected with one end of the resistor R41 and one input end of the second proportion module The ends are connected, and the other ends of the resistor R40 and the resistor R41 are both grounded. The output end of the seventh voltage control unit is connected with the other input end of the first differencing module, the input end of the eighth summing module is respectively connected with the output ends of the first differencing module and the second proportional module, the output end of the eighth summing module is connected with one input end of the second differencing module, the other input end of the second differencing module is connected with the output end of the third proportional module in the reinforcement module, and the output end of the second differencing module outputs a happy emotion signal N7; the input end of the eighth voltage control unit is connected with the output end of the same logic gate D8 in the habituation control module, the input end of the controlled voltage side of the eighth voltage control unit is connected with the output end of the first proportion module in the habituation synapse module, and the output end of the controlled voltage side of the eighth voltage control unit is a fear emotion signal N6. When the input ends of the seventh voltage control unit and the eighth voltage control unit exceed the set 3.5V threshold voltage VT, the controlled voltage side of each voltage control unit is conducted; the eighth summing module is used for adding the output of the first difference-finding module and the output of the second proportion module to form the output of the eighth summing module; the first difference module is used for subtracting the voltage of the output end of the controlled voltage side of the voltage-controlled switch S9 from the output power supply V6 of the controlled voltage side of the seventh voltage-controlled unit as the output of the first difference module; and the second difference module subtracts the output of the third proportion module from the output of the eighth summation module to obtain the output of the second difference module. The second proportion module is used for carrying out proportion operation; the seventh voltage control unit comprises a voltage control switch S10, a power supply V6 and a resistor R42; the eighth voltage controlled cell includes a voltage controlled switch S12 and a resistor R50.
The first voltage control unit, the second voltage control unit, the third voltage control unit, the fourth voltage control unit, the fifth voltage control unit and the seventh voltage control unit respectively comprise a first voltage control switch, the positive input end of the first voltage control switch is connected with an input signal, the negative input end of the first voltage control switch is grounded, the controlled voltage side input end of the first voltage control switch is connected with a first power supply, and the controlled voltage side output end of the first voltage control switch is respectively connected with a first resistor and an output signal.
The sixth voltage-controlled unit, the eighth voltage-controlled unit, the ninth voltage-controlled unit, the tenth voltage-controlled unit and the eleventh voltage-controlled unit all comprise a second voltage-controlled switch and a second resistor, a positive input end of the second voltage-controlled switch is connected with the input signal, a negative input end of the second voltage-controlled switch is grounded, an input end of a controlled voltage side of the second voltage-controlled switch is connected with one end of the second resistor, the other end of the second resistor is grounded, and an output end of the controlled voltage side of the second voltage-controlled switch outputs a controlled voltage signal.
As shown in fig. 4, the enforcing module includes a rate varying module, a habituation feedback module and a spontaneous recovery feedback module, an input end of the rate varying module is connected to an output end of the recovery control module of the enforcing and logic control module, an output end of the rate varying module is respectively connected to input ends of the habituation feedback module and the spontaneous recovery feedback module, an output end of the habituation feedback module is connected to an input end of the habituation control module of the logic control module, and an output end of the spontaneous recovery feedback module is connected to the spontaneous recovery module. The rate change module outputs a feedback signal according to the habituated stimulation signal applied before; the habituation feedback module amplifies the output of the rate change module and feeds the output back to the habituation signal source; the spontaneous recovery feedback module is used for amplifying the output of the rate change module and feeding back the output to the spontaneous recovery module to be used as a spontaneous recovery signal source.
The speed rate change module comprises a ninth voltage control unit, a tenth voltage control unit, a ninth summation module, a third difference module, an NMOS tube T3, a power supply V7 and a capacitor C3, wherein the output end of a NOT gate D22 in the strengthening and recovering control module is respectively connected with the positive input ends of the ninth voltage control unit and the tenth voltage control unit, the output end of a same logic gate D19 in the strengthening and recovering control module is connected with the input end of the controlled voltage side of the ninth voltage control unit, the output end of the same logic gate D21 in the strengthening and recovering control module is respectively connected with one input end of the ninth summation module and the input end of the controlled voltage side of the tenth voltage control unit, the output end of the controlled voltage side of the ninth voltage control unit is connected with the other input end of the ninth summation module, the output end of the controlled voltage side of the tenth voltage control unit is connected with the gate of the NMOS tube T3, and the output end of the ninth summation module is connected with one input end of the third difference module, the other input end of the third difference-finding module is connected with the positive electrode of a power supply V7, the negative electrode of the power supply V7 is grounded, the output end of the third difference-finding module is connected with the drain electrode of an NMOS tube T3, the source electrode of the NMOS tube T3 is respectively connected with the input ends of the habituation feedback module and the spontaneous recovery feedback module and one end of a capacitor C3, and the other end of the capacitor C3 is grounded. The connection and disconnection of the NMOS transistor T3 controls whether the output of the third difference module is input to the capacitor C3 as a sample-and-hold device, the sample-and-hold device C3 collects the voltage signal output by the third difference module when the NMOS transistor T3 is connected, and the collected signal is amplified by the scaling module and then outputs a feedback voltage signal. When the voltage input by the controlled voltage side of the ninth voltage-controlled unit and the tenth voltage-controlled unit exceeds the set 3.5V threshold voltage VT, the controlled voltage side of each voltage-controlled unit is conducted. The ninth summing module is used for adding the output of the controlled voltage side of the ninth voltage-controlled unit and the output of the same logic gate D21 to form the output of the ninth summing module; the third difference module subtracts the power supply V7 from the output of the ninth summation module to obtain the output of the third difference module. The ninth voltage controlled unit comprises a voltage controlled switch S16 and a resistor R76; the tenth voltage controlled unit comprises a voltage controlled switch S15 and a resistor R73; the ninth summing module comprises an operational amplifier OP20, a resistor R71, a resistor R72, a resistor R74 and a resistor R75; the third difference module includes an operational amplifier OP19, a resistor R68, a resistor R69, a resistor R70, and a memristor M2.
The habituation feedback module comprises a voltage control switch S13 and a third proportion module, the output of a same logic gate D11 in the habituation control module is connected with the positive input end of a voltage control switch S13, the negative input end of the voltage control switch S13 is grounded, the source of an NMOS (N-channel metal oxide semiconductor) tube T3 is connected with the input end of the controlled voltage side of the voltage control switch S13, the output end of the voltage control switch S13 is connected with the input end of the third proportion module, the output end of the third proportion module is connected with the other input end of a seventh summation module in the habituation control module, and the voltage control switch S13 outputs a voltage signal collected by a sampling holder C3 in the habituation period. The spontaneous recovery feedback module comprises a voltage control switch S14 and a fourth proportion module, the output end of an AND gate D16 in the strengthening and recovery control module is connected with the positive input end of a voltage control switch S14, the negative input end of the voltage control switch S14 is grounded, the source of an NMOS tube T3 is connected with the input end of the controlled voltage side of the voltage control switch S14, the output end of the controlled voltage side of the voltage control switch S14 is connected with the input end of the fourth proportion module, the output end of the fourth proportion module is connected with the spontaneous recovery module, and the voltage control switch S14 outputs a voltage signal collected by a sampling holder C3 in the spontaneous recovery period. The third proportion module and the fourth proportion module carry out proportion operation. The third proportion module comprises an operational amplifier OP15, an operational amplifier OP16 and resistors R60-R63; the fourth proportion module comprises an operational amplifier OP17, an operational amplifier OP18 and resistors R64-R67.
As shown in fig. 5, the spontaneous recovery module includes a voltage comparison module, a start module, and a recovery voltage module, the voltage comparison module is connected to the logic control module and the habituation module, the start module is connected to the logic control module, and the recovery voltage module is respectively connected to the voltage comparison module, the start module, the logic control module, and the reinforcement module. The voltage comparison module stops outputting signals to the recovery voltage module when the resistance value of the memristor M1 of the habituation synapse module of the habituation module is recovered to the initial value 1K; the starting module generates a 0.09S pulse signal at the spontaneous recovery starting moment to enable the voltage comparison module to function at the spontaneous recovery starting moment; the recovery voltage module applies a spontaneous recovery voltage to the habituation module.
The voltage comparison module comprises a voltage-controlled switch S17, a Diode1, a fifth proportion module, a fourth difference module, a tenth summation module, a power supply V8, a power supply V9, an NMOS tube T4, a PMOS tube T5, a resistor R77, a resistor R86, a resistor R87 and a same logic gate D23, wherein the output end of the AND gate D16 in the strengthening and recovering control module is connected with the positive input end of the voltage-controlled switch S17, the negative end of the memristor M1 in the habituation synapse module is connected with the input end of the controlled voltage side of the voltage-controlled switch S17, the output end and the negative input end of the controlled voltage side of the voltage-controlled switch S17 are both grounded, and the voltage-controlled switch S17 is an autonomous recovering circuit when an autonomous recovering voltage signal exists. The output end of the controlled voltage side of the voltage-controlled switch S6 of the sixth voltage-controlled unit in the intensified and recovered control module is respectively connected with the input end of a Diode1 and one end of a resistor R77, the output end of the Diode1 is connected with the input end of a fifth proportional module, the other end of the resistor R77 is respectively connected with the positive electrode end of a memristor M1 and the gate of an NMOS transistor T4 in the habituation module, the output end of the fifth proportional module is respectively connected with one input end of a fourth differencing module, one input end of a tenth summing module and one end of a resistor R86, the positive electrode of a power supply V8 is connected with the other input end of the fourth differencing module, the positive electrode of a power supply V9 is connected with the other input end of a tenth summing module, the negative electrodes of the power supply V8 and V9 are both grounded, the output end of the fourth differencing module is connected with the source of the NMOS transistor T4, the output end of the tenth summing module is connected with the source of a PMOS transistor T5, the drain of the NMOS transistor T4 is connected with the other end of the resistor R86 and the gate of the PMOS transistor T5, the drain of the PMOS transistor T5 is connected with one end of the resistor R87 and the input end of the same logic gate D23, and the other end of the resistor R87 is grounded. The output of the exclusive nor gate D23 is connected to the input of the restore voltage module. The fifth proportion module is used for carrying out proportion operation; the fourth difference module subtracts the power supply V8 from the output of the fifth proportion module to obtain the output of the fourth difference module; the tenth summation module is to add the output of the fifth scaling module and the power supply V9 as the output of the tenth summation module.
Diode1 ensures that the voltage comparison module can only input voltage signals; the NMOS transistor T4 and the PMOS transistor T5 are turned on and off according to the voltage signal applied to the gate, and the NMOS transistor T4 and the PMOS transistor T5 are core devices of the voltage comparison module. The exclusive-nor gate D23 outputs a logic signal to the input of the eleventh summing block according to the voltage signal output from the drain of the PMOS transistor T5, and the output of the eleventh summing block controls the application of the self-healing voltage signal by controlling the on and off of the voltage-controlled switch S19. When the difference between the output voltage of the fifth proportional module and the gate input voltage of the NMOS transistor T4 is greater than 0.8V, the NMOS transistor T4 is turned on and the output of the source fourth difference module is input to the gate of the PMOS transistor T5, when the difference between the source voltage signal of the NMOS transistor T4 and the gate input voltage of the PMOS transistor T5 is less than-1.7V, the PMOS transistor T5 is turned on and the output of the PMOS transistor T5 source tenth summing module is input to the same logic gate D23, the same logic gate D23 outputs a high level signal, and when the voltage across the resistor R77 is reduced to about half of the spontaneous recovery input voltage, the same logic gate D23 outputs a low level signal; when the difference between the output voltage of the fifth proportional module and the gate input voltage of the NMOS transistor T4 is less than 0.8V, neither the NMOS transistor T4 nor the PMOS transistor T5 is turned on, and the same logic gate D23 outputs a low level signal.
The starting module comprises an eleventh voltage control unit and a fifth difference module, the output end of an AND gate D16 in the strengthening and restoring control module is respectively connected with the input end and the positive input end of the controlled voltage side of the eleventh voltage control unit and one input end of the fifth difference module, the output end of the controlled voltage side of the eleventh voltage control unit is connected with the other input end of the fifth difference module, and the output end of the fifth difference module is connected with the input end of the restoring voltage module. When the input end of the eleventh voltage control unit exceeds the threshold value of the eleventh voltage control unit, the controlled voltage side of the eleventh voltage control unit is conducted. The fifth difference module subtracts the output of the eleventh voltage-controlled unit on the controlled voltage side from the output of the and gate D16 to obtain the output of the fifth difference module. The eleventh voltage controlled cell comprises a voltage controlled switch S18 and a resistor R95; the fifth difference module comprises an operational amplifier OP25, a resistor R92, a resistor R93, a resistor R94 and a resistor R96.
The recovery voltage module comprises a voltage controlled switch S19, a power supply V10, the output end of a same logic gate D23 in the voltage comparison module is connected with one input end of the eleventh summation module, the output end of a fifth difference-finding module in the starting module is connected with the other input end of the eleventh summation module, the output end of the eleventh summation module is connected with the positive input end of a voltage-controlled switch S19, the negative input end of the voltage-controlled switch S19 is grounded, the output end of the controlled voltage side of the voltage-controlled switch S19 is connected with the input end of the controlled voltage side of a sixth voltage-controlled unit in the strengthening and restoring control module, one input end of the twelfth summation module is connected with the output end of a fourth proportion module in the spontaneous restoring feedback module, the other input end of the twelfth summation module is connected with the positive pole of a power supply V10, and the negative pole of the power supply V10 is grounded. The output terminal of the twelfth summing module is connected to the controlled voltage side input terminal of the voltage controlled switch S19. The eleventh summation module adds the output of the fifth difference module and the output of the same logic gate D23 to form the output of the eleventh summation module; the twelfth summing module sums the output of the fourth scaling module and the power supply V10 as the output of the twelfth summing module. The eleventh summing module comprises an operational amplifier OP26 and resistors R97-R100; the twelfth summing module includes an operational amplifier OP27 and resistors R101-R104.
The first proportional module comprises an operational amplifier OP8, an operational amplifier OP9, a resistor R37, a resistor R38, a resistor R39, an NMOS tube T1 and a memristor M1, the positive terminal of the memristor M1 is the input terminal of the first proportional module, the drain of the NMOS tube T1 is connected with the negative terminal of the memristor M1, the source of the NMOS tube T1 is connected with the inverting input terminal of the operational amplifier OP8, one terminal of the resistor R37 is connected with the inverting input terminal of the operational amplifier OP8, the other terminal of the resistor R37 is connected with the output terminal of the operational amplifier OP8, the non-inverting input terminal of the operational amplifier OP8 is grounded, one terminal of the resistor R38 is connected with the output terminal of the operational amplifier OP8, the other terminal of the resistor R38 is connected with the inverting input terminal of the operational amplifier OP9, one terminal of the resistor R39 is connected with the inverting input terminal of the operational amplifier OP9, the other terminal of the resistor R39 is connected with the output terminal of the operational amplifier OP9, the non-inverting input terminal of the operational amplifier OP9 is grounded, and the output of the operational amplifier OP9 is the output of the first scaling module. The second proportional module, the third proportional module, the fourth proportional module and the fifth proportional module each include an operational amplifier OP12, an operational amplifier OP13, a resistor R51, a resistor R52, a resistor R53 and a resistor R54, one end of the resistor R51 is an input end of the second proportional module, the other end of the resistor R51 is connected to an inverting input end of the operational amplifier OP12, one end of the resistor R52 is connected to the inverting input end of the operational amplifier OP12 and the other end of the resistor R52 is connected to an output end of the operational amplifier OP12, a non-inverting input end of the operational amplifier OP12 is grounded, one end of the resistor R53 is connected to an output end of the operational amplifier OP12, the other end of the resistor R53 is connected to the inverting input end of the operational amplifier OP13, one end of the resistor (R54) is connected to the inverting input end of the operational amplifier OP13, the other end of the resistor R54 is connected to an output end of the operational amplifier OP13, and an non-phase input end of the operational amplifier OP13 is grounded, the output of the operational amplifier OP13 is the output of the second proportional module.
The first difference module, the second difference module, the third difference module, the fourth difference module and the fifth difference module respectively comprise a resistor R43 or a memristor M2, a resistor R44, a resistor R45, a resistor R46 and an operational amplifier OP10, one ends of a resistor R43 and a resistor R45 are two input ends of the first difference module, the other end of the resistor R43 is connected with a non-inverting input end of an operational amplifier OP10, the other end of the resistor R45 is connected with an inverting input end of the operational amplifier OP10, one end of the resistor R44 is connected with the non-inverting input end of the operational amplifier OP10, the other end of the resistor R44 is grounded, one end of the resistor R46 is connected with the inverting input end of the operational amplifier OP10, the other end of the resistor R46 is connected with an output end of the operational amplifier OP10, and an output of the operational amplifier OP10 is an output of the first difference module.
FIG. 6(a) is a simulation diagram of emotional habituation and spontaneous recovery when a positive weak stimulation habituation signal source is input, 0-5 s are a happy emotional habituation stage, 5-6 s continue to apply a positive weak stimulation habituation signal, the happy emotional signal does not change, the happy emotion is habituated, and 6-12.3 s are a habituated spontaneous recovery stage. FIG. 6(b) is a simulation diagram of emotion habituation and spontaneous recovery when a positive medium stimulation habituation signal source is input, the Happy emotion habituation stage is 0-6 s, the Happy emotion signal does not change when the positive medium stimulation habituation signal is continuously applied for 6-7 s, the Happy emotion is habituated, and the habituation spontaneous recovery stage is 7-13.5 s. Fig. 6(c) is an emotion habituation simulation diagram when a negative weak stimulation habituation signal source and a negative medium stimulation habituation signal source are input, and the fear emotion signals output when the negative stimulation signal source is input are not changed. As can be seen from FIG. 2, the emotional responses elicited by positive stimuli, regardless of intensity, were significantly habituated, while the emotional responses elicited by negative stimuli of different intensities were not habituated. In addition, habituation that occurs with low intensity stimulation is more pronounced than with high intensity stimulation.
FIG. 7 (a) is a habituation simulation diagram of habituation removal stimulation under the habituation condition of positive and weak stimulation, 0-5 s are happy emotion habituation induced by a positive and weak stimulation habituation signal source, 5-6 s test is carried out to determine whether happy emotion habituation is completely formed or not, and 6-9 s are applied with habituation removal stimulation signals; it can be seen that with the application of the de-habituation stimulation signal, the happy mood caused by the de-habituation stimulation also becomes habituated. FIG. 7 (b) is a habituation simulation diagram of habituation removal stimulation under a positive medium stimulation habituation condition, 0-6 s are happy emotion habituation induced by a positive medium stimulation habituation signal source, 6-7 s test is carried out to determine whether happy emotion habituation is completely formed, and 7-10 s are applied with habituation removal stimulation signals; it can be seen that with the application of the de-habituation stimulus signal, the happy mood caused by the de-habituation stimulus also becomes habituated.
FIG. 8 (a) is a simulation diagram of secondary emotion habituation and spontaneous recovery under a positive weak stimulation signal source, wherein 0-5 s are primary habituation, 5-11 s are primary spontaneous recovery, 15-19 s are secondary habituation, and 19-26 s are secondary spontaneous recovery. FIG. 8 (b) is a simulation diagram of secondary emotional habituation and spontaneous recovery under a positive and medium stimulus signal source, wherein 0-6 s are primary habituation, 6-12.2 s are primary spontaneous recovery, 15-20 s are secondary habituation, and 20-27.3 s are secondary spontaneous recovery. As can be seen from fig. 4, the second emotional habituation is faster than the first rate, and the second spontaneous recovery is slower than the first rate; habituation is more likely to occur with low intensity stimulation than with high intensity stimulation.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, which is intended to cover any modifications, equivalents, improvements, etc. within the spirit and scope of the present invention.

Claims (10)

1. A vision-induced emotion habituation characteristic neural network circuit is characterized by comprising an input signal source, an input module, a logic control module, a habituation module, a reinforcement module and a spontaneous recovery module, wherein the input signal source is respectively connected with the input module and the logic control module; the input module converts the amplitude and the effective level of an input signal source; the logic control module respectively generates control signals for controlling the habituation module, the strengthening module and the spontaneous recovery module according to the output of the input signal source and the output of the input module; the habituation module realizes the functions of habituation formation, recovery and output; the strengthening module outputs habituation and spontaneous recovery feedback signals according to the received stimulation; the spontaneous recovery module recovers the habituation that has formed when no stimulus is applied.
2. The visually evoked mood habituation characteristic neural network circuit of claim 1, wherein the input signal sources include a positive strong stimulus habituation signal source N1, a positive weak stimulus habituation signal source N2, a positive medium stimulus habituation signal source N3, a negative weak stimulus habituation signal source N4, and a negative medium stimulus habituation signal source N5; the positive strong stimulation habituation signal source N1, the positive weak stimulation habituation signal source N2, the positive medium stimulation habituation signal source N3, the negative weak stimulation habituation signal source N4 and the negative medium stimulation habituation signal source N5 are connected with the input module, and the positive strong stimulation habituation signal source N1, the positive weak stimulation habituation signal source N2, the positive medium stimulation habituation signal source N3, the negative weak stimulation habituation signal source N4 and the negative medium stimulation habituation signal source N5 are connected with the logic control module;
the input module comprises a positive strong stimulation habituation removing signal receiving and processing unit, a positive weak stimulation habituation signal receiving and processing unit, a positive medium stimulation habituation signal receiving and processing unit, a negative weak stimulation habituation signal receiving and processing unit and a negative medium stimulation habituation signal receiving and processing unit, the positive strong stimulation habituation signal source N1 is connected with the input end of the positive strong stimulation habituation removing signal receiving and processing unit, and the output end of the positive strong stimulation habituation removing signal receiving and processing unit is connected with the logic control module; the positive and weak stimulation habituation signal source N2 is connected with the input end of the positive and weak stimulation habituation signal receiving and processing unit, and the output end of the positive and weak stimulation habituation signal receiving and processing unit is connected with the logic control module; the positive medium stimulation habituation signal source N3 is connected with the input end of the positive medium stimulation habituation signal receiving and processing unit, and the output end of the positive medium stimulation habituation signal receiving and processing unit is connected with the logic control module; the negative weak stimulation habituation signal source N4 is connected with the input end of the negative weak stimulation habituation signal receiving and processing unit, and the output end of the negative weak stimulation habituation signal receiving and processing unit is connected with the logic control module; the negative medium stimulation habituation signal source N5 is connected with the input end of the negative medium stimulation habituation signal receiving and processing unit, and the output end of the negative medium stimulation habituation signal receiving and processing unit is connected with the logic control module;
the positive strong stimulation habituation removal signal receiving and processing unit comprises a first voltage control unit and a same logic gate D1, wherein a positive strong stimulation habituation removal signal source N1 is connected with the input end of the first voltage control unit, the output end of the first voltage control unit is connected with the input end of the same logic gate D1, and the output end of the same logic gate D1 is connected with a logic control module; the positive weak stimulation habituation signal receiving and processing unit comprises a second voltage control unit and a same logic gate D2, wherein the positive weak stimulation habituation signal source N2 is connected with the input end of the second voltage control unit, the output end of the second voltage control unit is connected with the input end of the same logic gate D2, and the output end of the same logic gate D2 is connected with the logic control module; the positive and medium stimulation habituation signal receiving and processing unit comprises a third voltage control unit and a same logic gate D3, wherein a positive and medium stimulation habituation signal source N3 is connected with the input end of the third voltage control unit, the output end of the third voltage control unit is connected with the input end of the same logic gate D3, and the output end of the same logic gate D3 is connected with a logic control module; the negative weak stimulation habituation signal receiving and processing unit comprises a fourth voltage control unit and a same logic gate D4, wherein a negative weak stimulation habituation signal source N4 is connected with the input end of the fourth voltage control unit, the output end of the fourth voltage control unit is connected with the input end of the same logic gate D4, and the output end of the same logic gate D4 is connected with a logic control module; the negative medium stimulation habituation signal receiving and processing module comprises a fifth voltage control unit and a same logic gate D5, wherein a negative medium stimulation habituation signal source N5 is connected with the input end of the fifth voltage control unit, the output end of the fifth voltage control unit is connected with the input end of the same logic gate D5, and the output end of the same logic gate D5 is connected with the logic control module.
3. The visually induced emotional habituation characteristic neural network circuit of claim 2, wherein the logic control module comprises a summing module, a de-habituation control module, a habituation control module, and an enhancement and recovery control module, wherein an output terminal of the input module is connected to input terminals of the summing module and the de-habituation control module, respectively, and an input signal source is connected to input terminals of the summing module and the enhancement and recovery control module, respectively; the positive strong stimulation habituation removing signal source N1 is connected with the input end of the spontaneous recovery module, and the positive weak stimulation habituation signal source N2, the positive medium stimulation habituation signal source N3, the negative weak stimulation habituation signal source N4 and the negative medium stimulation habituation signal source N5 are connected with the input end of the summation module; the input end of the habituation removal control module is connected with the output end of the positive strong stimulation habituation removal signal receiving and processing unit of the input module, the output ends of the positive weak stimulation habituation signal receiving and processing unit, the positive medium stimulation habituation signal receiving and processing unit, the negative weak stimulation habituation signal receiving and processing unit and the negative medium stimulation habituation signal receiving and processing unit of the input module are connected with the input end of the summation module, and the output end of the summation module is connected with the input ends of the habituation control module and the habituation control module respectively; the output ends of the habituation removal control module and the habituation control module are connected with the input end of the habituation module, and the output ends of the reinforcement and recovery control module are respectively connected with the input ends of the reinforcement module and the spontaneous recovery module.
4. The visually induced emotion habituation characteristic neural network circuit of claim 3, wherein the habit removal control module comprises a same logic gate D6, a same logic gate D7 and a voltage control switch S6, input voltages of controlled voltage sides of the input ends of the same logic gate D6, the same gate D7 and the voltage control switch S6 are all connected with an output end of the positive strong stimulation habit removal signal receiving processing unit of the input module, output voltages of a controlled voltage side of the same logic gate D6, the same logic gate D7 and the voltage control switch S6 are all connected with an input end of the habit removal module, an output end of the same logic gate D7 is connected with a positive input end of the voltage control switch S6, and a negative input end of the voltage control switch S6 is grounded;
the system comprises a plurality of habituation control modules and a plurality of habituation control modules, wherein each habituation control module comprises a first summing module and a second summing module, the input end of the first summing module is respectively connected with the output ends of a positive weak stimulation habituation signal receiving and processing unit and a positive medium stimulation habituation signal receiving and processing unit of an input module, the input end of the second summing module is respectively connected with the output ends of a negative weak stimulation habituation signal receiving and processing unit and a negative medium stimulation habituation signal receiving and processing unit of the input module, the output ends of the first summing module and the second summing module are respectively connected with a sixth summing module, the output end of the sixth summing module is respectively connected with a habituation control module and a strengthening module, and the output ends of the second summing module and the first summing module are respectively connected with the habituation module;
the habitual control module comprises an identity logic gate D10, an identity logic gate D12, an AND gate D13, a NOT gate D14, a voltage-controlled switch S7 and a seventh summing module, wherein the output end of the sixth summing module is respectively connected with the input ends of an identity logic gate D10, an identity logic gate D12 and one input end of the seventh summing module, the output end of the reinforced and recovery control module is connected with the input end of a NAND gate D14 of an AND gate D16, the output ends of the identity logic gate D12 and the NOT gate D14 are both connected with the input ends of a AND gate D13, the positive input end of the voltage-controlled switch S7 is connected with the output end of the AND gate D13, and the negative input end of the voltage-controlled switch S7 is grounded; the other input end of the seventh summing module is connected with the output end of the strengthening module, the output end of the seventh summing module is connected with the input end of the controlled voltage side of the voltage-controlled switch S7, the input end of the same logic gate D9 is connected with the output end of the first summing module, and the output ends of the same logic gate D9, the same logic gate D10 and the controlled voltage side of the voltage-controlled switch S7 are connected with the habituation module;
the positive weak stimulation habituation signal source N2 is connected with one input end of a third summing module, the other input end of the third summing module is connected with a positive medium stimulation habituation signal source N3, a negative weak stimulation habituation signal source N4 is connected with one input end of a fourth summing module, the other input end of the fourth summing module is connected with a negative medium stimulation habituation signal source N5, the output end of the third summing module is connected with one input end of a fifth summing module, the other input end of the fifth summing module is connected with the output end of the fourth summing module, and the output end of the fifth summing module is connected with the input end of a same logic gate D19 in the strengthening and restoring control module;
the strengthening and recovering control module comprises a third summing module, a fourth summing module, a fifth summing module, a NOT gate D15, a NOT gate D17, a NOT gate D20, a NOT gate D22, a same logic gate D19, a same logic gate D21, an AND gate D16, an AND gate D18, a D trigger DFF1 and a sixth voltage control unit, wherein a positive strong stimulation habituation signal source N1 is respectively connected with the CLK end of the D trigger DFF1 and the NOT gate D115, and the D terminal of a D flip-flop DFF1 and
Figure DEST_PATH_IMAGE002
the end is connected, the input end of the NOT gate D17 is connected with the Q end of the D trigger, and the output end of the NOT gate D17 is connected with the input end of the AND gate D18; the output end of the fifth summing module is connected with the input end of a same logic gate D19, the output end of the same logic gate D19 is connected with the input end of a NAND gate D20, the output end of a not gate D20 is connected with the input end of an AND gate D18, the output ends of a not gate D15 and an AND gate D18 are connected with the input end of an AND gate D16, the output end of an AND gate D16 is respectively connected with the input end of a sixth voltage control unit, the input end of a not gate D14 in the habitual control module, the input end of the same logic gate D21, the intensifying module and the input end of the spontaneous recovery module, the input end and the output end of the controlled voltage side of the sixth voltage control unit are both connected with the spontaneous recovery module, the output end of an NAND gate D22 in the fourth summing module is connected, and the output ends of the not gate D22 and the same logic gate D21 are both connected with the input end of the intensifying module.
5. A visually induced emotional habituation characteristic neural network circuit as claimed in any one of claims 2 to 4, wherein said habituation module comprises a habituation synapse module and a habituation output module, wherein outputs of the de-habituation control module and the habituation control module in the logic control module are connected to the habituation synapse module, outputs of the de-habituation control module and the habituation control module are connected to the habituation output module, the habituation synapse module is connected to the habituation output module, and the habituation output module outputs the fear emotion signal N6 or the happy emotion signal N7.
6. The visually induced mood habituation characteristic neural network circuit of claim 5, the habituation synapse module is characterized by comprising a memristor M1, an NMOS tube T1, an NMOS tube T2 and a first proportion module, wherein the output end of a controlled voltage side of a voltage-controlled switch S6 of the habituation removal control module is respectively connected with the positive end of the memristor M1 and the drain electrode of the NMOS tube T2, the output end of a same logic gate D6 is connected with the gate electrode of the NMOS tube T1, the output end of the same logic gate D10 of the habituation removal control module is connected with the gate electrode of the NMOS tube T2, the output end of the voltage-controlled switch S7 of the habituation control module is connected with the negative end of the memristor M1, the positive end of the memristor M1 is connected with the drain electrode of the NMOS tube T2, the negative end of the memristor M1 is connected with the drain electrode of the NMOS tube T1, the source electrode of the NMOS tube T1 is connected with the first proportion module, and a resistor R35 is connected with a capacitor C1 in parallel; the source electrode of the NMOS tube T2 is connected with the first proportional module;
the habituation output module comprises a voltage-controlled switch S9, a voltage-controlled switch S11, a seventh voltage-controlled unit, an eighth summation module, a first difference module, a second difference module and a second proportion module, wherein the output end of a same logic gate D7 of the habituation removal control module is respectively connected with the positive input end of the voltage-controlled switch S9 and the input end of the seventh voltage-controlled unit, the output end of the same logic gate D9 of the habituation control module is connected with the positive input end of the voltage-controlled switch S11, the negative input ends of the voltage-controlled switch S9 and the voltage-controlled switch S11 are both grounded, the input ends of the controlled voltage sides of the voltage-controlled switch S9 and the voltage-controlled switch S11 are both connected with the output end of the first proportion module of the habituation synapse module, the output end of the voltage-controlled switch S9 is respectively connected with one end of a resistor R40 and one input end of the first difference module, the output end of the controlled voltage-controlled voltage side of the voltage-controlled switch S11 is connected with one end of a resistor R41 and one input end of the second proportion module, the other ends of the resistor R40 and the resistor R41 are both grounded; the output end of the seventh voltage control unit is connected with the other input end of the first difference module, the input end of the eighth summing module is respectively connected with the output ends of the first difference module and the second proportion module, the output end of the eighth summing module is connected with one input end of the second difference module, the other input end of the second difference module is connected with the output end of the third proportion module in the reinforcement module, and the output end of the second difference module is a happy emotion signal N7; the input end of the eighth voltage control unit is connected with the output end of the same logic gate D8 in the habituation control module, the input end of the controlled voltage side of the eighth voltage control unit is connected with the output end of the first proportion module in the habituation synapse module, and the output end of the controlled voltage side of the eighth voltage control unit is a fear emotion signal N6.
7. The neural network circuit according to any one of claims 2-4 and 6, wherein the reinforcement module comprises a rate change module, a habituation feedback module and a spontaneous recovery feedback module, wherein an input end of the rate change module is connected to an output end of a recovery control module of the reinforcement and logic control module, output ends of the rate change module are respectively connected to input ends of the habituation feedback module and the spontaneous recovery feedback module, an output end of the habituation feedback module is connected to an input end of the habituation control module of the logic control module, and an output end of the spontaneous recovery feedback module is connected to the spontaneous recovery module; the rate change module outputs a feedback signal according to the habituated stimulation signal applied before; the habituation feedback module amplifies the output of the rate change module and feeds the output back to the habituation signal source; the spontaneous recovery feedback module amplifies the output of the rate change module and feeds back the amplified output to the spontaneous recovery module to be used as a spontaneous recovery signal source;
the spontaneous recovery module comprises a voltage comparison module, a starting module and a recovery voltage module, wherein the voltage comparison module is connected with the logic control module and the habituation module, the starting module is connected with the logic control module, and the recovery voltage module is respectively connected with the voltage comparison module, the starting module, the logic control module and the reinforcement module; the voltage comparison module stops outputting signals to the recovery voltage module when the resistance value of the memristor M1 of the habituation synapse module of the habituation module is recovered to the initial value 1K; the starting module generates a 0.09S pulse signal at the spontaneous recovery starting moment to enable the voltage comparison module to function at the spontaneous recovery starting moment; the recovery voltage module applies a spontaneous recovery voltage to the habituation module.
8. The neural network circuit according to claim 7, wherein the rate change module comprises a ninth voltage control unit, a tenth voltage control unit, a ninth summation module, a third difference module and an NMOS transistor T3, wherein the output terminal of the NOT gate D22 of the logic control module is connected to the positive input terminals of the ninth voltage control unit and the tenth voltage control unit, respectively, the output terminal of the XNOR gate D19 of the reinforcement and restoration control module is connected to the input terminal of the controlled voltage side of the ninth voltage control unit, the output terminal of the XNOR gate D21 of the reinforcement and restoration control module is connected to one input terminal of the ninth summation module and the input terminal of the controlled voltage side of the tenth voltage control unit, respectively, the output terminal of the controlled voltage side of the ninth voltage control unit is connected to the other input terminal of the ninth summation module, the output end of the controlled voltage side of the tenth voltage control unit is connected with the grid electrode of an NMOS tube T3, the output end of the ninth summing module is connected with one input end of a third difference-calculating module, the other input end of the third difference-calculating module is connected with the positive electrode of a power supply V7, and the negative electrode of the power supply V7 is grounded; the output end of the third difference finding module is connected with the drain electrode of an NMOS tube T3, the source electrode of the NMOS tube T3 is respectively connected with the input ends of the habituation feedback module and the spontaneous recovery feedback module and one end of a capacitor C3, and the other end of the capacitor C3 is grounded;
the habituation feedback module comprises a voltage control switch S13 and a third proportion module, wherein the output of a habituation control module of the logic control module, which is the same as a logic gate D11, is connected with the positive input end of a voltage control switch S13, the negative input end of the voltage control switch S13 is grounded, the source of an NMOS (N-channel metal oxide semiconductor) tube T3 is connected with the input end of the controlled voltage side of a voltage control switch S13, the output end of the voltage control switch S13 is connected with the input end of the third proportion module, and the output end of the third proportion module is connected with the other input end of a seventh summation module in the habituation control module;
the spontaneous recovery feedback module comprises a voltage control switch S14 and a fourth proportion module, the output end of an AND gate D16 in the strengthening and recovery control module is connected with the positive input end of a voltage control switch S14, the negative input end of the voltage control switch S14 is grounded, the source electrode of an NMOS (N-channel metal oxide semiconductor) tube T3 is connected with the input end of the controlled voltage side of the voltage control switch S14, the output end of the controlled voltage side of the voltage control switch S14 is connected with the input end of the fourth proportion module, and the output end of the fourth proportion module is connected with the spontaneous recovery module.
9. The visually induced emotion habituation characteristic neural network circuit of claim 8, wherein the voltage comparison module includes a voltage-controlled switch S17, a diode, a fifth proportion module, a fourth difference module, a tenth summation module, an NMOS transistor T4, a PMOS transistor T5 and a same logic gate D23, an output terminal of the and gate D16 of the logic control module is connected to a positive input terminal of the voltage-controlled switch S17, a negative terminal of a memristor M1 in the habituation synapse module of the habituation module is connected to an input terminal of a controlled voltage side of the voltage-controlled switch S17, and an output terminal and a negative input terminal of the controlled voltage side of the voltage-controlled switch S17 are both grounded; the output end of the controlled voltage side of a voltage-controlled switch S6 of a sixth voltage-controlled unit of the strengthening and recovering control module is respectively connected with the input end of a diode and one end of a resistor R77, the output end of the diode is connected with the input end of a fifth proportion module, the other end of the resistor R77 is respectively connected with the positive electrode end of a memristor M1 and the grid electrode of an NMOS tube T4 in the habituation module, the output end of the fifth proportion module is respectively connected with one input end of a fourth difference-calculating module, one input end of a tenth summing module and one end of a resistor R86, the other input end of the fourth difference-calculating module is connected with the positive electrode of a power supply V8, the other input end of the tenth summing module is connected with the positive electrode of a power supply V9, and the negative electrodes of the power supply V8 and the power supply V9 are both grounded; the output end of the fourth difference calculating module is connected with the source electrode of an NMOS transistor T4, the output end of the tenth difference calculating module is connected with the source electrode of a PMOS transistor T5, the drain electrode of the NMOS transistor T4 is connected with the other end of a resistor R86 and the grid electrode of the PMOS transistor T5, the drain electrode of the PMOS transistor T5 is connected with one end of a resistor R87 and the input end of a logic gate D23, and the other end of the resistor R87 is grounded; the output end of the same logic gate D23 is connected with the input end of the recovery voltage module;
the starting module comprises an eleventh voltage control unit and a fifth difference module, the output end of an AND gate D16 of the strengthening and recovering control module is respectively connected with the input end and the positive input end of the controlled voltage side of the eleventh voltage control unit and one input end of the fifth difference module, the output end of the controlled voltage side of the eleventh voltage control unit is connected with the other input end of the fifth difference module, and the output end of the fifth difference module is connected with the input end of the recovering voltage module;
the recovery voltage module includes a voltage controlled switch S19, an output end of a same logic gate D23 of the voltage comparison module is connected with one input end of the eleventh summation module, an output end of a fifth difference-finding module of the starting module is connected with the other input end of the eleventh summation module, an output end of the eleventh summation module is connected with a positive input end of a voltage-controlled switch S19, a negative input end of the voltage-controlled switch S19 is grounded, an output end of a controlled voltage side of the voltage-controlled switch S19 is connected with an input end of a controlled voltage side of a sixth voltage-controlled unit of the strengthening and restoring control module, one input end of the twelfth summation module is connected with an output end of a fourth proportion module in the spontaneous restoring feedback module of the strengthening module, the other input end of the twelfth summation module is connected with a positive electrode of a power supply V10, and a negative electrode of the power supply V10 is grounded; the output end of the twelfth summing module is connected with the input end of the controlled voltage side of the voltage-controlled switch S19.
10. The visually induced emotional habituation characteristic neural network circuit of claim 9, wherein an output of the first summing block is connected to an input of a AND logic gate D8, and an output of an AND logic gate D8 is connected to the habituation block; the output end of the second summation module is connected with a same logic gate D9, and the same logic gate D9 is connected with a habituation module;
the source electrode of the NMOS transistor T1 is respectively connected with one end of a resistor R35 and one end of a capacitor C1, and the resistor R36 is connected with the capacitor C2 in parallel; the source electrode of the NMOS tube T2 is respectively connected with one end of a resistor R36 and one end of a capacitor C2, and the other ends of the resistor R35, the capacitor C1, the resistor R36 and the capacitor C2 are all grounded;
the first voltage control unit, the second voltage control unit, the third voltage control unit, the fourth voltage control unit, the fifth voltage control unit and the seventh voltage control unit respectively comprise a first voltage control switch, the positive input end of the first voltage control switch is connected with an input signal, the negative input end of the first voltage control switch is grounded, the controlled voltage side input end of the first voltage control switch is connected with a first power supply, and the controlled voltage side output end of the first voltage control switch is respectively connected with a first resistor and an output signal;
the sixth voltage-controlled unit, the eighth voltage-controlled unit, the ninth voltage-controlled unit, the tenth voltage-controlled unit and the eleventh voltage-controlled unit respectively comprise a second voltage-controlled switch and a second resistor, the positive input end of the second voltage-controlled switch is connected with an input signal, the negative input end of the second voltage-controlled switch is grounded, the controlled voltage-side input end of the second voltage-controlled switch is connected with one end of the second resistor, the other end of the second resistor is grounded, and the controlled voltage-side output end of the second voltage-controlled switch is connected with an output signal;
the first summing module, the second summing module, the third summing module, the fourth summing module, the fifth summing module, the sixth summing module, the seventh summing module, the eighth summing module, the ninth summing module, the tenth summing module, the eleventh summing module and the twelfth summing module respectively comprise a first operational amplifier, the non-inverting input end of the first operational amplifier is respectively connected with a third resistor and a fourth resistor, the third resistor and the fourth resistor are respectively connected with two input signals, the inverting input end of the first operational amplifier is respectively connected with a fifth resistor and a sixth resistor, the fifth resistor is grounded, the sixth resistor is connected with the output end of the first operational amplifier, and the output end of the first operational amplifier outputs the summed signals;
the first proportion module comprises a second operational amplifier, a third operational amplifier, an NMOS tube T1 and a memristor M1, wherein the positive end of the memristor M1 is the input end of the first proportion module, the drain electrode of the NMOS tube T1 is connected with the negative end of the memristor M1, the source electrode of the NMOS tube T1 is respectively connected with the inverting input end and a seventh resistor of the second operational amplifier, the seventh resistor is connected with the output end of the second operational amplifier, and the non-inverting input end of the second operational amplifier is grounded; the output end of the second operational amplifier is connected with an eighth resistor, the eighth resistor is respectively connected with the inverting input end and a tenth resistor of the third operational amplifier, the tenth resistor is connected with the output end of the third operational amplifier, the non-inverting input end of the third operational amplifier is grounded, and the output of the third operational amplifier is the output of the first proportional module;
the second proportion module and the third proportion module, the fourth proportional module and the fifth proportional module respectively comprise a fourth operational amplifier and a fifth operational amplifier, the inverting input end of the fourth operational amplifier is connected with one end of an eleventh resistor, one end of a first resistor is the input end of the second proportional module, the inverting input end of the fourth operational amplifier is connected with the output end of the fourth operational amplifier through a twelfth resistor, the non-inverting input end of the fourth operational amplifier is grounded, the output end of the fourth operational amplifier is connected with one end of a thirteenth resistor, the other end of the thirteenth resistor is respectively connected with the inverting input end of the fifth operational amplifier and the fourteenth resistor, the fourteenth resistor is connected with the output end of the fifth operational amplifier, the non-inverting input end of the fifth operational amplifier is grounded, and the output of the fifth operational amplifier is the output of the second proportional module;
the first difference module, the second difference module, the fourth difference module and the fifth difference module respectively comprise a sixth operational amplifier, the non-inverting input end of the sixth operational amplifier is connected with one end of a fifteenth resistor, the inverting input end of the sixth operational amplifier is connected with the other end of a sixteenth resistor, one ends of the fifteenth resistor and the sixteenth resistor are two input ends of the fifteenth resistor and the sixteenth resistor respectively, and the non-inverting input end of the sixth operational amplifier is grounded through a seventeenth resistor; the inverting input end of the sixth operational amplifier is connected with the output end of the sixth operational amplifier through an eighteenth resistor, and the output of the sixth operational amplifier is the output of the sixth operational amplifier;
the third difference calculating module comprises a seventh operational amplifier, the non-inverting input end of the seventh operational amplifier is connected with one end of a memristor M2, the inverting input end of the seventh operational amplifier is connected with one end of a nineteenth resistor, the other ends of the memristor M2 and the nineteenth resistor are two input ends of the memristor, and the non-inverting input end of the seventh operational amplifier is grounded through a twentieth resistor; and the inverting input end of the sixth operational amplifier is connected with the output end of the seventh operational amplifier through a twenty-first resistor, and the output of the seventh operational amplifier is the output of the seventh operational amplifier.
CN202210751267.9A 2022-06-28 2022-06-28 Visual-evoked emotional habituation characteristic neural network circuit Pending CN114997387A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115363585A (en) * 2022-09-04 2022-11-22 北京中科心研科技有限公司 Standardized group depression risk screening system and method based on habituation removal and film watching tasks
CN116523012A (en) * 2023-07-03 2023-08-01 湖南师范大学 Memristor self-learning circuit based on generation countermeasure neural network

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115363585A (en) * 2022-09-04 2022-11-22 北京中科心研科技有限公司 Standardized group depression risk screening system and method based on habituation removal and film watching tasks
CN115363585B (en) * 2022-09-04 2023-05-23 北京中科心研科技有限公司 Standardized group depression risk screening system and method based on habit removal and film watching tasks
CN116523012A (en) * 2023-07-03 2023-08-01 湖南师范大学 Memristor self-learning circuit based on generation countermeasure neural network
CN116523012B (en) * 2023-07-03 2023-09-08 湖南师范大学 Memristor self-learning circuit based on generation countermeasure neural network

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