CN110910723A

CN110910723A - Pavlov dual-mode switching learning memory circuit based on memristor

Info

Publication number: CN110910723A
Application number: CN201911340520.6A
Authority: CN
Inventors: 孙军伟; 韩俊涛; 李金城; 王英聪; 王延峰; 黄春; 刘鹏; 方洁; 刘娜; 余培照; 栗三一; 王妍; 凌丹
Original assignee: Zhengzhou University of Light Industry
Current assignee: Zhengzhou University of Light Industry
Priority date: 2019-12-23
Filing date: 2019-12-23
Publication date: 2020-03-24
Anticipated expiration: 2039-12-23
Also published as: CN110910723B

Abstract

The invention provides a Pavlov dual-mode switching learning memory circuit based on a memristor, which comprises a first memory module and a second memory module, wherein the first memory module and the second memory module are mutually learning-inhibited, and are connected; the first memory module comprises a first learning voltage selection module, a first learning module and a first learning suppression module; the second memory module comprises a second learning voltage selection module, a second learning module and a second learning suppression module; the output ends of the first excitation signal source and the first learning module are connected with a first OR gate, and the output ends of the second excitation signal source and the second learning module are connected with a second OR gate. The invention uses the learning excitation signal to call the auditory module and the visual module, and the auditory mode learning and the visual mode learning can be switched, thereby achieving the purpose of dual-mode switching learning and solving the problem that the learning memory circuit can only carry out single-mode learning.

Description

Pavlov dual-mode switching learning memory circuit based on memristor

Technical Field

The invention relates to the technical field of digital-to-analog circuits, in particular to a memory learning circuit based on Pavlov dual-mode switching of a memristor.

Background

The Hewlett packard company produces a resistor with memory property in a laboratory, and the resistor is proved to be a fifth passive electronic component, namely a memristor, which is proposed many years ago. As a new element, there is increasing interest among the world's national scholars and has begun to study memristors from various aspects. With the deep understanding of the concept of the memristor, the characteristics of the memristor are found to be very similar to synapses in biological nerves, and partial functions of the brain can be simulated, so that the simulated memory learning of biological behaviors is carried out. From the existing literature, circuit simulation of biological memory behavior has become an extremely important part of memristor research.

At present, many learning memory circuit simulation models based on memristors are proposed, which provides greater possibility for wide application of the memristors. The invention patent application with the application number of 201611256568.5 discloses an artificial neural network circuit based on memristive Barplov associative memory, which realizes learning, forgetting, relearning again and natural forgetting, but the whole circuit is only traditional auditory mode training and does not relate to dual-mode training. Since the current single-mode training of learning and memory behavior based on memristors is too simple and idealized, more and more scholars are beginning to attach importance to more complex and objective dual-mode training. It is believed that memristor-based biological memory learning behavior research will develop better in the near future.

Disclosure of Invention

Aiming at the technical problem that the auditory mode is the traditional learning mode of Pavlov associative memory, but single mode learning cannot reflect the diversity of learning and memory in life, the invention provides a Pavlov dual-mode switching learning and memory circuit based on a memristor, which can realize the learning and memory of the auditory and visual modes and can also realize the switching learning and memory of the auditory and visual modes, thereby really realizing the diversity of learning and memory. Meanwhile, according to the actual situation of the learning process, the invention explores the suppression relation among different learning modes and realizes the suppression relation in a circuit.

In order to achieve the purpose, the technical scheme of the invention is realized as follows: a learning memory circuit based on a memristor and Pavlov dual-mode switching comprises a first memory module and a second memory module which are mutually learning-inhibited, wherein the first memory module is connected with a first excitation signal source, and the second memory module is connected with a second excitation signal source; the first memory module comprises a first learning voltage selection module, a first learning module and a first learning suppression module, a first excitation signal source is respectively connected with the input ends of the first learning voltage selection module, the first learning module and the first learning suppression module, the output end of the first learning voltage selection module is respectively connected with the input ends of the second memory module and the first learning module, the output end of the first learning module is connected with the first learning voltage selection module, the input end of the first learning suppression module is connected with the output end of the second memory module, and the output end of the first learning suppression module is connected with the input end of the first learning voltage selection module; the second memory module comprises a second learning voltage selection module, a second learning module and a second learning suppression module, a second excitation signal source is respectively connected with the second learning voltage selection module, the second learning module and the second learning suppression module, the output end of the second learning module is connected with the input end of the second learning voltage selection module, the output end of the second learning voltage selection module is respectively connected with the input ends of the second learning module and the first learning suppression module, the first learning voltage selection module is connected with the input end of the second learning suppression module, and the output end of the second learning suppression module is connected with the input end of the second learning voltage selection module; the output ends of the first excitation signal source and the first learning module are connected with a first OR gate, the output end of the first OR gate outputs a first learning and memory signal, the output ends of the second excitation signal source and the second learning module are connected with a second OR gate, and the output end of the second OR gate outputs a second learning and memory signal.

The first memory module is an auditory module, the second memory module is a visual module, and the first excitation signal source comprises a food signal F₁And an auditory stimulus signal L₁Food signal F₁Respectively connected with the first learning voltage selection module, the first OR gate and the first learning suppression module, and an auditory stimulation signal L₁The first learning voltage selection module, the first learning module and the first learning suppression module are respectively connected; the second excitation signal source comprises a food signal F₂And a visual stimulus signal S₁Food signal F₂Respectively connected with a second learning voltage selection module, a second OR gate and a second learning suppression module, and a visual stimulation signal S₁The learning voltage selection module, the learning suppression module and the learning suppression module are respectively connected with the first learning voltage selection module, the first learning module and the learning suppression module.

The first learning voltage selection module and the second learning voltage selection module respectively comprise a first AND gate, a first NOT gate, a first voltage absolute value device, a first voltage summation device, a first memristor, and a food signal F₁Or food signal F₂An auditory stimulation signal L₁Or visual stimulus signalsS₁The first AND gate is respectively connected with two input ends of the first AND gate, and outputs a first output end selected by the learning voltage; the first AND gate is connected with the first voltage selection circuit, and the auditory stimulation signal L₁Or visual stimulus signal S₁The output end of the first learning module or the second learning module is connected with the second selection circuit, the first selection circuit and the second selection circuit are both connected with a first voltage summing device, the first voltage summing device is connected with a first memristor, the first memristor is connected with a first voltage follower circuit, the output end of the first voltage follower circuit is respectively connected with a first voltage absolute value device and the first voltage selection circuit, the first voltage absolute value device is connected with the first voltage selection circuit, the output end of the first voltage selection circuit is connected with one input end of a second voltage summing device, the first learning suppression module or the second learning suppression module is connected with the other input end of the second voltage summing device, and the output end of the second voltage summing device outputs a second output end selected by the learning voltage; auditory stimulus signal L₁Or visual stimulus signal S₁The output end of the third selection circuit outputs a third output end selected by the learning voltage.

The first learning suppression module and the second learning suppression module respectively comprise a suppression signal unit and a suppression voltage selection unit, and the suppression signal unit is connected with the suppression voltage selection unit; the suppression signal unit comprises a fourth selection circuit, a fifth selection circuit, a sixth selection circuit, a third voltage summation device, a second memristor, a second voltage following circuit and a second voltage absolute value device, a first output end of the learning voltage selection of the second learning voltage selection module or the first learning voltage selection module is connected with the fourth selection circuit, and an auditory stimulation signal L₁Or visual stimulus signal S₁The output ends of the fourth selection circuit and the fifth selection circuit are connected with a third voltage summing device, the third voltage summing device is connected with a second memristor, the second memristor is connected with a second voltage following circuit, and the second voltage isThe following circuit is connected with the input end of a sixth selection circuit through a second voltage absolute value device, the output end of the sixth selection circuit is connected with one input end of a second AND gate, and an auditory stimulation signal L₁Or visual stimulus signal S₁Respectively connected with another input end of the second AND gate and one input end of the third AND gate, and a food signal F₁Or food signal F₂The other input end of the third AND gate is connected; the suppression voltage selection unit comprises a seventh selection circuit, an inverting proportional amplifier and a third voltage absolute value device, the output end of the second AND gate is connected with the seventh selection circuit, the seventh selection circuit is connected with the inverting proportional amplifier, the output end of the inverting proportional amplifier is respectively connected with the third voltage absolute value device and the input end of the second voltage selection circuit, and the output end of the third voltage absolute value device is connected with the second voltage selection circuit; and the output ends of the second AND gate and the third AND gate are connected with a fourth AND gate, the fourth AND gate is connected with a second voltage selection circuit, and the output end of the second voltage selection circuit is connected with the input end of a second voltage summation device of the first learning voltage selection module or the second learning voltage selection module.

The first learning module and the second learning module respectively comprise a third NOT gate, a voltage processing component, a third memristor, a third voltage following circuit, a fourth voltage summing component, a voltage comparison circuit and an auditory stimulation signal L₁Or visual stimulus signal S₁The third output end of the learning voltage selection of the first learning voltage selection module or the second learning voltage selection module is connected with a third memristor, the third memristor is connected with a third voltage follower circuit, the third voltage follower circuit is connected with one input end of a voltage processing component, the second output end of the learning voltage selection of the first learning voltage selection module or the second learning voltage selection module is connected with the other input end of the voltage processing component, the output end of the voltage processing component is connected with the other input end of a fourth voltage summing component, and the output end of the fourth voltage summing component is connected with a voltage comparison circuitAnd the output end of the voltage comparison circuit is the output end of the first learning module or the second learning module.

The first voltage selection circuit and the second voltage selection circuit respectively comprise a selection switch I, a selection switch II and a second NOT gate, the second NOT gate and the selection switch II are respectively connected with input control signals, the second NOT gate is connected with the selection switch I, voltage input ends of the selection switch I and the selection switch II are respectively connected with different voltage signals, and output ends of the selection switch I and the selection switch II are connected to be used as output ends of the voltage selection circuit; the selection switch I and the selection switch II are first selection switches with two inputs and one output, two input ends of each first selection switch are respectively connected with an input control signal and a voltage input signal, an output end of each first selection switch selects whether to output the voltage input signal according to the input control signal, and the other end of each first selection switch is grounded.

The first selection circuit, the second selection circuit, the third selection circuit, the fourth selection circuit, the fifth selection circuit, the sixth selection circuit and the seventh selection circuit respectively comprise a second selection switch with one input and one output, one input end of the second selection switch is grounded, one input end of the second selection switch is connected with the anode of the first power supply, the cathode of the first power supply is grounded, the other input end of the second selection switch is connected with an input control signal, and the output end of the second selection switch outputs a corresponding voltage signal according to the input control signal; the output end of the second selection switch is connected with a protection resistor, and the other end of the protection resistor is grounded.

The first voltage follower circuit, the second voltage follower circuit and the third voltage follower circuit respectively comprise a first operational amplifier, the non-inverting input end of the first operational amplifier is grounded, and the inverting input end of the first operational amplifier is connected with the output end of the first operational amplifier through a first resistor; the inverting proportional amplifier comprises a second operational amplifier, the non-inverting input end of the second operational amplifier is grounded, the inverting input end of the second operational amplifier is respectively connected with a second resistor and a third resistor, the second resistor is connected with an input signal, and the third resistor is connected with the output end of the second operational amplifier; the voltage comparison circuit comprises a third operational amplifier, the inverting input end of the third operational amplifier is connected with the input signal, the non-inverting input end of the third operational amplifier is connected with the anode of the second power supply, the cathode of the second power supply is grounded, and the output end of the third operational amplifier outputs the output signal of the first learning module or the second learning module.

Compared with the prior art, the invention has the beneficial effects that: the hearing module and the vision module are two learning modules. The hearing module and the vision module are called through the learning excitation signal, the hearing module is responsible for learning of a hearing mode, the vision module is responsible for learning of a vision mode, and mode switching can be carried out between the hearing mode learning and the vision mode learning, so that the purpose of dual-mode switching learning is achieved. When the dual-mode switching learning is performed, the learning memory circuit processes the input signal, and the learning voltage logic unit starts to respond. During the learning process, a learning suppression signal is generated between different learning modes, and the learning rate of another mode is suppressed during the learning process. The invention introduces the dual-mode learning and memory, solves the problem that the existing learning and memory mode is too single, and has very important practical significance for the biological memory field of the memristor and the expansion of the learning and memory circuit.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic circuit diagram of the present invention.

Fig. 2 is a circuit diagram of the auditory learning voltage selection module in fig. 1.

Fig. 3 is a circuit diagram of the visual learning voltage selection module in fig. 1.

Fig. 4 is a circuit diagram of the auditory learning suppression module of fig. 1.

Fig. 5 is a circuit diagram of the visual learning suppression module in fig. 1.

Fig. 6 is a circuit diagram of the auditory learning module of fig. 1.

Fig. 7 is a circuit diagram of the visual learning module of fig. 1.

Fig. 8 is a circuit diagram of the auditory-followed-visual mode simulation of the present invention.

Fig. 9 is a circuit diagram of a simulation of a visual-then-auditory mode of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.

A learning memory circuit based on double-mode switching of Pavlov associative memory of a memristor comprises a first memory module and a second memory module which are mutually subjected to learning suppression, wherein the first memory module is connected with the second memory module, the first memory module is connected with a first excitation signal source, and the second memory module is connected with a second excitation signal source; the first memory module comprises a first learning voltage selection module, a first learning module and a first learning suppression module, a first excitation signal source is respectively connected with the input ends of the first learning voltage selection module, the first learning module and the first learning suppression module, the output end of the first learning voltage selection module is respectively connected with the input ends of the second memory module and the first learning module, the output end of the first learning module is connected with the first learning voltage selection module, the input end of the first learning suppression module is connected with the output end of the second memory module, and the output end of the first learning suppression module is connected with the input end of the first learning voltage selection module; the second memory module comprises a second learning voltage selection module, a second learning module and a second learning suppression module, a second excitation signal source is respectively connected with the second learning voltage selection module, the second learning module and the second learning suppression module, the output end of the second learning module is connected with the input end of the second learning voltage selection module, the output end of the second learning voltage selection module is respectively connected with the input ends of the second learning module and the first learning suppression module, the first learning voltage selection module is connected with the input end of the second learning suppression module, and the output end of the second learning suppression module is connected with the input end of the second learning voltage selection module; the output ends of the first excitation signal source and the first learning module are connected with a first OR gate, the output end of the first OR gate outputs a first learning and memory signal, the output ends of the second excitation signal source and the second learning module are connected with a second OR gate, and the output end of the second OR gate outputs a second learning and memory signal.

As shown in fig. 1, the first memory module may be an audio module, the second memory module may be a visual module, and the audio module and the visual module are connected. The hearing module comprises a hearing learning voltage selection module, a hearing learning module and a hearing learning suppression module, wherein the input ends of the hearing learning voltage selection module, the hearing learning module and the hearing learning suppression module are connected with a first excitation signal source, the input end of the hearing learning module is connected with the output end of the hearing learning voltage selection module, the output end of the hearing learning suppression module is connected with the input end of the hearing learning module, the output end of the hearing learning voltage selection module is connected with the input end of the hearing learning module, the hearing learning suppression module is used for suppressing the work of the hearing learning voltage selection module, and the vision module is connected with the hearing learning suppression module; the vision module comprises a vision learning voltage selection module, a vision learning module and a vision learning suppression module, wherein the input ends of the vision learning voltage selection module, the vision learning module and the vision learning suppression module are all connected with a second excitation signal source, the input end of the vision learning module is connected with the output end of the vision learning voltage selection module, the output end of the auditory learning voltage selection module is connected with the input end of the vision learning suppression module, the output end of the vision learning suppression module is connected with the vision learning voltage selection module, namely, when the auditory learning voltage selection module works, a signal is sent to the vision learning suppression module, the work of the vision learning voltage selection module is suppressed through the vision learning suppression module, similarly, when the vision learning voltage selection module works, the signal is sent to the auditory learning suppression module, and the work of the auditory learning voltage selection module is suppressed through the auditory learning suppression module, namely, the two modes of auditory learning and visual learning are switched. The output end of the auditory learning module outputs a signal that the auditory learning is finished, and the output end of the visual learning module outputs a signal that the visual learning is finished.

The first excitation signal source and the second excitation signal source are respectively used for controlling the auditory learning voltage selection module, the visual learning voltage selection module, the auditory learning suppression module and the visual learning suppression module. The first driving signal source comprises a food signal F₁And an auditory stimulus signal L₁Food signal F₁Respectively connected with the first learning voltage selection module, the first OR gate and the first learning suppression module, and an auditory stimulation signal L₁The first learning voltage selection module, the first learning module and the first learning suppression module are respectively connected; the second excitation signal source comprises a food signal F₂And a visual stimulus signal S₁Food signal F₂Respectively connected with a second learning voltage selection module, a second OR gate and a second learning suppression module, and a visual stimulation signal S₁The learning voltage selection module, the learning suppression module and the learning suppression module are respectively connected with the first learning voltage selection module, the first learning module and the learning suppression module. Food signal F₁And the input ends of the auditory learning voltage selection module and the auditory learning suppression module are respectively connected. Auditory stimulus signal L₁And the input ends of the auditory learning voltage selection module, the auditory learning module and the auditory learning suppression module are respectively connected. Food signal F₂And the input ends of the visual learning voltage selection module and the visual learning suppression module are respectively connected. Visual stimulus signal S₁And the input ends of the visual learning voltage selection module, the visual learning module and the visual learning suppression module are respectively connected.

The food signal F1 and the auditory stimulation signal L1 both output a high level, the auditory mode proceeds, and the auditory learning voltage selection module and the visual learning suppression module start responding. The auditory learning voltage selection module starts to generate an auditory learning voltage, and the visual learning suppression signal unit in the visual learning suppression module starts to generate a visual learning suppression signal. The food signal F1 and the auditory stimulation signal L1 output a low level, the food signal F2 and the visual stimulation signal S1 output a high level, the auditory mode is stopped, and the visual mode is performed. The visual learning voltage selection module and the auditory learning suppression module start to respond, and the visual learning suppression signal begins to fade. And the visual learning voltage and the visual learning suppression voltage are output to the visual learning module together after being selected. The excitation signal is changed continuously, and the learning mode is switched continuously until the auditory learning module and the visual learning module output high level.

The voltage selection modules for auditory learning or visual learning respectively comprise three input ends and three output ends, the three input ends are respectively connected with two excitation signals of a first excitation signal source or a second excitation signal source and output signals of the auditory or visual learning module, the three output ends are connected with one of the three input ends and connected with the corresponding learning suppression module, namely the output end of the auditory learning voltage selection module is connected with the input end of the visual learning suppression module, and the output end of the visual learning voltage selection module is connected with the input end of the auditory learning suppression module; the other two output ends of the voltage selection module are connected with the corresponding learning modules. The single suppression module comprises three input ends and an output end, the three input ends are respectively connected with two excitation signals of the first excitation signal source or the second excitation signal source and one output end of the corresponding voltage selection module, and the output end is connected with the corresponding voltage selection module. The single learning module comprises three input ends and an output end, wherein the three input ends are respectively connected with the auditory stimulation signals L₁Or visual stimulus signal S₁And the output end is connected with the corresponding voltage selection module. The output end of the auditory learning voltage selection module and the output end of the auditory learning suppression module are connected through a voltage summation device and then the voltage input end of the auditory learning module, and the output end of the visual learning voltage selection module and the output end of the visual learning suppression moduleAnd the voltage summing device is connected with the voltage input end of the vision learning module. The output ends of the two learning modules output signals of learning completion. The food signal F₁The output end of the hearing learning module is connected with a first OR gate, the output end of the first OR gate outputs a first learning and memory signal, and a food signal F₂And the output end of the visual learning module is connected with a second OR gate, and the output end of the second OR gate outputs a second learning and memory signal. The first learning and memory signal and the second learning and memory signal represent saliva signals.

The first learning voltage selection module and the second learning voltage selection module respectively comprise a first AND gate, a first NOT gate, a first voltage absolute value device, a first voltage summation device, a first memristor, and a food signal F₁Or food signal F₂An auditory stimulation signal L₁Or visual stimulus signal S₁The first AND gate is respectively connected with two input ends of the first AND gate, and outputs a first output end selected by the learning voltage; the first AND gate is connected with the first voltage selection circuit, and the auditory stimulation signal L₁Or visual stimulus signal S₁The output end of the first learning module or the second learning module is connected with the second selection circuit, the first selection circuit and the second selection circuit are both connected with a first voltage summing device, the first voltage summing device is connected with a first memristor, the first memristor is connected with a first voltage follower circuit, the output end of the first voltage follower circuit is respectively connected with a first voltage absolute value device and the first voltage selection circuit, the first voltage absolute value device is connected with the first voltage selection circuit, the output end of the first voltage selection circuit is connected with one input end of a second voltage summing device, the first learning suppression module or the second learning suppression module is connected with the other input end of the second voltage summing device, and the output end of the second voltage summing device outputs a second output end selected by the learning voltage; auditory stimulus signal L₁Or visual stimulus signal S₁The output end of the third selection circuit outputs a third output end selected by the learning voltage.

As shown in fig. 2, the first learning voltage selection module, i.e. the auditory learning voltage selection module, includes a first and gate a₁First NOT gate D₂First voltage absolute value device ABS₁First voltage summing device SUM₁And a first memristor M₂Food signal F₁And an auditory stimulus signal L₁Respectively connected with a first AND gate A₁Is connected with the first AND gate A₁The output terminal of (A) is a first output terminal V (A) selected by the learning voltage₁) (ii) a Auditory stimulus signal L₁Connected with a first selection circuit including a second selection switch S with an input and an output₁Second selection switch S₁Controlling the generation of an auditory excitation voltage, a second selection switch S₁An input terminal of the first power supply and the second power supply₁Is connected to the positive pole of a first power supply V₁Is grounded, the second selection switch S₁Is conducted with the input control signal, i.e. the auditory stimulation signal L₁Connected, a second selection switch S₁According to an input control signal, i.e. an auditory stimulus signal L₁Outputting a corresponding voltage signal; second selection switch S₁Is connected with a protective resistor R₁Protection resistor R₁The other end of the first and second electrodes is grounded; second selection switch S₁And the first voltage summing device SUM₁Is connected to one input terminal. Output terminal V (N) of hearing learning module₁) A second selection switch S connected to the second selection circuit, i.e. an input-output₂Is connected to the on-signal input terminal of the first selection switch S₂Controlling the generation of an auditory learning feedback voltage, a second selection switch S₂One input terminal of the first power supply is grounded, and the other input terminal is connected with the first power supply V₂Is connected to the positive pole of a first power supply V₂Is grounded, the second selection switch S₂Output terminal and protective resistor R₂Connected to protect the resistor R₂And the other end of the same is grounded. Second selection switch S₂And the first voltage summing device SUM₁Is connected to the other input terminal of the first voltage summing device SUM₁The accumulation of the output signals of the second selection switch S1 and the second selection switch S2 is achieved. SUM of Voltage summing device of the present invention₁- SUM₈A voltage summing device model SUM50N03 is used. When the output voltage value of the first voltage summing device SUM1 is less than the threshold voltage of the first memristor M2, the resistance value of the first memristor M2 is maintained at 100 Ω; when the output voltage value of the first voltage summing device SUM1 is greater than the threshold voltage of the first memristor M2, the resistance value of the first memristor M2 quickly rises to 200 Ω. First Voltage summing device SUM₁Output terminal and first memristor M₂Is connected with the positive terminal of the first memristor M₂And the first operational amplifier OP of the first voltage follower₁Is connected to the inverting input terminal of the first operational amplifier OP₁The non-inverting input terminal of the first operational amplifier OP is grounded₁Is connected with the inverting input end through a first resistor R₃And a first operational amplifier OP₁Are connected to the output of the first operational amplifier OP₁Respectively connected with the first voltage selection circuit and the first voltage absolute value device ABS₁Connected, first voltage absolute value device ABS₁Is connected to the other input of the first voltage selection circuit. First voltage absolute value device ABS₁Is a positive value, i.e., a learning voltage. The first memristor M2 is reverse connected. The voltage absolute value device ABS of the invention₁-ABS₆The voltage absolute value device with the model number of ABS05 is adopted, and the output voltage is the absolute value of the input voltage. The first voltage selection circuit comprises a selection switch IS₃Selection switch IIS₄And a second not gate D₁Second NOT gate D₁And a selection switch IIS₄Are respectively connected with an input control signal which is a first output end V (A)₁) Output signal of, a second not gate D₁And selection switch I S₃Phase connection, selection switch I S₃And a selector switch IIS₄Are respectively connected with different voltage signals, i.e. selection switch I S₃Conducting the signal input terminal and the second NOT gate D₁Is connected with the output terminal of the selection switch IIS₄On signal input ofTerminal and first AND gate A₁Is connected to the output terminal of the selection switch I S₃Voltage input terminal and first operational amplifier OP₁Is connected with the output end of the selection switch IIS₄Voltage input terminal and first voltage absolute value device ABS₁Is connected to the output terminal of the selection switch I S₃And a selector switch IIS₄The output end of the voltage selection circuit is connected with the output end of the voltage selection circuit; second NOT gate D₁Control selection switch I S₃And a selector switch IIS₄The first voltage selection circuit is used for realizing the output of auditory learning or forgetting signals. Selection switch IS₃And a selector switch IIS₄The voltage-controlled switch comprises a first selection switch with two inputs and one output, wherein two input ends of the first selection switch are respectively connected with an input control signal and a voltage input signal, an output end of the first selection switch selects whether to output the voltage input signal according to the input control signal, and the other end of the first selection switch is grounded. Selection switch I S₃And a selector switch IIS₄And the output terminal of the second summing voltage summing device SUM₂IN of₁Input terminal connected, second summing voltage summing device SUM₂IN of₂Input end is connected with output end VSUM of auditory suppression module₂（IN₂) Connected and output end VSUM₂(out) is connected to the auditory learning module. Auditory stimulus signal L₁Through a first not gate D₂A second selection switch S connected to an input and an output of the third selection circuit₅Is connected to the on-signal input terminal of the first selection switch S₅With ground and the first power supply V, respectively₃Is connected to the positive pole of a first power supply V₃Is grounded, the second selection switch S₅Is output terminal V (S)₅) A third output terminal selected for learning voltage, output terminal V (S)₅) Is connected with the input end of the hearing learning module.

As shown in FIG. 3, the visual learning voltage selection module comprises a first AND gate A₅First NOT gate D₆First voltage absolute value device ABS₄First voltage summing device SUM₅A first memristor,Second voltage summing device SUM₆And a selection switch S₁₂Composed of a first selection circuit and a selection switch S₁₃Second selection circuit, selection switch S₁₄And a selector switch S₁₅First power supply selection circuit voltage, selection switch S₁₆Third selection circuit, first operational amplifier OP₆The first voltage follower, the first AND gate A₅Input terminal of (3) receiving food signal F₂With visual stimulus signal S₁The first AND gate A₅Is output terminal V (A)₅) Connected with the input end of the auditory learning suppression module, a first AND gate A₅Output ends of the first and second NOT gates are respectively connected with a first NOT gate D₅Input terminal and selection switch S₁₅To the on signal input terminal. First AND gate A₅Is connected with the selection switch S₁₄To the on signal input terminal. First NOT gate D₆The input end of the optical fiber is connected with the visual stimulation signal S₁An output terminal of the first not gate D₆Is connected with the selection switch S₁₆Is turned on signal input terminal, the selection switch S₁₆Respectively connected to ground and a first power supply V₁₁Positive electrode of (1), first power supply V₁₁Is grounded, i.e. selection switch S₁₆Is connected with a first voltage source V₁₁Selection switch S₁₆Is output terminal V (S)₁₆) The third output end of the device is connected with the input end of the visual learning module. Voltage absolute value device ABS₄Is connected with the first operational amplifier OP₆Voltage absolute value device ABS₄Is connected with the selection switch S₁₅To the voltage input terminal. Memristor M₄Input terminal of SUM₅Is connected with the first operational amplifier OP₆Is a first operational amplifier OP₆Through a first resistor R₁₆And a first operational amplifier OP₆The output ends of the voltage-stabilizing circuit are connected to realize the function of voltage proportion change. A first operational amplifier OP₆The anode is grounded, and the output is connected with the voltage absolute value device ABS₄And a selection switch S₁₄To the voltage input terminal. Selection switch S₁₂The input end of the conducting signal is connected with the visual stimulation signal S₁The voltage input end of the output end of the voltage source V is connected with₉The voltage output end is connected with the first voltage summation device SUM₅IN of₁An input terminal. Selection switch S₁₃The conduction signal input end of the optical fiber is connected with the visual stimulation signal S₁Selection switch S₁₂Is connected with a first voltage source V₉Positive pole of (2), selection switch S₁₂Voltage output terminal of (1) is connected with first voltage summation device SUM₅IN of₂Input terminal and protective resistor R₁₄Protection resistor R₁₄And the other end of the same is grounded. Selection switch S₁₃The input end of the conducting signal is connected with the output end V (N) of the vision learning module₂) Selection switch S₁₃Is connected with a first voltage source V₁₀Positive pole of (2), selection switch S₁₃Voltage output terminal of (1) is connected with first voltage summation device SUM₅IN of₂Input terminal and protective resistor R₁₅Protection resistor R₁₅And the other end of the same is grounded. Selection switch S₁₄The conducting signal input end of the first NOT gate D is connected with the first NOT gate₅The output end and the voltage input end of the first operational amplifier OP₆Voltage output terminal of the first voltage summing device SUM₆IN of₁An input terminal. Selection switch S₁₅The input end of the conducting signal is connected with the first AND gate A₅The voltage input end of the voltage input end is connected with a voltage absolute value device ABS₄Voltage output terminal connected to the second voltage summing device SUM₆IN of₁An input terminal. Second voltage summing device SUM₆IN of₂The input end is connected with the output end of the visual suppression module.

The first learning suppression module and the second learning suppression module respectively comprise a suppression signal unit and a suppression voltage selection unit, and the suppression signal unit is connected with the suppression voltage selection unit. The suppression signal unit comprises a fourth selection circuit, a fifth selection circuit, a sixth selection circuit, a third voltage summation device, a second memristor, a second voltage following circuit and a second voltage absolute value device, and the learning voltage selection of the second learning voltage selection module or the first learning voltage selection moduleIs connected with a fourth selection circuit, an auditory stimulation signal L₁Or visual stimulus signal S₁The output ends of the fourth selection circuit and the fifth selection circuit are connected with a third voltage summing device, the third voltage summing device is connected with a second memristor, the second memristor is connected with a second voltage following circuit, the second voltage following circuit is connected with the input end of a sixth selection circuit through a second voltage absolute value device, and the output end of the sixth selection circuit is connected with one input end of a second AND gate of the suppression voltage selection unit; the suppression voltage selection unit comprises a seventh selection circuit, an inverting proportional amplifier, a third voltage absolute value device and an auditory stimulation signal L₁Or visual stimulus signal S₁Respectively connected with another input end of the second AND gate and one input end of the third AND gate, and a food signal F₁Or food signal F₂The other input end of the third AND gate is connected; the output end of the second AND gate is connected with a seventh selection circuit, the seventh selection circuit is connected with an inverting proportional amplifier, the output end of the inverting proportional amplifier is respectively connected with the input ends of a third voltage absolute value device and a second voltage selection circuit, and the output end of the third voltage absolute value device is connected with the second voltage selection circuit; and the output ends of the second AND gate and the third AND gate are connected with a fourth AND gate, the fourth AND gate is connected with a second voltage selection circuit, and the output end of the second voltage selection circuit is connected with the input end of a second voltage summation device of the first learning voltage selection module or the second learning voltage selection module.

As shown in fig. 4, the auditory learning suppression module includes an auditory learning suppression signal unit including a third voltage summing device SUM and an auditory learning suppression voltage selection unit₄The second memristor M₃A first operational amplifier OP₄And a first resistor R₉Second voltage follower circuit and second voltage absolute value device ABS formed₂Selection switch S₆Fourth selection circuit, selection switch S₇Composed of a fifth selection circuit and a selection switch S₈Composition ofThe sixth selection circuit of (1). Output end V (A) of visual learning voltage selection module₅) And a selector switch S₆Is connected with the conducting signal input end of the selector switch S₆Voltage input terminal and first voltage source V₄Is connected to the positive pole of a first voltage source V₄Is grounded, the selection switch S₆Respectively with a third voltage summing device SUM₄IN of₁Input terminal and protective resistor R₇Connected to protect the resistor R₇And the other end of the same is grounded. Auditory stimulus signal L₁And a selector switch S₇Is connected with the conducting signal input end of the selector switch S₇Voltage input terminal and first voltage source V₅Is connected to the positive pole of a first voltage source V₅Is grounded, the selection switch S₇Respectively with a third voltage summing device SUM₄IN of₂Input terminal and protective resistor R₈Connected to protect the resistor R₈And the other end of the same is grounded. The resistance value of the second memristor M3 is continuously reduced under the action of positive voltage, and the smaller the positive voltage is, the faster the resistance value is reduced; the resistance value of the resistor continuously rises under the action of negative voltage, and the resistance value rises more slowly as the negative voltage is smaller. Second memristor M₃Is connected to the third voltage summing device SUM₄The positive terminal of the second memristor M3 is connected with the first operational amplifier OP₄A negative phase input terminal of the first operational amplifier OP₄The positive input terminal of the first operational amplifier OP is grounded₄Through a first resistor R₉Connected to its output, a first operational amplifier OP₄Is connected with the second voltage absolute value device ABS₂Of the second voltage absolute value device ABS₂Is connected with the selection switch S₈To the on signal input terminal. Selection switch S₈The conduction signal input end of the second voltage absolute value device ABS₂Of the output terminal, the selection switch S₈Voltage input end of the voltage source V₆The positive electrode and the voltage output end of the second AND gate of the hearing learning suppression voltage selection unit are connected. Voltage source V₆Negative electrode of (2), selection switch S₈Voltage output terminal and protectorProtective resistor R₁₀Phase connection, selection switch S₈Another input terminal of voltage source V₆Negative electrode and protective resistor R₁₀And (4) grounding.

The auditory sense learning suppression voltage selection unit comprises a second AND gate A₂And a third AND gate A₃Fourth AND gate A₄Selection switch S₉The seventh selection circuit and the third voltage absolute value device ABS are formed₃A first operational amplifier OP₅Formed inverting proportional amplifier and first NOT gate D₄Selection switch S₁₀And a selector switch S₁₁And forming a second voltage selection circuit. Second AND gate A₂Respectively with an auditory stimulus signal L₁Selection switch S₈Is connected to the voltage output terminal of the first and gate A₂The output end of the same is connected with a selection switch S₉On signal input terminal, fourth and gate a₄Are connected. Third AND gate A₃Respectively with the food signal F₁An auditory stimulation signal L₁Connected, the third AND gate A₃And the fourth and gate a₄Is connected to the input terminal of, i.e. the fourth and-gate a₄Respectively with a second AND gate A₂Output terminal of (1), third AND gate A₃Is connected to the output of the fourth and-gate A₄And the first not gate D₄Input terminal of (1), selection switch S₁₁Are connected to the on signal input terminal. First NOT gate D₄And the selection switch S₁₀Are connected to the on signal input terminal. Selection switch S₉Is connected with the second AND gate A₂Is connected to the output terminal of the selector switch S₉Is connected with a first voltage source V₇Selection switch S₉Voltage output terminal and protective resistor R₁₁Phase connection, selection switch S₉Of the other input terminal of the first voltage source V₇Negative electrode and protective resistor R₁₁Is grounded, the other end of the switch S is selected₉Is connected with the inverting proportional amplifier. The inverting proportional amplifier comprises a second operational amplifier OP₅A second operational amplifier OP₅ToThe phase input terminals are respectively connected with the second resistors R₁₂A third resistor R₁₃Connected, a second resistor R₁₂And a selector switch S₉Is connected to the voltage output terminal of the third resistor R₁₃And a second operational amplifier OP₅Are connected to the output terminal of the first operational amplifier OP₅Respectively with a third voltage absolute value device ABS₃Input terminal of (1), selection switch S₁₀Is connected to the voltage input terminal of the selector switch S₁₀Voltage output terminal of (2) is connected with SUM₂IN of₂An input terminal. Selection switch S₁₁The conducting signal input end of the first NOT gate D is connected with the first NOT gate₄The output end and the voltage input end of the voltage-measuring device are connected with a third voltage absolute value device ABS₃Voltage output terminal connected to the second voltage summing device SUM₂IN of₂Input terminal, selection switch S₁₀And a selector switch S₁₁The other input terminal of (b) is grounded.

As shown in fig. 5, the visual learning suppression module includes a visual learning suppression signal unit and a visual learning suppression voltage selection unit, and the visual learning suppression signal unit includes a third voltage summation device SUM₈The second memristor M₆A first operational amplifier OP₉Second voltage follower circuit and second voltage absolute value device ABS₅Three selection switches S₁₇、S₁₈、S₁₉A fourth selection circuit, a fifth selection circuit and a sixth selection circuit. The positive terminal of the second memristor M6 is connected to the output terminal of the third voltage summing device SUM8, and the negative terminal is connected to the inverting input terminal of the first operational amplifier OP 9. A first operational amplifier OP₉The non-inverting input terminal of the first operational amplifier OP is grounded₉Is connected to the inverting input terminal through a resistor R₂₂And a first operational amplifier OP₉Are connected to the output of the first operational amplifier OP₉Is connected with the second voltage absolute value device ABS₅Of the second voltage absolute value device ABS₅Is connected with the selection switch S₁₉To the on signal input terminal. Selection switch S₁₇The conduction signal input end of the first AND gate A of the visual learning voltage selection module₅Of the output terminalV（A₅) A voltage input terminal connected to a voltage source V₁₂The voltage output ends are respectively connected with a protective resistor R₂₀And a third voltage summing device SUM₈IN of₁Input terminal, protection resistor R₂₀Voltage source V₁₂Negative electrode of (2), selection switch S₁₇Are all grounded. Selection switch S₁₈The conduction signal input end of the optical fiber is connected with the visual stimulation signal S₁A voltage input terminal connected to a voltage source V₁₃The voltage output end is respectively connected with a protective resistor R₂₁And SUM₈IN of₂Input terminal, protection resistor R₂₁Voltage source V₁₃Negative electrode of (2), selection switch S₁₈Are all grounded. Selection switch S₁₉Voltage input end of the voltage source V₁₄The voltage output end is connected with the input end of the sixth AND gate of the visual learning suppression voltage selection unit, and the selection switch S₁₉Voltage output terminal of the resistor R is connected with a protective resistor R₂₃Protection resistor R₂₃Voltage source V₁₄The negative electrode of (2) is grounded.

The visual learning suppression voltage selection unit comprises a second AND gate A₆And a third AND gate A₇Fourth AND gate A₈Third voltage absolute value device ABS₆A second amplifier OP₁₀Formed inverting proportional amplifier and selective switch S₂₀The seventh selection circuit and the first NOT gate D₈Selection switch S₂₁Selection switch S₂₂And forming a second voltage selection circuit. Second AND gate A₆The input ends of the signals are respectively matched with the visual stimulation signals S₁Selection switch S₁₉Is connected to the voltage output terminal of the first and gate A₆Output end same selection switch S₂₀A of the fourth and gate₈The input ends are connected. Third AND gate A₇Respectively with the food signal F₂Visual stimulation signal S₁Connected, the third AND gate A₇And the fourth and gate a₈The input ends are connected. Fourth AND gate A₈Respectively with a second AND gate A₆Output terminal of (1), third AND gate A₇Is connected to the output of the fourth and-gate A₈Output of (2)End and first not gate D₈Input terminal, selection switch S₂₂Are connected to the on signal input terminal. First NOT gate D₈Input terminal and fourth AND gate A₈Output of the switch is connected with the output end of the selection switch S₂₁Are connected to the on signal input terminal. Selection switch S₂₀Is connected with the second AND gate A₆The output end and the voltage input end of the voltage transformer are connected with a voltage source V₁₅The voltage output end is connected with an inverting proportional amplifier which comprises a second operational amplifier OP₁₀A second operational amplifier OP₁₀Is grounded, and a second operational amplifier OP₁₀Respectively with the second resistor R₂₅And a third resistor R₂₆Connected, a second resistor R₂₅And a selector switch S₂₀Is connected to the voltage output terminal of the third resistor R₂₆And a second operational amplifier OP₁₀The output ends of the two are connected. Selection switch S₂₁The conducting signal input end of the first NOT gate D is connected with the first NOT gate₈Is connected with the second operational amplifier OP₁₀Voltage output terminal of the first voltage summing device SUM₆IN of₂An input terminal. Selection switch S₂₂The conducting signal input end of the first and gate A is connected with the fourth and gate₈The output end and the voltage input end are connected with a third voltage absolute value device ABS₆Voltage output terminal connected to the second voltage summing device SUM₆IN of₂An input terminal.

The first learning module and the second learning module respectively comprise a third NOT gate, a voltage processing component, a third memristor, a third voltage following circuit, a fourth voltage summing component, a voltage comparison circuit and an auditory stimulation signal L₁Or visual stimulus signal S₁The first learning voltage selection module or the second learning voltage selection module is connected with one input end of a fourth voltage summing device through a third NOT gate, a third output end of the learning voltage selection of the first learning voltage selection module or the second learning voltage selection module is connected with a third memristor, the third memristor is connected with a third voltage follower circuit, the third voltage follower circuit is connected with one input end of a voltage processing component, and the first learning voltage selection module or the second learning voltage selection module is connected with one input end of a fourth voltage summing deviceThe second output end of the learning voltage selection module is connected with the other input end of the voltage processing component, the output end of the voltage processing component is connected with the other input end of the fourth voltage summing component, the output end of the fourth voltage summing component is connected with the voltage comparison circuit, and the output end of the voltage comparison circuit is the output end of the first learning module or the second learning module.

As shown in FIG. 6, the auditory learning module includes a third NOT gate D₃Voltage processing element ABM₁Fourth voltage summing device SUM₃The third memristor M₁A first operational amplifier OP₂Third voltage follower circuit and third operational amplifier OP₃Forming a voltage comparison circuit. Third not gate D₃Input end and auditory stimulation signal L₁Is connected with the output end of the fourth voltage summing device SUM₃IN of₂The input ends are connected. Third memristor M₃The positive terminal of the same-hearing learning voltage selection module is connected with a second voltage summation device SUM of the same-hearing learning voltage selection module₂Is connected with the output end of the first memristor M₃The negative end of the output end of the first operational amplifier OP is connected with the negative end of the output end of the first operational amplifier₂A negative phase input terminal of the first operational amplifier OP₂The non-inverting input terminal of the first operational amplifier OP is grounded₂Through a first resistor R₅And a first operational amplifier OP₂Are connected to the output of the first operational amplifier OP₂Output end and voltage processing component ABM₁IN of₁The input ends are connected. Voltage processing component ABM₁IN of₁The input end is connected with a first operational amplifier OP₂Output terminal, IN₂Input terminal and second voltage summing device SUM₂Is connected with the output end of the voltage processing component ABM₁And the fourth voltage summing device SUM₃IN of₁The input ends are connected. Amplifier OP₃The negative input end of the voltage source is connected with the positive input end of the voltage source₁₂The output end is connected with S₂To the on signal input terminal. Voltage processing component ABM₁Is equal to IN₂Input terminal voltage divided by IN₁Absolute value of input voltage, i.e. M₁/R₅. When the first memristor M₁When the resistance value is reduced, the voltage processing component ABM₁The output voltage of (2) is reduced accordingly. Voltage processing component ABM₁When the output voltage of (2) is lowered to the threshold value, the third operational amplifier OP₃The voltage of the positive electrode is larger than that of the negative electrode, and a signal is output.

The voltage comparison circuit comprises a third operational amplifier OP₃A third operational amplifier OP₃And the input signal, i.e. the fourth voltage summing device SUM₃Are connected to the output terminal of the third operational amplifier OP₃Non-inverting input terminal of and a second power supply V₈Is connected to the positive pole of a second power supply V₈Is grounded at its negative pole, and a third operational amplifier OP₃Is the output terminal V (N)₁) Output signal of the hearing learning module.

As shown in FIG. 7, the vision learning module includes a third NOT gate D₇Voltage processing element ABM₂Fourth voltage summing device SUM₇The third memristor M₄And a first operational amplifier OP₇A third voltage follower circuit, a third operational amplifier OP₈The voltage comparison circuit is formed. Third not gate D₇Input terminal and visual stimulation signal S₁Connected, output terminal and fourth voltage summing device SUM₇IN of₂The input ends are connected. Third memristor M₄With the positive terminal of the second voltage summing device SUM₆Output terminal of (1), selection switch S₁₆Is connected with the voltage output end of the first memristor M₄Is connected with the negative end of the first operational amplifier OP₇The first operational amplifier OP₇The non-inverting input terminal of the first operational amplifier OP is grounded₇Is connected to the inverting input terminal through a resistor R₁₈And a first operational amplifier OP₇Are connected to the output of the first operational amplifier OP₇Output end and voltage processing component ABM₂IN of₁The input ends are connected. Voltage processing component ABM₂IN of₁The input end is connected with a first operational amplifier OP₇At the output end, pressure pointABM element managing device₂IN of₂The input terminal is connected with a second voltage summation device SUM₆Output terminal of (1), selection switch S₁₆Voltage output end of the voltage processing element ABM is connected₂And the fourth voltage summing device SUM₇IN of₁The input ends are connected. Third operational amplifier OP₈Is connected to the fourth voltage summing device SUM₇Of the third operational amplifier OP₈The non-inverting input terminal of the voltage source V₁₆A third operational amplifier OP₈Is connected to the output terminal of the selection S₁₃To the on signal input terminal.

The invention comprises two learning modules, namely an auditory module and a visual module, which respectively represent an auditory learning mode and a visual learning mode. The hearing module comprises a hearing learning voltage selection module, a hearing learning module and a visual learning suppression module, and the visual learning suppression module comprises a visual learning suppression signal module and a visual learning suppression voltage selection module. The visual module comprises a visual learning voltage selection module, a visual learning module and a visual learning suppression module, and the auditory learning suppression module comprises an auditory learning suppression signal unit and an auditory learning suppression voltage selection unit. Auditory stimulus signal L₁With food signal F₁A high level is output and the auditory learning mode begins. The auditory learning voltage selection module, the auditory learning module and the visual learning suppression signal unit are called, and visual learning suppression signals are generated while auditory learning is performed. Auditory stimulus signal L₁With food signal F₁Outputting a low level, visual stimulus signal S₁With food signal F₂The output high level, the auditory learning mode is stopped, and the visual learning mode is started. The visual learning voltage selection module, the visual learning module, the auditory learning suppression signal unit, the visual learning suppression signal unit and the visual learning suppression voltage selection module are called, and the visual learning module is under the dual functions of the visual learning voltage selection module and the visual learning suppression selection voltage module. The visual learning simultaneously generates an auditory learning suppression signal and a visual learning suppression elimination signal.

Specifically, the inventionThe circuit structure can complete the function of learning the switching mode of the auditory mode and the visual mode of the puppy. Puppy food signal F₁And an auditory stimulus signal L₁The hearing patterns are learned by the action of (1). Normally, the puppy can flow out of the water by the aid of the auditory signals alone after learning for T seconds, and accordingly auditory learning is completed. Puppy food signal F₂And a visual stimulus signal S₁The visual pattern is learned under the action of (1). Normally, when the dog learns for W seconds, the dog can flow out of the water solely under the action of the visual signals, namely, the visual learning is finished. The method comprises the following steps that a puppy firstly performs auditory mode learning for A seconds and then performs visual mode learning for A seconds, the learning modes are continuously switched until the learning is finished, and A<W<T。

In particular, the first step of mode switching learning, the food signal F₁And an auditory stimulus signal L₁Outputting high level, visual stimulation signal S₁With food signal F₂And outputting low level to perform auditory learning and visual learning suppression. And (3) auditory learning: selection switch S₁On, voltage source V₁To the first memristor M₂An output voltage passing through a first operational amplifier OP₁After acting, through the absolute value device ABS₁And (6) carrying out transformation. Selection switch S₄Conducting absolute value device ABS₁Outputting a voltage to a second voltage summing device SUM₂IN of₁Input terminals, i.e. VSUM₂(IN₁) And (4) an output end. Second voltage summing device SUM₂Output voltage VSUM₂(out) to a third memristor M₁And voltage processing component ABM₁IN of₂Input terminal, third memristor M₁The upper voltage passes through an ortho-amplifier OP₂Applied to voltage-treating components ABM after application₁IN of₁An input terminal. Voltage processing component ABM₁Output voltage VABM₁(out) to fourth Voltage summing device SUM₃IN of₁Input terminal, fourth Voltage summing device SUM₃Outputting the voltage to an operational amplifier OP₃To the negative input of (3). Visual learning inhibition: selection switch S₁₇On, voltage source V₁₂Beginning to the second memristor M₆Output voltage, second memristor M₆Is operated by an operational amplifier OP₉After conversion, via absolute value device ABS₅Calculating absolute value, and using it as selection switch S₁₉The turn-on voltage of (c). With the second memristor M₆The conduction voltage gradually increases after the memristance is reduced. When selecting switch S₁₉Is greater than the select switch S₁₉At the threshold voltage of (3), the voltage source V₁₉Starting output voltage, i.e. visual learning suppression signal VS₁₉(out)。

Second step, auditory stimulus signal L₁With food signal F₁Outputting a low level, visual stimulus signal S₁With food signal F₂And outputting a high level, starting mode switching, and performing visual learning, auditory learning suppression and visual learning suppression elimination. Visual learning: selection switch S₁₂On, voltage source V₉To the first memristor M₅The output voltage passes through an ortho-amplifier OP₆After acting, passing through voltage absolute value device ABS₄And (6) carrying out transformation. Selection switch S₁₅Conducting, voltage absolute value device ABS₄Output Voltage to Voltage summing device SUM₆IN of₁Input terminals, i.e. VSUM₆(IN₁). And gate D₆Output high level, select switch S₂₀On, voltage source V₁₅Output voltage, via an operational amplifier OP₁₀After acting, through the absolute value device ABS₆And (6) carrying out transformation. Selection switch S₂₂Conducting absolute value device ABS₆Output voltage to voltage summing device voltage processing component SUM₆IN of₂Input terminals, i.e. VSUM₆(IN₂). Voltage summing device SUM₆Output voltage VSUM₆(out) to memristor M₄And ABM₂IN of₂Input terminal, memristor M₄Voltage on via an amplifier OP₇Applied to voltage-treating components ABM after application₂IN of₁An input terminal. Voltage processing component ABM₂Output voltage VABM₁(out) to Voltage summing device SUM₃IN of₁Input terminal, voltage summing device SUM₃Outputting the voltage to an operational amplifier OP₃To the negative input of (3). Auditory learning suppression: selection switch S₆On, voltage source V₄Beginning to the second memristor M₃Output voltage, second memristor M₃Is operated by an operational amplifier OP₄After conversion, the voltage is processed by a voltage absolute value device ABS₂Calculating absolute value, and using it as selection switch S₈The turn-on voltage of (c). With the second memristor M₃The conduction voltage gradually increases after the memristance is reduced. When selecting switch S₈Is greater than the select switch S₈At the threshold voltage of (3), the voltage source V₆Starting output voltage, i.e. auditory learning suppression signal VS₈(out). Visual learning inhibition elimination: selection switch S₁₈On, voltage source V₁₃Outputting a voltage to a memristor M₆Upper, memristor M₆Is an amplifier OP of the voltage₉After conversion, the voltage is processed by a voltage absolute value device ABS₅Calculating absolute value, and using it as selection switch S₂₁The turn-on voltage of (c). With memory resistor M₆The conduction voltage is gradually reduced when the memristance is increased. When selecting switch S₁₉Is less than the select switch S₁₉At threshold Voltage of (VS)₁₄(out) is zero. And gate A₆Output low level, select switch S₂₀Disconnected, VSUM₆(IN₂) Zero, i.e. the visual learning inhibition is eliminated. The detailed learning mode switching simulation experiment is as shown in fig. 8 and 9. Fig. 8 is a waveform of learning simulation for switching between the auditory mode and the visual mode, and fig. 9 is a waveform of learning simulation for switching between the visual mode and the auditory mode.

According to the double-mode switching learning memory circuit based on the Pavlov associative memory of the memristor, when different excitation signals are input into the circuit, switching learning of different modes can be performed through processing of the logic circuit, and the inhibition effect of the double-mode switching learning on a single learning mode is explored through an output result.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A learning memory circuit based on Pavlov dual-mode switching of a memristor is characterized by comprising a first memory module and a second memory module which are mutually learning-inhibited, wherein the first memory module is connected with the second memory module, the first memory module is connected with a first excitation signal source, and the second memory module is connected with a second excitation signal source; the first memory module comprises a first learning voltage selection module, a first learning module and a first learning suppression module, a first excitation signal source is respectively connected with the input ends of the first learning voltage selection module, the first learning module and the first learning suppression module, the output end of the first learning voltage selection module is respectively connected with the input ends of the second memory module and the first learning module, the output end of the first learning module is connected with the first learning voltage selection module, the input end of the first learning suppression module is connected with the output end of the second memory module, and the output end of the first learning suppression module is connected with the input end of the first learning voltage selection module; the second memory module comprises a second learning voltage selection module, a second learning module and a second learning suppression module, a second excitation signal source is respectively connected with the second learning voltage selection module, the second learning module and the second learning suppression module, the output end of the second learning module is connected with the input end of the second learning voltage selection module, the output end of the second learning voltage selection module is respectively connected with the input ends of the second learning module and the first learning suppression module, the first learning voltage selection module is connected with the input end of the second learning suppression module, and the output end of the second learning suppression module is connected with the input end of the second learning voltage selection module; the output ends of the first excitation signal source and the first learning module are connected with a first OR gate, the output end of the first OR gate outputs a first learning and memory signal, the output ends of the second excitation signal source and the second learning module are connected with a second OR gate, and the output end of the second OR gate outputs a second learning and memory signal.

2. The memristor-based Pavlov dual-mode-switched learning memory circuit of claim 1, wherein the first memory module is an auditory module, the second memory module is a visual module, the first excitation signal source comprises a food signal F₁And an auditory stimulus signal L₁Food signal F₁Respectively connected with the first learning voltage selection module, the first OR gate and the first learning suppression module, and an auditory stimulation signal L₁The first learning voltage selection module, the first learning module and the first learning suppression module are respectively connected; the second excitation signal source comprises a food signal F₂And a visual stimulus signal S₁Food signal F₂Respectively connected with a second learning voltage selection module, a second OR gate and a second learning suppression module, and a visual stimulation signal S₁The learning voltage selection module, the learning suppression module and the learning suppression module are respectively connected with the first learning voltage selection module, the first learning module and the learning suppression module.

3. The memristor-based Pavlov dual-mode-switched learning memory circuit of claim 2, wherein the first and second learning voltage selection modules each comprise a first AND gate, a first NOT gate, a first voltage absolute value device, a first voltage summing device, a first memristor, a food signal F₁Or food signal F₂An auditory stimulation signal L₁Or visual stimulus signal S₁The first AND gate is respectively connected with two input ends of the first AND gate, and outputs a first output end selected by the learning voltage; the first AND gate is connected with the first voltage selection circuit, and the auditory stimulation signal L₁Or visual stimulus signal S₁The output end of the first learning module or the output end of the second learning module is connected with the second selection circuit, the first selection circuit and the second selection circuit are both connected with a first voltage summing device, the first voltage summing device is connected with a first memristor, the first memristor is connected with a first voltage follower circuit, and the output ends of the first voltage follower circuit are respectively connected with a first voltage absolute value deviceThe first voltage absolute value device is connected with the first voltage selection circuit, the output end of the first voltage selection circuit is connected with one input end of the second voltage summation device, the first learning suppression module or the second learning suppression module is connected with the other input end of the second voltage summation device, and the output end of the second voltage summation device outputs a second output end selected by the learning voltage; auditory stimulus signal L₁Or visual stimulus signal S₁The output end of the third selection circuit outputs a third output end selected by the learning voltage.

4. The pavlov dual-mode switching memristor-based learning memory circuit as claimed in claim 2 or 3, wherein the first and second learning suppression modules each comprise a suppression signal unit and a suppression voltage selection unit, the suppression signal unit and the suppression voltage selection unit being connected; the suppression signal unit comprises a fourth selection circuit, a fifth selection circuit, a sixth selection circuit, a third voltage summation device, a second memristor, a second voltage following circuit and a second voltage absolute value device, a first output end of the learning voltage selection of the second learning voltage selection module or the first learning voltage selection module is connected with the fourth selection circuit, and an auditory stimulation signal L₁Or visual stimulus signal S₁The output ends of the fourth selection circuit and the fifth selection circuit are connected with a third voltage summation device, the third voltage summation device is connected with a second memristor, the second memristor is connected with a second voltage follower circuit, the second voltage follower circuit is connected with the input end of a sixth selection circuit through a second voltage absolute value device, the output end of the sixth selection circuit is connected with one input end of a second AND gate, and an auditory stimulation signal L is generated₁Or visual stimulus signal S₁Respectively connected with another input end of the second AND gate and one input end of the third AND gate, and a food signal F₁Or food signal F₂The other input end of the third AND gate is connected; the suppression voltage selection sheetThe output end of the inverting proportional amplifier is respectively connected with the third voltage absolute value device and the input end of the second voltage selection circuit, and the output end of the third voltage absolute value device is connected with the second voltage selection circuit; and the output ends of the second AND gate and the third AND gate are connected with a fourth AND gate, the fourth AND gate is connected with a second voltage selection circuit, and the output end of the second voltage selection circuit is connected with the input end of a second voltage summation device of the first learning voltage selection module or the second learning voltage selection module.

5. The memory circuit of claim 4, in which each of the first and second learning modules comprises a third NOT gate, a voltage processing component, a third memristor, a third voltage follower circuit, a fourth voltage summing device, and a voltage comparison circuit, and an auditory stimulation signal L₁Or visual stimulus signal S₁The third output end of the learning voltage selection of the first learning voltage selection module or the second learning voltage selection module is connected with a third memristor, the third memristor is connected with a third voltage follower circuit, the third voltage follower circuit is connected with one input end of a voltage processing component, the second output end of the learning voltage selection of the first learning voltage selection module or the second learning voltage selection module is connected with the other input end of the voltage processing component, the output end of the voltage processing component is connected with the other input end of the fourth voltage summation device, the output end of the fourth voltage summation device is connected with a voltage comparison circuit, and the output end of the voltage comparison circuit is the output end of the first learning module or the second learning module.

6. The memory circuit of claim 5, wherein the first voltage selection circuit and the second voltage selection circuit each comprise a selection switch I, a selection switch II, and a second NOT gate, the second NOT gate and the selection switch II are respectively connected to an input control signal, the second NOT gate is connected to the selection switch I, voltage input ends of the selection switch I and the selection switch II are respectively connected to different voltage signals, and output ends of the selection switch I and the selection switch II are connected to serve as output ends of the voltage selection circuit; the selection switch I and the selection switch II are first selection switches with two inputs and one output, two input ends of each first selection switch are respectively connected with an input control signal and a voltage input signal, an output end of each first selection switch selects whether to output the voltage input signal according to the input control signal, and the other end of each first selection switch is grounded.

7. The memory circuit of claim 6, wherein the first, second, third, fourth, fifth, sixth, and seventh selection circuits each comprise a second selection switch having an input and an output, the second selection switch having an input connected to ground, an input connected to the positive terminal of the first power source, a negative terminal of the first power source connected to ground, another input connected to an input control signal, and an output outputting a corresponding voltage signal according to the input control signal; the output end of the second selection switch is connected with a protection resistor, and the other end of the protection resistor is grounded.

8. The memristor-based Pavlov dual-mode-switched learning memory circuit of claim 6, wherein the first, second and third voltage follower circuits each comprise a first operational amplifier, a non-inverting input of the first operational amplifier being connected to ground, an inverting input of the first operational amplifier being connected to an output of the first operational amplifier through a first resistor; the inverting proportional amplifier comprises a second operational amplifier, the non-inverting input end of the second operational amplifier is grounded, the inverting input end of the second operational amplifier is respectively connected with a second resistor and a third resistor, the second resistor is connected with an input signal, and the third resistor is connected with the output end of the second operational amplifier; the voltage comparison circuit comprises a third operational amplifier, the inverting input end of the third operational amplifier is connected with the input signal, the non-inverting input end of the third operational amplifier is connected with the anode of the second power supply, the cathode of the second power supply is grounded, and the output end of the third operational amplifier outputs the output signal of the first learning module or the second learning module.