CN110910723B - A Memristor-Based Pavlovian Dual-Mode Switching Learning and Memory Circuit - Google Patents

Abstract

The invention provides a learning and memory circuit based on memristor Pavlovian dual-mode switching, comprising a first memory module and a second memory module for mutual learning and inhibition, and the first memory module and the second memory module are connected; The first memory module includes a first learning voltage selection module, a first learning module and a first learning inhibition module; the second memory module includes a second learning voltage selection module, a second learning module and a second learning inhibition module; the first excitation signal Both the source and the output of the first learning module are connected with the first OR gate, and both the second excitation signal source and the output of the second learning module are connected with the second OR gate. The invention utilizes the learning excitation signal to call the auditory module and the visual module, and the auditory mode learning and the visual mode learning can be switched between modes, so as to achieve the purpose of dual-mode switching learning, and solve the problem that the learning and memory circuit can only perform single-mode learning.

Description

A Memristor-Based Pavlovian Dual-Mode Switching Learning and Memory Circuit

technical field

The invention relates to the technical field of digital-analog circuits, in particular to a learning and memory circuit based on memristor Pavlovian dual-mode switching.

Background technique

In 2008, Hewlett-Packard Company prepared a resistor with memory properties in the laboratory, which was confirmed to be the fifth passive electronic component proposed many years ago, the memristor. As a new type of component, scholars from all over the world pay more and more attention and begin to study the memristor from various aspects. With the deepening of people's understanding of the concept of memristors, it is found that the characteristics of memristors are very similar to the synapses in biological nerves, and they can imitate some functions of the brain to simulate memory learning of biological behaviors. From the existing literature, circuit simulation of biological memory behavior has become an extremely important part of memristor research.

At present, many simulation models of learning and memory circuits based on memristors have been proposed, which provides a greater possibility for the wide application of memristors in the future. The invention patent application with application number 201611256568.5 discloses an artificial neural network circuit based on memristive Pavlovian associative memory. Although the circuit realizes learning, forgetting, re-learning, re-forgetting and natural forgetting, the entire circuit is only a traditional auditory mode training, no dual mode training is involved. Because the current single-mode training based on memristor learning and memory behavior is too simple and ideal, more and more scholars begin to pay attention to more complex and objective dual-mode training. It is believed that in the near future, the research and development of memristor-based biological memory learning behavior will be better.

SUMMARY OF THE INVENTION

Aiming at the technical problem that the auditory mode is the traditional learning mode of Pavlovian associative memory, but the single mode learning cannot actually reflect the diversity of learning and memory in life, the present invention proposes a Pavlovian dual mode based on memristor The switched learning and memory circuit can not only realize the learning and memory of auditory and visual modes, but also can switch learning and memory of auditory and visual modes, which truly realizes the diversity of learning and memory. At the same time, according to the actual situation of the learning process, the present invention explores the inhibition relationship between different learning modes, and implements it in the circuit.

In order to achieve the above object, the technical scheme of the present invention is achieved as follows: a learning and memory circuit based on memristor Pavlovian dual-mode switching, comprising a first memory module and a second memory module that inhibit mutual learning, the A memory module is connected with the second memory module, the first memory module is connected with the first excitation signal source, and the second memory module is connected with the second excitation signal source; the first memory module includes a first learning voltage selection module , the first learning module and the first learning suppression module, the first excitation signal source is respectively connected with the input terminals of the first learning voltage selection module, the first learning module and the first learning suppression module, and the output of the first learning voltage selection module The terminals are respectively connected with the input terminals of the second memory module and the first learning module, the output terminal of the first learning module is connected with the first learning voltage selection module, and the input terminal of the first learning suppression module is connected with the output terminal of the second memory module. The output terminal of the first learning suppression module is connected with the input terminal of the first learning voltage selection module; the second memory module includes a second learning voltage selection module, a second learning module and a second learning suppression module, The second excitation signal source is respectively connected with the second learning voltage selection module, the second learning module and the second learning suppression module, the output terminal of the second learning module is connected with the input terminal of the second learning voltage selection module, and the second learning voltage selection module is connected to the second learning voltage selection module. The output end of the voltage selection module is respectively connected with the input end of the second learning module and the first learning suppression module, the first learning voltage selection module is connected with the input end of the second learning suppression module, and the output end of the second learning suppression module is connected with the input end of the second learning voltage selection module; the first excitation signal source and the output end of the first learning module are both connected with the first OR gate, and the output end of the first OR gate outputs the first learning memory signal , the second excitation signal source and the output end of the second learning module are both connected with the second OR gate, and the output end of the second OR gate outputs the second learning and memory signal.

The first memory module is an auditory module, the second memory module is a visual module, the first excitation signal source includes a food signal F ₁ and an auditory stimulation signal L ₁ , and the food signal F ₁ is respectively associated with the first learning voltage selection module, The first OR gate is connected with the first learning suppression module, and the auditory stimulation signal L1 is respectively connected with the _first learning voltage selection module, the first learning module and the first learning suppression module; the second excitation signal source includes food signals F2 and visual stimulation signal _S1 , food signal F2 are respectively connected with the _second learning voltage selection module, the _second OR gate and the second learning inhibition module, the visual stimulation signal _S1 is respectively connected with the second learning voltage selection module, the second learning voltage selection module, the second learning voltage selection module A second learning module and a second learning inhibition module.

The first learning voltage selection module and the second learning voltage selection module each include a first AND gate, a first NOT gate, a first voltage absolute value device, a first voltage summation device, a first memristor, and a food signal F. ₁ or the food signal F ₂ , the auditory stimulation signal L ₁ or the visual stimulation signal S ₁ are respectively connected with the two input ends of the first AND gate, the first AND gate outputs the first output end selected by the learning voltage; the first AND gate It is connected with the _first voltage selection circuit, the auditory stimulation signal L1 or the visual stimulation signal S1 is connected with the _first selection circuit, the output end of the first learning module or the second learning module is connected with the second selection circuit, the first The selection circuit and the second selection circuit are both connected with the first voltage summing device, the first voltage summing device is connected with the first memristor, the first memristor is connected with the first voltage follower circuit, the first voltage The output terminals of the follower circuit are respectively connected with the first voltage absolute value device and the first voltage selection circuit, the first voltage absolute value device is connected with the first voltage selection circuit, and the output terminal of the first voltage selection circuit is connected with the second voltage selection circuit. It is connected with one input end of the device, the first learning suppression module or the second learning suppression module is connected with the other input end of the second voltage summing device, and the output end of the second voltage summing device outputs the first selected by the learning voltage. Two output terminals; the auditory stimulation signal L1 or the visual stimulation signal S1 is connected to the third selection circuit through the _first NOT gate, and the output terminal _of the third selection circuit outputs the third output terminal selected by the learning voltage.

The first learning suppression module and the second learning suppression module both include a suppression signal unit and a suppression voltage selection unit, and the suppression signal unit and the suppression voltage selection unit are connected; the suppression signal unit includes a fourth selection circuit and a fifth selection circuit , the sixth selection circuit, the third voltage summation device, the second memristor, the second voltage follower circuit and the second absolute value device of the voltage, the learning voltage of the second learning voltage selection module or the first learning voltage selection module The selected _first output terminal is connected to the fourth selection circuit, the auditory stimulation signal L1 or the visual stimulation signal S1 is connected to the fifth selection circuit, and the output terminals _of the fourth selection circuit and the fifth selection circuit are both connected to the third voltage The summing device is connected, the third voltage summing device is connected with the second memristor, the second memristor is connected with the second voltage follower circuit, and the second voltage follower circuit is connected with the sixth voltage follower through the second absolute value device. The input end of the selection circuit is connected, the output end of the sixth selection circuit is connected with _one input end of the second AND gate, the auditory stimulation signal L1 or the visual stimulation signal S1 is respectively connected with the other input end _of the second AND gate and _One input end of the third AND gate is connected, and the food signal F1 or the food signal F2 is connected to the other input end of the third AND gate _; the suppression voltage selection unit includes a seventh selection circuit, an inverse proportional amplifier, The third voltage absolute value device, the output end of the second AND gate is connected with the seventh selection circuit, the seventh selection circuit is connected with the inverse proportional amplifier, and the output end of the inverse proportional amplifier is respectively connected with the third voltage absolute value device, The input terminal of the second voltage selection circuit is connected, the output terminal of the third voltage absolute value device is connected to the second voltage selection circuit; the output terminals of the second AND gate and the third AND gate are both connected to the fourth AND gate , the fourth AND gate is connected to the second voltage selection circuit, and the output terminal of the second voltage selection circuit is connected to the input terminal of the first learning voltage selection module or the second voltage summing device of the second learning voltage selection module.

The first learning module and the second learning module both include a third NOT gate, a voltage processing component, a third memristor, a third voltage follower circuit, a fourth voltage summing device and a voltage comparison circuit, and the auditory stimulation signal L ₁ or the visual stimulation signal S1 is connected to _one input end of the fourth voltage summing device through the third NOT gate, and the third output end of the learning voltage selection of the first learning voltage selection module or the second learning voltage selection module is connected to the first learning voltage selection module. The three memristors are connected, the third memristor is connected with the third voltage follower circuit, the third voltage follower circuit is connected with an input end of the voltage processing component, the first learning voltage selection module or the second learning voltage selection module The second output terminal of the learning voltage selection of the module is connected with the other input terminal of the voltage processing component, the output terminal of the voltage processing component is connected with the other input terminal of the fourth voltage summing device, and the fourth voltage summing device The output end of the device is connected with the voltage comparison circuit, and the output end of the voltage comparison circuit is the output end of the first learning module or the second learning module.

The first voltage selection circuit and the second voltage selection circuit both include a selection switch I, a selection switch II and a second NOT gate, the second NOT gate and the selection switch II are respectively connected with the input control signal, and the second NOT gate is connected to the selection switch. The switch I is connected, the voltage input terminals of the selection switch I and the selection switch II are respectively connected with different voltage signals, and the output terminals of the selection switch I and the selection switch II are connected as the output terminal of the voltage selection circuit; the selection switch I and the selection switch Switch II is a first selection switch with two inputs and one output. The two input terminals of the first selection switch are respectively connected with the input control signal and the voltage input signal. The output terminal of the first selection switch selects whether to output voltage according to the input control signal. Input signal, the other end of the first selection switch is grounded.

The first selection circuit, the second selection circuit, the third selection circuit, the fourth selection circuit, the fifth selection circuit, the sixth selection circuit and the seventh selection circuit all include a second selection switch with an input and an output, and the second selection switch One input terminal of the selection switch is grounded, one input terminal is connected to the positive pole of the first power supply, the negative pole of the first power supply is grounded, the other input terminal of the second selection switch is connected to the input control signal, and the output terminal of the second selection switch is connected to the ground. The corresponding voltage signal is output according to the input control signal; the output end of the second selection switch is connected with a protection resistor, and the other end of the protection resistor is grounded.

The first voltage follower circuit, the second voltage follower circuit and the third voltage follower circuit all include a first operational amplifier, the non-inverting input terminal of the first operational amplifier is grounded, and the inverting input terminal of the first operational amplifier is connected to the first operational amplifier through a first resistor. The output terminal of the first operational amplifier is connected; the inverting proportional amplifier includes a second operational amplifier, the non-inverting input terminal of the second operational amplifier is grounded, and the inverting input terminal of the second operational amplifier is respectively connected with the second resistor and the third resistor The second resistor is connected to the input signal, and the third resistor is connected to the output terminal of the second operational amplifier; the voltage comparison circuit includes a third operational amplifier, and the inverting input terminal of the third operational amplifier is in phase with the input signal. The non-inverting input terminal of the third operational amplifier is connected to the positive pole of the second power supply, the negative pole of the second power supply is grounded, and the output terminal of the third operational amplifier outputs the output signal of the first learning module or the second learning module.

Compared with the prior art, the present invention has the beneficial effects of two learning modules: an auditory module and a visual module. The auditory module and the visual module are called by learning the excitation signal. The auditory module is responsible for the learning of the auditory mode, and the visual module is responsible for the learning of the visual mode. When performing dual-mode switching learning, the learning and memory circuit will process the input signal, and the learning voltage logic unit will start to respond. During the learning process, a learning inhibition signal is generated between different learning modes, and the learning rate of another mode is inhibited during the learning process. The invention introduces dual-mode learning and memory, solves the problem that the existing learning and memory mode is too single, and has very important practical significance for the expansion of the biological memory field of the memristor and the learning and memory circuit.

Description of drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that are used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative efforts.

FIG. 1 is a circuit schematic diagram of the present invention.

FIG. 2 is a circuit diagram of the auditory learning voltage selection module in FIG. 1 .

FIG. 3 is a circuit diagram of the visual learning voltage selection module in FIG. 1 .

FIG. 4 is a circuit diagram of the auditory learning inhibition module in FIG. 1 .

FIG. 5 is a circuit diagram of the visual habit suppression module in FIG. 1 .

FIG. 6 is a circuit diagram of the auditory learning module in FIG. 1 .

FIG. 7 is a circuit diagram of the visual learning module in FIG. 1 .

FIG. 8 is a circuit diagram of a simulation circuit of the hearing first and then vision mode of the present invention.

FIG. 9 is a circuit diagram of a simulation circuit of the visual first and then hearing mode of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

A dual-mode switching learning and memory circuit based on memristor Pavlovian associative memory, comprising a first memory module and a second memory module for mutual learning and inhibition, the first memory module and the second memory module are connected, and the first memory module and the second memory module are connected. A memory module is connected to the first excitation signal source, and the second memory module is connected to the second excitation signal source; the first memory module includes a first learning voltage selection module, a first learning module and a first learning inhibition module, The first excitation signal source is respectively connected with the input terminals of the first learning voltage selection module, the first learning module and the first learning suppression module, and the output terminals of the first learning voltage selection module are respectively connected with the second memory module and the first learning module. The input end of the first learning module is connected with the first learning voltage selection module, the input end of the first learning suppression module is connected with the output end of the second memory module, the output end of the first learning suppression module is connected with is connected with the input end of the first learning voltage selection module; the second memory module includes a second learning voltage selection module, a second learning module and a second learning suppression module, and the second excitation signal source is selected from the second learning voltage The module, the second learning module and the second learning suppression module are connected, the output terminal of the second learning module is connected with the input terminal of the second learning voltage selection module, and the output terminal of the second learning voltage selection module is respectively connected with the second learning module. , the input end of the first learning suppression module is connected, the first learning voltage selection module is connected with the input end of the second learning suppression module, and the output end of the second learning suppression module is connected with the input end of the second learning voltage selection module ; The output end of the first excitation signal source and the first learning module are all connected with the first OR gate, and the output end of the first OR gate outputs the first learning memory signal, the second excitation signal source and the second learning The output ends of the modules are all connected with the second OR gate, and the output end of the second OR gate outputs the second learning and memory signal.

As shown in FIG. 1 , the first memory module may be an auditory module, the second memory module may be a visual module, and the auditory module and the visual module are connected. The auditory module includes an auditory learning voltage selection module, an auditory learning module and an auditory learning inhibition module. The input terminals of the auditory learning voltage selection module, the auditory learning module and the auditory learning inhibition module are all connected with the first excitation signal source. The input of the auditory learning module The output terminal of the auditory learning voltage selection module is connected to the output terminal of the auditory learning voltage selection module, the output terminal of the auditory learning suppression module is connected to the output terminal of the auditory learning voltage selection module, and the output terminal of the auditory learning voltage selection module is connected to the input terminal of the auditory learning module. The input end of the learning voltage selection module is connected, the auditory learning inhibition module is used to inhibit the work of the auditory learning voltage selection module, and the visual module is connected with the auditory learning inhibition module; the visual module includes a visual learning voltage selection module, a visual learning module and a visual learning module. The visual learning inhibition module, the input terminals of the visual learning voltage selection module, the visual learning module and the visual learning inhibition module are all connected with the second excitation signal source, and the input terminal of the visual learning module is connected with the output terminal of the visual learning voltage selection module, The output terminal of the auditory learning voltage selection module is connected with the input terminal of the visual learning inhibition module, and the output terminal of the visual learning inhibition module is connected with the visual learning voltage selection module, that is, when the auditory learning voltage selection module works, it will send a signal to the visual The learning inhibition module suppresses the work of the visual learning voltage selection module through the visual learning inhibition module. Similarly, when the visual learning voltage selection module works, it will send a signal to the auditory learning inhibition module, and the auditory learning inhibition module inhibits the auditory learning voltage selection module. Work, that is, switching between two modes of auditory learning and visual learning. The output terminal of the auditory learning module outputs a signal of completion of auditory learning, and the output terminal of the visual learning module outputs a signal of completion of visual learning.

The first excitation signal source and the second excitation signal source are respectively used to control the auditory learning voltage selection module, the visual learning voltage selection module, the auditory learning suppression module and the visual learning suppression module. The first excitation signal source includes a food signal F ₁ and an auditory stimulation signal L ₁ , the food signal F ₁ is respectively connected with the first learning voltage selection module, the first OR gate and the first learning inhibition module, and the auditory stimulation signal L ₁ is respectively connected with the first learning voltage selection module, the first OR gate and the first learning inhibition module. The first learning voltage selection module, the first learning module and the first learning inhibition module are connected; the second excitation signal source includes the food signal F ₂ and the visual stimulation signal S ₁ , and the food signal F ₂ is selected from the second learning voltage respectively _The module, the second OR gate and the second learning inhibition module are connected, and the visual stimulation signal S1 is respectively connected with the second learning voltage selection module, the second learning module and the second learning inhibition module. _The food signal F1 is respectively connected to the input terminals of the auditory learning voltage selection module and the auditory learning inhibition module. _The auditory stimulation signal L1 is respectively connected to the input terminals of the auditory learning voltage selection module, the auditory learning module and the auditory learning inhibition module. _The food signal F2 is connected to the input terminals of the visual learning voltage selection module and the visual learning inhibition module, respectively. _The visual stimulation signal S1 is respectively connected to the input terminals of the visual learning voltage selection module, the visual learning module and the visual learning inhibition module.

The food signal F1 and the auditory stimulation signal L1 both output a high level, the auditory mode is in progress, and the auditory learning voltage selection module and the visual learning inhibition module start to respond. The auditory learning voltage selection module starts to generate the auditory learning voltage, and the visual learning inhibition signal unit in the visual learning inhibition module starts to generate the visual learning inhibition signal. The food signal F1 and the auditory stimulation signal L1 output a low level, the food signal F2 and the visual stimulation signal S1 output a high level, the auditory mode is stopped, and the visual mode is performed. The visual learning voltage selection module and the auditory learning inhibition module began to respond, and the visual learning inhibition signal began to fade. The visual learning voltage and the visual learning inhibition voltage are output to the visual learning module together after the selection is completed. The excitation signal is constantly changing, and the learning mode is constantly switched, until the auditory learning module and the visual learning module output a high level.

The voltage selection modules of auditory learning or visual learning all include three input terminals and three output terminals, and the three input terminals are respectively connected with the two excitation signals of the first excitation signal source or the second excitation signal source and the two excitation signals of the auditory or visual learning module. The output signals are connected, and the three output terminals are connected, and one of them is connected with the corresponding learning inhibition module, that is, the output terminal of the auditory learning voltage selection module is connected with the input terminal of the visual learning inhibition module, and the output terminal of the visual learning voltage selection module is connected to the input terminal of the visual learning inhibition module. The input terminals of the auditory learning inhibition module are connected; the other two output terminals of the voltage selection module are both connected with the corresponding learning modules. The separate suppression module includes three input terminals and one output terminal, the three input terminals are respectively connected with the two excitation signals of the first excitation signal source or the second excitation signal source and an output terminal of the corresponding voltage selection module, and the output terminal Connect with the corresponding voltage selection module. The separate learning module includes three input terminals and _one output terminal, the _three input terminals are respectively connected with the auditory stimulation signal L1 or the visual stimulation signal S1 and the corresponding voltage selection module, and the output terminal is connected with the corresponding voltage selection module. . The output terminal of the auditory learning voltage selection module and the output terminal of the auditory learning inhibition module are connected through a voltage summation device and then connected to the voltage input terminal of the auditory learning module. Connect to the device and then connect to the voltage input terminal of the visual learning module. The two learning module output terminals output learning completion signals. The output end of the food signal F ₁ and the auditory learning module are all connected with the first OR gate, the output end of the first OR gate outputs the first learning and memory signal, and the output end of the food signal F ₂ and the visual learning module are both connected with the first OR gate. The two OR gates are connected, and the output end of the second OR gate outputs a second learning and memory signal. The first learning and memory signal and the second learning and memory signal represent saliva signals.

The first learning voltage selection module and the second learning voltage selection module each include a first AND gate, a first NOT gate, a first voltage absolute value device, a first voltage summation device, a first memristor, and a food signal F. ₁ or the food signal F ₂ , the auditory stimulation signal L ₁ or the visual stimulation signal S ₁ are respectively connected with the two input ends of the first AND gate, the first AND gate outputs the first output end selected by the learning voltage; the first AND gate It is connected with the _first voltage selection circuit, the auditory stimulation signal L1 or the visual stimulation signal S1 is connected with the _first selection circuit, the output end of the first learning module or the second learning module is connected with the second selection circuit, the first The selection circuit and the second selection circuit are both connected with the first voltage summing device, the first voltage summing device is connected with the first memristor, the first memristor is connected with the first voltage follower circuit, the first voltage The output terminals of the follower circuit are respectively connected with the first voltage absolute value device and the first voltage selection circuit, the first voltage absolute value device is connected with the first voltage selection circuit, and the output terminal of the first voltage selection circuit is connected with the second voltage selection circuit. It is connected with one input end of the device, the first learning suppression module or the second learning suppression module is connected with the other input end of the second voltage summing device, and the output end of the second voltage summing device outputs the first selected by the learning voltage. Two output terminals; the auditory stimulation signal L1 or the visual stimulation signal S1 is connected to the third selection circuit through the _first NOT gate, and the output terminal _of the third selection circuit outputs the third output terminal selected by the learning voltage.

As shown in FIG. 2 , the first learning voltage selection module, namely the auditory learning voltage selection module, includes a first AND gate A ₁ , a first NOT gate D ₂ , a first voltage absolute value device ABS ₁ , and a first voltage summation device SUM ₁ and the first memristor M ₂ , the food signal F ₁ and the auditory stimulation signal L ₁ are respectively connected with the two input terminals of the first AND gate A ₁ , and the output terminal of the first AND gate A ₁ is the first one selected by the learning voltage. An output terminal V(A ₁ ); the auditory stimulation signal L ₁ is connected to the first selection circuit, the first selection circuit includes an input-output second selection switch S ₁ , and the second selection switch S ₁ controls the auditory excitation voltage. Generated, one input terminal of the second selection switch S1 is grounded, _one input terminal is connected to the positive pole of the _first power supply V1, the negative pole of the _first power supply V1 is grounded, and the conduction signal input terminal _of the second selection switch S1 is connected to the The input control signal, that is, the auditory stimulation signal L1, is connected, and the output end _of the second selection switch S1 outputs _a corresponding voltage signal according to the input control signal, that is, the auditory stimulation signal L1 _; the output end of the second selection switch S1 is connected with _a protection resistor. R ₁ , the other end of the protection resistor R ₁ is grounded; the output end of the second selection switch S ₁ is connected to an input end of the first voltage summing device SUM ₁ . The output terminal V (N ₁ ) of the auditory learning module is connected to the second selection circuit, namely the conduction signal input terminal of the _second selection switch S2 with one input and one output, and the _second selection switch S2 controls the generation of the auditory learning feedback voltage , one input terminal of the _second selection switch S2 is grounded, the other input terminal is connected to the positive pole of the first power supply _V2 , the negative pole of the first power supply V2 is grounded, and the output terminal of the _second selection switch _S2 is connected to the protection resistor R _{2 -} phase connection, the other end of the protection resistor R2 is grounded. The output terminal of the _second selection switch S2 is connected to the other input terminal of the _first voltage summation device SUM1, and the _first voltage summation device SUM1 realizes the output signal of the second selection switch S1 and the second selection switch S2. accumulate. The voltage summation devices SUM ₁ to SUM ₈ of the present invention use voltage summation devices with a model of SUM50N03. When the output voltage value of the first voltage summing device SUM1 is less than the threshold voltage of the first memristor M2, the resistance value of the first memristor M2 is maintained at 100Ω; when the output voltage value of the first voltage summing device SUM1 is greater than the first memristor M2 A threshold voltage of the memristor M2, the resistance value of the first memristor M2 rapidly rises to 200Ω. The output terminal of the _first voltage summation device SUM1 is connected to the positive terminal of the first memristor _M2 , and the negative terminal of the first memristor _M2 is connected to the inverse of the _first operational amplifier OP1 of the first voltage follower. The phase input terminals are connected to each other, the non-inverting input terminal of the _first operational amplifier OP1 is grounded, and the phase-inverting input terminal of the _first operational amplifier OP1 is connected to the output terminal of the _first operational amplifier OP1 through the first resistor _R3 , The output terminals of the first operational amplifier OP ₁ are respectively connected with the first voltage selection circuit and the first voltage absolute value device ABS ₁ , and the output terminal of the first voltage absolute value device ABS ₁ is connected with another input terminal of the first voltage selection circuit connected. The output voltage of the _first voltage absolute value device ABS1 is a positive value, that is, a learning voltage. The first memristor M2 is reversely connected. The voltage absolute value devices ABS ₁ to ABS ₆ of the present invention use voltage absolute value devices whose model is ABS05, and the output voltage is the absolute value of the input voltage. The first voltage selection circuit includes a selection switch IS ₃ , a selection switch IIS ₄ and a second NOT gate D ₁ , the second NOT gate D ₁ and the selection switch IIS ₄ are respectively connected with an input control signal, and the input control signal is the first output terminal The output signal of V(A ₁ ), the second NOT gate D ₁ is connected to the selection switch IS ₃ , and the voltage input terminals of the selection switch IS ₃ and the selection switch II S ₄ are respectively connected with different voltage signals, that is, the selection switch IS ₃ The turn-on signal input terminal is connected to the output terminal of the second NOT gate D1, the turn-on signal input terminal of the selection switch _IIS4 is connected to the output terminal _of the _first AND gate A1, and the voltage input terminal _of the selection switch IS3 It is connected to the output end of the first operational amplifier OP ₁ , the voltage input end of the selection switch II S ₄ is connected to the output end of the first voltage absolute value device ABS ₁ , the output end of the selection switch IS ₃ and the selection switch II S ₄ After connection, it is used as the output terminal of the voltage selection circuit _; the second NOT gate D1 controls the conduction _of the selection switch IS ₃ and the selection switch II S4, and the function of the first voltage selection circuit is to realize the output of auditory learning or forgetting signals. The selection switch IS ₃ and the selection switch II S ₄ are both first selection switches with two inputs and one output. The two input terminals of the first selection switch are respectively connected with the input control signal and the voltage input signal. The output terminal of the first selection switch Whether to output the voltage input signal is selected according to the input control signal, and the other end of the first selection switch is grounded. The output terminals of the selection switch IS ₃ and the selection switch II S ₄ are connected to the IN ₁ input terminal of the second addition voltage summation device SUM ₂ , and the IN ₂ input terminal of the second addition voltage summation device SUM ₂ is connected to the auditory suppression module. The output terminal VSUM ₂ (IN ₂ ) is connected, and the output terminal VSUM ₂ (out) is connected with the auditory learning module. _The auditory stimulation signal L1 is connected to the conduction signal input end of the second selection switch _S5 of one input and _one output of the third selection circuit through the first NOT gate D2, and the other _two input ends of the second selection switch S5 It is respectively connected to the ground and the positive pole of the first power supply _V3 , the negative pole of the first power supply _V3 is grounded, and the output terminal V ( _{S5 )} of the second selection switch S5 is the third output terminal of the learning voltage selection, and the output terminal V (S ₅ ) is connected to the input terminal of the auditory learning module.

As shown in FIG. 3 , the visual learning voltage selection module includes a first AND gate A ₅ , a first NOT gate D ₆ , a first voltage absolute value device ABS ₄ , a first voltage summation device SUM ₅ , a first memristor, The first selection circuit composed of the second voltage summation device SUM ₆ and the selection switch _S12 , the second selection circuit composed of the selection switch _S13 , the first power selection circuit composed of the selection switch _S14 and the selection switch _S15 voltage, selection _The third selection circuit composed of the switch _S16 , the first voltage follower composed of the first operational amplifier _OP6 , the input end of the first AND gate A5 is connected to the output end of the food signal _F2 and the visual stimulation signal S1, the _first The output end V (A ₅ ) of the AND gate A ₅ is connected with the input end of the auditory learning inhibition module, and the output end of the first AND gate A ₅ is respectively connected with the input end of the first NOT gate D ₅ and the lead of the selection switch S ₁₅ . signal input terminal. _The output terminal of the first AND gate A5 is connected to the turn-on signal input terminal of the selection switch _S14 . _The input end of the first NOT gate _D6 is connected to the output end of the visual stimulus signal S1, the output end of the _first NOT gate D6 is connected to the conduction signal input end of the selection switch _S16 , and the other two input ends of the selection switch _S16 Ground and the positive pole of the first power supply V ₁₁ respectively, and the negative pole of the first power supply V ₁₁ is grounded, that is, the voltage input terminal of the selection switch S ₁₆ is connected to the first voltage source V ₁₁ , and the output terminal V (S ₁₆ ) of the selection switch S ₁₆ is The third output terminal is connected with the input terminal of the visual learning module. The input terminal of the voltage absolute value device _ABS4 is connected to the output terminal of the first operational amplifier _OP6 , and the output terminal of the voltage absolute value device _ABS4 is connected to the voltage input terminal of the selection switch _S15 . _The input terminal of the memristor M4 is connected to the output terminal of the SUM ₅ , and the output terminal is connected to the negative input of the first operational amplifier _OP6 , and the negative terminal of the first operational amplifier _OP6 is connected with the first operational amplifier _OP6 through the first resistor _R16 . The output terminals are connected to realize the effect of voltage proportional change. The positive input of the first operational amplifier _OP6 is grounded, and the output terminal is connected to the input terminal of the voltage absolute value device _ABS4 and the voltage input terminal of the selection switch _S14 . The selection switch _S12 turns on the signal input end connected to the output end _of the visual stimulation signal S1, the voltage input end connected to the voltage source V9, and the voltage output end connected to the _IN1 input end of the _first voltage summation device _SUM5 . The turn-on signal input terminal of the selection switch _S13 is connected to the visual stimulation signal S1, the voltage input terminal _of the selection switch _S12 is connected to the positive pole of the first voltage source _V9 , and the voltage output terminal of the selection switch _S12 is connected to the first voltage summing device The IN ₂ input terminal of SUM ₅ is connected to the protection resistor R ₁₄ , and the other terminal of the protection resistor R ₁₄ is grounded. The on-signal input terminal of the selection switch _S13 is connected to the output terminal V(N ₂ ) of the visual learning module, the voltage input terminal of the selection switch _S13 is connected to the positive pole of the first voltage source _V10 , and the voltage output terminal of the selection switch _S13 is connected to The IN ₂ input terminal of the first voltage summing device SUM ₅ is connected to the protection resistor R ₁₅ , and the other terminal of the protection resistor R ₁₅ is grounded. The turn- _on signal input end of the selection switch _S14 is connected to the output end of the first NOT gate D5, the voltage input end is connected to the output end of the first operational amplifier _OP6 , and the voltage output end is connected to the IN1 _of the second voltage summing device _SUM6 input. The selection switch _S15 turns on the signal input terminal and is connected to the output terminal of the first AND gate A5, the voltage input terminal is connected to the output terminal of the voltage absolute value device _ABS4 , and the voltage output terminal is connected to the IN ₁ input _of the second voltage summation device _SUM6 end. The IN ₂ input of the second voltage summing device SUM ₆ is connected to the output of the visual suppression module.

The first learning suppression module and the second learning suppression module both include a suppression signal unit and a suppression voltage selection unit, and the suppression signal unit and the suppression voltage selection unit are connected. The suppression signal unit includes a fourth selection circuit, a fifth selection circuit, a sixth selection circuit, a third voltage summing device, a second memristor, a second voltage follower circuit, and a second voltage absolute value device. The second learning voltage selection module or the _first output terminal of the learning voltage selection of the _first learning voltage selection module is connected to the fourth selection circuit, the auditory stimulation signal L1 or the visual stimulation signal S1 is connected to the fifth selection circuit, and the fourth selection circuit The output terminals of the selection circuit and the fifth selection circuit are both connected with the third voltage summing device, the third voltage summing device is connected with the second memristor, and the second memristor is connected with the second voltage follower circuit, The second voltage follower circuit is connected to the input end of the sixth selection circuit through the second voltage absolute value device, and the output end of the sixth selection circuit is connected to an input end of the second AND gate of the suppression voltage selection unit; the suppression The voltage selection unit includes a seventh selection circuit, an inverse proportional amplifier, a third voltage absolute value device, and the auditory stimulation signal L1 or the visual stimulation signal S1 is respectively connected with the other input end _of the second AND gate and _one of the third AND gates The input terminal is connected, the food signal F1 or the food signal F2 is connected with the other input terminal of the third AND gate _; the output terminal of the _second AND gate is connected with the seventh selection circuit, and the seventh selection circuit is proportional to the inverse phase. The amplifier is connected with the amplifier, the output end of the inverse proportional amplifier is respectively connected with the third voltage absolute value device and the input end of the second voltage selection circuit, and the output end of the third voltage absolute value device is connected with the second voltage selection circuit; The output terminals of the second AND gate and the third AND gate are both connected to the fourth AND gate, the fourth AND gate is connected to the second voltage selection circuit, and the output terminal of the second voltage selection circuit is connected to the first learning voltage selection module or The input terminal of the second voltage summing device of the second learning voltage selection module is connected.

As shown in FIG. 4 , the auditory learning inhibition module includes an auditory learning inhibition signal unit and an auditory learning inhibition voltage selection unit, and the auditory learning inhibition signal unit includes a third voltage summation device SUM ₄ , a second memristor M ₃ , a first arithmetic operation A second voltage follower circuit composed of an amplifier OP ₄ and a first resistor R ₉ , a second voltage absolute value device ABS ₂ , a fourth selection circuit composed of a selection switch S ₆ , a fifth selection circuit composed of a selection switch S ₇ , and a selection switch The sixth selection circuit composed of _S8 . The output terminal V (A ₅ ) of the visual learning voltage selection module is connected with the turn-on signal input terminal of the selection switch S ₆ , the voltage input terminal of the selection switch S ₆ is connected with the positive pole of the first voltage source V ₄ , and the first voltage The negative pole of the source _V4 is grounded, and the voltage output terminal of the selection switch _S6 is respectively connected to the IN1 input terminal _of the third voltage summing device _SUM4 and the protection resistor _R7 , and the other terminal of the protection resistor _R7 is grounded. _The auditory stimulation signal L1 is connected to the conduction signal input end _of the selection switch _S7 , the voltage input end of the selection switch S7 is connected to the positive electrode of the first voltage source _V5 , the negative electrode of the first voltage source _V5 is grounded, and the selection _The voltage output terminal of the switch S7 is respectively connected to the _IN2 input terminal of the third voltage summing device _SUM4 and the protection resistor _R8 , and the other terminal of the protection resistor _R8 is grounded. The resistance value of the second memristor M3 decreases continuously under the action of positive voltage, the smaller the positive voltage is, the faster the resistance value decreases; under the action of negative voltage, the resistance value increases continuously, the smaller the negative voltage is, the slower the resistance value increases speed. _The negative terminal of the second memristor M3 is connected to the output terminal of the third voltage summing device SUM ₄ , and the positive terminal of the second memristor M3 is connected to the negative phase input terminal of the first operational amplifier _OP4 , and the first operational amplifier OP The positive input terminal of OP ₄ is grounded, the negative input terminal of the first operational amplifier OP ₄ is connected to its output terminal through the first resistor R ₉ , and the output terminal of the first operational amplifier OP ₄ is connected to the second voltage absolute value device ABS ₂ . The input terminal, the output terminal of the _second voltage absolute value device ABS2 is connected to the turn-on signal input terminal of the selection switch _S8 . The on-signal input terminal of the selection switch _S8 is connected to the output terminal of the _second voltage absolute value device ABS2, the voltage input terminal of the selection switch _S8 is connected to the positive pole of the voltage source _V6 , and the voltage output terminal is connected to the auditory learning suppression voltage selection unit The input of the second AND gate. _The negative terminal of the voltage source _V6 , the voltage output terminal of the selection switch _S8 is connected to the protection resistor R10, the other input terminal of the selection switch _S8 , the negative terminal of the voltage source _V6 and the protection resistor _R10 are grounded.

The auditory learning inhibition voltage selection unit includes a second AND gate A ₂ , a third AND gate A ₃ , a fourth AND gate A ₄ , a seventh selection circuit composed of a selection switch S ₉ , a third voltage absolute value device ABS ₃ , a first An inverse proportional amplifier composed of an operational amplifier OP ₅ and a second voltage selection circuit composed of a first NOT gate D ₄ , a selection switch S ₁₀ and a selection switch S ₁₁ . The input end of the _second AND gate A2 is respectively connected with the auditory stimulation signal L1 and the voltage output end _of the selection switch _S8 , and the output end of the _second AND gate A2 is connected with the conduction signal input end of the selection switch _S9 , the first _Four AND gate A4 is connected to the input. The input end of the _third AND gate A3 is connected with the food signal F1 and the auditory stimulation signal L1 respectively, and the output end _of the _third AND gate A3 is connected with the input end _of the fourth AND gate A4, that is, the _fourth AND gate is connected with the input end of the fourth AND gate A4. _The input end of the gate A4 is respectively connected with the output end of the _second AND gate A2, the output end of the _third AND gate A3, the output end of the _fourth AND gate A4 is connected with the input end of the first NOT gate _D4 , The ON signal input terminal of the selection switch _S11 is connected. _The output end of the first NOT gate D4 is connected to the turn-on signal input end of the selection switch _S10 . The turn-on signal input terminal of the selection switch _S9 is connected to the output terminal of the _second AND gate A2, the voltage input terminal of the selection switch _S9 is connected to the first voltage source _V7 , and the voltage output terminal of the selection switch _S9 is connected to the protection resistor _R11 is connected, the other input terminal of the selection switch _S9 , the negative terminal of the first voltage source _V7 , and the other terminal of the protection resistor _R11 are grounded, and the voltage output terminal of the selection switch _S9 is connected to the inverting proportional amplifier. The inverting proportional amplifier includes a second operational amplifier OP ₅ , and the inverting input terminal of the second operational amplifier OP ₅ is respectively connected with the second resistor R ₁₂ and the third resistor R ₁₃ , and the second resistor R ₁₂ is connected with the selection switch S ₉ . The voltage output terminal is connected, the third resistor _R13 is connected with the output terminal of the second operational amplifier OP5, and the output terminal of the second operational amplifier _OP5 is respectively connected with the input terminal of the _third voltage absolute value device _ABS3 , the selection switch S The voltage input terminal of ₁₀ is connected to each other, and the voltage output terminal of the selection switch _S10 is connected to the IN ₂ input terminal of SUM ₂ . The turn-on signal input terminal of the selection switch _S11 is connected to the output terminal of the first NOT gate D4, the voltage input terminal is connected to the output terminal of the _third voltage absolute value device _ABS3 , and the voltage output terminal is connected to the output terminal of the _second voltage summation device SUM2. IN ₂ input terminal, the other input terminals of the selection switch _S10 and the selection switch _S11 are grounded.

As shown in FIG. 5 , the visual learning inhibition module includes a visual learning inhibition signal unit and a visual learning inhibition voltage selection unit, and the visual learning inhibition signal unit includes a third voltage summation device SUM ₈ , a second memristor M ₆ , a first operation The second voltage follower circuit formed by the amplifier OP9, the second voltage absolute value device _ABS5 , and the three selection switches _S17 , _S18 , _S19 respectively comprise the fourth selection circuit, the _fifth selection circuit and the sixth selection circuit. The positive terminal of the second memristor M6 is connected to the output terminal of the third voltage summing device SUM8, and the negative terminal is connected to the inverting input terminal of the first operational amplifier OP9. The non-inverting input terminal of the first operational amplifier OP ₉ is grounded, the inverting input terminal of the first operational amplifier OP ₉ is connected to the output terminal of the first operational amplifier OP ₉ through the resistor R ₂₂ , and the output terminal of the first operational amplifier OP ₉ is connected to the ground. It is connected to the input end of the second voltage absolute value device _ABS5 , and the output end of the second voltage absolute value device _ABS5 is connected to the turn-on signal input end of the selection switch _S19 . The turn-on signal input terminal of the selection switch _S17 is connected to the output terminal V(A5 ₎ of the first _AND gate A5 of the visual learning voltage selection module, the voltage input terminal is connected to the voltage source _V12 , and the voltage output terminal is respectively connected to the protection resistor _R20 The IN ₁ input terminal of the third voltage summing device SUM ₈ , the protection resistor R ₂₀ , the negative terminal of the voltage source V ₁₂ and the other input terminal of the selection switch S ₁₇ are all grounded. The turn-on signal input terminal of the selection switch _S18 is connected to the visual stimulation signal S1, the voltage input terminal is connected to the voltage source _V13 , and the voltage output terminal is connected to the protection resistor _R21 and the IN2 input terminal of the _{SUM8 respectively} . _The protection resistor _R21 , the voltage The negative terminal of source V ₁₃ and the other input terminal of select switch S ₁₈ are both grounded. The voltage input terminal of the selection switch _S19 is connected to the voltage source _V14 , the voltage output terminal is connected to the input terminal of the sixth AND gate of the visual learning suppression voltage selection unit, the voltage output terminal of the selection switch _S19 is connected to the protection resistor _R23 , and the protection resistor R _23. The negative electrode of the voltage source _V14 is grounded.

The visual learning inhibition voltage selection unit includes an inverse proportional amplifier composed of a second AND gate A ₆ , a third AND gate A ₇ , a fourth AND gate A ₈ , a third voltage absolute value device ABS ₆ , and a second amplifier OP ₁₀ . _A seventh selection circuit composed of a switch _S20 , a first NOT gate _D8 , a selection switch S21, and a second voltage selection circuit composed of a selection switch _S22 . The input end of the second AND gate A6 is respectively connected with the visual stimulation signal S1 and _the voltage output end _of the selection switch _S19 , the output end of the second AND gate A6 is connected with the turn _{- on} signal input end of the selection switch S20, the fourth AND gate _The A8 input of the gate is connected. _The input terminal of the third AND gate _A7 is respectively connected with the food signal F2 and the visual stimulation signal S1, and the output terminal _of the third AND gate _A7 is connected with the input terminal of the fourth AND gate _A8 . _The input end of the fourth AND gate _A8 is respectively connected with the output end of the second AND gate A6 and the output end of the third AND gate _A7 , and the output end of the fourth AND gate _A8 is input to the first NOT gate _D8 terminal and the turn-on signal input terminal of the selection switch _S22 are connected. _The input end of the first NOT gate _D8 is connected to the output of the fourth AND gate _A8 , and the output end is connected to the turn-on signal input end of the selection switch S21. The turn- _on signal input end of _the selection switch S20 is connected to the output end of the second AND gate A6, the voltage input end is connected to the voltage source _V15 , and the voltage output end is connected to an inverse proportional amplifier, which includes a second operational amplifier OP ₁₀ , the non-inverting input terminal of the second operational amplifier OP ₁₀ is grounded, the inverting input terminal of the second operational amplifier OP ₁₀ is respectively connected to the second resistor R ₂₅ and the third resistor R ₂₆ , and the second resistor R ₂₅ is connected to the selection switch _The voltage output terminal of S20 is connected, and the third resistor _R26 is connected to the output terminal of the second operational amplifier _OP10 . The turn-on signal input terminal of the selection switch S21 is connected to the output terminal of the first NOT gate _D8 , the voltage input terminal is connected to the output terminal of the second operational amplifier _OP10 , and the voltage output terminal is connected to the _IN2 of the _second voltage summing device _SUM6 input. The turn-on signal input end of the selection switch _S22 is connected to the output end of the fourth AND gate _A8 , the voltage input end is connected to the output end of the third voltage absolute value device _ABS6 , and the voltage output end is connected to the IN of the second voltage summing device _{SUM6 2} inputs.

The first learning module and the second learning module both include a third NOT gate, a voltage processing component, a third memristor, a third voltage follower circuit, a fourth voltage summing device and a voltage comparison circuit, and the auditory stimulation signal L ₁ or the visual stimulation signal S1 is connected to _one input end of the fourth voltage summing device through the third NOT gate, and the third output end of the learning voltage selection of the first learning voltage selection module or the second learning voltage selection module is connected to the first learning voltage selection module. The three memristors are connected, the third memristor is connected with the third voltage follower circuit, the third voltage follower circuit is connected with an input end of the voltage processing component, the first learning voltage selection module or the second learning voltage selection module The second output terminal of the learning voltage selection of the module is connected with the other input terminal of the voltage processing component, the output terminal of the voltage processing component is connected with the other input terminal of the fourth voltage summing device, and the fourth voltage summing device The output end of the device is connected with the voltage comparison circuit, and the output end of the voltage comparison circuit is the output end of the first learning module or the second learning module.

As shown in FIG. 6 , the auditory learning module includes a third NOT gate D ₃ , a voltage processing component ABM ₁ , a fourth voltage summing device SUM ₃ , a third memristor M ₁ , and a first operational amplifier OP ₂ . The three voltage follower circuits and the third operational amplifier OP ₃ form a voltage comparison circuit. The input terminal of the third NOT gate _D3 is connected to the output terminal _of the auditory stimulation signal L1, and the output terminal is connected to the _IN2 input terminal of the fourth voltage summing device _SUM3 . The positive terminal of the _third memristor M3 is connected to the output terminal of the _second voltage summing device _SUM2 of the auditory learning voltage selection module, and the negative terminal of the output terminal of the _third memristor M3 is connected to the first operational amplifier OP2 The negative phase input terminal of the first operational amplifier OP ₂ is grounded, the negative phase input terminal of the first operational amplifier OP ₂ is connected to the output terminal of the first operational amplifier OP ₂ through the first resistor R ₅ , the first The output terminal of the operational amplifier OP ₂ is connected to the IN ₁ input terminal of the voltage processing element ABM ₁ . The IN ₁ input terminal of the voltage processing component ABM ₁ is connected to the output terminal of the first operational amplifier OP ₂ , the IN ₂ input terminal is connected to the output terminal of the second voltage summation device SUM ₂ , and the output terminal of the voltage processing component ABM ₁ is connected to the output terminal of the second voltage summation device SUM 2. The IN ₁ input of the fourth voltage summing device SUM ₃ is connected. The negative input terminal of the amplifier OP ₃ is connected to the negative input terminal, the positive input terminal is connected to the voltage source V ₁₂ , and the output terminal is connected to the conduction signal input terminal of S ₂ . The output voltage of the voltage processing component ABM ₁ is equal to the absolute value of the voltage at the input terminal of IN ₂ divided by the voltage at the input terminal of IN ₁ , ie M ₁ /R ₅ . When the resistance value of the _first memristor M1 decreases, the output voltage of the voltage processing component _ABM1 decreases accordingly. When the output voltage of the voltage processing component ABM ₁ drops to a threshold value, the positive voltage of the third operational amplifier OP ₃ is greater than the negative voltage, and a signal is output.

The voltage comparison circuit includes a third operational amplifier OP ₃ , the inverting input terminal of the third operational amplifier OP ₃ is connected with the input signal, that is, the output terminal of the fourth voltage summing device SUM ₃ , and the non-inverting input terminal of the third operational amplifier OP ₃ It is connected to the positive pole of the second power supply _V8 , the negative pole of the second power supply V8 is grounded, the output terminal of the _third operational amplifier _OP3 is the output terminal V(N1 ₎ , the output signal of the auditory learning module.

As shown in FIG. 7 , the visual learning module includes a third NOT gate D ₇ , a voltage processing component ABM ₂ , a fourth voltage summing device SUM ₇ , a third memristor M ₄ and a first operational amplifier OP ₇ . Three voltage follower circuits and a voltage comparison circuit composed of a third operational amplifier OP ₈ . The input terminal of the third NOT gate D ₇ is connected to the visual stimulation signal S ₁ , and the output terminal is connected to the IN ₂ input terminal of the fourth voltage summing device SUM ₇ . _The positive terminal of the third memristor M4 is connected to the output terminal of the second voltage summing device _SUM6 and the voltage output terminal of the selection switch _S16 , and the negative terminal of the third _memristor M4 is connected to the first operational amplifier OP The inverting input terminal of ₇ , the non-inverting input terminal of the first operational amplifier OP ₇ is grounded, the inverting input terminal of the first operational amplifier OP ₇ is connected to the output terminal of the first operational amplifier OP 7 through the resistor R ₁₈ , and the first operational amplifier OP ₇ The output of the amplifier OP ₇ is connected to the IN ₁ input of the voltage processing element ABM ₂ . The IN ₁ input terminal of the voltage processing component ABM ₂ is connected to the output terminal of the first operational amplifier OP ₇ , and the IN ₂ input terminal of the voltage processing component ABM ₂ is connected to the output terminal and the selection switch S of the second voltage summing device SUM ₆ The voltage output terminal ₁₆ is connected to each other, and the output terminal of the voltage processing component ABM ₂ is connected to the IN ₁ input terminal of the fourth voltage summing device SUM ₇ . The inverting input terminal of the third operational amplifier OP ₈ is connected to the output terminal of the fourth voltage summing device SUM ₇ , the non-inverting input terminal of the third operational amplifier OP ₈ is connected to the voltage source V ₁₆ , and the output terminal of the third operational amplifier OP ₈ is connected to Select the turn-on signal input of _S13 .

The present invention includes two learning modules, an auditory module and a visual module, respectively representing the auditory learning mode and the visual learning mode. The auditory module includes an auditory learning voltage selection module, an auditory learning module and a visual learning inhibition module, and the visual learning inhibition module includes a visual learning inhibition signal module and a visual learning inhibition voltage selection module. The visual module includes a visual learning voltage selection module, a visual learning module and a visual learning inhibition module, and the auditory learning inhibition module includes an auditory learning inhibition signal unit and an auditory learning inhibition voltage selection unit. _The auditory stimulation signal L1 and the food signal _F1 output high level, and the auditory learning mode starts. The auditory learning voltage selection module, the auditory learning module and the visual learning inhibitory signal unit are called, and the visual learning inhibitory signal is generated at the same time as the auditory learning. _{The auditory stimulation signal L1 and the food signal F1 output a low level, the visual stimulation signal S1 and the food signal F2 output a high level ,} the auditory learning mode stops, and the visual learning mode starts. The visual learning voltage selection module, the visual learning module, the auditory learning inhibition signal unit, the visual learning inhibition signal unit and the visual learning inhibition voltage selection module are called, and the visual learning module is in the dual of the visual learning voltage selection module and the visual learning inhibition selection voltage module. under the action. Visual learning simultaneously generates auditory learning inhibition signals and cancels visual learning inhibition signals.

Specifically, the circuit structure of the present invention can complete the switching mode learning function of the dog's auditory mode and visual mode. Under the action of food signal F ₁ and auditory stimulation signal L ₁ , the puppy learns auditory patterns. Under normal circumstances, after learning T seconds, the puppy can salivate under the action of auditory signals alone, that is, auditory learning is completed. Under the action of food signal F ₂ and visual stimulus signal S ₁ , puppy learns visual patterns. Under normal circumstances, after learning W seconds, the puppy can salivate under the action of visual signals alone, that is, the visual learning is completed. Dual-mode switching learning, the puppy first learns the auditory mode for A seconds, and then performs the visual mode learning for A seconds. The learning mode is continuously switched until the learning is completed, and A<W<T.

Specifically, in the _first step _of mode switching learning, the food signal F1 and auditory stimulation signal L1 output high level, and the visual stimulation signal _S1 and food signal _F2 output low level for auditory learning and visual learning inhibition. Auditory learning: the selection switch S ₁ is turned on, the voltage source V ₁ outputs a voltage to the first memristor M ₂ , and after the first operational amplifier OP ₁ acts, the absolute value device ABS ₁ converts the voltage. _The selection switch S4 is turned on, and the absolute value device ABS1 outputs the voltage to the IN1 input terminal _of the _second voltage summing device _SUM2 , that is, the _VSUM2 (IN1 ₎ output terminal. The second voltage summing device SUM ₂ outputs the voltage VSUM ₂ (out) to the IN ₂ input of the third memristor M ₁ and the voltage processing device ABM ₁ , the voltage on the third memristor M ₁ is passed through the ortho-amplifier OP ₂ is applied to the IN ₁ input of the voltage processing component ABM ₁ after being applied. The voltage processing element ABM ₁ outputs the voltage VABM ₁ (out) to the IN ₁ input of the fourth voltage summing device SUM ₃ , and the fourth voltage summing device SUM ₃ outputs the voltage to the negative input of the operational amplifier OP ₃ . Visual learning inhibition: the selection switch S ₁₇ is turned on, the voltage source V ₁₂ starts to output voltage to the second memristor M ₆ , the voltage of the second memristor M ₆ is converted by the operational amplifier OP ₉ , and the absolute value device ABS ₅ The absolute value is calculated and then used as the turn-on voltage of the selection switch _S19 . As the memristor value of the second memristor _M6 decreases, the turn-on voltage gradually increases. When the turn-on voltage of the selection switch S19 is greater than the threshold voltage of the selection switch _S19 , the voltage source _V19 starts to output a voltage, that is, _the visual learning inhibition signal _VS19 (out).

In the second step, the auditory stimulation signal L ₁ and the food signal F ₁ output a low level, the visual stimulation signal S ₁ and the food signal F ₂ output a high level, the mode switching starts, and the visual learning, auditory learning inhibition and visual learning inhibition elimination are carried out. . Visual learning: the selection switch _S12 is turned _on , the voltage source V9 outputs the voltage to the first memristor M5, and after the ortho-acid amplifier _OP6 acts, the voltage is converted by the voltage absolute value device _{ABS4 .} The selection switch S15 is turned _on , and the voltage absolute value device _ABS4 outputs the voltage to the IN1 input terminal _of the voltage summing device _SUM6 , namely _VSUM6 (IN1 ₎ . The AND gate D6 outputs a high level, the selection switch _S20 is turned _on , and the voltage source _V15 outputs a voltage, which is converted by the absolute value device _ABS6 after the operation amplifier _OP10 acts. The selection switch _S22 is turned on, and the absolute value device ABS ₆ outputs the voltage to the IN ₂ input terminal of the voltage processing element SUM ₆ of the voltage summing device, namely VSUM ₆ (IN ₂ ). The voltage summation device SUM ₆ outputs the voltage VSUM ₆ (out) to the IN ₂ input terminals of the memristor M ₄ and ABM ₂ , and the voltage on the memristor M ₄ is applied to the voltage processing element ABM ₂ after being acted by the amplifier OP ₇ the IN ₁ input. The voltage processing element ABM ₂ outputs the voltage VABM ₁ (out) to the IN ₁ input of the voltage summing device SUM ₃ , and the voltage summing device SUM ₃ outputs the voltage to the negative input of the operational amplifier OP ₃ . Auditory learning inhibition: the selection switch _S6 is turned _on , the voltage source _V4 starts to output voltage to the second memristor M3, the voltage _of the second memristor M3 is converted by the operational amplifier _OP4 , and then passed through the voltage absolute value device ABS. ₂ for absolute value calculation, and then as the turn-on voltage of the selection switch _S8 . As the memristor value _of the second memristor M3 decreases, the turn-on voltage gradually increases. When the turn-on voltage of the selection switch _S8 is greater than the threshold voltage of the selection switch _S8 , the voltage source _V6 starts to output a voltage, that is, the auditory learning inhibition signal _VS8 (out). Visual learning inhibition is eliminated: the selection switch _S18 is turned on, the voltage source _V13 outputs the voltage to the memristor _M6 , the voltage of the memristor M6 is converted by the ortho _- acid amplifier _OP9 , and the voltage absolute value device _ABS5 conducts The absolute value is calculated and then used as the turn-on voltage of the selector switch _S21 . With the increase of the memristor value of the memristor _M6 , the turn-on voltage gradually decreases. When the turn-on voltage of the selection switch _{S19 is less than the threshold voltage of the selection switch S19, VS 14 ( out} ) is zero. The AND gate A6 outputs a low level, the selection switch S20 is turned off, and _{VSUM 6} (IN _{2 )} is zero, that is, the visual learning inhibition is eliminated. The detailed learning mode switching simulation experiment is shown in Figure 8 and Figure 9. FIG. 8 is a simulation waveform of switching learning of visual mode after hearing mode first, and FIG. 9 is a simulation waveform of switching learning of auditory mode after visual mode first.

The dual-mode switching learning and memory circuit based on the memristor-based Pavlovian associative memory proposed by the present invention, when different excitation signals are input into the circuit, through logic circuit processing, the switching learning of different modes will be carried out, and the output results will be used to learn To explore the inhibitory effect of dual-modal switching learning on a single learning mode.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the scope of the present invention. within the scope of protection.

Claims (7)

1. A learning memory circuit based on Pavlov dual-mode switching of a memristor is characterized by comprising a first memory module and a second memory module which are mutually learning-inhibited, wherein the first memory module is connected with the second memory module, the first memory module is connected with a first excitation signal source, and the second memory module is connected with a second excitation signal source; the first memory module comprises a first learning voltage selection module, a first learning module and a first learning suppression module, a first excitation signal source is respectively connected with the input ends of the first learning voltage selection module, the first learning module and the first learning suppression module, the output end of the first learning voltage selection module is respectively connected with the input ends of the second memory module and the first learning module, the output end of the first learning module is connected with the first learning voltage selection module, the input end of the first learning suppression module is connected with the output end of the second memory module, and the output end of the first learning suppression module is connected with the input end of the first learning voltage selection module; the second memory module comprises a second learning voltage selection module, a second learning module and a second learning suppression module, a second excitation signal source is respectively connected with the second learning voltage selection module, the second learning module and the second learning suppression module, the output end of the second learning module is connected with the input end of the second learning voltage selection module, the output end of the second learning voltage selection module is respectively connected with the input ends of the second learning module and the first learning suppression module, the first learning voltage selection module is connected with the input end of the second learning suppression module, and the output end of the second learning suppression module is connected with the input end of the second learning voltage selection module; the output ends of the first excitation signal source and the first learning module are connected with a first OR gate, the output end of the first OR gate outputs a first learning memory signal, the output ends of the second excitation signal source and the second learning module are connected with a second OR gate, and the output end of the second OR gate outputs a second learning memory signal;

the first memory module is an auditory module, the second memory module is a visual module, and the first excitation signal source comprises a food signal F₁And an auditory stimulus signal L₁Food signal F₁Respectively connected with the first learning voltage selection module, the first OR gate and the first learning suppression module, and an auditory stimulation signal L₁The first learning voltage selection module, the first learning module and the first learning suppression module are respectively connected; the second excitation signal source comprises a food signal F₂And a visual stimulus signal S₁Food signal F₂Respectively connected with a second learning voltage selection module, a second OR gate and a second learning suppression module, and a visual stimulation signal S₁The learning voltage selection module, the learning suppression module and the learning suppression module are respectively connected with the first learning voltage selection module, the first learning module and the learning suppression module.

2. According to claim 1The memory circuit based on the memristor and Pavlov dual-mode switching is characterized in that the first learning voltage selection module and the second learning voltage selection module respectively comprise a first AND gate, a first NOT gate, a first voltage absolute value device, a first voltage summation device, a first memristor, and a food signal F₁Or food signal F₂An auditory stimulation signal L₁Or visual stimulus signal S₁The first AND gate is respectively connected with two input ends of the first AND gate, and outputs a first output end selected by the learning voltage; the first AND gate is connected with the first voltage selection circuit, and the auditory stimulation signal L₁Or visual stimulus signal S₁The output end of the first learning module or the second learning module is connected with the second selection circuit, the first selection circuit and the second selection circuit are both connected with a first voltage summing device, the first voltage summing device is connected with a first memristor, the first memristor is connected with a first voltage follower circuit, the output end of the first voltage follower circuit is respectively connected with a first voltage absolute value device and the first voltage selection circuit, the first voltage absolute value device is connected with the first voltage selection circuit, the output end of the first voltage selection circuit is connected with one input end of a second voltage summing device, the first learning suppression module or the second learning suppression module is connected with the other input end of the second voltage summing device, and the output end of the second voltage summing device outputs a second output end selected by the learning voltage; auditory stimulus signal L₁Or visual stimulus signal S₁The output end of the third selection circuit outputs a third output end selected by the learning voltage.

3. The pavlov dual-mode switching memristor-based learning memory circuit of claim 1 or 2, wherein the first and second learning suppression modules each comprise a suppression signal unit and a suppression voltage selection unit, the suppression signal unit and the suppression voltage selection unit being connected; the signal suppression unit comprises a fourth selection circuit, a fifth selection circuit and a sixth selection circuitThe first output end of the learning voltage selection of the second learning voltage selection module or the first learning voltage selection module is connected with the fourth selection circuit, and an auditory stimulus signal L₁Or visual stimulus signal S₁The output ends of the fourth selection circuit and the fifth selection circuit are connected with a third voltage summation device, the third voltage summation device is connected with a second memristor, the second memristor is connected with a second voltage follower circuit, the second voltage follower circuit is connected with the input end of a sixth selection circuit through a second voltage absolute value device, the output end of the sixth selection circuit is connected with one input end of a second AND gate, and an auditory stimulation signal L is generated₁Or visual stimulus signal S₁Respectively connected with another input end of the second AND gate and one input end of the third AND gate, and a food signal F₁Or food signal F₂The other input end of the third AND gate is connected; the suppression voltage selection unit comprises a seventh selection circuit, an inverting proportional amplifier and a third voltage absolute value device, the output end of the second AND gate is connected with the seventh selection circuit, the seventh selection circuit is connected with the inverting proportional amplifier, the output end of the inverting proportional amplifier is respectively connected with the third voltage absolute value device and the input end of the second voltage selection circuit, and the output end of the third voltage absolute value device is connected with the second voltage selection circuit; and the output ends of the second AND gate and the third AND gate are connected with a fourth AND gate, the fourth AND gate is connected with a second voltage selection circuit, and the output end of the second voltage selection circuit is connected with the input end of a second voltage summation device of the first learning voltage selection module or the second learning voltage selection module.

4. The memristor-based Pavlov dual-mode-switched learning memory circuit of claim 3, wherein the first learning module and the second learning module each comprise a third NOT gate, a voltage processing component, a third memristor, a third voltage follower circuit, a fourth voltage summing device, and a voltage comparison circuitAuditory stimulus signal L₁Or visual stimulus signal S₁The third output end of the learning voltage selection of the first learning voltage selection module or the second learning voltage selection module is connected with a third memristor, the third memristor is connected with a third voltage follower circuit, the third voltage follower circuit is connected with one input end of a voltage processing component, the second output end of the learning voltage selection of the first learning voltage selection module or the second learning voltage selection module is connected with the other input end of the voltage processing component, the output end of the voltage processing component is connected with the other input end of the fourth voltage summation device, the output end of the fourth voltage summation device is connected with a voltage comparison circuit, and the output end of the voltage comparison circuit is the output end of the first learning module or the second learning module.

5. The memory circuit of claim 4, wherein the first voltage selection circuit and the second voltage selection circuit each comprise a selection switch I, a selection switch II, and a second NOT gate, the second NOT gate and the selection switch II are respectively connected to an input control signal, the second NOT gate is connected to the selection switch I, voltage input ends of the selection switch I and the selection switch II are respectively connected to different voltage signals, and output ends of the selection switch I and the selection switch II are connected to serve as output ends of the voltage selection circuit; the selection switch I and the selection switch II are first selection switches with two inputs and one output, two input ends of each first selection switch are respectively connected with an input control signal and a voltage input signal, an output end of each first selection switch selects whether to output the voltage input signal according to the input control signal, and the other end of each first selection switch is grounded.

6. The memory circuit of claim 5, wherein the first, second, third, fourth, fifth, sixth, and seventh selection circuits each comprise a two-input one-output second selection switch, one input of the second selection switch is grounded, one input of the second selection switch is connected to the positive electrode of the first power supply, the negative electrode of the first power supply is grounded, the other input of the second selection switch is connected to the input control signal, and the output of the second selection switch outputs a corresponding voltage signal according to the input control signal; the output end of the second selection switch is connected with a protection resistor, and the other end of the protection resistor is grounded.

7. The memristor-based Pavlov dual-mode-switched learning memory circuit of claim 5, wherein the first, second and third voltage follower circuits each comprise a first operational amplifier, a non-inverting input of the first operational amplifier being connected to ground, an inverting input of the first operational amplifier being connected to an output of the first operational amplifier through a first resistor; the inverting proportional amplifier comprises a second operational amplifier, the non-inverting input end of the second operational amplifier is grounded, the inverting input end of the second operational amplifier is respectively connected with a second resistor and a third resistor, the second resistor is connected with an input signal, and the third resistor is connected with the output end of the second operational amplifier; the voltage comparison circuit comprises a third operational amplifier, the inverting input end of the third operational amplifier is connected with the input signal, the non-inverting input end of the third operational amplifier is connected with the anode of the second power supply, the cathode of the second power supply is grounded, and the output end of the third operational amplifier outputs the output signal of the first learning module or the second learning module.

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