CN110232443A - Realize the impulsive neural networks Digital Analog Hybrid Circuits system of liquid condition machine - Google Patents
Realize the impulsive neural networks Digital Analog Hybrid Circuits system of liquid condition machine Download PDFInfo
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- 239000007788 liquid Substances 0.000 title claims abstract description 22
- 210000002569 neuron Anatomy 0.000 claims abstract description 70
- 238000012421 spiking Methods 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 145
- 210000000225 synapse Anatomy 0.000 claims description 54
- 108010052164 Sodium Channels Proteins 0.000 claims description 34
- 102000018674 Sodium Channels Human genes 0.000 claims description 34
- 102000004257 Potassium Channel Human genes 0.000 claims description 30
- 239000012528 membrane Substances 0.000 claims description 30
- 108020001213 potassium channel Proteins 0.000 claims description 30
- 230000002964 excitative effect Effects 0.000 claims description 26
- 230000002401 inhibitory effect Effects 0.000 claims description 23
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- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 claims description 2
- NPYPAHLBTDXSSS-UHFFFAOYSA-N Potassium ion Chemical compound [K+] NPYPAHLBTDXSSS-UHFFFAOYSA-N 0.000 claims description 2
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 claims description 2
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Abstract
The invention discloses a kind of impulsive neural networks Digital Analog Hybrid Circuits systems for realizing liquid condition machine, including A2S coding input layer, SNN computation layer, S2A decoding layer, on-line study and o controller and hyper parameter controller.SNN computation layer includes N number of spiking neuron circuit, is connected by interference networks restructural between neuron, and by the restructural interference networks connection of input and output between A2S coding input layer and SNN computation layer, A2S coding input layer includes M A2S coding unit；S2A decoding layer is connect by the restructural interference networks of input and output with SNN computation layer and A2S coding input layer, and S2A decoding layer includes M+N S2A decoding unit.The characteristics of hybrid circuit system combines the high advantage of the fast and digital circuit counting flexibility of analog circuit calculating speed, makes it have high computational efficiency, strong real-time and on-line study, to push application of the ANN technology in Internet of Things application scenarios.
Description
Technical field
The present invention relates to neuromorphic engineerings more particularly to a kind of reality that mimic biology neuroid realizes artificial intelligence
The impulsive neural networks Digital Analog Hybrid Circuits system of existing liquid condition machine.
Background technique
Neuroscience Research show biological nervous system be as a large amount of neuron be connected with each other made of high complexity,
The network information system of strong nonlinearity.Scientists are observed the structure and function of biological neural network, test and model,
The mechanism by imitating its expression, transmitting, processing and recall info is attempted to explore its working principle, is established at class brain information
Reason system, to realize real artificial intelligence.Therefore, artificial neural network (ANN) technology is produced.First generation ANN is used
Jump function is feedovered connection network structure using shallow-layer as activation primitive, Typical Representative include M-P model, perceptron model,
Adaline model etc..First generation neural network is difficult to the problem of coping with linearly inseparable, and scientist replaces with jump function more
Smooth nonlinear function (such as Sigmoid function, ReLU function), while (such as gradient with the help of Novel learning algorithm
Descent algorithm), develop second generation ANN, Typical Representative include multilayer perceptron, deep neural network, hopfield network,
Self-organizing network, convolutional neural networks and support vector machines etc..Currently, mature artificial intelligence technology mainly uses the second generation
ANN technology, using graphics acceleration card (GPU) array largely labeled data concentration the network parameter of ANN is trained,
The quantitative requirement of this labeled data to the computing capability of hardware system and is very high, and it is also very big to calculate energy consumption.Therefore, this technology
When applied to scenes of internet of things, it usually needs the data that internet of things sensors acquires are uploaded onto the server by information network
End carries out off-line learning to it and result is passed back to the execution terminal of Internet of Things again after handling, generates response action.Therefore,
ANN technology is applied to scenes of internet of things, is faced with the technology of reduce power consumption, improve computational efficiency and realize on-line study etc.
Challenge.
In response to this problem, academia proposes third generation ANN technology, i.e. impulsive neural networks (SNN).It is will be continuous
Analog sensed Signal coding at discrete pulsed signal (Electrophysiology field is known as action potential) spatial and temporal distributions information；It uses
Biological neuron electrophysiological model (such as HH model, FHN model, LIF model etc.) is used as information process unit, it can be to pulse
Sequence carries out non-linear integration；Use nerve synapse model (such as chemical synapse, electrical synapse) as network connection unit, it can
Simulate the transmitting and neurotransmitter function and effect (IPSP of the EPSP of such as excitatory synapse, inhibitory synapse) of postsynaptic potential；
And then combine the topological attributes complicated composition network structures such as scale free, worldlet；In supervised learning mechanism (such as gradient decline, line
Property return etc.) or unsupervised learning plastic mechanism (such as Hebb study mechanism, the plastic mechanism of STDP, E-I balancing)
Control is lower to optimize network weight parameter, realizes the function of class brain Intelligent Information Processing.
Liquid condition machine (Liquid State Machine, LSM) is the Typical Representative of SNN, its liquid level is (implicit
Layer) use SNN computation model.The pulse train input signal of low-dimensional can be converted into dimensional state by LSM, be mentioned in higher dimensional space
Take signal characteristic.Its maximum feature is that the connection weight of liquid level remains unchanged during calculating, only to hidden layer with
The connection weight of output layer is trained, and has easy a calculating process and dynamic characteristic abundant, liquid condition thus possess
Powerful computing capability.Therefore, it realizes and the circuit system of liquid condition machine computation model is supported to be expected to solution ANN and answer in Internet of Things
It is the problem of with the power consumption, computational efficiency and on-line study encountered in scene, with important application prospects.
Summary of the invention
The technical problem to be solved by the present invention is to how provide a kind of high computational efficiency, strong real-time and can on-line study
Realization liquid condition machine impulsive neural networks Digital Analog Hybrid Circuits system.
In order to solve the above technical problems, the technical solution used in the present invention is: a kind of pulse for realizing liquid condition machine
Neural network Digital Analog Hybrid Circuits system, it is characterised in that: including A2S coding input layer, SNN computation layer, S2A decoding layer,
Line study is with o controller and hyper parameter controller, the continuous multichannel mould that the A2S coding input layer acquires sensor
Quasi- signal is converted into the discrete multichannel pulse signal with spatial-temporal distribution characteristic, is input to SNN computation layer, and wherein A2S is compiled
Each coding unit of code input layer corresponds to analog signal all the way, and element number M is identical as the quantity of analog signal array, mould
The encryption algorithm that quasi- signal is converted into pulse signal is selected by hyper parameter controller；
SNN computation layer includes N number of spiking neuron circuit, is connected by interference networks restructural between neuron, A2S coding input
It is connected between layer and SNN computation layer by the restructural interference networks of input and output, A2S coding unit both can be with whole pulse minds
Through first circuit connection, can also be connected with partial nerve member, specific connection type is determined by hyper parameter controller；
S2A decoding layer is connect by the restructural interference networks of input and output with SNN computation layer and A2S coding input layer, S2A decoding
Layer includes M+N 2A decoding unit；
On-line study and o controller to the output of S2A decoding layer sum up operation and with the supervision from A2S input layer
Signal carries out linear regression analysis, and the resistance value of restructural electric resistance array in S2A decoding layer is adjusted according to error result, realizes information
The optimization closed loop of output layer on-line study；After on-line study, it will no longer change S2A decoding layer internal resistance value, and be summed it up operation knot
Fruit exports as the signal of classification foundation or modeling and forecasting；
Hyper parameter controller be used to determine the encryption algorithm that A2S coding input layer choosing selects, in SNN computation layer neuron circuit number
It is restructural in internetwork connection mode, excitatory synapse circuit and inhibitory synapse circuit between amount and membrane capacitance parameter, neuron
The resistance value of electric resistance array and the connection topology of input and output interference networks.
The beneficial effects of adopting the technical scheme are that the hybrid circuit system combines analog circuit meter
It calculates speed fastly and the high advantage of digital circuit counting flexibility, makes it have computational efficiency height, strong real-time and on-line study
Feature, to push application of the ANN technology in Internet of Things application scenarios.The hybrid circuit system realizes biological neural system
The calculating of the electrophysiological model of neuron and nerve synapse in system, this multidimensional nonlinear kinetics equation are using digital display circuit
Very high computing resource can be expended when solution, and computational efficiency is greatly reduced with the promotion of time precision, to be difficult to protect
The real-time of card output result, analog circuit calculating can be effectively solved the above problem.The hybrid circuit system uses embedding
Enter formula controller in conjunction with the hyper parameter of restructural digital circuitry control network, such as input coding, network topology, network weight
Weight, input and output connection, to make the flexibility of system be substantially improved, a variety of different application scenarios can be used and appoint
Business feature, and can flexibly switch between different task.The hybrid circuit system can be weighed using embedded controller combination
Structure digital circuitry realizes on-line study function, has the parameter amount of study optimization small, as a result the characteristics of fast convergence rate.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
Fig. 1 is the functional block diagram of hybrid circuit system described in the embodiment of the present invention；
Fig. 2 is the circuit diagram that A2S is coded into unit in hybrid circuit system described in the embodiment of the present invention；
Fig. 3 is the schematic diagram of neuron circuit in hybrid circuit system described in the embodiment of the present invention；
Fig. 4 is the schematic diagram of restructural capacitor array in the embodiment of the present invention；
Fig. 5 is the schematic diagram of restructural interference networks between neuron in the embodiment of the present invention；
Fig. 6 is the schematic diagram of excitatory synapse circuit in the embodiment of the present invention；
Fig. 7 is the schematic diagram of inhibitory synapse circuit in the embodiment of the present invention；
Fig. 8 is the schematic diagram of restructural electric resistance array in the embodiment of the present invention；
Fig. 9 is the schematic diagram of the restructural interference networks of input and output in the embodiment of the present invention；
Figure 10 is the schematic diagram of S2A decoding unit in the embodiment of the present invention.
Specific embodiment
With reference to the attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiment is only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
Implemented using other than the one described here other way, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
As shown in Figure 1, the embodiment of the invention discloses a kind of impulsive neural networks numerical model analysis for realizing liquid condition machine
Circuit system, including A2S coding input layer, SNN computation layer, S2A decoding layer, on-line study and o controller and hyper parameter control
Device processed.
A2S coding input layer acquires sensor (such as camera, sound pick-up and wireless aerial battle array) continuous more
Road analog signal is converted into the discrete multichannel pulse signal with spatial-temporal distribution characteristic, is input to SNN computation layer, wherein
Each coding unit of A2S coding input layer corresponds to analog signal all the way, the quantity phase of element number M and analog signal array
Together, the encryption algorithm that analog signal is converted into pulse signal is selected by hyper parameter controller.A2S coding unit (as shown in Figure 2)
Digital circuits section and pulse including micro controller module generate the artificial circuit part of part.Micro controller module is according to super
The A2S encryption algorithm of parameter controller selection will be encoded into discrete pulse sequence from the original analog of sensor, such as
The a certain moment needs to generate a pulse signal, when microcontroller controls one section of switch (such as midget relay) closure
Between, so that current source is charged to pulse-generating circuit and it is made to generate pulsatile once electric discharge behavior, completes the generation of a pulse
Journey.This process is repeated, pulse train sequence is generated.Micro controller module by markup information corresponding to each original signal or
Person's training signal exports the supervisory signals to on-line study and o controller, as on-line study.
As shown in Fig. 2, the A2S coding input unit includes that the digital circuits section of micro controller module and pulse generate
Partial artificial circuit part, micro controller module input the A2S encryption algorithm autobiography in future of selection according to hyper parameter controller
The original analog of sensor is encoded into discrete pulse sequence, and micro controller module is by mark corresponding to each original signal
Information or training signal export the supervisory signals to on-line study and o controller, as on-line study；
The analog module includes capacitor Cm, bleeder resistance RL, sodium channel module and potassium channel module, the capacitor Cm
Respectively with the bleeder resistance RL, sodium channel module and potassium channel wired in parallel, the capacitor CmOne end receives internal current source
Output electric current Iout, and membrane voltage V is exported in this one endmem, as the output for corresponding to coding unit in A2S coding input layer,
Capacitor CmThe other end ground connection.
Capacitor CmReceive the current signal I of internal current source outputout, current signal IoutFirst to the capacitor CmIt carries out
Charging, as the capacitor CmVoltage be greater than the sodium channel module in triode Q1 cut-in voltage when, the sodium channel mould
Block is to can capacitor CmAnd the potassium channel module charges, and opens for simulating biological neuron sodium-ion channel, works as institute
When stating cut-in voltage of the voltage of capacitor C1 in potassium channel module greater than triode Q3, the capacitor CmPass through the potassium channel again
Module is discharged, and simulation biological neuron potassium-channel is opened, and the sodium channel current that then sodium channel module generates stops
To capacitor CmIt charges, sodium-ion channel is closed on imictron cell membrane；Finally, capacitor CmAlso stop passing through the potassium channel
Module discharge, the current signal I of internal current source outputoutContinue to capacitor CmCharging, makes capacitor CmThe voltage at both ends is restored to
Resting potential completes the generation process an of action pulse.
As shown in Fig. 2, the sodium channel module includes triode Q1, triode Q2, resistance R2, resistance R4 and voltage source
VNa, the base stage of the triode Q1 is divided into two-way, the first via and the capacitor CmOne end connection, the second tunnel and triode Q2 current collection
Pole connection, the emitter of the triode Q1 are grounded through resistance R4, and the collector of the triode Q1 is with the triode Q2's
Base stage connection, the emitter of the triode Q2 is through resistance R2 and the voltage source VNaAnode connection, the voltage source VNa's
Cathode ground connection, a terminals of the extremely described sodium channel module of the current collection of the triode Q2, the terminals and the potassium are logical
One terminals of road module connect；
As shown in Fig. 2, the potassium channel module includes triode Q3, resistance Rr, resistance R3, capacitor C1 and voltage source VK, institute
The one end for stating resistance R3 is divided into three tunnels, and the first via is connect with a terminals of the sodium channel module, the second tunnel and resistance Rr
One end connection, third road connect with the output end of the neuron circuit, the other end and the triode of the resistance R3
The collector of Q3 connects, the emitter of the triode Q3 and the voltage source VKCathode connection, the voltage source VKAnode
Ground connection, the base stage of the triode Q3 are divided into two-way, the first via and resistance RrThe other end connection, the second tunnel connects through capacitor C1
Ground；
Capacitor CmReceive external input current signal Iout, the membrane voltage V at both endsmemConstantly increase；As membrane voltage VmemGreater than three
When the cut-in voltage of pole pipe Q1, triode Q1, triode Q2 are opened, and triode Q2 collector exports sodium channel current, to can weigh
Structure capacitor array carries out quick charge, film potential VmemIt increases rapidly, which opens for simulating biological neuron sodium-ion channel
It opens, the rapid interior process flowed of neuronal cell film extracellular sodium ion；
Sodium channel current is to capacitor CmWhile quick charge, slowly charge to the capacitor C1 in potassium channel module, capacitor C1 electricity
Press VrSlowly rise, as the VrWhen value is greater than the cut-in voltage of triode Q3, triode Q3 is opened, capacitor CmBy resistance R3,
The electric discharge of triode Q3 branch, triode Q3 emitter export potassium channel current, membrane voltage VmemDecline rapidly, the process are used for mould
Quasi- biological neuron potassium-channel is opened, and potassium ion outflows rapidly and makes membrane voltage V in neuronal cell filmmemDecline rapidly
Process, wherein VkFor the voltage source for simulating potassium channel balanced voltage, the voltage source value is bigger, and after Q3 is opened, Q3 emitter is defeated
Potassium channel current out is bigger, membrane voltage VmemThe speed of decline is also bigger；
As membrane voltage VmemWhen dropping to less than the cut-in voltage of triode Q1, triode Q1 cut-off, the sodium that sodium channel module generates
Channel current stops to capacitor CmCharging, the process which closes for sodium-ion channel on imictron cell membrane；
As membrane voltage VmemWhen less than resting potential, if triode Q3 is still opened, membrane voltage VmemContinue to decline, works as membrane voltage
VmemWhen dropping to less than the cut-in voltage of triode Q3, triode Q3 cut-off, the capacitor CmStop by potassium channel module into
Row electric discharge, external input current signal IoutContinue to capacitor CmCharging, to make membrane voltage VmemIt is restored to resting potential, thus
Complete the generation process an of action pulse.
SNN computation layer is to connect into one kind again by interference networks restructural between neuron by a large amount of spiking neuron circuits
Miscellaneous neural network, the resistance value of the restructural electric resistance array in network topology, excitatory synapse circuit and inhibitory synapse circuit
All it is to be determined by hyper parameter controller, is remained unchanged in on-line study.Lead between A2S coding input layer and SNN computation layer
The connection (as shown in Figure 9) of the restructural interference networks of input and output is crossed, A2S coding unit can both be connected with whole neurons,
It can be connected with partial nerve member, specific connection type is determined by hyper parameter controller.(the principle of neuron circuit such as Fig. 3 institute
Showing, working principle is similar with A2S coding input unit in Fig. 2) neuron circuit can be according to the input of hyper parameter controller
The capacitance of its restructural capacitor array (as shown in Figure 4) is determined, to reach the different membrane capacitances of simulation and show pulse signal
The non-thread sex differernce of integration.The restructural capacitor array of neuron circuit can also be determined by microcontroller, be transported in microcontroller
The different inside plasticity algorithm of row, changes the capacitance of membrane capacitance according to the situation of change of the film potential of acquisition, reaches simulation
Inside neurons plasticity realizes the dynamic equilibrium of neuronal messages processing.Restructural capacitor array is (logical by programmable switch
Cross state latch and driving chip, midget relay be composed) and parallel form capacitor array composition, programmable switch control
Whether the capacitor for making different capacitances is incorporated between input and output both ends.The input and output side of each neuron circuit accesses
Restructural internet (as shown in Figure 5) between neuron, N number of left side port of restructural internet connects each mind between neuron
Output end through member, N number of downside port connect the input terminal of each neuron, and the output end of any one neuron may all pass through
A kind of Sudden-touch circuit (excitatory synapse or inhibitory synapse, as shown in Figure 6 and Figure 7) is connected to the input of any one neuron
End, therefore restructural internet can form a fully-connected network between neuron, but whether every connection connects, connects and dash forward
The type on electric shock road is to be controlled by hyper parameter controller by state latch and controller and relay switch, to realize difference
Network topology, and connect the synapse weight (i.e. restructural electric resistance array) of Sudden-touch circuit and also determined by hyper parameter control.It is prominent
Getting an electric shock road can be according to the resistance value of its determining restructural electric resistance array of input of hyper parameter controller, so that it is different prominent to reach simulation
Touching weight and show the difference of pulse signal transmission efficiency.The restructural electric resistance array of Sudden-touch circuit can also be by microcontroller
It determines, the different non-supervisory synaptic plasticity algorithm of operation, is input to microcontroller according to hyper parameter controller in microcontroller
Signal, microcontroller can choose specific performed non-supervisory synaptic plasticity algorithm, according to the prominent of microcontroller acquisition
Electric shock road outputs and inputs the situation of change of terminal potential and changes resistance value, reaches imictron synaptic plasticity, realizes nerve
The ability of network unsupervised learning.Restructural electric resistance array is by programmable switch (by state latch and driving chip, miniature
Relay assembly forms) and cascade electric resistance array composition, whether the resistance that programmable switch controls different resistance values go here and there
Enter between input and output both ends.
As shown in figure 4, the restructural capacitor array include m × n relay, m × n capacitor and state latch with
Controller, if the end C+ of the restructural capacitor array is divided into main line, the 1st tunnel is through single-pole double throw in capacitor C1n and relay K1n
The common terminal of switch connects, in relay K1n other two terminals of single-pole double-throw switch (SPDT) respectively with it is described restructural
The end C+ of capacitor array and the connection of the end C-；2nd tunnel through in capacitor C1n-1 and relay K1n-1 single-pole double-throw switch (SPDT) it is public
Terminals connection, in relay K1n-1 other two terminals of single-pole double-throw switch (SPDT) respectively with the restructural capacitor array
The end C+ and the end C- connection；3rd tunnel connects through the common terminal of single-pole double-throw switch (SPDT) in capacitor C1n-2 and relay K1n-2
Connect, in relay K1n-2 other two terminals of single-pole double-throw switch (SPDT) respectively with the end C+ of the restructural capacitor array with
And the connection of the end C-, and so on, the n-th tunnel is connect through capacitor C11 with the common terminal of single-pole double-throw switch (SPDT) in relay K11,
In relay K11 other two terminals of single-pole double-throw switch (SPDT) respectively with the end C+ and the end C- of the restructural capacitor array
Connection；
(n+1)th tunnel is connect through capacitor C2n with the common terminal of single-pole double-throw switch (SPDT) in relay K2n, hilted broadsword in relay K2n
Other two terminals of commutator are connect with the end C+ of the restructural capacitor array and the end C- respectively；N-th+2 road warp
Capacitor C2n-1 is connect with the common terminal of single-pole double-throw switch (SPDT) in relay K2n-1, and single-pole double throw is opened in relay K2n-1
Other two terminals closed are connect with the end C+ of the restructural capacitor array and the end C- respectively；N-th+3 tunnel is through capacitor
C2n-2 is connect with the common terminal of single-pole double-throw switch (SPDT) in relay K2n-2, single-pole double-throw switch (SPDT) in relay K2n-2
Other two terminals is connect with the end C+ of the restructural capacitor array and the end C- respectively, and so on, the n-th+n Lu Jing electricity
Hold C21 to connect with the common terminal of single-pole double-throw switch (SPDT) in relay K21, single-pole double-throw switch (SPDT) is in addition in relay K21
Two terminals are connect with the end C+ of the restructural capacitor array and the end C- respectively；
And so on ,+1 tunnel (m × n-1) connects through the common terminal of single-pole double-throw switch (SPDT) in capacitor Cmn and relay Kmn
Connect, in relay Kmn other two terminals of single-pole double-throw switch (SPDT) respectively with the end C+ of the restructural capacitor array and
The connection of the end C-；Public wiring of+2 tunnel (m × n-1) through single-pole double-throw switch (SPDT) in capacitor C m × n-1 and relay K m × n-1
End connection, in relay K m × n-1 other two terminals of single-pole double-throw switch (SPDT) respectively with the restructural capacitor array
The end C+ and the connection of the end C-；Public affairs of+2 tunnel (m × n-1) through single-pole double-throw switch (SPDT) in capacitor Cm × n-2 and relay Km × n-2
Terminals connection altogether, in relay Km × n-2 other two terminals of single-pole double-throw switch (SPDT) respectively with the restructural capacitor
The end C+ of array and the connection of the end C-, and so on, the road m × n is through single-pole double-throw switch (SPDT) in capacitor Cm1 and relay Km1
Common terminal connection, in relay Km1 other two terminals of single-pole double-throw switch (SPDT) respectively with the restructural capacitor battle array
The end C+ of column and the connection of the end C-；The control terminal and state latch of the relay and the control signal output of controller connect
It connects.
The excitatory synapse circuit includes micro controller module, artificial circuit part and restructural electric resistance array, institute
The input terminal for stating artificial circuit part is the signal input part of the excitatory synapse circuit, the output of the artificial circuit part
End is connect with the end R+ of the restructural electric resistance array, and the end R- of the restructural electric resistance array is the excitatory synapse circuit
Signal output end；
The artificial circuit part is used to export forward current, the control of the restructural electric resistance array to restructural electric resistance array
End is connect with the output end of the control output end of the micro controller module and hyper parameter controller；The resistance of restructural electric resistance array
The signal that value can be input to restructural electric resistance array control terminal according to hyper parameter controller is determining, can also be true by microcontroller
It is fixed；
A variety of non-supervisory synaptic plasticity algorithms can be loaded in the microcontroller, and microcontroller is input to according to hyper parameter controller
The signal of device, microcontroller can choose specific performed non-supervisory synaptic plasticity algorithm, according to microcontroller acquisition
Sudden-touch circuit outputs and inputs the situation of change of terminal potential, the non-supervisory synaptic plasticity algorithm run according to microcontroller,
The resistance value for changing restructural electric resistance array reaches imictron synaptic plasticity, realizes the energy of neural network unsupervised learning
Power；
As shown in fig. 6, the analog circuit of the excitatory synapse circuit include including diode D1, resistance R5-R8, capacitor C2,
Diode Q4-Q5 and voltage source V1, the input terminal of the excitatory synapse analog module and the diode D1 are just
The cathode connection of pole connection, the diode D1 is connect with one end of resistance R5, and the other end of the resistance R5 is divided into three tunnels, the
It is grounded all the way through capacitor C2, the second tunnel is grounded through resistance R6, and third road is connect with the base stage of triode Q4, the transmitting of triode Q4
Pole is grounded through resistance R7, and the collector of triode Q4 is connect with the base stage of triode Q5, and the emitter of triode Q5 is through resistance R8
It is connect with the anode of voltage source V1, the cathode ground connection of the voltage source V1, the collector of triode Q5 and the excitatory synapse
The output end of analog module connects；
Excitatory synapse analog circuit input terminal receives neuron output action pulse signal, is limited by diode D1 through resistance R5
Stream charges to capacitor C2, while the slow leakage current of resistance R6, the charging rate of capacitor C2 is controlled, when capacitor C2 both end voltage is big
When the cut-in voltage of triode Q4, triode Q4 and triode Q5 conducting, excitatory synapse analog circuit output end are exported just
To electric current.
The inhibitory synapse circuit includes micro controller module, artificial circuit part and restructural electric resistance array, institute
The input terminal for stating artificial circuit part is the signal input part of the inhibitory synapse circuit, the output of the artificial circuit part
End is connect with the end R+ of the restructural electric resistance array, and the end R- of the restructural electric resistance array is the inhibitory synapse circuit
Signal output end；
The artificial circuit part is used to export negative current, the control of the restructural electric resistance array to restructural electric resistance array
End is connect with the output end of the control output end of the micro controller module and hyper parameter controller；The resistance of restructural electric resistance array
The signal that value can be input to restructural electric resistance array control terminal according to hyper parameter controller is determining, can also be true by microcontroller
It is fixed；
A variety of non-supervisory synaptic plasticity algorithms can be loaded in the microcontroller, and microcontroller is input to according to hyper parameter controller
The signal of device, microcontroller can choose specific performed non-supervisory synaptic plasticity algorithm, according to microcontroller acquisition
Sudden-touch circuit outputs and inputs the situation of change of terminal potential, the non-supervisory synaptic plasticity algorithm run according to microcontroller,
The resistance value for changing restructural electric resistance array reaches imictron synaptic plasticity, realizes the energy of neural network unsupervised learning
Power；
As shown in fig. 7, the artificial circuit part of the inhibitory synapse circuit include resistance R9-R10, capacitor C3, diode D2,
Triode Q6 and voltage source V2, the input terminal of the inhibitory synapse analog module are connect with the anode of diode D2,
The cathode of the diode D2 is connect with one end of resistance R9, and the other end of the resistance R9 is divided into three tunnels, and the first via is through capacitor
C3 ground connection, the second tunnel are grounded through resistance R10, and third road is connect with the base stage of triode Q6, the emitter and voltage of triode Q6
The cathode of source V2 connects, the plus earth of voltage source V2, the collector of triode Q6 and the inhibitory synapse circuit module
Output end connection；
The input terminal of the inhibitory synapse analog module receives neuron output action pulse signal, passes through diode D2
It charges through resistance R9 current limliting to capacitor C3, while the slow leakage current of resistance R10, controls the charging rate of capacitor C3, work as capacitor
When C3 both end voltage is greater than the cut-in voltage of triode Q6, triode Q6 conducting, electric current is by the inhibitory synapse analog circuit
Output end flow into triode Q6 collector, i.e., inhibitory synapse analog circuit output end export negative current.
S2A decoding layer is encoded by the restructural interference networks of input and output (as shown in Figure 9) with SNN computation layer and A2S defeated
Enter layer connection, the quantity M+N of S2A decoding unit is equal to the quantity M of quantity N and the A2S coding unit of neuron in SNN computation layer
The sum of.S2A decoding unit (as shown in Figure 10) is formed by excitatory synapse circuit and a capacitor and a resistor coupled in parallel, excited
Property Sudden-touch circuit by pulse signal be converted to analog current charging signals give shunt capacitance charge, discrete sequences of pulsed signals is just
It is converted to the continuous analog signal of capacitor both end voltage, resistance in parallel realizes discharging function, keeps charge in capacitor slow
Release, the characteristic of oblivion of analog neuron information processing.The analog signal of S2A decoding layer output passes to on-line study and output is controlled
Device processed.Wherein, the restructural electric resistance array of S2A decoding unit is by on-line study and output controller controls, the size pair of resistance value
Ying Yuqi receive pulse train in extract information number.The restructural interference networks of input and output are by state latch and controller control
Multiple selector processed determines that state latch and controller realize control according to hyper parameter controller input control multiple selector
A2S coding input layer unit and SNN processed calculate the connection relationship between layer unit and S2A decoding layer unit.A2S coding unit
It can export to any one or multiple SNN calculating layer unit, but can only export to a S2A decoding unit.SNN computation layer
Unit and S2A decoding unit are one-to-one relationships.
As shown in figure 8, the restructural electric resistance array includes m × n relay, m × n resistance and state latch and control
The end R+ of device processed, the restructural electric resistance array is connect with one end of resistance R1n, and the other end of resistance R1n is with resistance R1n-1's
One end connection, and so on, the other end of resistance R12 is connect with one end of resistance R11, the other end and resistance R21 of resistance R11
One end connection, the other end of resistance R21 connect with one end of resistance R22, and so on, the other end of resistance R2n-1
It is connect with one end of resistance R2n, and so on, one end of resistance Rm-1n is connect with one end of resistance Rm1, resistance Rm1's
The other end is connect with one end of resistance Rm2, and so on, the other end of resistance Rmn-1 is connect with one end of resistance Rmn, resistance
The end R- of the other end of Rmn and restructural electric resistance array；Corresponding one of each resistance is in parallel therewith in restructural electric resistance array
Relay, and the control terminal of the relay is connect with the control signal output of state latch and controller, according to hyper parameter
Controller input, state latch realizes the control to relay with controller, to be connected into restructural electric resistance array to control
The quantity of middle resistance finally realizes the adjustment of restructural electric resistance array resistance value.
On-line study and o controller to the output of S2A decoding layer sum up operation and with from A2S input layer
Supervisory signals carry out linear regression analysis, and the resistance value of restructural electric resistance array in S2A layers is adjusted according to error result, realize information
The optimization closed loop of output layer on-line study.After on-line study, it will no longer change S2A decoding layer internal resistance value, and be summed it up operation knot
Fruit exports as the signal of classification foundation or modeling and forecasting.
Hyper parameter controller determines the encryption algorithm that A2S coding input layer choosing is selected, the number of neuron circuit in SNN computation layer
Amount and membrane capacitance parameter, internetwork connection mode and synapse weight (the i.e. prominent electricity of excitability Sudden-touch circuit and inhibition between neuron
The resistance value of restructural electric resistance array in road), the connection topology of input and output interference networks.The selection gist LSM's of above-mentioned parameter
Mathematical theory determine, will not change in a certain subtask, thus when reducing on-line study required optimization parameter amount, mention
Computationally efficient.And for different tasks, it can be from new adjustment above-mentioned parameter to adapt to different mission requirements, to improve
The flexibility of system.
To sum up, the Digital Analog Hybrid Circuits system combines the fast and digital circuit counting flexibility of analog circuit calculating speed
High advantage makes it have computational efficiency height, the characteristics of strong real-time and on-line study, to push ANN technology in Internet of Things
Application in application scenarios.The Digital Analog Hybrid Circuits system realizes the electricity of neuron and nerve synapse in biological nervous system
The calculating of physiological models, this multidimensional nonlinear kinetics equation can expend very high calculating money when solving using digital display circuit
Source, and computational efficiency is greatly reduced with the promotion of time precision, so that it is difficult to ensure the real-time of output result, simulation electricity
Road, which calculates, can be effectively solved the above problem.The Digital Analog Hybrid Circuits system combines restructural number using embedded controller
Word circuit system control network hyper parameter, if input coding, network topology, network weight, input and output connection, thus make be
The flexibility of system is substantially improved, and can use a variety of different application scenarios and task feature, and can appoint in difference
Flexibly switch between business.The Digital Analog Hybrid Circuits system combines restructural digital circuitry to realize using embedded controller
On-line study function has the parameter amount of study optimization small, as a result the characteristics of fast convergence rate.
Claims (9)
1. a kind of impulsive neural networks Digital Analog Hybrid Circuits system for realizing liquid condition machine, it is characterised in that: encoded including A2S
Input layer, SNN computation layer, S2A decoding layer, on-line study and o controller and hyper parameter controller, the A2S coding input
The continuous multichannel analog signals of sensor acquisition are converted into the discrete multichannel pulse with spatial-temporal distribution characteristic by layer to be believed
Number, it is input to SNN computation layer, wherein each coding unit of A2S coding input layer corresponds to analog signal all the way, element number
M is identical as the quantity of analog signal array, and the encryption algorithm that analog signal is converted into pulse signal is selected by hyper parameter controller；
SNN computation layer includes N number of spiking neuron circuit, is connected by interference networks restructural between neuron, A2S coding input
It is connected between layer and SNN computation layer by the restructural interference networks of input and output, A2S coding unit both can be with whole pulse minds
Through first circuit connection, can also be connected with partial nerve member, specific connection type is determined by hyper parameter controller；
S2A decoding layer is connect by the restructural interference networks of input and output with SNN computation layer and A2S coding input layer, S2A decoding
Layer includes M+N S2A decoding unit；
On-line study and o controller to the output of S2A decoding layer sum up operation and with the supervision from A2S input layer
Signal carries out linear regression analysis, and the resistance value of restructural electric resistance array in S2A decoding layer is adjusted according to error result, realizes information
The optimization closed loop of output layer on-line study；After on-line study, it will no longer change S2A decoding layer internal resistance value, and be summed it up operation knot
Fruit exports as the signal of classification foundation or modeling and forecasting；
Hyper parameter controller be used to determine the encryption algorithm that A2S coding input layer choosing selects, in SNN computation layer neuron circuit number
It is restructural in internetwork connection mode, excitatory synapse circuit and inhibitory synapse circuit between amount and membrane capacitance parameter, neuron
The resistance value of electric resistance array and the connection topology of input and output interference networks.
2. realizing the impulsive neural networks Digital Analog Hybrid Circuits system of liquid condition machine as described in claim 1, feature exists
In: the A2S coding input unit includes the digital circuits section of micro controller module and the analog circuit of pulse generation part
Part, micro controller module input the A2S encryption algorithm of selection for the original analog from sensor according to hyper parameter controller
Signal coding believes markup information corresponding to each original signal or training at discrete pulse sequence, micro controller module
Number supervisory signals of the output to on-line study and o controller, as on-line study；
The analog module includes capacitor Cm, bleeder resistance RL, sodium channel module and potassium channel module, the capacitor Cm
Respectively with the bleeder resistance RL, sodium channel module and potassium channel wired in parallel, the capacitor CmOne end receives internal current source
Output electric current Iout, and membrane voltage V is exported in this one endmem, as the output for corresponding to coding unit in A2S coding input layer,
Capacitor CmThe other end ground connection；
Capacitor CmReceive the current signal I of internal current source outputout, current signal IoutFirst to the capacitor CmIt charges,
As the capacitor CmVoltage when being greater than the cut-in voltage of triode Q1 in the sodium channel module, the sodium channel module is to can
Capacitor CmAnd the potassium channel module charges, and opens for simulating biological neuron sodium-ion channel, when the potassium is logical
When the voltage of capacitor C1 is greater than the cut-in voltage of triode Q3 in road module, the capacitor CmAgain by the potassium channel module into
Row electric discharge, simulation biological neuron potassium-channel are opened, and the sodium channel current that then sodium channel module generates stops to capacitor
CmIt charges, sodium-ion channel is closed on imictron cell membrane；Finally, capacitor CmAlso stop putting by the potassium channel module
Electricity, the current signal I of internal current source outputoutContinue to capacitor CmCharging, makes capacitor CmThe voltage at both ends is restored to tranquillization electricity
Position, completes the generation process an of action pulse；
The sodium channel module includes triode Q1, triode Q2, resistance R2, resistance R4 and voltage source VNa, the triode
The base stage of Q1 is divided into two-way, the first via and the capacitor CmOne end connection, the second tunnel are connect with triode Q2 collector, and described three
The emitter of pole pipe Q1 is grounded through resistance R4, and the collector of the triode Q1 is connect with the base stage of the triode Q2, described
The emitter of triode Q2 is through resistance R2 and the voltage source VNaAnode connection, the voltage source VNaCathode ground connection, it is described
One of one terminals of the extremely described sodium channel module of the current collection of triode Q2, the terminals and the potassium channel module connects
Line end connection；
The potassium channel module includes triode Q3, resistance Rr, resistance R3, capacitor C1 and voltage source VK, the one of the resistance R3
End is divided into three tunnels, and the first via is connect with a terminals of the sodium channel module, the second tunnel and resistance RrOne end connection, the
Three tunnels are connect with the output end of the neuron circuit, and the collector of the other end of the resistance R3 and the triode Q3 connect
It connects, the emitter of the triode Q3 and the voltage source VKCathode connection, the voltage source VKPlus earth, described three
The base stage of pole pipe Q3 is divided into two-way, the first via and resistance RrThe other end connection, the second tunnel is grounded through capacitor C1；
Capacitor CmReceive external input current signal Iout, the membrane voltage V at both endsmemConstantly increase；As membrane voltage VmemGreater than three
When the cut-in voltage of pole pipe Q1, triode Q1, triode Q2 are opened, and triode Q2 collector exports sodium channel current, to can weigh
Structure capacitor array carries out quick charge, film potential VmemIt increases rapidly, which opens for simulating biological neuron sodium-ion channel
It opens, the rapid interior process flowed of neuronal cell film extracellular sodium ion；
Sodium channel current is to capacitor CmWhile quick charge, slowly charge to the capacitor C1 in potassium channel module, capacitor C1 voltage
VrSlowly rise, as the VrWhen value is greater than the cut-in voltage of triode Q3, triode Q3 is opened, capacitor CmPass through resistance R3, three
The electric discharge of pole pipe Q3 branch, triode Q3 emitter export potassium channel current, membrane voltage VmemDecline rapidly, the process is for simulating
Biological neuron potassium-channel is opened, and potassium ion outflows rapidly and makes membrane voltage V in neuronal cell filmmemDecline rapidly
Process, wherein VkFor the voltage source for simulating potassium channel balanced voltage, the voltage source value is bigger, after Q3 is opened, the output of Q3 emitter
Potassium channel current it is bigger, membrane voltage VmemThe speed of decline is also bigger；
As membrane voltage VmemWhen dropping to less than the cut-in voltage of triode Q1, triode Q1 cut-off, the sodium that sodium channel module generates
Channel current stops to capacitor CmCharging, the process which closes for sodium-ion channel on imictron cell membrane；
As membrane voltage VmemWhen less than resting potential, if triode Q3 is still opened, membrane voltage VmemContinue to decline, works as membrane voltage
VmemWhen dropping to less than the cut-in voltage of triode Q3, triode Q3 cut-off, the capacitor CmStop by potassium channel module into
Row electric discharge, external input current signal IoutContinue to capacitor CmCharging, to make membrane voltage VmemIt is restored to resting potential, thus
Complete the generation process an of action pulse.
3. realizing the impulsive neural networks Digital Analog Hybrid Circuits system of liquid condition machine as described in claim 1, feature exists
In:
The spiking neuron circuit includes digital circuit blocks and analog module, and the analog module includes can
Reconstruct capacitor array, bleeder resistance, sodium channel module and potassium channel module, the capacitance of the restructural capacitor array are controlled by
The digital circuit blocks, digital circuit blocks are used to run internal plasticity rule, according to the membrane voltage V of monitoringmemValue with can
Plasticity rule, changes the capacitance size of restructural capacitor array, to realize the electric discharge behavior for adjusting neuron circuit, imitates life
The excitatoty adjusting of object neuron；The input terminal of power supply is connect with the end C+ of the restructural capacitor array, the restructural electricity
The end C+ for holding array connects the output end of the neuron circuit, the end the C- ground connection of the restructural capacitor array；It is described to weigh
Structure capacitor array and bleeder resistance RLParallel connection, the sodium channel module and the potassium channel module and the bleeder resistance RLIt is in parallel；
The spiking neuron circuit can determine the capacitance of its restructural capacitor array according to the input of hyper parameter controller, from
And reach the non-thread sex differernce simulated different membrane capacitances and show pulse signal integration；The restructural electricity of the neuron circuit
Holding array can also be determined by micro controller module, the different inside plasticity algorithm of operation in micro controller module, according to adopting
The situation of change of the film potential of collection and the capacitance for changing membrane capacitance reach plasticity inside imictron, realize neuron letter
Cease the dynamic equilibrium of processing；Restructural capacitor array includes the capacitor array of programmable switch and parallel form, programmable switch
Whether the capacitor for controlling different capacitances is incorporated between input and output both ends；The input and output side of each spiking neuron circuit
All restructural internet between access neuron, one row of left end of internet meet the output end of each neuron, one row of bottom end
The input terminal of each neuron is connect, the output end of any one neuron can be connected to any one neuron by Sudden-touch circuit
Input terminal, make SNN computation layer realize arbitrary network topology；
The restructural capacitor array may also comprise m × n relay, m × n capacitor and state latch and controller, institute
If the end C+ for stating restructural capacitor array is divided into main line, public affairs of the 1st tunnel through single-pole double-throw switch (SPDT) in capacitor C1n and relay K1n
Terminals connection altogether, in relay K1n other two terminals of single-pole double-throw switch (SPDT) respectively with the restructural capacitor array
The end C+ and the end C- connection；2nd tunnel connects through the common terminal of single-pole double-throw switch (SPDT) in capacitor C1n-1 and relay K1n-1
Connect, in relay K1n-1 other two terminals of single-pole double-throw switch (SPDT) respectively with the end C+ of the restructural capacitor array with
And the end C- connection；3rd tunnel is connect through capacitor C1n-2 with the common terminal of single-pole double-throw switch (SPDT) in relay K1n-2, relay
Other two terminals of single-pole double-throw switch (SPDT) connect with the end C+ of the restructural capacitor array and the end C- respectively in K1n-2
It connects, and so on, the n-th tunnel is connect through capacitor C11 with the common terminal of single-pole double-throw switch (SPDT) in relay K11, relay K11
Other two terminals of middle single-pole double-throw switch (SPDT) are connect with the end C+ of the restructural capacitor array and the end C- respectively；
(n+1)th tunnel is connect through capacitor C2n with the common terminal of single-pole double-throw switch (SPDT) in relay K2n, hilted broadsword in relay K2n
Other two terminals of commutator are connect with the end C+ of the restructural capacitor array and the end C- respectively；N-th+2 road warp
Capacitor C2n-1 is connect with the common terminal of single-pole double-throw switch (SPDT) in relay K2n-1, and single-pole double throw is opened in relay K2n-1
Other two terminals closed are connect with the end C+ of the restructural capacitor array and the end C- respectively；N-th+3 tunnel is through capacitor
C2n-2 is connect with the common terminal of single-pole double-throw switch (SPDT) in relay K2n-2, single-pole double-throw switch (SPDT) in relay K2n-2
Other two terminals is connect with the end C+ of the restructural capacitor array and the end C- respectively, and so on, the n-th+n Lu Jing electricity
Hold C21 to connect with the common terminal of single-pole double-throw switch (SPDT) in relay K21, single-pole double-throw switch (SPDT) is in addition in relay K21
Two terminals are connect with the end C+ of the restructural capacitor array and the end C- respectively；
And so on ,+1 tunnel (m × n-1) connects through the common terminal of single-pole double-throw switch (SPDT) in capacitor Cmn and relay Kmn
Connect, in relay Kmn other two terminals of single-pole double-throw switch (SPDT) respectively with the end C+ of the restructural capacitor array and
The connection of the end C-；Public wiring of+2 tunnel (m × n-1) through single-pole double-throw switch (SPDT) in capacitor C m × n-1 and relay K m × n-1
End connection, in relay K m × n-1 other two terminals of single-pole double-throw switch (SPDT) respectively with the restructural capacitor array
The end C+ and the connection of the end C-；Public affairs of+2 tunnel (m × n-1) through single-pole double-throw switch (SPDT) in capacitor Cm × n-2 and relay Km × n-2
Terminals connection altogether, in relay Km × n-2 other two terminals of single-pole double-throw switch (SPDT) respectively with the restructural capacitor
The end C+ of array and the connection of the end C-, and so on, the road m × n is through single-pole double-throw switch (SPDT) in capacitor Cm1 and relay Km1
Common terminal connection, in relay Km1 other two terminals of single-pole double-throw switch (SPDT) respectively with the restructural capacitor battle array
The end C+ of column and the connection of the end C-；The control terminal of all relays and the control signal output of state latch and controller
Connection.
4. realizing the impulsive neural networks Digital Analog Hybrid Circuits system of liquid condition machine as claimed in claim 3, feature exists
In:
Restructural internet includes that a excitatory synapse circuit of N × (N-1), N × (N-1) a inhibition are prominent between the neuron
Electric shock road, N number of relay switch, state latch and controller module, N number of left side port and N number of downside port；N number of left-hand end
Mouthful be connected respectively with the output end of N number of spiking neuron circuit, N number of downside port respectively with N number of spiking neuron
The input terminal of circuit is connected；Status register connects the control terminal of relay switch with the output end of controller module, according to super
Parameter controller output signal, status register and controller module can control the state of relay switch；According to relay
The state of switch, it may be determined that the connection type between spiking neuron circuit described in any two: pass through excitatory synapse circuit
Connection by inhibitory synapse circuit connection or makes two spiking neuron circuits not establish connection.
5. realizing the impulsive neural networks Digital Analog Hybrid Circuits system of liquid condition machine as claimed in claim 4, feature exists
In:
The excitatory synapse circuit includes micro controller module, artificial circuit part and restructural electric resistance array, the mould
The input terminal of quasi- circuit part is the signal input part of the excitatory synapse circuit, the output end of the artificial circuit part with
The end R+ of the restructural electric resistance array connects, and the end R- of the restructural electric resistance array is the letter of the excitatory synapse circuit
Number output end；
The artificial circuit part is used to export forward current, the control of the restructural electric resistance array to restructural electric resistance array
End is connect with the output end of the control output end of the micro controller module and hyper parameter controller；The resistance of restructural electric resistance array
The signal that value can be input to restructural electric resistance array control terminal according to hyper parameter controller is determining, can also be true by microcontroller
It is fixed；
A variety of non-supervisory synaptic plasticity algorithms can be loaded in the microcontroller, and microcontroller is input to according to hyper parameter controller
The signal of device, microcontroller can choose specific performed non-supervisory synaptic plasticity algorithm, according to microcontroller acquisition
Sudden-touch circuit outputs and inputs the situation of change of terminal potential, the non-supervisory synaptic plasticity algorithm run according to microcontroller,
The resistance value for changing restructural electric resistance array reaches imictron synaptic plasticity, realizes the energy of neural network unsupervised learning
Power；
The artificial circuit part includes diode D1, resistance R5-R8, capacitor C2, diode Q4-Q5 and voltage source V1, institute
The input terminal for stating excitatory synapse artificial circuit part is connect with the anode of the diode D1, and the cathode of the diode D1 connects
It connects and is connect with one end of resistance R5, the other end of the resistance R5 is divided into three tunnels, and the first via is grounded through capacitor C2, the second Lu Jing electricity
R6 ground connection is hindered, third road is connect with the base stage of triode Q4, and the emitter of triode Q4 is grounded through resistance R7, the collection of triode Q4
Electrode is connect with the base stage of triode Q5, and the emitter of triode Q5 is connect through resistance R8 with the anode of voltage source V1, the electricity
The cathode of potential source V1 is grounded, and the collector of triode Q5 is connect with the output end of the excitatory synapse artificial circuit part；
Excitatory synapse analog circuit input terminal receives neuron output action pulse signal, is limited by diode D1 through resistance R5
Stream charges to capacitor C2, while the slow leakage current of resistance R6, the charging rate of capacitor C2 is controlled, when capacitor C2 both end voltage is big
When the cut-in voltage of triode Q4, triode Q4 and triode Q5 conducting, excitatory synapse analog circuit output end are exported just
To electric current.
6. realizing the impulsive neural networks Digital Analog Hybrid Circuits system of liquid condition machine as claimed in claim 4, feature exists
In:
The inhibitory synapse circuit includes micro controller module, artificial circuit part and restructural electric resistance array, the mould
The input terminal of quasi- circuit part is the signal input part of the inhibitory synapse circuit, the output end of the artificial circuit part with
The end R+ of the restructural electric resistance array connects, and the end R- of the restructural electric resistance array is the letter of the inhibitory synapse circuit
Number output end；
The artificial circuit part is used to export negative current, the control of the restructural electric resistance array to restructural electric resistance array
End is connect with the output end of the control output end of the micro controller module and hyper parameter controller；The resistance of restructural electric resistance array
The signal that value can be input to restructural electric resistance array control terminal according to hyper parameter controller is determining, can also be true by microcontroller
It is fixed；
A variety of non-supervisory synaptic plasticity algorithms can be loaded in the microcontroller, and microcontroller is input to according to hyper parameter controller
The signal of device, microcontroller can choose specific performed non-supervisory synaptic plasticity algorithm, according to microcontroller acquisition
Sudden-touch circuit outputs and inputs the situation of change of terminal potential, the non-supervisory synaptic plasticity algorithm run according to microcontroller,
The resistance value for changing restructural electric resistance array reaches imictron synaptic plasticity, realizes the energy of neural network unsupervised learning
Power；
The artificial circuit part includes resistance R9-R10, capacitor C3, diode D2, triode Q6 and voltage source V2, described
The input terminal of inhibitory synapse artificial circuit part is connect with the anode of diode D2, the cathode and resistance R9 of the diode D2
One end connection, the other end of the resistance R9 is divided into three tunnels, and the first via is grounded through capacitor C3, and the second tunnel is grounded through resistance R10,
Third road is connect with the base stage of triode Q6, and the emitter of triode Q6 is connect with the cathode of voltage source V2, and voltage source V2 is just
Pole ground connection, the collector of triode Q6 are connect with the output end of artificial circuit part in the inhibitory synapse circuit；
The artificial circuit part input terminal receives neuron output action pulse signal, by diode D2 through resistance R9 current limliting
It charges to capacitor C3, while the slow leakage current of resistance R10, the charging rate of capacitor C3 is controlled, when capacitor C3 both end voltage is big
When the cut-in voltage of triode Q6, triode Q6 conducting, electric current flows into three by the inhibitory synapse analog circuit output end
The collector of pole pipe Q6, i.e. inhibitory synapse analog circuit output end export negative current.
7. such as the impulsive neural networks Digital Analog Hybrid Circuits system described in claim 5 or 6 for realizing liquid condition machine, feature
It is:
The restructural electric resistance array includes m × n relay, m × n resistance and state latch and controller, described to weigh
The end R+ of structure electric resistance array is connect with one end of resistance R1n, and the other end of resistance R1n is connect with one end of resistance R1n-1, successively
Analogize, the other end of resistance R12 is connect with one end of resistance R11, and the other end of resistance R11 is connect with one end of resistance R21, electricity
The other end of resistance R21 is connect with one end of resistance R22, and so on, the other end and resistance R2n of resistance R2n-1
One end connection, and so on, one end of resistance Rm-1n is connect with one end of resistance Rm1, the other end and resistance of resistance Rm1
One end of Rm2 connects, and so on, the other end of resistance Rmn-1 is connect with one end of resistance Rmn, the other end of resistance Rmn and
The end R- of restructural electric resistance array；Corresponding one of each resistance relay in parallel therewith in restructural electric resistance array, and it is described
The control terminal of relay is connect with the control signal output of state latch and controller, is inputted according to hyper parameter controller, shape
State latches with controller and realizes the control to relay, thus to control the quantity for being connected into resistance in restructural electric resistance array,
Finally realize the adjustment of restructural electric resistance array resistance value.
8. realizing the impulsive neural networks Digital Analog Hybrid Circuits system of liquid condition machine as described in claim 1, feature exists
In:
The S2A decoding unit is formed by excitatory synapse circuit and a capacitor and a resistor coupled in parallel, excitatory synapse
Pulse signal is converted to analog current charging signals and charged to shunt capacitance by circuit, and discrete sequences of pulsed signals is converted into electricity
Hold the continuous analog signal of both end voltage, resistance in parallel realizes discharging function, makes charge slow release in capacitor, simulation mind
Characteristic of oblivion through information processing；The analog signal of S2A decoding layer output passes to on-line study and o controller；Wherein,
The restructural electric resistance array of S2A decoding unit is by on-line study and output controller controls, and the size of resistance value is corresponding to its reception
In pulse train extract information number.
9. realizing the impulsive neural networks Digital Analog Hybrid Circuits system of liquid condition machine as described in claim 1, feature exists
In:
The restructural interference networks of input and output are to control multiple selector with controller by state latch to determine, status lock
It deposits with controller according to hyper parameter controller input control multiple selector, realizes that control A2S coding input layer unit and SNN are counted
Calculate the connection relationship between layer unit and S2A decoding layer unit；A2S coding unit can export to any one or it is multiple
SNN calculates layer unit；But it can only export to a S2A decoding unit；SNN calculates layer unit and S2A decoding unit is an a pair
It should be related to.
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