CN115577758A - Multi-mode generalization and differentiation association memory neural network circuit based on memristor - Google Patents

Multi-mode generalization and differentiation association memory neural network circuit based on memristor Download PDF

Info

Publication number
CN115577758A
CN115577758A CN202210259727.6A CN202210259727A CN115577758A CN 115577758 A CN115577758 A CN 115577758A CN 202210259727 A CN202210259727 A CN 202210259727A CN 115577758 A CN115577758 A CN 115577758A
Authority
CN
China
Prior art keywords
operational amplifier
resistor
output end
gate
input end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210259727.6A
Other languages
Chinese (zh)
Inventor
孙军伟
雷霆
王洋洋
杨建领
燕奕霖
马永幸
余培照
王英聪
黄春
王延峰
凌丹
王妍
刘娜
方洁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhengzhou University of Light Industry
Original Assignee
Zhengzhou University of Light Industry
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhengzhou University of Light Industry filed Critical Zhengzhou University of Light Industry
Priority to CN202210259727.6A priority Critical patent/CN115577758A/en
Publication of CN115577758A publication Critical patent/CN115577758A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/061—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using biological neurons, e.g. biological neurons connected to an integrated circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Theoretical Computer Science (AREA)
  • Neurology (AREA)
  • Molecular Biology (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • General Health & Medical Sciences (AREA)
  • Computational Linguistics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)

Abstract

The invention provides a multi-mode generalization and differentiation associative memory neural network circuit based on memristance, which comprises input signal terminals N1-N7, a synaptic neuron module I-synaptic neuron module VII, an inhibition module I-inhibition module V and an output signal terminal, wherein the synaptic neuron module I-synaptic neuron module VII is connected with the output signal terminal through an OR gate. The method realizes the secondary differentiation process of the copllov associative memory through the associative learning and forgetting process among a plurality of prominent neuron modules, so that the associative memory is more in line with the actual condition of brain memory; the multiple generalization and differentiation of the coporov associative memory are realized, the more the generalization times, the less the learning cycle and the differentiation cycle, and the slower and gradually consolidated forgetting speed, and the long-term memory is possibly formed. The elimination inhibition and differentiation inhibition in forgetting are realized through the inhibition module, so that the associative memory is more consistent with the biological characteristics.

Description

Multi-mode generalization and differentiation association memory neural network circuit based on memristor
Technical Field
The invention relates to the technical field of neural network circuits, in particular to a multi-mode generalization and differentiation copuloff associative memory neural network circuit based on memristions.
Background
Memristors are a class of nonlinear circuit elements with resistive memory behavior, considered as the fourth basic circuit element in addition to resistance, capacitance, inductance. The memristor has a very potential application prospect in the aspects of nonvolatile storage, logic operation, artificial neural networks, chaotic secret communication and the like. The characteristics of memristors are very similar to synapses in biological nerves, and are important modules for simulating the behaviors of learning, memory and the like of organisms.
The physiologist, papuloff, discovered by salivary tests on dogs the conditioned reflex laws including the acquisition law, the extinction law, the generalization law and the differentiation law, wherein the acquisition law and the extinction law correspond to the learning and forgetting process in associative memory, and the learning and forgetting process between two neurons has been widely studied and applied. However, the acquisition rate, the resolution rate, and the generalization and differentiation rate of a plurality of neurons have been studied relatively rarely.
Disclosure of Invention
Aiming at the technical problem that the existing Barpurov associative memory theory cannot realize learning and forgetting among a plurality of neurons, the invention provides a multi-mode generalization and differentiation associative memory neural network circuit based on memory resistance, and the secondary differentiation process of the Barpurov associative memory is realized through the associative learning and forgetting process among a plurality of neurons; regression inhibition and differentiation inhibition in amnesia are achieved by the inhibition module.
In order to achieve the purpose, the technical scheme of the invention is realized as follows: a multi-mode generalization and differentiation associative memory neural network circuit based on memristors comprises input signal terminals N1-N7, a synaptic neuron module I-synaptic neuron module VII, an inhibition module I-inhibition module V and an output signal terminal, wherein the input signal terminal N1 is connected with the synaptic neuron module I; the input signal terminal N1 and the input signal terminal N2 are connected with a synaptic neuron module II through a logic circuit I; the input signal terminal N1, the input signal terminal N2 and the synaptic neuron module II are all connected with the inhibition module I through a logic circuit II, the inhibition module I is connected with the input signal terminal N3, and the inhibition module I and the input signal terminal N3 are all connected with the synaptic neuron module III through a logic circuit III; the input signal terminal N1 and the input signal terminal N4 are both connected with an inhibition module II, and the inhibition module II and the input signal terminal N4 are both connected with a synaptic neuron module IV through a logic circuit IV; the input signal end N1, the input signal end N2 and the synaptic neuron module II are all connected with an inhibition module III, and the inhibition module III and the input signal end N5 are all connected with the synaptic neuron module V through a logic circuit V; the input signal terminal N1, the input signal terminal N2 and the synaptic neuron module II are all connected with an inhibition module IV, and the inhibition module IV and the input signal terminal N6 are all connected with the synaptic neuron module VI through a logic circuit VI; the input signal end N1, the input signal end N2 and the synaptic neuron module II are all connected with an inhibition module V, and the inhibition module V and the input signal end N7 are connected with the synaptic neuron module VII through a logic circuit VII; and the synaptic neuron module I-synaptic neuron module VII is connected with an output signal end through an OR gate.
The synaptic neuron module I comprises a first proportional amplifier, and an input signal end N1 is connected with the first proportional amplifier; the first proportional amplifier is connected with the absolute value module ABS1, the output end of the absolute value module ABS1 is an output signal end OUT1, and the output signal end OUT1 is connected with an OR gate; the first proportional amplifier comprises a resistor R1, an operational amplifier OP1 and a resistor R2, an output signal end OUT1 is connected with the resistor R1, the resistor R1 is respectively connected with the resistor R2 and the inverting input end of the operational amplifier OP1, the resistor R2 and the output end of the operational amplifier OP1, the non-inverting input end of the operational amplifier OP1 is grounded, and the output end of the operational amplifier OP1 is connected with the input end of an absolute value module ABS 1.
The logic circuit I comprises a first voltage control unit, a second voltage control unit, an AND gate D1 and a voltage summation unit SUM1, an input signal end N1 and an input signal end N2 are both connected with the AND gate D1, the output end of the AND gate D1 is connected with the first voltage control unit, the input signal end N2 is connected with the second voltage control unit, the first voltage control unit and the second voltage control unit are respectively connected with two input ends of the voltage summation unit SUM1, and the output end of the voltage summation unit SUM1 is connected with a synaptic neuron module II; the first voltage control unit comprises a voltage control switch S1, the output end of the AND gate D1 is connected with the positive phase input end of the voltage control switch S1, a first contact of the voltage control switch S1 is respectively connected with the first input end of the voltage summation unit SUM1 and the resistor R3, a second contact of the voltage control switch S1 is connected with the positive electrode of the power supply V1, and the negative electrode of the power supply V1, the resistor R3 and the reverse phase input end of the voltage control switch S1 are all grounded; the second voltage control unit comprises a voltage control switch S2, a positive phase input end of the voltage control switch S2 is connected with an input signal end N2, a first contact of the voltage control switch S2 is respectively connected with a second input end of the voltage summation unit SUM1 and a resistor R4, a second contact of the voltage control switch S2 is connected with a positive electrode of the power supply V2, and a negative electrode of the power supply V2, the resistor R4 and an inverted phase input end of the voltage control switch S2 are all grounded.
The synaptic neuron module II comprises a second proportional amplifier, an absolute value module ABS2, a third proportional amplifier, a first comparator and a second comparator which are sequentially connected, wherein the input end of the second proportional amplifier is connected with a voltage summation unit SUM1 of the logic circuit I, and the output end of the second comparator is connected with an OR gate; the second proportional amplifier comprises a memristor M1, an operational amplifier OP2 and a resistor R5, wherein the positive end of the memristor M1 is connected with the output end of a voltage summing unit SUM1 of the logic circuit I, the negative end of the memristor M1 is respectively connected with the inverting input end of the operational amplifier OP2 and the resistor R5, the non-inverting input end of the operational amplifier OP2 is grounded, the resistor R5 is connected with the output end of the operational amplifier OP2, the output end of the operational amplifier OP2 is connected with the input end of an absolute value module ABS2, and the output end of the absolute value module ABS2 is connected with a third proportional amplifier; the third proportional amplifier comprises a resistor R6, an operational amplifier OP3 and a resistor R7, the output end of the absolute value module ABS2 is connected with the resistor R6, the resistor R6 is respectively connected with the resistor R7 and the inverting input end of the operational amplifier OP3, the resistor R7 is connected with the output end of the operational amplifier OP3, the non-inverting input end of the operational amplifier OP3 is grounded, and the output end of the operational amplifier OP3 is connected with the first comparator; the second comparator comprises an operational amplifier OP4, the inverting input end of the operational amplifier OP4 is connected with the output end of the operational amplifier OP3, the non-inverting input end of the operational amplifier OP4 is connected with the positive electrode of the power supply V3, the negative electrodes of the power supply V3 are grounded, and the output end of the operational amplifier OP4 is connected with the second comparator; the second comparator comprises an NMOS tube T1, the grid electrode of the NMOS tube T1 is connected with the output end of the operational amplifier OP4, the drain electrode of the NMOS tube T1 is connected with a resistor R8, the resistor R8 is connected with the positive electrode of a power supply V4, the source electrode of the NMOS tube T1 is connected with a resistor R9, the negative electrode of the power supply V4 and the resistor R9 are both grounded, the drain electrode of the NMOS tube T1 is an output signal end OUT II, and the output signal end OUT II is connected with an OR gate.
The logic circuit II comprises a third comparator, an AND gate D2 and a NOT gate D5, wherein the input end of the third comparator is connected with the output end of an absolute value module ABS2 of the synaptic neuron module II, the output end of the third comparator and the output end of an AND gate D1 of the logic circuit I are both connected with the input end of the AND gate D2, the output end of the AND gate D2 is connected with the input end of the NOT gate D5, and the output end of the NOT gate D5 is connected with the inhibition module I; the suppression module I comprises a fourth comparator, an AND gate D6, a third voltage control unit and a fourth proportional amplifier, the output end of the NOT gate D5 is connected with the input end of the fourth comparator, the output end of the fourth comparator and an input signal end N3 are both connected with the input end of the AND gate D6, the output end of the AND gate D6 is connected with the third voltage control unit, the third voltage control unit is connected with the fourth proportional amplifier, and the output end of the fourth proportional amplifier is connected with the logic circuit III; the logic circuit III comprises a first adder, a fifth proportional amplifier, a fourth voltage-controlled unit, a fifth voltage-controlled unit, a NOT gate D3 and an AND gate D4, an input signal end N3 is connected with the input end of the NAND gate D3, the output end of the NOT gate D3 and the output end of the AND gate D2 are connected with the input end of the AND gate D4, the output end of the AND gate D4 is connected with the fourth voltage-controlled unit, an input signal end N3 is connected with the fifth voltage-controlled unit, the output ends of the fourth voltage-controlled unit and the fifth voltage-controlled unit are connected with the first adder, the first adder is connected with the fifth proportional amplifier, and the fifth proportional amplifier is connected with a synaptic neuron module III; the synaptic neuron module III comprises a sixth proportional amplifier, an absolute value module ABS3, a seventh proportional amplifier, a fifth comparator and a sixth comparator which are sequentially connected, wherein the output end of the fifth proportional amplifier is connected with the input end of the sixth proportional amplifier, the output end of the sixth comparator is an output signal end OUT III, and the output signal end OUT III is connected with an OR gate.
The suppression module II comprises a seventh comparator, an AND gate D4, a sixth voltage control unit and an eighth proportional amplifier, the output end of a NAND gate D9 of the seventh comparator is connected, the input end of the NOT gate D9 is connected with an input end signal N1, the output end of the seventh comparator and an input signal end N4 are connected with the input end of the AND gate D4, the output end of the AND gate D4 is connected with the input end of the sixth voltage control unit, the output end of the sixth voltage control unit is connected with the input end of the eighth proportional amplifier, and the output end of the eighth proportional amplifier is connected with the logic circuit IV; the logic circuit IV comprises a second adder, a ninth proportional amplifier, a seventh voltage control unit, an eighth voltage control unit, a NOT gate D7 and an AND gate D8, an input signal end N4 is connected with the input end of the NAND gate D7, the output end of the NOT gate D7 and the output end of the AND gate D2 are connected with the input end of the AND gate D8, the output end of the AND gate D8 is connected with the seventh voltage control unit, an input signal end N4 is connected with the eighth voltage control unit, the output ends of the seventh voltage control unit and the eighth voltage control unit are connected with the second adder, the second adder is connected with the ninth proportional amplifier, and the ninth proportional amplifier is connected with a synaptic neuron module IV; the synaptic neuron module IV comprises a tenth proportional amplifier, an absolute value module ABS4, an eleventh proportional amplifier, a ninth comparator and a tenth comparator which are sequentially connected, wherein the output end of the ninth proportional amplifier is connected with the input end of the tenth proportional amplifier, the output end of the tenth comparator is an output signal end OUT IV, and the output signal end OUT IV is connected with an OR gate.
The third comparator comprises an operational amplifier OP5, the inverting input end of the operational amplifier OP5 is connected with the output end of the absolute value module ABS2, the non-inverting input end of the operational amplifier OP5 is grounded through a power supply V5, and the output end of the operational amplifier OP5 is connected with one input end of an AND gate D2D;
the fourth comparator comprises an NMOS tube T2 and a PMOS tube T3, the output end of the NOT gate D5 is connected with the grid electrode of the NMOS tube T2, the drain electrode of the NMOS tube T2 is connected with the positive electrode of a power supply V11 through a resistor R10, the source electrode of the NMOS tube T2 is connected with the positive electrode of a power supply V12, the negative electrodes of the power supply V11 and the power supply V12 are grounded, the drain electrode of the NMOS tube T2 is connected with the grid electrode of the PMOS tube T3, the drain electrode of the PMOS tube T3 is connected with the positive electrode of a power supply V13 through a resistor R11, the source electrode of the PMOS tube T3 is connected with the positive electrode of a power supply V14, and the negative electrodes of the power supply V13 and the power supply V14 are grounded; the drain electrode of the PMOS tube T3 is connected with one input end of the AND gate D6;
the third voltage control unit comprises a voltage control switch S5, the output end of the AND gate D6 is connected with the positive phase input end of the voltage control switch S5, the first contact of the voltage control switch S5 is respectively connected with the fourth proportional amplifier and the resistor R52, the second contact of the voltage control switch S5 is connected with the positive electrode of the power supply V15, and the negative electrode of the power supply V15, the resistor R52 and the reverse phase input end of the voltage control switch S5 are all grounded;
the fourth proportional amplifier comprises a memristor M3, an operational amplifier OP9 and a resistor R12, the positive end of the memristor M3 is connected with a first contact of the voltage-controlled switch S5, the negative end of the memristor M3 is respectively connected with the inverting input end of the operational amplifier OP9 and the resistor R12, the non-inverting input end of the operational amplifier OP9 is grounded, the resistor R12 is connected with the output end of the operational amplifier OP9, and the output end of the operational amplifier OP9 is connected with the first adder;
the first adder comprises a resistor R13, a resistor R14, a resistor R15 and an operational amplifier OP10, wherein the resistor R13 is connected with the output end of the operational amplifier OP9, the resistor R14 is respectively connected with a fourth voltage-controlled unit and a fifth voltage-controlled unit, the resistor R13, the resistor R14 and the resistor R15 are all connected with the positive input end of the operational amplifier OP10, the resistor R15 is connected with the output end of the operational amplifier OP10, the negative input end of the operational amplifier OP10 is grounded, and the output end of the operational amplifier OP10 is connected with a fifth proportional amplifier;
the fifth proportional amplifier comprises a resistor R16, an operational amplifier OP11 and a resistor R17, the output end of the operational amplifier OP10 is connected with the resistor R16, the resistor R16 is respectively connected with the resistor R17 and the inverting input end of the operational amplifier OP11, the resistor R17 is connected with the output end of the operational amplifier OP11, the non-inverting input end of the operational amplifier OP11 is grounded, and the output end of the operational amplifier OP11 is connected with the sixth proportional amplifier of the synaptic neuron module III;
the fourth voltage control unit comprises a voltage control switch S3, the output end of the AND gate D4 is connected with the positive phase input end of the voltage control switch S3, the first contact of the voltage control switch S3 is connected with the resistor R14, the second contact of the voltage control switch S3 is connected with the positive electrode of the power supply V9, and the negative electrode of the power supply V9 and the negative phase input end of the voltage control switch S3 are both grounded;
the fifth voltage control unit comprises a voltage control switch S4, an input signal end N3 is connected with a positive phase input end of the voltage control switch S4, a first contact of the voltage control switch S4 is connected with a resistor R14, a second contact of the voltage control switch S4 is connected with a positive electrode of a power supply V10, and a negative electrode of the power supply V10 and an inverted phase input end of the voltage control switch S4 are both grounded;
the sixth proportional amplifier comprises a memristor M2, an operational amplifier OP12 and a resistor R18, the positive end of the memristor M2 is connected with the output end of the operational amplifier OP11, the negative end of the memristor M2 is respectively connected with the inverting input end of the operational amplifier OP12 and the resistor R18, the non-inverting input end of the operational amplifier OP12 is grounded, the resistor R18 is connected with the output end of the operational amplifier OP12, and the output end of the operational amplifier OP12 is connected with an absolute value module ABS 3;
the seventh proportional amplifier comprises a resistor R19, an operational amplifier OP13 and a resistor R20, the output end of the absolute value module ABS3 is connected with the resistor R19, the resistor R19 is respectively connected with the resistor R20 and the inverting input end of the operational amplifier OP13, the resistor R20 is connected with the output end of the operational amplifier OP13, the non-inverting input end of the operational amplifier OP13 is grounded, and the output end of the operational amplifier OP13 is connected with a fifth comparator;
the fifth comparator comprises an operational amplifier OP14, the output end of the operational amplifier OP13 is connected with the inverting input end of the operational amplifier OP14, the non-inverting input end of the operational amplifier OP14 is grounded through a power supply V6, and the output end of the operational amplifier OP14 is connected with the sixth comparator;
the sixth comparator comprises an NMOS tube T4, the grid electrode of the NMOS tube T4 is connected with the output end of the operational amplifier OP14, the drain electrode of the NMOS tube T4 is connected with a resistor R21, the resistor R21 is connected with the positive electrode of a power supply V17, the source electrode of the NMOS tube T4 is connected with a resistor R22, the negative electrode of the power supply V17 and the resistor R22 are both grounded, the drain electrode of the NMOS tube T4 is an output signal end OUT III, and the output signal end OUT III is connected with an OR gate;
the seventh comparator comprises an NMOS tube T5 and a PMOS tube T6, the output end of the NOT gate D9 is connected with the grid electrode of the NMOS tube T5, the drain electrode of the NMOS tube T5 is connected with the positive electrode of a power supply V20 through a resistor R23, the source electrode of the NMOS tube T5 is connected with the positive electrode of the power supply V21, the negative electrodes of the power supply V20 and the power supply V21 are grounded, the drain electrode of the NMOS tube T5 is connected with the grid electrode of the PMOS tube T6, the drain electrode of the PMOS tube T6 is connected with the positive electrode of a power supply V22 through a resistor R24, the source electrode of the PMOS tube T6 is connected with the positive electrode of the power supply V23, and the negative electrodes of the power supply V22 and the power supply V23 are grounded; the drain electrode of the PMOS tube T6 is connected with one input end of the AND gate D4;
the sixth voltage control unit comprises a voltage control switch S8, the output end of the AND gate D16 is connected with the positive phase input end of the voltage control switch S8, the first contact of the voltage control switch S8 is respectively connected with the eighth proportional amplifier and the resistor R25, the second contact of the voltage control switch S8 is connected with the positive electrode of the power supply V24, and the negative electrode of the power supply V24, the resistor R25 and the inverting input end of the voltage control switch S8 are all grounded;
the eighth proportional amplifier comprises a memristor M5, an operational amplifier OP15 and a resistor R26, the positive end of the memristor M5 is connected with the first contact of the voltage-controlled switch S8, the negative end of the memristor M5 is respectively connected with the inverting input end of the operational amplifier OP15 and the resistor R26, the non-inverting input end of the operational amplifier OP15 is grounded, the resistor R26 is connected with the output end of the operational amplifier OP15, and the output end of the operational amplifier OP15 is connected with the second adder;
the second adder comprises a resistor R27, a resistor R28, a resistor 29 and an operational amplifier OP16, the resistor R27 is connected with the output end of the operational amplifier OP15, the resistor R28 is respectively connected with the seventh voltage-controlled unit and the eighth voltage-controlled unit, the resistor R27, the resistor R28 and the resistor R295 are all connected with the non-inverting input end of the operational amplifier OP10, the resistor R27 is connected with the output end of the operational amplifier OP16, the inverting input end of the operational amplifier OP16 is grounded, and the output end of the operational amplifier OP16 is connected with the ninth proportional amplifier;
the ninth proportional amplifier comprises a resistor R30, an operational amplifier OP17 and a resistor R31, wherein the output end of the operational amplifier OP16 is connected with the resistor R30, the resistor R30 is respectively connected with the resistor R31 and the inverting input end of the operational amplifier OP17, the resistor R31 is connected with the output end of the operational amplifier OP17, the non-inverting input end of the operational amplifier OP17 is grounded, and the output end of the operational amplifier OP17 is connected with the tenth proportional amplifier of the synaptic neuron module IV;
the seventh voltage control unit comprises a voltage control switch S6, the output end of the AND gate D8 is connected with the positive phase input end of the voltage control switch S6, the first contact of the voltage control switch S6 is connected with the resistor R28, the second contact of the voltage control switch S3 is connected with the positive electrode of the power supply V18, and the negative electrode of the power supply V18 and the negative phase input end of the voltage control switch S6 are both grounded;
the eighth voltage control unit comprises a voltage control switch S7, an input signal end N4 is connected with a positive phase input end of the voltage control switch S7, a first contact of the voltage control switch S7 is connected with a resistor R28, a second contact of the voltage control switch S7 is connected with a positive electrode of a power supply V19, and a negative electrode of the power supply V19 and a negative phase input end of the voltage control switch S7 are both grounded;
the tenth proportional amplifier comprises a memristor M4, an operational amplifier OP18 and a resistor R32, wherein the positive end of the memristor M2 is connected with the output end of the operational amplifier OP17, the negative end of the memristor M2 is respectively connected with the inverting input end of the operational amplifier OP12 and the resistor R32, the non-inverting input end of the operational amplifier OP18 is grounded, the resistor R32 is connected with the output end of the operational amplifier OP18, and the output end of the operational amplifier OP18 is connected with an absolute value module ABS 4;
the eleventh proportional amplifier comprises a resistor R33, an operational amplifier OP19 and a resistor R34, the output end of the absolute value module ABS4 is connected with the resistor R33, the resistor R33 is respectively connected with the resistor R34 and the inverting input end of the operational amplifier OP19, the resistor R34 is connected with the output end of the operational amplifier OP19, the non-inverting input end of the operational amplifier OP19 is grounded, and the output end of the operational amplifier OP13 is connected with a fifth comparator;
the ninth comparator comprises an operational amplifier OP20, the output end of the operational amplifier OP19 is connected with the inverting input end of the operational amplifier OP20, the non-inverting input end of the operational amplifier OP20 is grounded through a power supply V25, and the output end of the operational amplifier OP20 is connected with the tenth comparator;
the tenth comparator comprises an NMOS tube T7, the grid electrode of the NMOS tube T7 is connected with the output end of the operational amplifier OP20, the drain electrode of the NMOS tube T7 is connected with a resistor R35, the resistor R35 is connected with the positive electrode of a power supply V26, the source electrode of the NMOS tube T7 is connected with a resistor R36, the negative electrode of the power supply V26 and the resistor R36 are both grounded, the drain electrode of the NMOS tube T7 is an output signal end OUT IV, and the output signal end OUT IV is connected with an OR gate.
The logic circuit V comprises a tenth comparator, a NOT gate D10, an AND gate D11, a voltage summation unit SUM2 and a voltage summation unit SUM3, wherein the input end of the tenth comparator is connected with the output end of an absolute value module ABS2 of a synaptic neuron module II, the output end of the tenth comparator is connected with one input end of the AND gate D11, and the other input end of the AND gate D11 is connected with the output end of an AND gate D1 of the logic circuit I; the input signal end N5 is connected with the input end of a NAND gate D10, the output ends of the NAND gate D10 and the AND gate D11 are both connected with the input end of a voltage summation unit SUM2, the output end of the AND gate D11 is connected with an inhibition module III, the output ends of the inhibition module III and the voltage summation unit SUM2 are both connected with the input end of a voltage summation unit SUM3, the output end of the voltage summation unit SUM3 is connected with the input end of a synaptic neuron module V, the output end of the synaptic neuron module V is an output signal end OUT V, and the output signal end OUT V is connected with an OR gate;
the suppression module III comprises a ninth voltage control unit, a twelfth proportional amplifier and an absolute value module ABS5 which are sequentially connected, wherein the input end of the ninth voltage control unit is connected with the output end of the AND gate D11, and the output end of the absolute value module ABS5 is connected with one input end of the voltage summation unit SUM 3;
the salient neuron module V comprises a thirteenth proportional amplifier, an absolute value module ABS6, an eleventh comparator and a twelfth comparator which are sequentially connected, the output end of the voltage summation unit SUM3 is connected with the input end of the thirteenth proportional amplifier, and the output end of the twelfth comparator is an output signal end OUT V;
the logic circuit VI comprises a thirteenth comparator, a not gate D12, an AND gate D13, a voltage summation unit SUM4 and a voltage summation unit SUM5, wherein the input end of the thirteenth comparator is connected with the output end of the absolute value module ABS2 of the synaptic neuron module II, the output end of the thirteenth comparator is connected with one input end of the AND gate D13, and the other input end of the AND gate D13 is connected with the output end of the AND gate D1 of the logic circuit I; the input signal end N6 is connected with the input end of the NAND gate D12, the output ends of the NOT gate D12 and the AND gate D13 are both connected with the input end of the voltage summation unit SUM4, the output end of the AND gate D13 is connected with the suppression module IV, the output ends of the suppression module IV and the voltage summation unit SUM4 are both connected with the input end of the voltage summation unit SUM5, the output end of the voltage summation unit SUM5 is connected with the input end of the synaptic neuron module VI, the output end of the synaptic neuron module VI is an output signal end OUT VI, and the output signal end OUT VI is connected with an OR gate;
the suppression module IV comprises a tenth voltage control unit, a fourteenth proportional amplifier and an absolute value module ABS7, which are connected in sequence, wherein an input end of the tenth voltage control unit is connected with an output end of the and gate D13, and an output end of the absolute value module ABS7 is connected with one input end of the voltage summation unit SUM 5;
the salient neuron module VI comprises a fifteenth proportional amplifier, an absolute value module ABS8, a fourteenth comparator and a fifteenth comparator which are sequentially connected, the output end of the voltage summation unit SUM5 is connected with the input end of the fifteenth proportional amplifier, and the output end of the fifteenth comparator is an output signal end OUT VI;
the logic circuit VII comprises a sixteenth comparator, a not gate D14, an AND gate D15, a voltage summation unit SUM6 and a voltage summation unit SUM7, wherein the input end of the sixteenth comparator is connected with the output end of the absolute value module ABS2 of the synaptic neuron module II, the output end of the sixteenth comparator is connected with one input end of the AND gate D15, and the other input end of the AND gate D15 is connected with the output end of the AND gate D1 of the logic circuit I; the input signal end N7 is connected with the input end of a NAND gate D14, the output ends of the NAND gate D14 and the AND gate D15 are both connected with the input end of a voltage summation unit SUM6, the output end of the AND gate D15 is connected with an inhibition module V, the output ends of the inhibition module V and the voltage summation unit SUM4 are both connected with the input end of the voltage summation unit SUM7, the output end of the voltage summation unit SUM7 is connected with the input end of a synaptic neuron module VII, the output end of the synaptic neuron module VII is an output signal end OUT VII, and the output signal end OUT VII is connected with an OR gate;
the suppression module V comprises an eleventh voltage control unit, a sixteenth proportional amplifier and an absolute value module ABS9 which are sequentially connected, wherein the input end of the eleventh voltage control unit is connected with the output end of the AND gate D15, and the output end of the absolute value module ABS9 is connected with one input end of a voltage summation unit SUM 7;
the protruding neuron module VII comprises a seventeenth proportional amplifier, an absolute value module ABS10, a seventeenth comparator and an eighteenth comparator which are sequentially connected, the output end of the voltage summing unit SUM7 is connected with the input end of the seventeenth proportional amplifier, and the output end of the eighteenth comparator is an output signal end OUT VII.
The tenth comparator comprises an operational amplifier OP6, wherein the inverting input end of the operational amplifier OP6 is connected with the absolute value module ABS2, the non-inverting input end of the operational amplifier OP6 is connected with the positive electrode of the power supply V6, the negative electrode of the power supply V5 is grounded, and the output end of the operational amplifier OP6 is connected with one input end of the AND gate D11;
the ninth voltage control unit comprises a voltage control switch S9, the output end of the AND gate D11 is connected with the positive phase input end of the voltage control switch S9, the first contact of the voltage control switch S9 is respectively connected with the twelfth proportional amplifier and the resistor R37, the second contact of the voltage control switch S9 is connected with the positive electrode of the power supply V27, and the negative electrode of the power supply V27, the resistor R37 and the reverse phase input end of the voltage control switch S9 are all grounded;
the twelfth proportional amplifier comprises a memristor M7, an operational amplifier OP21 and a resistor R38, the positive end of the memristor M7 is connected with the first contact of the voltage-controlled switch S9, the negative end of the memristor M7 is respectively connected with the inverting input end of the operational amplifier OP21 and the resistor R38, the non-inverting input end of the operational amplifier OP21 is grounded, the resistor R38 is connected with the output end of the operational amplifier OP21, and the output end of the operational amplifier OP21 is connected with the absolute value module ABS 5;
the thirteenth proportional amplifier comprises a memristor M6, an operational amplifier OP22 and a resistor R39, wherein the positive end of the memristor M6 is connected with the output end of the voltage summing unit SUM3, the negative end of the memristor M6 is respectively connected with the inverting input end of the operational amplifier OP22 and the resistor R39, the non-inverting input end of the operational amplifier OP22 is grounded, the resistor R39 is connected with the output end of the operational amplifier OP22, and the output end of the operational amplifier OP22 is connected with the input end of the absolute value module ABS 6;
the eleventh comparator comprises an operational amplifier OP23, the inverting input end of the operational amplifier OP23 is connected with the output end of the absolute value module ABS6, the non-inverting input end of the operational amplifier OP23 is grounded through a power supply V28, and the output end of the operational amplifier OP23 is connected with the twelfth comparator;
the twelfth comparator comprises an NMOS tube T8, the grid electrode of the NMOS tube T8 is connected with the output end of the operational amplifier OP23, the drain electrode of the NMOS tube T8 is connected with a resistor R40, the resistor R40 is connected with the anode of a power supply V29, the source electrode of the NMOS tube T8 is connected with a resistor R41, the cathode of the power supply V29 and the resistor R41 are both grounded, the drain electrode of the NMOS tube T8 is an output signal end OUT V, and the output signal end OUT V is connected with an OR gate;
the thirteenth comparator comprises an operational amplifier OP7, the inverting input end of the operational amplifier OP7 is connected with the output end of the absolute value module ABS2, the non-inverting input end of the operational amplifier OP7 is grounded through a power supply V7, and the output end of the operational amplifier OP7 is connected with an AND gate D13;
the tenth voltage control unit comprises a voltage control switch S10, the output end of the AND gate D13 is connected with the positive phase input end of the voltage control switch S10, the first contact of the voltage control switch S10 is respectively connected with the fourteenth proportional amplifier and the resistor R42, the second contact of the voltage control switch S10 is connected with the positive electrode of the power supply V30, and the negative electrode of the power supply V30, the resistor R42 and the reverse phase input end of the voltage control switch S10 are all grounded;
the fourteenth proportional amplifier comprises a memristor M9, an operational amplifier OP24 and a resistor R43, wherein the positive end of the memristor M9 is connected with a first contact of the voltage-controlled switch S9, the negative end of the memristor M9 is respectively connected with the inverting input end of the operational amplifier OP24 and the resistor R43, the non-inverting input end of the operational amplifier OP24 is grounded, the resistor R43 is connected with the output end of the operational amplifier OP24, and the output end of the operational amplifier OP24 is connected with the absolute value module ABS 7;
the fifteenth proportional amplifier comprises a memristor M8, an operational amplifier OP25 and a resistor R44, wherein the positive end of the memristor M8 is connected with the output end of the voltage summing unit SUM5, the negative end of the memristor M8 is respectively connected with the inverting input end of the operational amplifier OP25 and the resistor R44, the non-inverting input end of the operational amplifier OP25 is grounded, the resistor R44 is connected with the output end of the operational amplifier OP25, and the output end of the operational amplifier OP25 is connected with the input end of the absolute value module ABS 8;
the fourteenth comparator comprises an operational amplifier OP26, wherein the inverting input end of the operational amplifier OP26 is connected with the output end of the absolute value module ABS8, the non-inverting input end of the operational amplifier OP26 is grounded through a power supply V31, and the output end of the operational amplifier OP26 is connected with the fifteenth comparator;
the fifteenth comparator comprises an NMOS tube T9, the grid electrode of the NMOS tube T9 is connected with the output end of the operational amplifier OP26, the drain electrode of the NMOS tube T9 is connected with a resistor R45, the resistor R45 is connected with the positive electrode of a power supply V32, the source electrode of the NMOS tube T9 is connected with a resistor R46, the negative electrode of the power supply V32 and the resistor R46 are both grounded, the drain electrode of the NMOS tube T9 is an output signal end OUT VI, and the output signal end OUT VI is connected with an OR gate;
the sixteenth comparator comprises an operational amplifier OP8, wherein the inverting input end of the operational amplifier OP8 is connected with the output end of the absolute value module ABS2, the non-inverting input end of the operational amplifier OP8 is grounded through a power supply V8, and the output end of the operational amplifier OP6 is connected with an AND gate D13;
the eleventh voltage-controlled unit comprises a voltage-controlled switch S11, the output end of the AND gate D15 is connected with the positive-phase input end of the voltage-controlled switch S10, the first contact of the voltage-controlled switch S10 is respectively connected with the twelfth proportional amplifier and the resistor R47, the second contact of the voltage-controlled switch S10 is connected with the positive electrode of the power supply V33, and the negative electrode of the power supply V33, the resistor R47 and the reverse-phase input end of the voltage-controlled switch S10 are all grounded;
the sixteenth proportional amplifier comprises a memristor M11, an operational amplifier OP27 and a resistor R48, wherein the positive end of the memristor M11 is connected with a first contact of the voltage-controlled switch S11, the negative end of the memristor M11 is respectively connected with the inverting input end of the operational amplifier OP27 and the resistor R48, the non-inverting input end of the operational amplifier OP27 is grounded, the resistor R48 is connected with the output end of the operational amplifier OP27, and the output end of the operational amplifier OP27 is connected with the absolute value module ABS 7;
the seventeenth proportional amplifier comprises a memristor M10, an operational amplifier OP28 and a resistor R49, wherein the positive end of the memristor M10 is connected with the output end of the voltage summing unit SUM7, the negative end of the memristor M10 is respectively connected with the inverting input end of the operational amplifier OP28 and the resistor R49, the non-inverting input end of the operational amplifier OP29 is grounded, the resistor R49 is connected with the output end of the operational amplifier OP28, and the output end of the operational amplifier OP28 is connected with the input end of the absolute value module ABS 10;
the seventeenth comparator comprises an operational amplifier OP29, wherein the inverting input end of the operational amplifier OP29 is connected with the output end of the absolute value module ABS10, the non-inverting input end of the operational amplifier OP29 is grounded through a power supply V34, and the output end of the operational amplifier OP29 is connected with the eighteenth comparator;
the eighteenth comparator comprises an NMOS tube T10, the grid electrode of the NMOS tube T10 is connected with the output end of the operational amplifier OP29, the drain electrode of the NMOS tube T10 is connected with a resistor R50, the resistor R50 is connected with the positive electrode of a power supply V35, the source electrode of the NMOS tube T10 is connected with a resistor R51, the negative electrode of the power supply V35 and the resistor R51 are both grounded, the drain electrode of the NMOS tube T10 is an output signal end OUT VII, and the output signal end OUT is connected with an OR gate.
Compared with the prior art, the invention has the following beneficial effects:
1) Through the associative learning and forgetting process among a plurality of prominent neuron modules, the process of secondary differentiation of the Brapurov associative memory is realized: similar ringtones can be generalized, the ringtones with different attributes are subjected to primary differentiation, and the ringtones with the same attributes but different degree ranges are subjected to secondary differentiation, so that the associative memory is more in line with the actual condition of brain memory, and reference can be provided for more intelligent brain-like nerves.
2) According to the nonvolatile property and the threshold characteristic of the memristor, the multiple generalization and differentiation of the Brapurlous associative memory are realized, the more generalization times, the less learning period and the less differentiation period, and the slower forgetting speed, the gradual consolidation and the possibility of forming long-term memory.
3) The elimination inhibition and differentiation inhibition in forgetting are realized through the inhibition module, so that the associative memory is more consistent with the biological characteristics.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of the present invention.
Fig. 2 is a graph of simulation results of learning and forgetting of the present invention.
FIG. 3 is a graph of voltage simulation results of learning and generalization among multiple neurons according to the present invention.
FIG. 4 is a graph showing the results of a simulation of primary and secondary differentiation between a plurality of neurons according to the invention.
FIG. 5 is a graph showing simulation results of multiple generalization and differentiation according to the present invention, wherein (a) is a graph showing simulation results of the first generalization and differentiation, (b) is a graph showing simulation results of the second generalization and differentiation, and (c) is a graph showing simulation results of the third generalization and differentiation.
FIG. 6 is a graph showing the results of the simulation of the inhibition of differentiation by the inhibition voltage according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
As shown in figure 1, the multi-mode generalization and differentiation associative memory neural network circuit based on the memristor comprises input signal terminals N1-N7, a synaptic neuron module I-synaptic neuron module VII, an inhibition module I-inhibition module V and an output signal terminal, wherein the synaptic neuron module transmits signals of input neurons to output neurons, and the inhibition module eliminates misjudgments caused by similar ringtones. The input signal terminals N1-N7 are defined as seven anterior neurons, with anterior neuron N1 corresponding to unconditional reflex signals (food signals) in pavlov associative memory, anterior neurons N2-N7 corresponding to conditional reflex signals, anterior neuron N2 being a 500Hz ring signal, N3 being a 800Hz ring signal, N4 being a 400Hz ring signal, N5 being a 500Hz buzzer signal, N6 being a 800Hz buzzer signal, and N7 being a 400Hz buzzer signal. In the specific implementation, the amplitude of the electric bell input signal is 5V, and the amplitude of the buzzer input signal is 2.5V. The output signal terminal OUT is a signal sent by the posterior neuron after receiving the stimulation, and is expressed as saliva secretion in the Brapurov associative memory.
The input signal terminal N1 is connected with a synaptic neuron module I, and the synaptic neuron module I transmits a food input signal to an output neuron; the input signal terminal N1 and the input signal terminal N2 are connected with a synaptic neuron module II through a logic circuit I; the logic circuit I ensures that the input signal terminals N1 and N2 can be conducted only by inputting signals at the same time, and the synaptic neuron module II transmits a 500Hz electric bell input signal to the input neuron. The input signal terminal N1, the input signal terminal N2 and the synaptic neuron module II are all connected with the inhibition module I through the logic circuit II, the inhibition module I is connected with the input signal terminal N3, the logic circuit II ensures that the inhibition module can be conducted when the input signal terminals N1 and N2 are input simultaneously, and the inhibition module I inhibits misjudgment generated by 800Hz electric bell. The inhibition module I and the input signal end N3 are both connected with a synaptic neuron module III through a logic circuit III; the logic circuit III ensures that the input signal terminal N3 is generalized when the input signal terminals N1 and N2 exist simultaneously, and the synaptic neuron module III transmits an 800Hz electric bell input signal to the input neuron. The input signal terminal N1 and the input signal terminal N4 are both connected with an inhibition module II, and the inhibition module II and the input signal terminal N4 are both connected with a synaptic neuron module IV through a logic circuit IV; the inhibition module II is used for inhibiting misjudgment generated by 400Hz electric bell, the logic circuit IV is used for ensuring that the circuit can be conducted when the input signal ends N1 and N2 are input simultaneously, and the synaptic neuron module IV is used for transmitting the 400Hz electric bell input signal to the input neuron. The input signal end N1, the input signal end N2 and the synaptic neuron module II are all connected with the inhibition module III, and the inhibition module III and the input signal end N5 are all connected with the synaptic neuron module V through the logic circuit V; the inhibition module III is used for inhibiting misjudgment generated by the 500Hz buzzer, the logic circuit V is used for transmitting input signals of the inhibition module III and the input signal end N5 to the output neuron, and the synaptic neuron module V is used for transmitting the input signals of the 500Hz buzzer to the input neuron. The input signal terminal N1, the input signal terminal N2 and the synaptic neuron module II are all connected with an inhibition module IV, and the inhibition module IV and the input signal terminal N6 are all connected with the synaptic neuron module VI through a logic circuit VI; the inhibition module IV is used for inhibiting misjudgment generated by the 800Hz buzzer, the logic circuit VI is used for transmitting input signals of the inhibition module IV and an input signal terminal N6 to the output neuron, and the synaptic neuron module VI is used for transmitting the input signals of the 800Hz buzzer to the input neuron. The input signal end N1, the input signal end N2 and the synaptic neuron module II are all connected with an inhibition module V, and the inhibition module V and the input signal end N7 are connected with the synaptic neuron module VII through a logic circuit VII; the suppression module V is used for suppressing misjudgment generated by the 400Hz buzzer, the input signal end N7 is used for transmitting the input signal of the 400Hz buzzer to the input neuron, and the logic circuit VII is used for transmitting the input signals of the suppression module IV and the input signal end N6 to the output neuron. And the synaptic neuron module I-synaptic neuron module VII is connected with an output signal end through an OR gate.
As shown in fig. 1, the synaptic neuron module i comprises a first proportional amplifier, and an input signal terminal N1 is connected with the first proportional amplifier; the first proportional amplifier is connected with the absolute value module ABS1, the output end of the absolute value module ABS1 is an output signal end OUT1, and the output signal end OUT1 is connected with an OR gate; the first proportional amplifier comprises a resistor R1, an operational amplifier OP1 and a resistor R2, an output signal end OUT1 is connected with one end of the resistor R1, the other end of the resistor R1 is respectively connected with one end of the resistor R2 and the inverting input end of the operational amplifier OP1, the other end of the resistor R2 is connected with the output end of the operational amplifier OP1, the non-inverting input end of the operational amplifier OP1 is grounded, and the output end of the operational amplifier OP1 is connected with the input end of an absolute value module ABS 1. The output end of the absolute value module ABS1 is connected with the output signal end OUTI. The first proportional amplifier performs a proportional operation, the absolute value block ABS1 modulo the output value of the operational amplifier OP1, and the output signal terminal OUT1 outputs a 2.8v pulse signal.
The logic circuit I comprises a first voltage control unit, a second voltage control unit, an AND gate D1 and a voltage summation unit SUM1, an input signal end N1 and an input signal end N2 are both connected with the AND gate D1, the output end of the AND gate D1 is connected with the first voltage control unit, the input signal end N2 is connected with the second voltage control unit, the first voltage control unit and the second voltage control unit are respectively connected with two input ends of the voltage summation unit SUM1, and the output end of the voltage summation unit SUM1 is connected with a synaptic neuron module II. The first voltage control unit comprises a voltage control switch S1, the output end of the AND gate D1 is connected with the positive phase input end of the voltage control switch S1, a first contact of the voltage control switch S1 is respectively connected with the first input end of the voltage summation unit SUM1 and the resistor R3, a second contact of the voltage control switch S1 is connected with the positive electrode of the power supply V1, and the negative electrode of the power supply V1, the resistor R3 and the reverse phase input end of the voltage control switch S1 are all grounded; the voltage-controlled switch S1 can be conducted only when the voltage exceeds the threshold value of the voltage-controlled switch S1, the voltage of V1 is output by the first contact, and the voltage of V1 is input by the second contact. The second voltage control unit comprises a voltage control switch S2, a positive phase input end of the voltage control switch S2 is connected with an input signal end N2, a first contact of the voltage control switch S2 is respectively connected with a second input end of the voltage summation unit SUM1, and a resistor R4, a second contact of the voltage control switch S2 is connected with a positive electrode of the power supply V2, and a negative electrode of the power supply V2, the resistor R4 and an inverted phase input end of the voltage control switch S2 are all grounded.
And the synaptic neuron module II comprises a second proportional amplifier, an absolute value module ABS2, a third proportional amplifier, a first comparator and a second comparator which are sequentially connected, wherein the input end of the second proportional amplifier is connected with a voltage summation unit SUM1 of the logic circuit I, and the output end of the second comparator is an output signal end OUTII and is connected with an OR gate. The second and third proportional amplifiers perform proportional operation, the first comparator compares the output voltage of the operational amplifier OP3 with the power supply V3, and if the output voltage is less than the power supply V3, a high level is output; otherwise, a low level is output. The second comparator outputs a power supply V4 if the output voltage of the operational amplifier OP4 is greater than the threshold voltage T1; otherwise, 0v is output.
The second proportional amplifier comprises a memristor M1, an operational amplifier OP2 and a resistor R5, wherein the positive end, namely a K pole, of the memristor M1 is connected with the output end of a voltage summing unit SUM1 of the logic circuit I, the negative end, namely an A pole, of the memristor M1 is respectively connected with the inverting input end of the operational amplifier OP2 and one end of the resistor R5, the non-inverting input end of the operational amplifier OP2 is grounded, the other end of the resistor R5 is connected with the output end of the operational amplifier OP2, the output end of the operational amplifier OP2 is connected with the input end of an absolute value module ABS2, and the output end of the absolute value module ABS2 is connected with a third proportional amplifier. The signal output by the output terminal of the absolute value block ABS2 is the absolute value of the output voltage of the operational amplifier OP 2. The third proportional amplifier comprises a resistor R6, an operational amplifier OP3 and a resistor R7, the output end of the absolute value module ABS2 is connected with one end of the resistor R6, the other end of the resistor R6 is respectively connected with one end of the resistor R7 and the inverting input end of the operational amplifier OP3, the other end of the resistor R7 is connected with the output end of the operational amplifier OP3, the non-inverting input end of the operational amplifier OP3 is grounded, and the output end of the operational amplifier OP3 is connected with the first comparator. The second comparator comprises an operational amplifier OP4, the inverting input end of the operational amplifier OP4 is connected with the output end of the operational amplifier OP3, the non-inverting input end of the operational amplifier OP4 is connected with the positive pole of the power supply V3, the negative poles of the power supply V3 are grounded, and the output end of the operational amplifier OP4 is connected with the second comparator. The second comparator comprises an NMOS tube T1, the grid electrode of the NMOS tube T1 is connected with the output end of the operational amplifier OP4, the drain electrode of the NMOS tube T1 is connected with one end of a resistor R8, the other end of the resistor R8 is connected with the anode of a power supply V4, the source electrode of the NMOS tube T1 is connected with one end of a resistor R9, the cathode of the power supply V4 and the other end of the resistor R9 are both grounded, the drain electrode of the NMOS tube T1 is an output signal end OUT II, and the output signal end OUT II is connected with an OR gate. The output signal terminal OUT II outputs a 2.8v pulse signal.
As shown in fig. 2, 0-5s are the testing stages, the food is unconditional stimulation, i.e. the input signal terminal N1 outputs a signal, and the output signal terminal OUT outputs a high level; the electric bell is a condition stimulus, namely an input signal end N2 outputs a signal, and an output signal end OUT outputs a low level. 5-24s is a learning stage, and the food and the 500Hz electric bell output signals simultaneously. 24-33s is a test stage, a 500Hz electric bell signal is separately applied, and the output signal terminal OUT outputs high level, which indicates that the dog receives the 500Hz electric bell signal and can also generate saliva. 33s-42s is the forgetting stage, and after a period of time, the dog receives a 500Hz electric bell signal and can not produce saliva.
The logic circuit II comprises a third comparator, an AND gate D2 and a NOT gate D5, wherein the input end of the third comparator is connected with the output end of an absolute value module ABS2 of the synaptic neuron module II, the third comparator is used for comparing the output voltage of the absolute value module ABS2 with a power supply V5, and if the output voltage is smaller than the power supply V5, a high level is output; otherwise, a low level is output. The output end of the third comparator and the output end of the AND gate D1 of the logic circuit I are connected with the input end of the AND gate D2, the output end of the AND gate D2 is connected with the input end of the NAND gate D5, and the output end of the NOT gate D5 is connected with the suppression module I. The suppression module I comprises a fourth comparator, an AND gate D6, a third voltage control unit and a fourth proportional amplifier, wherein the output end of the NOT gate D5 is connected with the input end of the fourth comparator, and the fourth comparator is used for outputting a low level if the output voltage of the NOT gate D5 is smaller than the threshold voltage T2; otherwise, a high level is output. The output end of the fourth comparator and the input signal end N3 are both connected with the input end of an AND gate D6, the output end of the AND gate D6 is connected with a third voltage control unit, the third voltage control unit is connected with a fourth proportional amplifier, and the output end of the fourth proportional amplifier is connected with a logic circuit III; the third voltage control unit can be conducted only when the threshold value of the third voltage control unit exceeds the threshold value of the third voltage control unit, and the fourth proportional amplifier is used for performing proportional operation. The logic circuit III comprises a first adder, a fifth proportional amplifier, a fourth voltage-controlled unit, a fifth voltage-controlled unit, a NOT gate D3 and an AND gate D4, an input signal end N3 is connected with the input end of the NOT gate D3, the output end of the NOT gate D3 and the output end of the AND gate D2 are connected with the input end of the AND gate D4, the output end of the AND gate D4 is connected with the fourth voltage-controlled unit, an input signal end N3 is connected with the fifth voltage-controlled unit, the output ends of the fourth voltage-controlled unit and the fifth voltage-controlled unit are connected with the first adder, the first adder is connected with the fifth proportional amplifier, and the fifth proportional amplifier is connected with a synaptic neuron module III; the first adder adds the voltage of the suppression module I and the voltages of the fourth voltage-controlled unit and the fifth voltage-controlled unit, the fifth proportional amplifier performs proportional operation, and the fourth voltage-controlled unit and the fifth voltage-controlled unit have the function of being conducted only when the voltage exceeds a threshold value of the fourth voltage-controlled unit and the fifth voltage-controlled unit. The synaptic neuron module III comprises a sixth proportional amplifier, an absolute value module ABS3, a seventh proportional amplifier, a fifth comparator and a sixth comparator which are sequentially connected, wherein the output end of the fifth proportional amplifier is connected with the input end of the sixth proportional amplifier, the output end of the sixth comparator is an output signal end OUT III, and the output signal end OUT III is connected with an OR gate. The sixth proportional amplifier and the seventh proportional amplifier perform proportional operation, the fifth comparator compares the output voltage of the operational amplifier OP13 with the power supply V16, and if the output voltage is less than the power supply V16, a high level is output; otherwise, a low level is output. The second comparator outputs the voltage of the power supply V17 if the output voltage of the operational amplifier OP14 is greater than the threshold voltage T4; otherwise, 0v is output. The output signal terminal OUT III outputs a 2.8v pulse signal.
The third comparator comprises an operational amplifier OP5, the inverting input end of the operational amplifier OP5 is connected with the output end of the absolute value module ABS2, the non-inverting input end of the operational amplifier OP5 is grounded through a power supply V5, and the output end of the operational amplifier OP5 is connected with one input end of an AND gate D2D.
The fourth comparator comprises an NMOS tube T2 and a PMOS tube T3, the output end of the NOT gate D5 is connected with the grid electrode of the NMOS tube T2, the drain electrode of the NMOS tube T2 is connected with the positive electrode of a power supply V11 through a resistor R10, the source electrode of the NMOS tube T2 is connected with the positive electrode of a power supply V12, the negative electrodes of the power supply V11 and the power supply V12 are grounded, the drain electrode of the NMOS tube T2 is connected with the grid electrode of the PMOS tube T3, the drain electrode of the PMOS tube T3 is connected with the positive electrode of a power supply V13 through a resistor R11, the source electrode of the PMOS tube T3 is connected with the positive electrode of a power supply V14, and the negative electrodes of the power supply V13 and the power supply V14 are grounded; the drain of the PMOS transistor T3 is connected to an input of the and gate D6.
The fourth voltage control unit comprises a voltage control switch S3, the output end of the AND gate D4 is connected with the positive phase input end of the voltage control switch S3, the first contact of the voltage control switch S3 is connected with one end of a resistor R14, the second contact of the voltage control switch S3 is connected with the positive electrode of a power supply V9, and the negative electrode of the power supply V9 and the inverting input end of the voltage control switch S3 are both grounded.
The fifth voltage control unit comprises a voltage control switch S4, an input signal end N3 is connected with a positive phase input end of the voltage control switch S4, a first contact of the voltage control switch S4 is connected with one end of a resistor R14, a second contact of the voltage control switch S4 is connected with a positive electrode of a power supply V10, and a negative electrode of the power supply V10 and an inverting input end of the voltage control switch S4 are grounded.
The third voltage control unit comprises a voltage control switch S5, the output end of the AND gate D6 is connected with the positive phase input end of the voltage control switch S5, the first contact of the voltage control switch S5 is respectively connected with the fourth proportional amplifier and the resistor R52, the second contact of the voltage control switch S5 is connected with the positive electrode of the power supply V15, and the negative electrode of the power supply V15, the resistor R52 and the reverse phase input end of the voltage control switch S5 are all grounded.
The fourth proportional amplifier comprises a memristor M3, an operational amplifier OP9 and a resistor R12, the positive end of the memristor M3 is connected with a first contact of the voltage-controlled switch S5, the negative end of the memristor M3 is respectively connected with the inverting input end of the operational amplifier OP9 and one end of the resistor R12, the non-inverting input end of the operational amplifier OP9 is grounded, the other end of the resistor R12 is connected with the output end of the operational amplifier OP9, and the output end of the operational amplifier OP9 is connected with the first adder.
The first adder comprises a resistor R13, a resistor R14, a resistor R15 and an operational amplifier OP10, one end of the resistor R13 is connected with the output end of the operational amplifier OP9, one end of the resistor R14 is respectively connected with a fourth voltage-controlled unit and a fifth voltage-controlled unit, the other end of the resistor R13, the other end of the resistor R14 and one end of the resistor R15 are all connected with the positive input end of the operational amplifier OP10, the other end of the resistor R15 is connected with the output end of the operational amplifier OP10, the inverting input end of the operational amplifier OP10 is grounded, and the output end of the operational amplifier OP10 is connected with a fifth proportional amplifier.
The fifth proportional amplifier comprises a resistor R16, an operational amplifier OP11 and a resistor R17, wherein the output end of the operational amplifier OP10 is connected with the resistor R16, the resistor R16 is respectively connected with the resistor R17 and the inverting input end of the operational amplifier OP11, the resistor R17 is connected with the output end of the operational amplifier OP11, the non-inverting input end of the operational amplifier OP11 is grounded, and the output end of the operational amplifier OP11 is connected with the sixth proportional amplifier of the synaptic neuron module III.
The sixth proportional amplifier comprises a memristor M2, an operational amplifier OP12 and a resistor R18, wherein the positive end of the memristor M2 is connected with the output end of the operational amplifier OP11, the negative end of the memristor M2 is respectively connected with the inverting input end of the operational amplifier OP12 and the resistor R18, the non-inverting input end of the operational amplifier OP12 is grounded, the resistor R18 is connected with the output end of the operational amplifier OP12, and the output end of the operational amplifier OP12 is connected with an absolute value module ABS 3.
The seventh proportional amplifier comprises a resistor R19, an operational amplifier OP13 and a resistor R20, the output end of the absolute value module ABS3 is connected with the resistor R19, the resistor R19 is respectively connected with the resistor R20 and the inverting input end of the operational amplifier OP13, the resistor R20 is connected with the output end of the operational amplifier OP13, the non-inverting input end of the operational amplifier OP13 is grounded, and the output end of the operational amplifier OP13 is connected with the fifth comparator.
The fifth comparator comprises an operational amplifier OP14, the output end of the operational amplifier OP13 is connected with the inverting input end of the operational amplifier OP14, the non-inverting input end of the operational amplifier OP14 is grounded through a power supply V6, and the output end of the operational amplifier OP14 is connected with the sixth comparator.
The sixth comparator comprises an NMOS tube T4, the grid electrode of the NMOS tube T4 is connected with the output end of the operational amplifier OP14, the drain electrode of the NMOS tube T4 is connected with a resistor R21, the resistor R21 is connected with the positive electrode of a power supply V17, the source electrode of the NMOS tube T4 is connected with a resistor R22, the negative electrode of the power supply V17 and the resistor R22 are both grounded, the drain electrode of the NMOS tube T4 is an output signal end OUT III, and the output signal end OUT III is connected with an OR gate.
The suppression module II comprises a seventh comparator, an AND gate D4, a sixth voltage control unit and an eighth proportional amplifier, wherein the output end of a NAND gate D9 of the seventh comparator is connected, the input end of the NOT gate D9 is connected with an input end signal N1, the output end of the seventh comparator and an input signal end N4 are connected with the input end of the AND gate D4, the output end of the AND gate D4 is connected with the input end of the sixth voltage control unit, the output end of the sixth voltage control unit is connected with the input end of the eighth proportional amplifier, and the output end of the eighth proportional amplifier is connected with the logic circuit IV; the seventh comparator and the sixth voltage control unit can be conducted only when the self threshold value is exceeded. The eighth proportional amplifier performs a proportional operation. The logic circuit IV comprises a second adder, a ninth proportional amplifier, a seventh voltage control unit, an eighth voltage control unit, a NOT gate D7 and an AND gate D8, an input signal end N4 is connected with the input end of the NAND gate D7, the output end of the NOT gate D7 and the output end of the AND gate D2 are connected with the input end of the AND gate D8, the output end of the AND gate D8 is connected with the seventh voltage control unit, an input signal end N4 is connected with the eighth voltage control unit, the output ends of the seventh voltage control unit and the eighth voltage control unit are connected with the second adder, the second adder is connected with the ninth proportional amplifier, and the ninth proportional amplifier is connected with a synaptic neuron module IV; the second adder adds the voltage of the suppression module II and the voltages of the seventh voltage control unit and the eighth voltage control unit, the ninth proportional amplifier performs proportional operation, and the seventh voltage control unit and the eighth voltage control unit can be conducted only when the voltage exceeds the threshold value of the seventh voltage control unit and the eighth voltage control unit. The synaptic neuron module IV comprises a tenth proportional amplifier, an absolute value module ABS4, an eleventh proportional amplifier, a ninth comparator and a tenth comparator which are sequentially connected, wherein the output end of the ninth proportional amplifier is connected with the input end of the tenth proportional amplifier, the output end of the tenth comparator is an output signal end OUT IV, and the output signal end OUT IV is connected with an OR gate. The tenth proportional amplifier and the eleventh proportional amplifier perform proportional operation, the ninth comparator compares the output voltage of the operational amplifier OP19 with the power supply V25, and outputs a high level if the output voltage is less than the power supply V25; otherwise, a low level is output. The tenth comparator outputs the voltage of the power supply V26 if the output voltage of the operational amplifier OP20 is greater than the threshold voltage T7; otherwise, 0v is output. The output signal terminal OUT IV outputs a 2.8v pulse signal.
The synaptic neuron module III and the synaptic neuron module IV have the same structure, wherein the synaptic neuron module III is an output signal of an 800Hz electric bell, and the synaptic neuron module IV is an output signal of a 400Hz electric bell.
The seventh comparator comprises an NMOS tube T5 and a PMOS tube T6, the output end of the NOT gate D9 is connected with the grid electrode of the NMOS tube T5, the drain electrode of the NMOS tube T5 is connected with the positive electrode of a power supply V20 through a resistor R23, the source electrode of the NMOS tube T5 is connected with the positive electrode of the power supply V21, the negative electrodes of the power supply V20 and the power supply V21 are grounded, the drain electrode of the NMOS tube T5 is connected with the grid electrode of the PMOS tube T6, the drain electrode of the PMOS tube T6 is connected with the positive electrode of the power supply V22 through a resistor R24, the source electrode of the PMOS tube T6 is connected with the positive electrode of the power supply V23, and the negative electrodes of the power supply V22 and the power supply V23 are grounded; the drain of the PMOS transistor T6 is connected to an input of the and gate D4.
The sixth voltage control unit comprises a voltage control switch S8, the output end of the AND gate D16 is connected with the positive phase input end of the voltage control switch S8, the first contact of the voltage control switch S8 is respectively connected with the eighth proportional amplifier and the resistor R25, the second contact of the voltage control switch S8 is connected with the positive electrode of the power supply V24, and the negative electrode of the power supply V24, the resistor R25 and the reverse phase input end of the voltage control switch S8 are all grounded.
The eighth proportional amplifier comprises a memristor M5, an operational amplifier OP15 and a resistor R26, the positive end of the memristor M5 is connected with a first contact of the voltage-controlled switch S8, the negative end of the memristor M5 is respectively connected with the inverting input end of the operational amplifier OP15 and the resistor R26, the non-inverting input end of the operational amplifier OP15 is grounded, the resistor R26 is connected with the output end of the operational amplifier OP15, and the output end of the operational amplifier OP15 is connected with the second adder.
The second adder includes a resistor R27, a resistor R28, a resistor 29, and an operational amplifier OP16, the resistor R27 is connected to the output terminal of the operational amplifier OP15, the resistor R28 is connected to the seventh voltage-controlled unit and the eighth voltage-controlled unit, the resistor R27, the resistor R28, and the resistor R295 are all connected to the non-inverting input terminal of the operational amplifier OP10, the resistor R27 is connected to the output terminal of the operational amplifier OP16, the inverting input terminal of the operational amplifier OP16 is grounded, and the output terminal of the operational amplifier OP16 is connected to the ninth proportional amplifier.
The ninth proportional amplifier comprises a resistor R30, an operational amplifier OP17 and a resistor R31, wherein the output end of the operational amplifier OP16 is connected with the resistor R30, the resistor R30 is respectively connected with the resistor R31 and the inverting input end of the operational amplifier OP17, the resistor R31 is connected with the output end of the operational amplifier OP17, the non-inverting input end of the operational amplifier OP17 is grounded, and the output end of the operational amplifier OP17 is connected with the tenth proportional amplifier of the synaptic neuron module IV.
The seventh voltage control unit comprises a voltage control switch S6, the output end of the AND gate D8 is connected with the positive phase input end of the voltage control switch S6, the first contact of the voltage control switch S6 is connected with the resistor R28, the second contact of the voltage control switch S3 is connected with the positive electrode of the power supply V18, and the negative electrode of the power supply V18 and the negative phase input end of the voltage control switch S6 are both grounded.
The eighth voltage control unit comprises a voltage control switch S7, an input signal end N4 is connected with a positive phase input end of the voltage control switch S7, a first contact of the voltage control switch S7 is connected with a resistor R28, a second contact of the voltage control switch S7 is connected with a positive electrode of a power supply V19, and a negative electrode of the power supply V19 and an inverted phase input end of the voltage control switch S7 are both grounded.
The tenth proportional amplifier comprises a memristor M4, an operational amplifier OP18 and a resistor R32, wherein the positive end of the memristor M2 is connected with the output end of the operational amplifier OP17, the negative end of the memristor M2 is respectively connected with the inverting input end of the operational amplifier OP12 and the resistor R32, the non-inverting input end of the operational amplifier OP18 is grounded, the resistor R32 is connected with the output end of the operational amplifier OP18, and the output end of the operational amplifier OP18 is connected with an absolute value module ABS 4.
The eleventh proportional amplifier comprises a resistor R33, an operational amplifier OP19 and a resistor R34, the output end of the absolute value module ABS4 is connected to the resistor R33, the resistor R33 is respectively connected to the resistor R34 and the inverting input end of the operational amplifier OP19, the resistor R34 is connected to the output end of the operational amplifier OP19, the non-inverting input end of the operational amplifier OP19 is grounded, and the output end of the operational amplifier OP13 is connected to the fifth comparator.
The ninth comparator comprises an operational amplifier OP20, an output end of the operational amplifier OP19 is connected with an inverting input end of the operational amplifier OP20, a non-inverting input end of the operational amplifier OP20 is grounded through a power supply V25, and an output end of the operational amplifier OP20 is connected with the tenth comparator.
The tenth comparator comprises an NMOS tube T7, a grid electrode of the NMOS tube T7 is connected with an output end of the operational amplifier OP20, a drain electrode of the NMOS tube T7 is connected with a resistor R35, the resistor R35 is connected with an anode of a power supply V26, a source electrode of the NMOS tube T7 is connected with a resistor R36, a cathode of the power supply V26 and the resistor R36 are both grounded, a drain electrode of the NMOS tube T7 is an output signal end OUT IV, and the output signal end OUT IV is connected with an OR gate.
The logic circuit V comprises a tenth comparator, a not gate D10, an AND gate D11, a voltage summation unit SUM2 and a voltage summation unit SUM3, wherein the input end of the tenth comparator is connected with the output end of the absolute value module ABS2 of the synaptic neuron module II, the output end of the tenth comparator is connected with one input end of the AND gate D11, and the other input end of the AND gate D11 is connected with the output end of the AND gate D1 of the logic circuit I; the input signal end N5 is connected with the input end of the NAND gate D10, the output ends of the NAND gate D10 and the AND gate D11 are connected with the input end of the voltage summation unit SUM2, the output end of the AND gate D11 is connected with the inhibition module III, the output ends of the inhibition module III and the voltage summation unit SUM2 are connected with the input end of the voltage summation unit SUM3, the output end of the voltage summation unit SUM3 is connected with the input end of the synaptic neuron module V, the output end of the synaptic neuron module V is an output signal end OUT V, and the output signal end OUT V is connected with an OR gate. The tenth comparator is used for comparing the output voltage of the ABS2 with the power supply V6 and outputting a high level if the output voltage is less than the voltage of the power supply V6; otherwise, a low level is output.
The suppression module III includes a ninth voltage control unit, a twelfth proportional amplifier, and an absolute value module ABS5, which are connected in sequence, where an input end of the ninth voltage control unit is connected to an output end of the and gate D11, and an output end of the absolute value module ABS5 is connected to one input end of the voltage summation unit SUM 3. The twelfth proportional amplifier performs proportional operation, the absolute value module ABS5 modulo the output value of the operational amplifier OP21, the salient neuron module V includes a thirteenth proportional amplifier, an absolute value module ABS6, an eleventh comparator and a twelfth comparator connected in sequence, the output end of the voltage summing unit SUM3 is connected to the input end of the thirteenth proportional amplifier, and the output end of the twelfth comparator is an output signal end OUT V. The thirteenth proportional amplifier performs proportional operation, the absolute value module ABS6 modulo the output value of the operational amplifier OP22, the eleventh comparator compares the output voltage of ABS6 with the power supply V28, and if less than the power supply V28, outputs a high level; otherwise, a low level is output. The twelfth comparator outputs the voltage of the power supply V29 if the output voltage of the operational amplifier OP23 is greater than the threshold voltage T8; otherwise, 0v is output. The tenth comparator comprises an operational amplifier OP6, wherein the inverting input end of the operational amplifier OP6 is connected with the absolute value module ABS2, the non-inverting input end of the operational amplifier OP6 is connected with the positive electrode of the power supply V6, the negative electrode of the power supply V5 is grounded, and the output end of the operational amplifier OP6 is connected with one input end of the AND gate D11;
the ninth voltage control unit comprises a voltage control switch S9, the output end of the AND gate D11 is connected with the positive phase input end of the voltage control switch S9, the first contact of the voltage control switch S9 is respectively connected with the twelfth proportional amplifier and the resistor R37, the second contact of the voltage control switch S9 is connected with the positive electrode of the power supply V27, and the negative electrode of the power supply V27, the resistor R37 and the inverting input end of the voltage control switch S9 are all grounded.
The twelfth proportional amplifier comprises a memristor M7, an operational amplifier OP21 and a resistor R38, the positive end of the memristor M7 is connected with the first contact of the voltage-controlled switch S9, the negative end of the memristor M7 is respectively connected with the inverting input end of the operational amplifier OP21 and the resistor R38, the non-inverting input end of the operational amplifier OP21 is grounded, the resistor R38 is connected with the output end of the operational amplifier OP21, and the output end of the operational amplifier OP21 is connected with the absolute value module ABS 5;
the thirteenth proportional amplifier comprises a memristor M6, an operational amplifier OP22 and a resistor R39, wherein the positive end of the memristor M6 is connected with the output end of the voltage summing unit SUM3, the negative end of the memristor M6 is respectively connected with the inverting input end of the operational amplifier OP22 and the resistor R39, the non-inverting input end of the operational amplifier OP22 is grounded, the resistor R39 is connected with the output end of the operational amplifier OP22, and the output end of the operational amplifier OP22 is connected with the input end of the absolute value module ABS 6;
the eleventh comparator comprises an operational amplifier OP23, the inverting input end of the operational amplifier OP23 is connected with the output end of the absolute value module ABS6, the non-inverting input end of the operational amplifier OP23 is grounded through a power supply V28, and the output end of the operational amplifier OP23 is connected with the twelfth comparator;
the twelfth comparator comprises an NMOS tube T8, a gate of the NMOS tube T8 is connected to an output end of the operational amplifier OP23, a drain of the NMOS tube T8 is connected to the resistor R40, the resistor R40 is connected to an anode of the power supply V29, a source of the NMOS tube T8 is connected to the resistor R41, a cathode of the power supply V29 and the resistor R41 are both grounded, a drain of the NMOS tube T8 is an output signal end OUT V, and the output signal end OUT V is connected to an or gate.
The logic circuit VI comprises a thirteenth comparator, a not gate D12, an AND gate D13, a voltage summation unit SUM4 and a voltage summation unit SUM5, wherein the input end of the thirteenth comparator is connected with the output end of the absolute value module ABS2 of the synaptic neuron module II, the output end of the thirteenth comparator is connected with one input end of the AND gate D13, and the other input end of the AND gate D13 is connected with the output end of the AND gate D1 of the logic circuit I; the input signal end N6 is connected with the input end of the NAND gate D12, the output ends of the NAND gate D12 and the AND gate D13 are both connected with the input end of the voltage summation unit SUM4, the output end of the AND gate D13 is connected with the inhibition module IV, the output ends of the inhibition module IV and the voltage summation unit SUM4 are both connected with the input end of the voltage summation unit SUM5, the output end of the voltage summation unit SUM5 is connected with the input end of the synaptic neuron module VI, the output end of the synaptic neuron module VI is an output signal end OUT VI, and the output signal end OUT VI is connected with an OR gate.
The suppression module IV includes a tenth voltage control unit, a fourteenth proportional amplifier, and an absolute value module ABS7, which are connected in sequence, an input end of the tenth voltage control unit is connected to an output end of the and gate D13, and an output end of the absolute value module ABS7 is connected to one input end of the voltage summation unit SUM 5.
The salient neuron module VI comprises a fifteenth proportional amplifier, an absolute value module ABS8, a fourteenth comparator and a fifteenth comparator which are connected in sequence, an output end of the voltage summing unit SUM5 is connected with an input end of the fifteenth proportional amplifier, and an output end of the fifteenth comparator is an output signal end OUT VI.
The thirteenth comparator comprises an operational amplifier OP7, wherein the inverting input end of the operational amplifier OP7 is connected with the output end of the absolute value module ABS2, the non-inverting input end of the operational amplifier OP7 is grounded through a power supply V7, and the output end of the operational amplifier OP7 is connected with an AND gate D13.
The tenth voltage control unit comprises a voltage control switch S10, the output end of the AND gate D13 is connected with the positive phase input end of the voltage control switch S10, the first contact of the voltage control switch S10 is respectively connected with the fourteenth proportional amplifier and the resistor R42, the second contact of the voltage control switch S10 is connected with the positive electrode of the power supply V30, and the negative electrode of the power supply V30, the resistor R42 and the reverse phase input end of the voltage control switch S10 are all grounded;
the fourteenth proportional amplifier comprises a memristor M9, an operational amplifier OP24 and a resistor R43, wherein the positive end of the memristor M9 is connected with a first contact of the voltage-controlled switch S9, the negative end of the memristor M9 is respectively connected with the inverting input end of the operational amplifier OP24 and the resistor R43, the non-inverting input end of the operational amplifier OP24 is grounded, the resistor R43 is connected with the output end of the operational amplifier OP24, and the output end of the operational amplifier OP24 is connected with the absolute value module ABS 7.
The fifteenth proportional amplifier comprises a memristor M8, an operational amplifier OP25 and a resistor R44, wherein the positive end of the memristor M8 is connected with the output end of the voltage summing unit SUM5, the negative end of the memristor M8 is respectively connected with the inverting input end of the operational amplifier OP25 and the resistor R44, the non-inverting input end of the operational amplifier OP25 is grounded, the resistor R44 is connected with the output end of the operational amplifier OP25, and the output end of the operational amplifier OP25 is connected with the input end of the absolute value module ABS 8.
The fourteenth comparator includes an operational amplifier OP26, an inverting input terminal of the operational amplifier OP26 is connected to the output terminal of the absolute value block ABS8, a non-inverting input terminal of the operational amplifier OP26 is grounded via a power supply V31, and an output terminal of the operational amplifier OP26 is connected to the fifteenth comparator.
The fifteenth comparator comprises an NMOS tube T9, a grid electrode of the NMOS tube T9 is connected with an output end of the operational amplifier OP26, a drain electrode of the NMOS tube T9 is connected with a resistor R45, the resistor R45 is connected with an anode of a power supply V32, a source electrode of the NMOS tube T9 is connected with a resistor R46, a cathode of the power supply V32 and the resistor R46 are both grounded, a drain electrode of the NMOS tube T9 is an output signal end OUT VI, and the output signal end OUT VI is connected with an OR gate.
The logic circuit VII comprises a sixteenth comparator, a not gate D14, an AND gate D15, a voltage summation unit SUM6 and a voltage summation unit SUM7, wherein the input end of the sixteenth comparator is connected with the output end of the absolute value module ABS2 of the synaptic neuron module II, the output end of the sixteenth comparator is connected with one input end of the AND gate D15, and the other input end of the AND gate D15 is connected with the output end of the AND gate D1 of the logic circuit I; the input signal end N7 is connected with the input end of a NAND gate D14, the output ends of a NOT gate D14 and an AND gate D15 are both connected with the input end of a voltage summation unit SUM6, the output end of the AND gate D15 is connected with an inhibition module V, the output ends of the inhibition module V and the voltage summation unit SUM4 are both connected with the input end of the voltage summation unit SUM7, the output end of the voltage summation unit SUM7 is connected with the input end of a synaptic neuron module VII, the output end of the synaptic neuron module VII is an output signal end OUT VII, and the output signal end OUT VII is connected with an OR gate;
the suppression module V includes an eleventh voltage control unit, a sixteenth proportional amplifier, and an absolute value module ABS9, which are connected in sequence, an input end of the eleventh voltage control unit is connected to an output end of the and gate D15, and an output end of the absolute value module ABS9 is connected to one input end of the voltage summation unit SUM 7.
The protruding neuron module VII comprises a seventeenth proportional amplifier, an absolute value module ABS10, a seventeenth comparator and an eighteenth comparator which are sequentially connected, the output end of the voltage summing unit SUM7 is connected with the input end of the seventeenth proportional amplifier, and the output end of the eighteenth comparator is an output signal end OUT VII.
The sixteenth comparator comprises an operational amplifier OP8, wherein the inverting input end of the operational amplifier OP8 is connected with the output end of the absolute value module ABS2, the non-inverting input end of the operational amplifier OP8 is grounded through a power supply V8, and the output end of the operational amplifier OP6 is connected with an AND gate D13.
The eleventh voltage-controlled unit comprises a voltage-controlled switch S11, the output end of the AND gate D15 is connected with the positive-phase input end of the voltage-controlled switch S10, the first contact of the voltage-controlled switch S10 is respectively connected with the twelfth proportional amplifier and the resistor R47, the second contact of the voltage-controlled switch S10 is connected with the positive electrode of the power supply V33, and the negative electrode of the power supply V33, the resistor R47 and the reverse-phase input end of the voltage-controlled switch S10 are all grounded.
The sixteenth proportional amplifier comprises a memristor M11, an operational amplifier OP27 and a resistor R48, wherein the positive end of the memristor M11 is connected with a first contact of the voltage-controlled switch S11, the negative end of the memristor M11 is respectively connected with the inverting input end of the operational amplifier OP27 and the resistor R48, the non-inverting input end of the operational amplifier OP27 is grounded, the resistor R48 is connected with the output end of the operational amplifier OP27, and the output end of the operational amplifier OP27 is connected with the absolute value module ABS 7.
The seventeenth proportional amplifier comprises a memristor M10, an operational amplifier OP28 and a resistor R49, wherein the positive end of the memristor M10 is connected with the output end of the voltage summing unit SUM7, the negative end of the memristor M10 is respectively connected with the inverting input end of the operational amplifier OP28 and the resistor R49, the non-inverting input end of the operational amplifier OP29 is grounded, the resistor R49 is connected with the output end of the operational amplifier OP28, and the output end of the operational amplifier OP28 is connected with the input end of the absolute value module ABS 10.
The seventeenth comparator comprises an operational amplifier OP29, wherein the inverting input end of the operational amplifier OP29 is connected with the output end of the absolute value module ABS10, the non-inverting input end of the operational amplifier OP29 is grounded through a power supply V34, and the output end of the operational amplifier OP29 is connected with the eighteenth comparator.
The eighteenth comparator comprises an NMOS tube T10, the grid electrode of the NMOS tube T10 is connected with the output end of the operational amplifier OP29, the drain electrode of the NMOS tube T10 is connected with a resistor R50, the resistor R50 is connected with the positive electrode of a power supply V35, the source electrode of the NMOS tube T10 is connected with a resistor R51, the negative electrode of the power supply V35 and the resistor R51 are both grounded, the drain electrode of the NMOS tube T10 is an output signal end OUT VII, and the output signal end OUT is connected with an OR gate.
As shown in fig. 3, 0-15s is a testing stage, 15-45s is a learning stage, 45-95s is a generalization stage, and after the food signal and the 500Hz electric bell signal are learned, the flow of the dog can be rippled by the 400Hz electric bell signal, the 800Hz electric bell signal, the 500Hz buzzer signal, the 400Hz buzzer signal and the 800Hz buzzer signal.
As shown in FIG. 4, 100-220s is differentiation stage, and after two training times, the 800Hz buzzer signal can not produce saliva; after three times of training, the 400Hz buzzer signal can not produce saliva; after four training sessions, the 500Hz buzzer signal failed to produce saliva. The above is food and 500Hz electric bell learning, so that the buzzer generalization can also generate saliva, and after 2-4 times of training, the ring signals with different attributes are differentiated, which is the first-stage differentiation. After six times of training, the 800Hz electric bell signal can not generate saliva; after seven times of training, the 400Hz electric bell signal can not generate saliva; the ringtones with the same attribute and different frequencies are differentiated after 6-7 times of training, which is the second-level differentiation and needs more training than the first-level differentiation. As shown in fig. 6, the output signal of V (OP 9) is an inhibit voltage for separating two similar ringtones.
As shown in fig. 5 (a), 0-180s is the process of first learning, generalization, differentiation and forgetting of food and 500Hz electric bell, as shown in fig. 5 (b), 247-400 s is the process of second learning, generalization, differentiation and forgetting of food and 500Hz electric bell, as shown in fig. 5 (c), 400-539 s is the process of third learning, generalization, differentiation and forgetting of food and 500Hz electric bell. In the third learning, the learning period is shorter than the first learning period and the second learning period, which indicates that the learning speed is faster; the third differentiation cycle was less than the first and second, indicating a faster rate of differentiation; the third and second forgetting require more cycles than the first, indicating that the speed of forgetting is slower.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (9)

1. A multi-mode generalization and differentiation associative memory neural network circuit based on memristors is characterized by comprising input signal terminals N1-N7, a synaptic neuron module I-synaptic neuron module VII, an inhibition module I-inhibition module V and an output signal terminal, wherein the input signal terminal N1 is connected with the synaptic neuron module I; the input signal terminal N1 and the input signal terminal N2 are connected with a synaptic neuron module II through a logic circuit I; the input signal terminal N1, the input signal terminal N2 and the synaptic neuron module II are all connected with the inhibition module I through a logic circuit II, the inhibition module I is connected with the input signal terminal N3, and the inhibition module I and the input signal terminal N3 are all connected with the synaptic neuron module III through a logic circuit III; the input signal end N1 and the input signal end N4 are both connected with the inhibition module II, and the inhibition module II and the input signal end N4 are both connected with the synaptic neuron module IV through the logic circuit IV; the input signal end N1, the input signal end N2 and the synaptic neuron module II are all connected with the inhibition module III, and the inhibition module III and the input signal end N5 are all connected with the synaptic neuron module V through the logic circuit V; the input signal terminal N1, the input signal terminal N2 and the synaptic neuron module II are all connected with an inhibition module IV, and the inhibition module IV and the input signal terminal N6 are all connected with the synaptic neuron module VI through a logic circuit VI; the input signal end N1, the input signal end N2 and the synaptic neuron module II are all connected with an inhibition module V, and the inhibition module V and the input signal end N7 are connected with the synaptic neuron module VII through a logic circuit VII; and the synaptic neuron module I-synaptic neuron module VII is connected with an output signal end through an OR gate.
2. The memristive-based multi-mode generalization and differentiation associative memory neural network circuit according to claim 1, wherein the synaptic neuron module I comprises a first proportional amplifier, and the input signal terminal N1 is connected with the first proportional amplifier; the first proportional amplifier is connected with the absolute value module ABS1, the output end of the absolute value module ABS1 is an output signal end OUT1, and the output signal end OUT1 is connected with an OR gate; the first proportional amplifier comprises a resistor R1, an operational amplifier OP1 and a resistor R2, an output signal end OUT1 is connected with the resistor R1, the resistor R1 is respectively connected with the resistor R2 and the inverting input end of the operational amplifier OP1, the resistor R2 and the output end of the operational amplifier OP1, the non-inverting input end of the operational amplifier OP1 is grounded, and the output end of the operational amplifier OP1 is connected with the input end of an absolute value module ABS 1.
3. The memristor-based multi-mode generalization and differentiation associative memory neural network circuit according to claim 2, wherein the logic circuit I comprises a first voltage-controlled unit, a second voltage-controlled unit, an and gate D1 and a voltage summing unit SUM1, the input signal terminal N1 and the input signal terminal N2 are both connected to the and gate D1, the output terminal of the and gate D1 is connected to the first voltage-controlled unit, the input signal terminal N2 is connected to the second voltage-controlled unit, the first voltage-controlled unit is connected to the first voltage-controlled unit, the second voltage-controlled unit is connected to the two input terminals of the voltage summing unit SUM1, and the output terminal of the voltage summing unit SUM1 is connected to the synaptic neuron module ii; the first voltage control unit comprises a voltage control switch S1, the output end of the AND gate D1 is connected with the positive phase input end of the voltage control switch S1, a first contact of the voltage control switch S1 is respectively connected with the first input end of the voltage summation unit SUM1 and the resistor R3, a second contact of the voltage control switch S1 is connected with the positive electrode of the power supply V1, and the negative electrode of the power supply V1, the resistor R3 and the reverse phase input end of the voltage control switch S1 are all grounded; the second voltage control unit comprises a voltage control switch S2, a positive phase input end of the voltage control switch S2 is connected with an input signal end N2, a first contact of the voltage control switch S2 is respectively connected with a second input end of the voltage summation unit SUM1 and a resistor R4, a second contact of the voltage control switch S2 is connected with a positive electrode of the power supply V2, and a negative electrode of the power supply V2, the resistor R4 and an inverted phase input end of the voltage control switch S2 are all grounded.
4. The memristance-based multi-mode generalization and differentiation associative memory neural network circuit according to any one of claims 1 to 3, wherein the synaptic neuron module II comprises a second proportional amplifier, an absolute value module ABS2, a third proportional amplifier, a first comparator and a second comparator which are connected in sequence, wherein an input end of the second proportional amplifier is connected with a voltage summation unit SUM1 of the logic circuit I, and an output end of the second comparator is connected with an OR gate; the second proportional amplifier comprises a memristor M1, an operational amplifier OP2 and a resistor R5, the positive end of the memristor M1 is connected with the output end of a voltage summing unit SUM1 of the logic circuit I, the negative end of the memristor M1 is respectively connected with the inverting input end of the operational amplifier OP2 and the resistor R5, the non-inverting input end of the operational amplifier OP2 is grounded, the resistor R5 is connected with the output end of the operational amplifier OP2, the output end of the operational amplifier OP2 is connected with the input end of an absolute value module ABS2, and the output end of the absolute value module ABS2 is connected with a third proportional amplifier; the third proportional amplifier comprises a resistor R6, an operational amplifier OP3 and a resistor R7, the output end of the absolute value module ABS2 is connected with the resistor R6, the resistor R6 is respectively connected with the resistor R7 and the inverting input end of the operational amplifier OP3, the resistor R7 is connected with the output end of the operational amplifier OP3, the non-inverting input end of the operational amplifier OP3 is grounded, and the output end of the operational amplifier OP3 is connected with the first comparator; the second comparator comprises an operational amplifier OP4, the inverting input end of the operational amplifier OP4 is connected with the output end of the operational amplifier OP3, the non-inverting input end of the operational amplifier OP4 is connected with the positive electrode of the power supply V3, the negative electrodes of the power supply V3 are grounded, and the output end of the operational amplifier OP4 is connected with the second comparator; the second comparator comprises an NMOS tube T1, the grid electrode of the NMOS tube T1 is connected with the output end of the operational amplifier OP4, the drain electrode of the NMOS tube T1 is connected with a resistor R8, the resistor R8 is connected with the positive electrode of a power supply V4, the source electrode of the NMOS tube T1 is connected with a resistor R9, the negative electrode of the power supply V4 and the resistor R9 are both grounded, the drain electrode of the NMOS tube T1 is an output signal end OUT II, and the output signal end OUT II is connected with an OR gate.
5. The memristance-based multi-mode generalization and differentiation associative memory neural network circuit according to claim 4, wherein the logic circuit II comprises a third comparator, an AND gate D2 and a NOT gate D5, an input end of the third comparator is connected with an output end of the absolute value block ABS2 of the synaptic neuron module II, an output end of the third comparator and an output end of the AND gate D1 of the logic circuit I are both connected with an input end of the AND gate D2, an output end of the AND gate D2 is connected with an input end of the NAND gate D5, and an output end of the NOT gate D5 is connected with the inhibit module I; the suppression module I comprises a fourth comparator, an AND gate D6, a third voltage control unit and a fourth proportional amplifier, the output end of the NOT gate D5 is connected with the input end of the fourth comparator, the output end of the fourth comparator and an input signal end N3 are both connected with the input end of the AND gate D6, the output end of the AND gate D6 is connected with the third voltage control unit, the third voltage control unit is connected with the fourth proportional amplifier, and the output end of the fourth proportional amplifier is connected with the logic circuit III; the logic circuit III comprises a first adder, a fifth proportional amplifier, a fourth voltage control unit, a fifth voltage control unit, a NOT gate D3 and an AND gate D4, an input signal end N3 is connected with the input end of the NAND gate D3, the output end of the NOT gate D3 and the output end of the AND gate D2 are connected with the input end of the AND gate D4, the output end of the AND gate D4 is connected with the fourth voltage control unit, an input signal end N3 is connected with the fifth voltage control unit, the output ends of the fourth voltage control unit and the fifth voltage control unit are connected with the first adder, the first adder is connected with the fifth proportional amplifier, and the fifth proportional amplifier is connected with a synaptic neuron module III; the synaptic neuron module III comprises a sixth proportional amplifier, an absolute value module ABS3, a seventh proportional amplifier, a fifth comparator and a sixth comparator which are sequentially connected, wherein the output end of the fifth proportional amplifier is connected with the input end of the sixth proportional amplifier, the output end of the sixth comparator is an output signal end OUT III, and the output signal end OUT III is connected with an OR gate.
6. The memristor-based multi-mode generalization and differentiation associative memory neural network circuit according to claim 5, wherein the suppressing module II comprises a seventh comparator, an AND gate D4, a sixth voltage-controlled unit and an eighth proportional amplifier, an output end of a NAND gate D9 of the seventh comparator is connected, an input end of the NOT gate D9 is connected with the input end signal N1, an output end and an input signal end N4 of the seventh comparator are connected with an input end of the AND gate D4, an output end of the AND gate D4 is connected with an input end of the sixth voltage-controlled unit, an output end of the sixth voltage-controlled unit is connected with an input end of the eighth proportional amplifier, and an output end of the eighth proportional amplifier is connected with the logic circuit IV; the logic circuit IV comprises a second adder, a ninth proportional amplifier, a seventh voltage control unit, an eighth voltage control unit, a NOT gate D7 and an AND gate D8, an input signal end N4 is connected with the input end of the NAND gate D7, the output end of the NOT gate D7 and the output end of the AND gate D2 are connected with the input end of the AND gate D8, the output end of the AND gate D8 is connected with the seventh voltage control unit, an input signal end N4 is connected with the eighth voltage control unit, the output ends of the seventh voltage control unit and the eighth voltage control unit are connected with the second adder, the second adder is connected with the ninth proportional amplifier, and the ninth proportional amplifier is connected with a synaptic neuron module IV; the synaptic neuron module IV comprises a tenth proportional amplifier, an absolute value module ABS4, an eleventh proportional amplifier, a ninth comparator and a tenth comparator which are sequentially connected, wherein the output end of the ninth proportional amplifier is connected with the input end of the tenth proportional amplifier, the output end of the tenth comparator is an output signal end OUT IV, and the output signal end OUT IV is connected with an OR gate.
7. The memristor-based multi-mode generalization and differentiation associative memory neural network circuit according to claim 6, wherein the third comparator comprises an operational amplifier OP5, an inverting input terminal of the operational amplifier OP5 is connected to the output terminal of the absolute value block ABS2, a non-inverting input terminal of the operational amplifier OP5 is connected to the ground through a power supply V5, and an output terminal of the operational amplifier OP5 is connected to one input terminal of an AND gate D2D;
the fourth comparator comprises an NMOS tube T2 and a PMOS tube T3, the output end of the NOT gate D5 is connected with the grid electrode of the NMOS tube T2, the drain electrode of the NMOS tube T2 is connected with the positive electrode of a power supply V11 through a resistor R10, the source electrode of the NMOS tube T2 is connected with the positive electrode of a power supply V12, the negative electrodes of the power supply V11 and the power supply V12 are grounded, the drain electrode of the NMOS tube T2 is connected with the grid electrode of the PMOS tube T3, the drain electrode of the PMOS tube T3 is connected with the positive electrode of a power supply V13 through a resistor R11, the source electrode of the PMOS tube T3 is connected with the positive electrode of a power supply V14, and the negative electrodes of the power supply V13 and the power supply V14 are grounded; the drain electrode of the PMOS tube T3 is connected with one input end of the AND gate D6;
the third voltage control unit comprises a voltage control switch S5, the output end of the AND gate D6 is connected with the positive phase input end of the voltage control switch S5, the first contact of the voltage control switch S5 is respectively connected with the fourth proportional amplifier and the resistor R52, the second contact of the voltage control switch S5 is connected with the positive electrode of the power supply V15, and the negative electrode of the power supply V15, the resistor R52 and the reverse phase input end of the voltage control switch S5 are all grounded;
the fourth proportional amplifier comprises a memristor M3, an operational amplifier OP9 and a resistor R12, the positive end of the memristor M3 is connected with a first contact of the voltage-controlled switch S5, the negative end of the memristor M3 is respectively connected with the inverting input end of the operational amplifier OP9 and the resistor R12, the non-inverting input end of the operational amplifier OP9 is grounded, the resistor R12 is connected with the output end of the operational amplifier OP9, and the output end of the operational amplifier OP9 is connected with the first adder;
the first adder comprises a resistor R13, a resistor R14, a resistor R15 and an operational amplifier OP10, wherein the resistor R13 is connected with the output end of the operational amplifier OP9, the resistor R14 is respectively connected with a fourth voltage-controlled unit and a fifth voltage-controlled unit, the resistor R13, the resistor R14 and the resistor R15 are all connected with the positive input end of the operational amplifier OP10, the resistor R15 is connected with the output end of the operational amplifier OP10, the negative input end of the operational amplifier OP10 is grounded, and the output end of the operational amplifier OP10 is connected with a fifth proportional amplifier;
the fifth proportional amplifier comprises a resistor R16, an operational amplifier OP11 and a resistor R17, the output end of the operational amplifier OP10 is connected with the resistor R16, the resistor R16 is respectively connected with the resistor R17 and the inverting input end of the operational amplifier OP11, the resistor R17 is connected with the output end of the operational amplifier OP11, the non-inverting input end of the operational amplifier OP11 is grounded, and the output end of the operational amplifier OP11 is connected with the sixth proportional amplifier of the synaptic neuron module III;
the fourth voltage control unit comprises a voltage control switch S3, the output end of the AND gate D4 is connected with the positive phase input end of the voltage control switch S3, the first contact of the voltage control switch S3 is connected with the resistor R14, the second contact of the voltage control switch S3 is connected with the positive electrode of the power supply V9, and the negative electrode of the power supply V9 and the negative phase input end of the voltage control switch S3 are both grounded;
the fifth voltage control unit comprises a voltage control switch S4, an input signal end N3 is connected with a positive phase input end of the voltage control switch S4, a first contact of the voltage control switch S4 is connected with a resistor R14, a second contact of the voltage control switch S4 is connected with a positive electrode of a power supply V10, and a negative electrode of the power supply V10 and an inverted phase input end of the voltage control switch S4 are both grounded;
the sixth proportional amplifier comprises a memristor M2, an operational amplifier OP12 and a resistor R18, wherein the positive end of the memristor M2 is connected with the output end of the operational amplifier OP11, the negative end of the memristor M2 is respectively connected with the inverting input end of the operational amplifier OP12 and the resistor R18, the non-inverting input end of the operational amplifier OP12 is grounded, the resistor R18 is connected with the output end of the operational amplifier OP12, and the output end of the operational amplifier OP12 is connected with an absolute value module ABS 3;
the seventh proportional amplifier comprises a resistor R19, an operational amplifier OP13 and a resistor R20, the output end of the absolute value module ABS3 is connected with the resistor R19, the resistor R19 is respectively connected with the resistor R20 and the inverting input end of the operational amplifier OP13, the resistor R20 is connected with the output end of the operational amplifier OP13, the non-inverting input end of the operational amplifier OP13 is grounded, and the output end of the operational amplifier OP13 is connected with a fifth comparator;
the fifth comparator comprises an operational amplifier OP14, the output end of the operational amplifier OP13 is connected with the inverting input end of the operational amplifier OP14, the non-inverting input end of the operational amplifier OP14 is grounded through a power supply V6, and the output end of the operational amplifier OP14 is connected with the sixth comparator;
the sixth comparator comprises an NMOS tube T4, the grid electrode of the NMOS tube T4 is connected with the output end of the operational amplifier OP14, the drain electrode of the NMOS tube T4 is connected with a resistor R21, the resistor R21 is connected with the positive electrode of a power supply V17, the source electrode of the NMOS tube T4 is connected with a resistor R22, the negative electrode of the power supply V17 and the resistor R22 are both grounded, the drain electrode of the NMOS tube T4 is an output signal end OUT III, and the output signal end OUT III is connected with an OR gate;
the seventh comparator comprises an NMOS tube T5 and a PMOS tube T6, the output end of the NOT gate D9 is connected with the grid electrode of the NMOS tube T5, the drain electrode of the NMOS tube T5 is connected with the positive electrode of a power supply V20 through a resistor R23, the source electrode of the NMOS tube T5 is connected with the positive electrode of the power supply V21, the negative electrodes of the power supply V20 and the power supply V21 are grounded, the drain electrode of the NMOS tube T5 is connected with the grid electrode of the PMOS tube T6, the drain electrode of the PMOS tube T6 is connected with the positive electrode of a power supply V22 through a resistor R24, the source electrode of the PMOS tube T6 is connected with the positive electrode of the power supply V23, and the negative electrodes of the power supply V22 and the power supply V23 are grounded; the drain electrode of the PMOS tube T6 is connected with one input end of the AND gate D4;
the sixth voltage control unit comprises a voltage control switch S8, the output end of the AND gate D16 is connected with the positive phase input end of the voltage control switch S8, the first contact of the voltage control switch S8 is respectively connected with the eighth proportional amplifier and the resistor R25, the second contact of the voltage control switch S8 is connected with the positive electrode of the power supply V24, and the negative electrode of the power supply V24, the resistor R25 and the inverting input end of the voltage control switch S8 are all grounded;
the eighth proportional amplifier comprises a memristor M5, an operational amplifier OP15 and a resistor R26, the positive end of the memristor M5 is connected with the first contact of the voltage-controlled switch S8, the negative end of the memristor M5 is respectively connected with the inverting input end of the operational amplifier OP15 and the resistor R26, the non-inverting input end of the operational amplifier OP15 is grounded, the resistor R26 is connected with the output end of the operational amplifier OP15, and the output end of the operational amplifier OP15 is connected with the second adder;
the second adder comprises a resistor R27, a resistor R28, a resistor 29 and an operational amplifier OP16, the resistor R27 is connected with the output end of the operational amplifier OP15, the resistor R28 is respectively connected with the seventh voltage-controlled unit and the eighth voltage-controlled unit, the resistor R27, the resistor R28 and the resistor R295 are all connected with the non-inverting input end of the operational amplifier OP10, the resistor R27 is connected with the output end of the operational amplifier OP16, the inverting input end of the operational amplifier OP16 is grounded, and the output end of the operational amplifier OP16 is connected with the ninth proportional amplifier;
the ninth proportional amplifier comprises a resistor R30, an operational amplifier OP17 and a resistor R31, wherein the output end of the operational amplifier OP16 is connected with the resistor R30, the resistor R30 is respectively connected with the resistor R31 and the inverting input end of the operational amplifier OP17, the resistor R31 is connected with the output end of the operational amplifier OP17, the non-inverting input end of the operational amplifier OP17 is grounded, and the output end of the operational amplifier OP17 is connected with the tenth proportional amplifier of the synaptic neuron module IV;
the seventh voltage control unit comprises a voltage control switch S6, the output end of the AND gate D8 is connected with the positive phase input end of the voltage control switch S6, the first contact of the voltage control switch S6 is connected with the resistor R28, the second contact of the voltage control switch S3 is connected with the positive electrode of the power supply V18, and the negative electrode of the power supply V18 and the negative phase input end of the voltage control switch S6 are both grounded;
the eighth voltage control unit comprises a voltage control switch S7, an input signal end N4 is connected with a positive phase input end of the voltage control switch S7, a first contact of the voltage control switch S7 is connected with a resistor R28, a second contact of the voltage control switch S7 is connected with a positive electrode of a power supply V19, and a negative electrode of the power supply V19 and a negative phase input end of the voltage control switch S7 are both grounded;
the tenth proportional amplifier comprises a memristor M4, an operational amplifier OP18 and a resistor R32, the positive end of the memristor M2 is connected with the output end of the operational amplifier OP17, the negative end of the memristor M2 is respectively connected with the inverting input end of the operational amplifier OP12 and the resistor R32, the non-inverting input end of the operational amplifier OP18 is grounded, the resistor R32 is connected with the output end of the operational amplifier OP18, and the output end of the operational amplifier OP18 is connected with an absolute value module ABS 4;
the eleventh proportional amplifier comprises a resistor R33, an operational amplifier OP19 and a resistor R34, the output end of the absolute value module ABS4 is connected with the resistor R33, the resistor R33 is respectively connected with the resistor R34 and the inverting input end of the operational amplifier OP19, the resistor R34 is connected with the output end of the operational amplifier OP19, the non-inverting input end of the operational amplifier OP19 is grounded, and the output end of the operational amplifier OP13 is connected with a fifth comparator;
the ninth comparator comprises an operational amplifier OP20, the output end of the operational amplifier OP19 is connected with the inverting input end of the operational amplifier OP20, the non-inverting input end of the operational amplifier OP20 is grounded through a power supply V25, and the output end of the operational amplifier OP20 is connected with the tenth comparator;
the tenth comparator comprises an NMOS tube T7, a grid electrode of the NMOS tube T7 is connected with an output end of the operational amplifier OP20, a drain electrode of the NMOS tube T7 is connected with a resistor R35, the resistor R35 is connected with an anode of a power supply V26, a source electrode of the NMOS tube T7 is connected with a resistor R36, a cathode of the power supply V26 and the resistor R36 are both grounded, a drain electrode of the NMOS tube T7 is an output signal end OUT IV, and the output signal end OUT IV is connected with an OR gate.
8. The memristor-based multi-mode generalization and differentiation associative memory neural network circuit according to any one of claims 3 and 5 to 7, wherein the logic circuit V comprises a tenth comparator, a not gate D10, an AND gate D11, a voltage summing unit SUM2 and a voltage summing unit SUM3, wherein an input end of the tenth comparator is connected with an output end of an absolute value module ABS2 of the synaptic neuron module II, an output end of the tenth comparator is connected with one input end of the AND gate D11, and the other input end of the AND gate D11 is connected with an output end of an AND gate D1 of the logic circuit I; the input signal end N5 is connected with the input end of a NAND gate D10, the output ends of the NAND gate D10 and the AND gate D11 are both connected with the input end of a voltage summation unit SUM2, the output end of the AND gate D11 is connected with an inhibition module III, the output ends of the inhibition module III and the voltage summation unit SUM2 are both connected with the input end of a voltage summation unit SUM3, the output end of the voltage summation unit SUM3 is connected with the input end of a synaptic neuron module V, the output end of the synaptic neuron module V is an output signal end OUT V, and the output signal end OUT V is connected with an OR gate;
the suppression module III comprises a ninth voltage control unit, a twelfth proportional amplifier and an absolute value module ABS5 which are sequentially connected, wherein the input end of the ninth voltage control unit is connected with the output end of the AND gate D11, and the output end of the absolute value module ABS5 is connected with one input end of the voltage summation unit SUM 3;
the salient neuron module V comprises a thirteenth proportional amplifier, an absolute value module ABS6, an eleventh comparator and a twelfth comparator which are sequentially connected, the output end of the voltage summation unit SUM3 is connected with the input end of the thirteenth proportional amplifier, and the output end of the twelfth comparator is an output signal end OUT V;
the logic circuit VI comprises a thirteenth comparator, a not gate D12, an AND gate D13, a voltage summation unit SUM4 and a voltage summation unit SUM5, wherein the input end of the thirteenth comparator is connected with the output end of the absolute value module ABS2 of the synaptic neuron module II, the output end of the thirteenth comparator is connected with one input end of the AND gate D13, and the other input end of the AND gate D13 is connected with the output end of the AND gate D1 of the logic circuit I; the input signal end N6 is connected with the input end of the NAND gate D12, the output ends of the NOT gate D12 and the AND gate D13 are both connected with the input end of the voltage summation unit SUM4, the output end of the AND gate D13 is connected with the suppression module IV, the output ends of the suppression module IV and the voltage summation unit SUM4 are both connected with the input end of the voltage summation unit SUM5, the output end of the voltage summation unit SUM5 is connected with the input end of the synaptic neuron module VI, the output end of the synaptic neuron module VI is an output signal end OUT VI, and the output signal end OUT VI is connected with an OR gate;
the suppression module IV comprises a tenth voltage control unit, a fourteenth proportional amplifier and an absolute value module ABS7 which are connected in sequence, an input end of the tenth voltage control unit is connected with an output end of the and gate D13, and an output end of the absolute value module ABS7 is connected with one input end of the voltage summation unit SUM 5;
the salient neuron module VI comprises a fifteenth proportional amplifier, an absolute value module ABS8, a fourteenth comparator and a fifteenth comparator which are sequentially connected, the output end of the voltage summation unit SUM5 is connected with the input end of the fifteenth proportional amplifier, and the output end of the fifteenth comparator is an output signal end OUT VI;
the logic circuit VII comprises a sixteenth comparator, a not gate D14, an AND gate D15, a voltage summation unit SUM6 and a voltage summation unit SUM7, wherein the input end of the sixteenth comparator is connected with the output end of the absolute value module ABS2 of the synaptic neuron module II, the output end of the sixteenth comparator is connected with one input end of the AND gate D15, and the other input end of the AND gate D15 is connected with the output end of the AND gate D1 of the logic circuit I; the input signal end N7 is connected with the input end of a NAND gate D14, the output ends of a NOT gate D14 and an AND gate D15 are both connected with the input end of a voltage summation unit SUM6, the output end of the AND gate D15 is connected with an inhibition module V, the output ends of the inhibition module V and the voltage summation unit SUM4 are both connected with the input end of the voltage summation unit SUM7, the output end of the voltage summation unit SUM7 is connected with the input end of a synaptic neuron module VII, the output end of the synaptic neuron module VII is an output signal end OUT VII, and the output signal end OUT VII is connected with an OR gate;
the suppression module V comprises an eleventh voltage control unit, a sixteenth proportional amplifier and an absolute value module ABS9 which are sequentially connected, wherein the input end of the eleventh voltage control unit is connected with the output end of the AND gate D15, and the output end of the absolute value module ABS9 is connected with one input end of the voltage summation unit SUM 7;
the protruding neuron module VII comprises a seventeenth proportional amplifier, an absolute value module ABS10, a seventeenth comparator and an eighteenth comparator which are sequentially connected, the output end of the voltage summing unit SUM7 is connected with the input end of the seventeenth proportional amplifier, and the output end of the eighteenth comparator is an output signal end OUT VII.
9. A memristor-based multi-mode generalization and differentiation associative memory neural network circuit according to claim 8, wherein the tenth comparator comprises an operational amplifier OP6, an inverting input terminal of the operational amplifier OP6 is connected to the absolute value block ABS2, a non-inverting input terminal of the operational amplifier OP6 is connected to a positive terminal of the power supply V6, a negative terminal of the power supply V5 is grounded, and an output terminal of the operational amplifier OP6 is connected to one input terminal of the and gate D11;
the ninth voltage control unit comprises a voltage control switch S9, the output end of the AND gate D11 is connected with the positive phase input end of the voltage control switch S9, the first contact of the voltage control switch S9 is respectively connected with the twelfth proportional amplifier and the resistor R37, the second contact of the voltage control switch S9 is connected with the positive electrode of the power supply V27, and the negative electrode of the power supply V27, the resistor R37 and the reverse phase input end of the voltage control switch S9 are all grounded;
the twelfth proportional amplifier comprises a memristor M7, an operational amplifier OP21 and a resistor R38, the positive end of the memristor M7 is connected with the first contact of the voltage-controlled switch S9, the negative end of the memristor M7 is respectively connected with the inverting input end of the operational amplifier OP21 and the resistor R38, the non-inverting input end of the operational amplifier OP21 is grounded, the resistor R38 is connected with the output end of the operational amplifier OP21, and the output end of the operational amplifier OP21 is connected with the absolute value module ABS 5;
the thirteenth proportional amplifier comprises a memristor M6, an operational amplifier OP22 and a resistor R39, wherein the positive end of the memristor M6 is connected with the output end of the voltage summing unit SUM3, the negative end of the memristor M6 is respectively connected with the inverting input end of the operational amplifier OP22 and the resistor R39, the non-inverting input end of the operational amplifier OP22 is grounded, the resistor R39 is connected with the output end of the operational amplifier OP22, and the output end of the operational amplifier OP22 is connected with the input end of the absolute value module ABS 6;
the eleventh comparator comprises an operational amplifier OP23, the inverting input end of the operational amplifier OP23 is connected with the output end of the absolute value module ABS6, the non-inverting input end of the operational amplifier OP23 is grounded through a power supply V28, and the output end of the operational amplifier OP23 is connected with the twelfth comparator;
the twelfth comparator comprises an NMOS tube T8, the grid electrode of the NMOS tube T8 is connected with the output end of the operational amplifier OP23, the drain electrode of the NMOS tube T8 is connected with a resistor R40, the resistor R40 is connected with the positive electrode of a power supply V29, the source electrode of the NMOS tube T8 is connected with a resistor R41, the negative electrode of the power supply V29 and the resistor R41 are both grounded, the drain electrode of the NMOS tube T8 is an output signal end OUT V, and the output signal end OUT V is connected with an OR gate;
the thirteenth comparator comprises an operational amplifier OP7, the inverting input end of the operational amplifier OP7 is connected with the output end of the absolute value module ABS2, the non-inverting input end of the operational amplifier OP7 is grounded through a power supply V7, and the output end of the operational amplifier OP7 is connected with an AND gate D13;
the tenth voltage control unit comprises a voltage control switch S10, the output end of the AND gate D13 is connected with the positive phase input end of the voltage control switch S10, the first contact of the voltage control switch S10 is respectively connected with the fourteenth proportional amplifier and the resistor R42, the second contact of the voltage control switch S10 is connected with the positive electrode of the power supply V30, and the negative electrode of the power supply V30, the resistor R42 and the reverse phase input end of the voltage control switch S10 are all grounded;
the fourteenth proportional amplifier comprises a memristor M9, an operational amplifier OP24 and a resistor R43, wherein the positive end of the memristor M9 is connected with a first contact of the voltage-controlled switch S9, the negative end of the memristor M9 is respectively connected with the inverting input end of the operational amplifier OP24 and the resistor R43, the non-inverting input end of the operational amplifier OP24 is grounded, the resistor R43 is connected with the output end of the operational amplifier OP24, and the output end of the operational amplifier OP24 is connected with the absolute value module ABS 7;
the fifteenth proportional amplifier comprises a memristor M8, an operational amplifier OP25 and a resistor R44, wherein the positive end of the memristor M8 is connected with the output end of the voltage summing unit SUM5, the negative end of the memristor M8 is respectively connected with the inverting input end of the operational amplifier OP25 and the resistor R44, the non-inverting input end of the operational amplifier OP25 is grounded, the resistor R44 is connected with the output end of the operational amplifier OP25, and the output end of the operational amplifier OP25 is connected with the input end of the absolute value module ABS 8;
the fourteenth comparator comprises an operational amplifier OP26, wherein the inverting input end of the operational amplifier OP26 is connected with the output end of the absolute value module ABS8, the non-inverting input end of the operational amplifier OP26 is grounded through a power supply V31, and the output end of the operational amplifier OP26 is connected with the fifteenth comparator;
the fifteenth comparator comprises an NMOS tube T9, the grid electrode of the NMOS tube T9 is connected with the output end of the operational amplifier OP26, the drain electrode of the NMOS tube T9 is connected with a resistor R45, the resistor R45 is connected with the positive electrode of a power supply V32, the source electrode of the NMOS tube T9 is connected with a resistor R46, the negative electrode of the power supply V32 and the resistor R46 are both grounded, the drain electrode of the NMOS tube T9 is an output signal end OUT VI, and the output signal end OUT VI is connected with an OR gate;
the sixteenth comparator comprises an operational amplifier OP8, wherein the inverting input end of the operational amplifier OP8 is connected with the output end of the absolute value module ABS2, the non-inverting input end of the operational amplifier OP8 is grounded through a power supply V8, and the output end of the operational amplifier OP6 is connected with an AND gate D13;
the eleventh voltage-controlled unit comprises a voltage-controlled switch S11, the output end of the AND gate D15 is connected with the positive-phase input end of the voltage-controlled switch S10, the first contact of the voltage-controlled switch S10 is respectively connected with the twelfth proportional amplifier and the resistor R47, the second contact of the voltage-controlled switch S10 is connected with the positive electrode of the power supply V33, and the negative electrode of the power supply V33, the resistor R47 and the reverse-phase input end of the voltage-controlled switch S10 are all grounded;
the sixteenth proportional amplifier comprises a memristor M11, an operational amplifier OP27 and a resistor R48, wherein the positive end of the memristor M11 is connected with a first contact of the voltage-controlled switch S11, the negative end of the memristor M11 is respectively connected with the inverting input end of the operational amplifier OP27 and the resistor R48, the non-inverting input end of the operational amplifier OP27 is grounded, the resistor R48 is connected with the output end of the operational amplifier OP27, and the output end of the operational amplifier OP27 is connected with the absolute value module ABS 7;
the seventeenth proportional amplifier comprises a memristor M10, an operational amplifier OP28 and a resistor R49, wherein the positive end of the memristor M10 is connected with the output end of the voltage summing unit SUM7, the negative end of the memristor M10 is respectively connected with the inverting input end of the operational amplifier OP28 and the resistor R49, the non-inverting input end of the operational amplifier OP29 is grounded, the resistor R49 is connected with the output end of the operational amplifier OP28, and the output end of the operational amplifier OP28 is connected with the input end of the absolute value module ABS 10;
the seventeenth comparator comprises an operational amplifier OP29, wherein the inverting input end of the operational amplifier OP29 is connected with the output end of the absolute value module ABS10, the non-inverting input end of the operational amplifier OP29 is grounded through a power supply V34, and the output end of the operational amplifier OP29 is connected with the eighteenth comparator;
the eighteenth comparator comprises an NMOS tube T10, the grid electrode of the NMOS tube T10 is connected with the output end of the operational amplifier OP29, the drain electrode of the NMOS tube T10 is connected with a resistor R50, the resistor R50 is connected with the anode of a power supply V35, the source electrode of the NMOS tube T10 is connected with a resistor R51, the cathode of the power supply V35 and the resistor R51 are both grounded, the drain electrode of the NMOS tube T10 is an output signal end OUT VII, and the output signal end OUT VII is connected with an OR gate.
CN202210259727.6A 2022-03-16 2022-03-16 Multi-mode generalization and differentiation association memory neural network circuit based on memristor Pending CN115577758A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210259727.6A CN115577758A (en) 2022-03-16 2022-03-16 Multi-mode generalization and differentiation association memory neural network circuit based on memristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210259727.6A CN115577758A (en) 2022-03-16 2022-03-16 Multi-mode generalization and differentiation association memory neural network circuit based on memristor

Publications (1)

Publication Number Publication Date
CN115577758A true CN115577758A (en) 2023-01-06

Family

ID=84579289

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210259727.6A Pending CN115577758A (en) 2022-03-16 2022-03-16 Multi-mode generalization and differentiation association memory neural network circuit based on memristor

Country Status (1)

Country Link
CN (1) CN115577758A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116523012A (en) * 2023-07-03 2023-08-01 湖南师范大学 Memristor self-learning circuit based on generation countermeasure neural network
CN118278478A (en) * 2024-04-09 2024-07-02 武汉工程大学 Memristor-based variable forgetting rate circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116523012A (en) * 2023-07-03 2023-08-01 湖南师范大学 Memristor self-learning circuit based on generation countermeasure neural network
CN116523012B (en) * 2023-07-03 2023-09-08 湖南师范大学 Memristor self-learning circuit based on generation countermeasure neural network
CN118278478A (en) * 2024-04-09 2024-07-02 武汉工程大学 Memristor-based variable forgetting rate circuit

Similar Documents

Publication Publication Date Title
CN115577758A (en) Multi-mode generalization and differentiation association memory neural network circuit based on memristor
Zhang et al. Exponential stabilization of memristor-based chaotic neural networks with time-varying delays via intermittent control
CN102971753B (en) For using the method and system of three memristor synapse of STDP and dopamine signaling
CN108804786B (en) Memristive model circuit design method for realizing plasticity of synaptic weights of associative neural network
CN105160401A (en) WTA neural network based on memristor array and application thereof
CN109165730B (en) State quantization network implementation method in cross array neuromorphic hardware
CN108491567B (en) Simulink modeling method of magnetic flux control type memristor
Babacan et al. FCS based memristor emulator with associative learning circuit application
CN114757345A (en) Memristor association memory neural network circuit and control method thereof
CN116245151A (en) Multifunctional operational conditional reflex neural network circuit with blocking and competing effects
CN114169511B (en) Associative memory circuit and method based on physical memristor
CN114997387A (en) Visual-evoked emotional habituation characteristic neural network circuit
CN110428049A (en) A kind of voltage-type neural network and its operating method based on polymorphic memristor
CN116611487A (en) Love associative memory circuit with latent inhibiting effect and multiple forget modes
Chakraborty et al. Homeostatic plasticity in a leaky integrate and fire neuron using tunable leak
Sinha et al. Evolving nanoscale associative memories with memristors
CN110443356A (en) A kind of current mode neural network based on more resistance state memristors
CN114970850A (en) Emotional habituation neural network circuit with situation dependence and generalization
KR102480434B1 (en) A synapse component having linear current-voltage characteristic and neural network using the synapse
CN113344194B (en) Operational condition reflecting circuit based on memristor
Howard et al. A spice model of the peo-pani memristor
CN110175384B (en) Secondary smooth flow control memristor simulation circuit
CN109255437B (en) A kind of memristor nerve network circuit of flexibly configurable
CN114742217A (en) Circuit of VFL-RELU pulse neuron based on memristor
CN110198164B (en) Absolute value flow control memristor simulation circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination