CN113344194B - Operational condition reflecting circuit based on memristor - Google Patents
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- 230000000946 synaptic effect Effects 0.000 claims abstract description 85
- 230000001629 suppression Effects 0.000 claims abstract description 84
- 210000002569 neuron Anatomy 0.000 claims abstract description 63
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- 239000003990 capacitor Substances 0.000 claims description 24
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- 241000272201 Columbiformes Species 0.000 abstract description 35
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- 230000002401 inhibitory effect Effects 0.000 abstract description 7
- 235000019627 satiety Nutrition 0.000 abstract description 5
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Abstract
The invention provides an operational condition reflecting circuit based on memristance, which comprises an input module, a voltage control module, a promotion module I, a promotion module II, a suppression module I, a suppression module II, a synaptic neuron module I, a synaptic neuron module II and a synaptic neuron module III; the promoting module I realizes that the negative punishment of electric shock has promoting effect on the positive punishment of food, the promoting module II realizes that the positive punishment of food is realized, the repetition rate of pigeons towards food is improved, the inhibiting module I realizes that the negative punishment of electric shock is realized, the repetition rate of pigeons towards electric shock is reduced, and the inhibiting module II realizes that the positive punishment of food has inhibiting effect on the negative punishment of electric shock; the synaptic neuron module I, II realizes the operational conditional reflex of the pigeon in different environments through the parallel connection of two groups of memristors. The invention realizes the process of the operative condition reflection, the promotion and inhibition relation between positive and negative, and the influence of instantaneity and satiety on the operative condition reflection.
Description
Technical Field
The invention relates to the technical field of digital-analog circuits, in particular to an operational condition reflecting circuit based on memristor, which is realized based on the idea of the operational condition reflection of gold.
Background
In 1971, the university of california, berkeley division Cai Shaotang taught the concept of memristance, with the first successful memristor developed by the american hewlett-packard laboratory in 2008. Memristive properties are very similar to synapses in biological nerves, and partial functions of the brain can be simulated, so that simulation memory learning of biological behaviors is performed, and circuit simulation of the biological memory behaviors has become an extremely important part of memristive research. Memristors have great potential application prospects in the aspects of nonvolatile storage, logic operation, novel calculation, storage fusion architecture calculation, novel nerve morphology calculation and the like.
The schwaner Skinner provides an operational condition reflection theory system through experiments, and the team applies the operational condition reflection to the training of dogs in China, and then Vollmer et al provide the influence of factors such as instantaneity and satiety on the operational condition reflection, but the influence is not realized through a circuit.
Disclosure of Invention
Aiming at the existing operational condition reflection theory, the invention provides an operational condition reflection circuit based on memristors, and the operational condition reflection process is realized through two groups of memristors in-and-out parallel circuits; by the promotion and inhibition circuit, promotion and inhibition relation among different emotions is realized; by means of the voltage control circuit, the influence of instantaneity and satiety on the reflection of the operation condition is achieved.
The technical scheme of the invention is realized as follows:
an operational condition reflecting circuit based on memristance comprises an input module, a voltage control module, a promotion module I, a promotion module II, a suppression module I, a suppression module II, a synaptic neuron module I, a synaptic neuron module II and a synaptic neuron module III; the input module is respectively connected with the pulse power supply signal, the promotion module I, the promotion module II, the inhibition module I, the inhibition module II, the synaptic neuron module I and the synaptic neuron module II, the synaptic neuron module II is respectively connected with the promotion module I, the promotion module II, the inhibition module I and the inhibition module II, and the synaptic neuron module I is respectively connected with the promotion module II and the inhibition module II; the pulse power supply signal is respectively connected with a voltage control module and a suppression module I, and the voltage control module is connected with a synaptic neuron module III.
Preferably, the input module comprises a first voltage control unit, a second voltage control unit and an addition operation unit; the synaptic neuron module I comprises a voltage module I and a synaptic module I; the synaptic neuron module II comprises a voltage module II and a synaptic module II; the suppression module I comprises a suppression signal judging module I, a suppression signal receiving and processing module I and a suppression signal recovery module I; the suppression module II comprises a suppression signal judging module II and a suppression signal receiving and processing module II; the promotion module I comprises a promotion signal judgment module I, a promotion signal receiving and processing module I and a promotion signal recovery module I; the promotion module II comprises a promotion signal judgment module II and a promotion signal receiving processing module II; the voltage control module comprises a voltage judging module and a voltage receiving and processing module;
The input end of the first voltage-controlled unit is provided with a NAND gate D 1 Output terminals of (a) are connected with each other, not gate D 1 The input end of the voltage control unit is connected with a pulse power supply signal, the pulse power supply signal is respectively connected with the input end of the second voltage control unit, the inhibition signal judging module I and the voltage judging module, the voltage judging module is connected with the voltage receiving processing module, and the voltage receiving processing module is connected with the synaptic neuron module III; the output end of the first voltage control unit and the output end of the second voltage control unit are respectively connected with the input end of the addition operation unit; the output end of the addition unit is respectively connected with a promotion signal receiving processing module I, a promotion signal receiving processing module II, a suppression signal receiving processing module I, a suppression signal receiving processing module II, a voltage module I and a voltage module II, the voltage module I is connected with a synaptic module I, the synaptic module I is respectively connected with a promotion signal judging module II and a suppression signal judging module II, the voltage module II is connected with a synaptic module II, and the synaptic module II is respectively connected with a suppression signal judging module I, a suppression signal receiving processing module II, a promotion signal judging module I and a promotion signal receiving position module II; promotion signal judging module I respectively NAND gate D 1 Is connected with the output end of the signal receiving and processing promotion module I and the signal recovery promotion module I phaseThe promotion signal judging module II is connected with the promotion signal receiving and processing module II; the suppression signal judging module I is respectively connected with the pulse power supply signal, the suppression signal receiving and processing module I and the suppression signal recovering module I; the suppression signal judging module II is connected with the suppression signal receiving and processing module II.
Preferably, the first voltage control unit comprises a voltage control switch S 1 Power supply V 1 And resistance R 1 The method comprises the steps of carrying out a first treatment on the surface of the The second voltage control unit comprises a voltage control switch S 2 Power supply V 2 And resistance R 2 The method comprises the steps of carrying out a first treatment on the surface of the The addition unit comprises a resistor R 3 Resistance R 4 Resistance R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 Resistance R 11 Operational amplifier OP 1 And operational amplifier OP 2 ；
Voltage-controlled switch S 1 Non-inverting input of NAND gate D 1 Is connected with the output end of the voltage-controlled switch S 1 Respectively with resistor R 1 One end of (1) resistor R 3 Is connected with one end of a voltage-controlled switch S 1 Second contact of (2) and power supply V 1 Is connected with the positive electrode of the power supply V 1 Negative electrode of (d), resistance R 1 And voltage-controlled switch S 1 The inverting input ends of the two are grounded;
voltage-controlled switch S 2 The positive input end of (2) is connected with a pulse power supply signal, and the voltage-controlled switch S 2 Respectively with resistor R 2 One end of (1) resistor R 4 Is connected with one end of a voltage-controlled switch S 2 Second contact of (2) and power supply V 2 Is connected with the positive electrode of the power supply V 2 Negative electrode of (d), resistance R 2 And voltage-controlled switch S 2 The inverting input ends of the two are grounded;
resistor R 3 Respectively with resistor R at the other end 5 One end of (1) resistor R 7 Is connected to one end of the operational amplifier OP 1 Is connected with the non-inverting input terminal of the resistor R 5 The other end of the resistor R is connected with the suppression signal receiving and processing module I 7 Is provided with the other end and the suppression signal receiving and processing moduleII, connecting; resistor R 4 Respectively with resistor R at the other end 6 One end of (1) resistor R 8 Is connected to one end of the operational amplifier OP 1 Is connected with the non-inverting input terminal of the resistor R 6 The other end of the resistor R is connected with the promotion signal receiving processing module I 8 The other end of the signal receiving and processing module II is connected with an operational amplifier OP 1 Is not connected to the operational amplifier OP 1 Is connected with a resistor R between the output ends of 9 Operational amplifier OP 1 Output terminal of (d) and resistor R 10 Is connected with one end of resistor R 10 Is connected with the other end of the operational amplifier OP 2 Is connected with the inverting input terminal of the operational amplifier OP 2 Is connected to the inverting input terminal of the operational amplifier OP 2 Is connected with a resistor R between the output ends of 11 Operational amplifier OP 2 The output ends of the (a) are respectively connected with the voltage module I and the voltage module II, and the operational amplifier OP 2 Is connected to the non-inverting input terminal of the operational amplifier OP 1 The inverting input terminals of which are grounded.
Preferably, the voltage module I includes memristance M 1 Memristor M 2 Capacitance C 1 Resistance R 12 And operational amplifier OP 3 The synaptic module I comprises memristors M 5 Resistance R 14 Operational amplifier OP 4 Arithmetic unit ABM 1 Operational amplifier OP 17 And power supply V 5 The method comprises the steps of carrying out a first treatment on the surface of the The memristance M 1 K pole of (C) and memristance M 2 K-pole of (a) and operational amplifier OP 2 Is connected with the output end of the memristor M 1 Is of the A pole and memristance M 2 The A pole of (a) is connected with the operational amplifier OP 3 Is connected with the inverting input terminal of the operational amplifier OP 3 Is connected to the inverting input terminal of the operational amplifier OP 3 Is connected with a resistor R between the output ends of 12 Resistance R 12 A capacitor C is connected in parallel with 1 Operational amplifier OP 3 Respectively with memristor M 5 K pole of (a) mathematical operation unit ABM 1 IN of (2) 2 Input ends are connected with each other, memristor M 5 A pole of (a) and operational amplifier OP 4 Is connected with the inverting input terminal of the operational amplifier OP 4 Is the inverse of (2)Phase input terminal and operational amplifier OP 4 Is connected with a resistor R between the output ends of 14 Operational amplifier OP 4 Output terminal of (a) and mathematical operation unit ABM 1 IN of (2) 1 Input ends are connected, and the mathematical operation unit ABM 1 OUT output terminal of (a) and operational amplifier OP 17 Is connected with the non-inverting input terminal of the operational amplifier OP 17 Is connected with the power supply V 5 Is connected with the positive electrode of the operational amplifier OP 17 The output end of the (a) is respectively connected with the suppression signal judging module II and the promotion signal judging module II; operational amplifier OP 3 Is not connected with the normal phase input end of the operational amplifier OP 4 Is connected with the positive input terminal of the power supply V 5 The negative electrodes of the battery are grounded.
Preferably, the voltage module II comprises memristance M 3 Memristor M 4 Capacitance C 2 Resistance R 13 Operational amplifier OP 5 The synaptic module II comprises memristors M 6 Resistance R 15 Operational amplifier OP 6 Arithmetic unit ABM 2 Operational amplifier OP 7 Operational amplifier OP 8 Power supply V 6 And power supply V 7 The method comprises the steps of carrying out a first treatment on the surface of the Memristor M 3 K pole of (C) and memristance M 4 K-pole of (a) and operational amplifier OP 2 Is connected with the output end of the memristor M 3 Is of the A pole and memristance M 4 The A pole of (a) is connected with the operational amplifier OP 5 Is connected with the inverting input terminal of the operational amplifier OP 5 Is connected to the inverting input terminal of the operational amplifier OP 5 Is connected with a resistor R between the output ends of 13 Resistance R 13 A capacitor C is connected in parallel with 2 Operational amplifier OP 5 Respectively with memristor M 6 K pole of (a) mathematical operation unit ABM 2 IN of (2) 2 Input ends are connected with each other, memristor M 6 A pole of (a) and operational amplifier OP 6 Is connected with the inverting input terminal of the operational amplifier OP 6 Is connected to the inverting input terminal of the operational amplifier OP 6 Is connected with a resistor R between the output ends of 15 Operational amplifier OP 6 Output terminal of (a) and mathematical operation unit ABM 2 IN of (2) 1 Input ends are connected, and the mathematical operation unit ABM 2 OU of (2)The T output end is respectively connected with the operational amplifier OP 7 Is not connected with the normal phase input end of the operational amplifier OP 8 Is connected with the inverting input terminal of the operational amplifier OP 7 Is connected with the power supply V 6 Is connected with the positive electrode of the operational amplifier OP 7 The output ends of the (a) are respectively connected with the suppression signal judging module I and the suppression signal receiving and processing module II, and the operational amplifier OP 8 Is connected with the positive input end of the power supply V 7 Is connected with the positive electrode of the operational amplifier OP 8 The output end of the (a) is respectively connected with the promotion signal judging module I and the promotion signal receiving and processing module II; operational amplifier OP 5 Is not connected with the normal phase input end of the operational amplifier OP 6 Positive phase input terminal of (2) power supply V 6 Is connected with the negative electrode of the power supply V 7 The negative electrodes of the battery are grounded.
Preferably, the suppression signal judging module I includes an and gate D 2 Voltage-controlled switch S 3 Voltage pulse source V 3 And resistance R 16 The method comprises the steps of carrying out a first treatment on the surface of the The inhibition signal receiving and processing module I comprises memristors M 7 Operational amplifier OP 9 And resistance R 17 The method comprises the steps of carrying out a first treatment on the surface of the The suppression signal recovery module I comprises a voltage-controlled switch S 5 And resistance R 18 The method comprises the steps of carrying out a first treatment on the surface of the The AND gate D 2 The input end of (a) is respectively connected with a pulse power signal and an operational amplifier OP 7 Is connected with the output end of the AND gate D 2 Output terminal of (d) and voltage-controlled switch S 3 Is connected with the positive input terminal of the voltage-controlled switch S 3 Is grounded, and a voltage-controlled switch S 3 Respectively with memristance M 7 K pole, resistance R of (2) 16 Is connected with one end of a voltage-controlled switch S 3 Second contact of (2) and voltage pulse source V 3 Is connected with the positive electrode of the voltage pulse source V 3 Respectively with the resistor R 16 Is a voltage-controlled switch S 5 Is connected with the non-inverting input terminal of the voltage pulse source V 3 Is grounded, memristor M 7 A pole of (a) and operational amplifier OP 9 Is connected with the inverting input terminal of the operational amplifier OP 9 Is connected to the inverting input terminal of the operational amplifier OP 9 Is connected with a resistor R between the output ends of 17 Operational amplifier OP 9 Is grounded at the non-inverting input end of the transformer,operational amplifier OP 9 Output terminal of (d) and resistor R 5 Is connected with the other end of the voltage-controlled switch S 5 First contact of (a) and resistance R 18 Is connected with one end of a voltage-controlled switch S 5 Second contact of (2) and resistor R 5 Is connected with the other end of the resistor R 18 And voltage-controlled switch S 5 The inverting input ends of the two are grounded;
the suppression signal judging module II comprises an NMOS tube T 1 Resistance R 29 Power supply V 8 And power supply V 9 The method comprises the steps of carrying out a first treatment on the surface of the The inhibition signal receiving processing module II comprises memristor M 8 Capacitance C 3 Resistance R 19 Operational amplifier OP 10 SUM of voltages unit SUM 1 Operational amplifier OP 11 And power supply V 10 The method comprises the steps of carrying out a first treatment on the surface of the The NMOS tube T 1 Gate of (d) and operational amplifier OP 17 Is connected with the output end of NMOS tube T 1 The drain electrode of (a) is respectively connected with the resistor R 29 One end of (C) memristance M 8 The A pole of (C) is connected with the resistor R 29 Is connected with the other end of the power supply V 8 Is connected with the positive electrode of the power supply V 8 Is grounded with the negative electrode of NMOS tube T 1 Source of (d) and power supply V 9 Is connected with the positive electrode of the power supply V 9 Is grounded, memristor M 8 K pole of (a) and operational amplifier OP 10 Is connected with the inverting input terminal of the operational amplifier OP 10 Is connected to the inverting input terminal of the operational amplifier OP 10 Is connected with a resistor R between the output ends of 19 Resistance R 19 A capacitor C is connected in parallel with 3 Operational amplifier OP 10 Is grounded, and operational amplifier OP 10 Output terminal of (a) and voltage summing unit SUM 1 Is connected to the first input terminal of the voltage summing unit SUM 1 Is connected to the second input terminal of the operational amplifier OP 7 Is connected with the output end of the voltage summation unit SUM 1 Output terminal of (a) and operational amplifier OP 11 Is connected with the inverting input terminal of the operational amplifier OP 11 Is connected with the positive input end of the power supply V 10 Is connected with the positive electrode of the operational amplifier OP 11 Output terminal of (d) and resistor R 7 Is connected with the other end of the power supply V 10 The negative electrode of (2) is grounded.
Preferably, the promotion signal determination module I includes an and gate D 3 Voltage-controlled switch S 4 Voltage pulse source V 4 And resistance R 20 The method comprises the steps of carrying out a first treatment on the surface of the The signal receiving and processing module I comprises memristance M 9 Operational amplifier OP 12 And resistance R 21 The method comprises the steps of carrying out a first treatment on the surface of the The signal recovery promoting module I comprises a voltage-controlled switch S 6 And resistance R 22 The method comprises the steps of carrying out a first treatment on the surface of the The promotion signal judging module II comprises an NMOS tube T 2 Resistance R 30 Power supply V 11 And power supply V 12 The method comprises the steps of carrying out a first treatment on the surface of the The inhibition signal receiving and processing module II memristor M 10 Capacitance C 4 Resistance R 23 Operational amplifier OP 13 SUM of voltages unit SUM 2 NOT gate D 5 Operational amplifier OP 14 And power supply V 13 ；
The AND gate D 3 Respectively NAND gate D at the input end of (a) 1 Output terminal of (a), operational amplifier OP 8 Is connected with the output end of the AND gate D 3 Output terminal of (d) and voltage-controlled switch S 4 Is connected with the positive input terminal of the voltage-controlled switch S 4 Is grounded, and a voltage-controlled switch S 4 Respectively with memristance M 9 K pole, resistance R of (2) 20 Is connected with one end of a voltage-controlled switch S 4 Second contact of (2) and voltage pulse source V 4 Is connected with the positive electrode of the voltage pulse source V 4 Respectively with the resistor R 20 Is a voltage-controlled switch S 6 Is connected with the non-inverting input terminal of the voltage pulse source V 4 Is grounded, memristor M 9 A pole of (a) and operational amplifier OP 12 Is connected with the inverting input terminal of the operational amplifier OP 12 Is connected to the inverting input terminal of the operational amplifier OP 12 Is connected with a resistor R between the output ends of 21 Operational amplifier OP 12 Is grounded, and operational amplifier OP 12 Output terminal of (d) and resistor R 6 Is connected with the other end of the voltage-controlled switch S 6 First contact of (a) and resistance R 22 Is connected with one end of a voltage-controlled switch S 6 Second contact of (2) and resistor R 6 Is connected with the other end of the resistor R 22 And the other end of (2) is pressure-controlled to openSwitch S 6 The inverting input ends of the two are grounded;
the NMOS tube T 2 Gate of (d) and operational amplifier OP 17 Is connected with the output end of NMOS tube T 2 The drain electrode of (a) is respectively connected with the resistor R 30 One end of (C) memristance M 10 The A pole of (C) is connected with the resistor R 30 Is connected with the other end of the power supply V 11 Is connected with the positive electrode of the power supply V 11 Is grounded with the negative electrode of NMOS tube T 2 Source of (d) and power supply V 12 Is connected with the positive electrode of the power supply V 12 Is grounded, memristor M 10 K pole of (a) and operational amplifier OP 13 Is connected with the inverting input terminal of the operational amplifier OP 13 Is connected to the inverting input terminal of the operational amplifier OP 13 Is connected with a resistor R between the output ends of 23 Resistance R 23 A capacitor C is connected in parallel with 4 Operational amplifier OP 13 Is grounded, and operational amplifier OP 13 Output terminal of (a) and voltage summing unit SUM 2 Is connected to the first input terminal of the voltage summing unit SUM 2 And a second input NAND gate D 5 Output terminals of (a) are connected with each other, not gate D 5 Input terminal of (a) and operational amplifier OP 8 Is connected with the output end of the voltage summation unit SUM 2 Output terminal of (a) and operational amplifier OP 14 Is connected with the inverting input terminal of the operational amplifier OP 14 Is connected with the positive input end of the power supply V 13 Is connected with the positive electrode of the operational amplifier OP 14 Output terminal of (d) and resistor R 8 Is connected with the other end of the power supply V 13 The negative electrode of (2) is grounded.
Preferably, the voltage judging module includes a PMOS transistor T 3 Resistance R 24 Power supply V 15 Power supply V 16 NMOS tube T 4 Resistance R 25 Power supply V 17 Power supply V 18 And gate D 4 Voltage-controlled switch S 7 Voltage pulse source V 14 Resistance R 26 SUM-voltage summing unit SUM 3 ；
The pulse power supply signal is respectively connected with the PMOS tube T 3 Gate of (D) and gate D 4 And a voltage-controlled switch S 7 Is connected with the normal phase input end of (C)PMOS tube T 3 The drain electrode of (a) is respectively connected with the resistor R 24 One end of NMOS tube T 4 The grid electrode of (C) is connected with the resistor R 24 Is connected with the other end of the power supply V 15 Is connected with the positive electrode of the power supply V 15 The negative electrode of the PMOS tube T is grounded 3 Source of (d) and power supply V 16 Is connected with the positive electrode of the power supply V 16 Is grounded with the negative electrode of NMOS tube T 4 The drain electrode of (a) is respectively connected with the resistor R 25 And gate D 4 Is connected with the input end of the resistor R 25 Is connected with the other end of the power supply V 17 Is connected with the positive electrode of the power supply V 17 Is grounded with the negative electrode of NMOS tube T 4 Source of (d) and power supply V 18 Is connected with the positive electrode of the power supply V 18 Is grounded; voltage-controlled switch S 7 Respectively with resistor R 26 One end of (a) and voltage summing unit SUM 3 Is connected to the first input terminal of the voltage-controlled switch S 7 Second contact of (2) and voltage pulse source V 14 Positive electrode of (a) is connected with a voltage-controlled switch S 7 Is connected with the inverting input terminal of the voltage pulse source V 14 Negative electrode of (2) and resistance R 26 The other ends of the two electrodes are grounded; AND gate D 4 Output terminal of (a) and voltage summing unit SUM 3 Is connected to the second input terminal of the voltage summing unit SUM 3 The output end of the voltage receiving and processing module is connected with the voltage receiving and processing module.
Preferably, the voltage receiving processing module comprises memristance M 11 Current source I 1 Current source I 2 PMOS tube T 5 PMOS tube T 6 NMOS tube T 7 NMOS tube T 8 NMOS tube T 9 PMOS tube T 10 PMOS tube T 11 NMOS tube T 12 Resistance R 27 Power supply V 19 And power supply V 20 The method comprises the steps of carrying out a first treatment on the surface of the The voltage summation unit SUM 3 Respectively with memristor M 11 A pole, resistance R of (2) 27 Is connected with one end of memristor M 11 K pole of (C) is respectively connected with PMOS tube T 6 Source electrode of NMOS transistor T 12 The source electrodes of the PMOS tube T are connected 6 Gate of (c) and current source I 1 Is connected with the negative pole of the current source I 1 The positive electrode of (a) is respectively connected with the NMOS tube T 7 Source, power supply V 19 Positive electrode of (2) and NMOS transistor T 8 Is connected with the source of the power supply V 19 Is grounded at the negative electrode of the current source I 1 The negative electrode of (a) is respectively connected with the PMOS tube T 5 Drain electrode of PMOS tube T 5 The grid electrode of the PMOS tube T is connected with 5 Source and NMOS transistor T 9 The source electrodes of the NMOS transistor T are all grounded 9 Drain electrode of NMOS transistor T 9 Gate and NMOS transistor T of (2) 12 Are all connected with the grid of the current source I 2 Is connected with the positive electrode of the current source I 2 Respectively with the negative electrode of the power supply V 20 Positive electrode of PMOS tube T 10 Source electrode of (C) and PMOS tube T 11 Is connected with the source of the power supply V 20 The negative electrode of the PMOS tube T is grounded 10 Drain electrode of PMOS tube T 10 Gate and PMOS transistor T 11 The grid electrode of (C) is connected with NMOS tube T 12 The drain electrodes of the PMOS tube T are connected 11 The drain electrode of (a) is respectively connected with the resistor R 27 Is the other end of NMOS tube T 8 Is connected with the synaptic neuron module III, NMOS tube T 8 Gate, NMOS transistor T 7 Gate, NMOS transistor T 7 Drain electrodes of (C) and PMOS tube T 6 Is connected to the drain of the transistor.
Preferably, the synaptic neuron module III comprises a memristor M 12 Resistance R 28 Operational amplifier OP 15 Arithmetic unit ABM 3 Power supply V 21 And operational amplifier OP 16 Resistance R 27 Is respectively connected with memristor M at the other end 12 K pole of (a) mathematical operation unit ABM 3 IN of (2) 2 Input ends are connected with each other, memristor M 12 A pole of (a) and operational amplifier OP 15 Is connected with the inverting input terminal of the operational amplifier OP 15 Is connected to the inverting input terminal of the operational amplifier OP 15 Is connected with a resistor R between the output ends of 28 Operational amplifier OP 15 Is grounded, and operational amplifier OP 15 Output terminal of (a) and mathematical operation unit ABM 3 IN of (2) 1 Input ends are connected, and the mathematical operation unit ABM 3 OUT output terminal of (a) and operational amplifier OP 16 Is connected with the non-inverting input terminal of the operational amplifier OP 16 Is connected with the power supply V 21 Is connected with the positive electrode of the power supply V 21 Negative of (2)The pole is grounded.
Compared with the prior art, the invention has the beneficial effects that:
1) According to the invention, the operational condition reflection is realized through the memristive circuit, different types of stimulus are given to the behavior result made by the biological individual, the frequency of occurrence of the result in the future can be changed, and the important significance is provided for more intelligentization of the brain-like nerve.
2) Different reactions of pigeons to positive rewards and negative penalties in different states can be realized, and a mutual promotion inhibition relation between the positive rewards and the negative penalties can be realized.
3) Through the two groups of memristive positive and negative parallel circuits, the process of operational condition reflection is realized, the promotion and inhibition relation among different emotions is realized, and the influence of instantaneity and satiety on the operational condition reflection is realized.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of the circuit principle of the present invention.
Fig. 2 is a simulation result diagram of the present invention in a specific environment of 0-90S, wherein 0-30S is a simulation result diagram in a starved and noiseless environment, 30-60S is a simulation result diagram in a starved and noiseless environment, and 60-90S is a simulation result diagram in a satiated and noiseless environment.
Fig. 3 is a graph of simulation results of output voltages of the promotion suppression module according to the present invention.
FIG. 4 is a memristor M of the present disclosure 1 、M 2 、M 3 、M 4 、M 7 、M 8 、M 9 And M 10 Is a simulation result graph of (1).
FIG. 5 is a graph of simulation results for instant comparison of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without any inventive effort, are intended to be within the scope of the invention.
First, the functions realized by the present invention will be described: in the stellera operativeness condition reflection theory, if a pigeon pecks red balls in a starving and noiseless environment, the pigeon can obtain food which belongs to positive rewards, the repetition rate of the pigeon pecking the red balls can be increased, and the forward enhancement in operativity condition reflection is realized, as shown in a 0-30S food graph in fig. 2; if the pigeons peck basketball, the pigeons can be subjected to electric shock, the electric shock belongs to negative punishment, the repetition rate of the pigeons pecking basketball can be reduced, and the forward punishment in the reflection of the operational condition is realized, as shown in a 0-30S electric shock diagram in fig. 2; if the pigeons peck yellow balls, the yellow balls represent noise elimination, and the repetition rate for the pigeons pecking yellow balls is unchanged, as shown in the noise elimination chart of 0-30S in FIG. 2. If the pigeons peck the red balls in a starving and noisy environment, the pigeons can get food which belongs to positive rewards and increase the repetition rate of pecking the red balls, as shown in a 30-60S food graph in fig. 2; if the pigeons peck basketball, the pigeons can be subjected to electric shock, the electric shock belongs to negative punishment, the repetition rate of the pigeons pecking basketball can be reduced, and the negative punishment in the reflection of the operational condition is realized, as shown in a 30-60S electric shock diagram in fig. 2; if the pigeons peck yellow balls, noise is eliminated, and the repetition rate of the pigeons pecking yellow balls is increased, as shown in the noise elimination chart of 30-60S in FIG. 2. If the pigeon pecks the red ball in a satiated and noisy environment, the pigeon is in a satiated state, so that the pigeon has no desire for food, and the repetition rate of pecking the red ball by the pigeon is unchanged, as shown in a 60-90S food graph in FIG. 2; if the pigeon pecks the basketball, the pigeon receives electric shock, the electric shock belongs to negative punishment, and the repetition rate of the pigeon pecking the basketball is reduced, as shown in a 60-90S electric shock diagram in fig. 2; if the pigeons peck yellow balls, noise is eliminated, the repetition rate of the pigeons pecking yellow balls is increased, and escape in negative enhancement in the reflection of the operational condition is realized, as shown in the noise elimination diagrams of 60-90S in FIG. 2. If the pigeon pecks the green ball, the green ball does not belong to positive rewarding or negative punishment, the pigeon can slowly forget, and the regression in the reflection of the operational condition is realized.
Under the condition of no use, the pigeons can realize the operative condition reflection by pecking balls with different colors; the satiety of the pigeons was analyzed by hunger and satiation status, and the instantaneity of the pigeons was analyzed by whether or not the pigeons were immediately acting.
As shown in fig. 1, an embodiment of the present invention provides a memristive-based operational condition-reflecting circuit, including an input module, a voltage control module, an acceleration module I, an acceleration module II, a suppression module I, a suppression module II, a synaptic neuron module I, a synaptic neuron module II, and a synaptic neuron module III; the input module is respectively connected with the pulse power supply signal, the promotion module I, the promotion module II, the inhibition module I, the inhibition module II, the synaptic neuron module I and the synaptic neuron module II, the synaptic neuron module II is respectively connected with the promotion module I, the promotion module II, the inhibition module I and the inhibition module II, and the synaptic neuron module I is respectively connected with the promotion module II and the inhibition module II; the pulse power supply signal is respectively connected with a voltage control module and a suppression module I, and the voltage control module is connected with a synaptic neuron module III. By inhibiting the module I, the operational conditional reflection of negative punishment is realized; by suppressing the module II, forward enhanced operational conditional reflection is realized; through the promotion module I, the negative penalty is realized to have promotion effect on positive excitation; by facilitating block ii, achieving positive stimulus is inhibitory to negative penalty.
The input module comprises a first voltage control unit, a second voltage control unit and an addition operation unit; the synaptic neuron module I comprises a voltage module I and a synaptic module I; the synaptic neuron module II comprises a voltage module II and a synaptic module II; the suppression module I comprises a suppression signal judging module I, a suppression signal receiving and processing module I and a suppression signal recovery module I; the suppression module II comprises a suppression signal judging module II and a suppression signal receiving and processing module II; the promotion module I comprises a promotion signal judgment module I, a promotion signal receiving and processing module I and a promotion signal recovery module I; the promotion module II comprises a promotion signal judgment module II and a promotion signal receiving processing module II; the voltage control module comprises a voltage judging module and a voltage receiving and processing module.
The input end of the first voltage-controlled unit is provided with a NAND gate D 1 Output terminals of (a) are connected with each other, not gate D 1 The input end of the voltage control unit is connected with a pulse power supply signal, the pulse power supply signal is respectively connected with the input end of the second voltage control unit, the inhibition signal judging module I and the voltage judging module, the voltage judging module is connected with the voltage receiving processing module, and the voltage receiving processing module is connected with the synaptic neuron module III; the output end of the first voltage control unit and the output end of the second voltage control unit are respectively connected with the input end of the addition operation unit; the output end of the addition unit is respectively connected with a promotion signal receiving processing module I, a promotion signal receiving processing module II, a suppression signal receiving processing module I, a suppression signal receiving processing module II, a voltage module I and a voltage module II, the voltage module I is connected with a synaptic module I, the synaptic module I is respectively connected with a promotion signal judging module II and a suppression signal judging module II, the voltage module II is connected with a synaptic module II, and the synaptic module II is respectively connected with a suppression signal judging module I, a suppression signal receiving processing module II, a promotion signal judging module I and a promotion signal receiving position module II; promotion signal judging module I respectively NAND gate D 1 The signal prompting judging module II is connected with the signal prompting receiving and processing module II; the suppression signal judging module I is respectively connected with the pulse power supply signal, the suppression signal receiving and processing module I and the suppression signal recovering module I; the suppression signal judging module II is connected with the suppression signal receiving and processing module II.
The first voltage control unit comprises a voltage control switch S 1 Power supply V 1 And resistance R 1 The method comprises the steps of carrying out a first treatment on the surface of the The second voltage control unit comprises a voltage control switch S 2 Power supply V 2 And resistance R 2 The method comprises the steps of carrying out a first treatment on the surface of the The addition is carried outThe computing unit comprises a resistor R 3 Resistance R 4 Resistance R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 Resistance R 11 Operational amplifier OP 1 And operational amplifier OP 2 . The input signal is 4v at 0-30S and 60-90S, and is-4 v at 30-60S.
Voltage-controlled switch S 1 Non-inverting input of NAND gate D 1 Is connected with the output end of the voltage-controlled switch S 1 Respectively with resistor R 1 One end of (1) resistor R 3 Is connected with one end of a voltage-controlled switch S 1 Second contact of (2) and power supply V 1 Is connected with the positive electrode of the power supply V 1 Negative electrode of (d), resistance R 1 And voltage-controlled switch S 1 The inverting input terminals of which are grounded.
Voltage-controlled switch S 2 The positive input end of (2) is connected with a pulse power supply signal, and the voltage-controlled switch S 2 Respectively with resistor R 2 One end of (1) resistor R 4 Is connected with one end of a voltage-controlled switch S 2 Second contact of (2) and power supply V 2 Is connected with the positive electrode of the power supply V 2 Negative electrode of (d), resistance R 2 And voltage-controlled switch S 2 The inverting input terminals of which are grounded.
Resistor R 3 Respectively with resistor R at the other end 5 One end of (1) resistor R 7 Is connected to one end of the operational amplifier OP 1 Is connected with the non-inverting input terminal of the resistor R 5 The other end of the resistor R is connected with the suppression signal receiving and processing module I 7 The other end of the signal receiving and processing module II is connected with the signal receiving and processing module II; resistor R 4 Respectively with resistor R at the other end 6 One end of (1) resistor R 8 Is connected to one end of the operational amplifier OP 1 Is connected with the non-inverting input terminal of the resistor R 6 The other end of the resistor R is connected with the promotion signal receiving processing module I 8 The other end of the signal receiving and processing module II is connected with an operational amplifier OP 1 Is not connected to the operational amplifier OP 1 Is connected with a resistor R between the output ends of 9 Operational amplifierOP device 1 Output terminal of (d) and resistor R 10 Is connected with one end of resistor R 10 Is connected with the other end of the operational amplifier OP 2 Is connected with the inverting input terminal of the operational amplifier OP 2 Is connected to the inverting input terminal of the operational amplifier OP 2 Is connected with a resistor R between the output ends of 11 Operational amplifier OP 2 The output ends of the (a) are respectively connected with the voltage module I and the voltage module II, and the operational amplifier OP 2 Is connected to the non-inverting input terminal of the operational amplifier OP 1 The inverting input terminals of which are grounded.
The voltage module I comprises memristors M 1 Memristor M 2 Capacitance C 1 Resistance R 12 And operational amplifier OP 3 The synaptic module I comprises memristors M 5 Resistance R 14 Operational amplifier OP 4 Arithmetic unit ABM 1 Operational amplifier OP 17 And power supply V 5 The method comprises the steps of carrying out a first treatment on the surface of the The memristance M 1 K pole of (C) and memristance M 2 K-pole of (a) and operational amplifier OP 2 Is connected with the output end of the memristor M 1 Is of the A pole and memristance M 2 The A pole of (a) is connected with the operational amplifier OP 3 Is connected with the inverting input terminal of the operational amplifier OP 3 Is connected to the inverting input terminal of the operational amplifier OP 3 Is connected with a resistor R between the output ends of 12 Resistance R 12 A capacitor C is connected in parallel with 1 Operational amplifier OP 3 Respectively with memristor M 5 K pole of (a) mathematical operation unit ABM 1 IN of (2) 2 Input ends are connected with each other, memristor M 5 A pole of (a) and operational amplifier OP 4 Is connected with the inverting input terminal of the operational amplifier OP 4 Is connected to the inverting input terminal of the operational amplifier OP 4 Is connected with a resistor R between the output ends of 14 Operational amplifier OP 4 Output terminal of (a) and mathematical operation unit ABM 1 IN of (2) 1 Input ends are connected, and the mathematical operation unit ABM 1 OUT output terminal of (a) and operational amplifier OP 17 Is connected with the non-inverting input terminal of the operational amplifier OP 17 Is connected with the power supply V 5 Is connected with the positive electrode of the operational amplifier OP 17 Respectively, the output ends of the (a) and (b) are respectively used for judging the inhibition signalsThe module II is connected with the promotion signal judging module II; operational amplifier OP 3 Is not connected with the normal phase input end of the operational amplifier OP 4 Is connected with the positive input terminal of the power supply V 5 The negative electrodes of the battery are grounded.
Memristance M, as shown by synaptic neuron I in FIG. 1 1 And memristance M 2 K pole of (a) and operational amplifier OP 2 Is connected with the output end of the input signal U in 0-18S 0 Voltage value of less than memristance M 1 And memristance M 2 Memristor M 1 The resistance value of (2) is maintained at 300 omega, and the memristor M 2 The resistance of (2) is maintained at 350 omega, and the signal U is input at 18-30S 0 Voltage value of (a) is greater than memristance M 1 Positive threshold voltage of memristor M 1 The resistance value of (2) is rapidly reduced from 600 omega to 300 omega, and the memristor M 2 The resistance value of (C) is kept unchanged, and a signal U is input at 30-60S 0 Voltage value of (a) is greater than memristance M 1 Negative threshold voltage and memristance M 2 Positive threshold voltage of memristor M 1 The resistance value of (2) rapidly rises to 600 omega, and the memristor M 2 The resistance of (a) is reduced from 350 omega to 300 omega, and the signal U is input at 60-90S 0 Voltage value of less than memristance M 1 And memristance M 2 Memristor M 1 And memristance M 2 The resistance of (c) remains unchanged. Capacitor C 1 Resistance R 12 Operational amplifier OP 3 Is the inverse input terminal of (a) and memristor M 1 And memristance M 2 Is connected with the A pole of the (B) and the operational amplifier OP 3 The non-inverting input terminal of (C) is grounded, the capacitor C 1 Another end, resistance R 12 Another end, operational amplifier OP 3 Output terminal of (2) and memristor M 5 K poles of (C) are connected, at 0-30S, memristor M 5 The resistance value of (2) is reduced from 800 omega to 200 omega, and the memristor M is between 30 and 60S 5 The resistance value of (2) is increased from 200Ω to 1kΩ, and a specific simulation diagram is shown in fig. 4. Memristor M 5 A pole of (2) and a resistor R 14 And operational amplifier OP 4 Is connected with the inverting input terminal of the operational amplifier OP 4 The non-inverting input terminal of (2) is grounded, the resistor R 14 And an operational amplifier OP 4 Output terminal of (a) and mathematical operation unit ABM 1 An input end is connected with the mathematical operation unit ABM 1 Another oneTerminal and capacitor C 1 Another end, resistance R 12 Another end, operational amplifier OP 3 Is connected with the output end of ABM 1 The output value of (2) is-IN 2 /IN 1 *10＝M 5 100, arithmetic unit ABM 1 Output terminal of (a) and operational amplifier OP 17 Is connected with the non-inverting input terminal of the operational amplifier OP 17 Is connected with the power supply V 5 Is connected with the positive electrode of the power supply V 5 Is grounded at the negative electrode of the operational amplifier OP 17 Corresponds to a threshold value of V 5 When OP 17 The voltage received at the non-inverting input of (a) is less than V 5 At the time OP 17 Outputting a voltage of-5V when the received voltage is greater than V 5 At the time OP 17 And 5v voltage is output and fed back to the promotion module II and the inhibition module II. Synaptic neuron module for simulating synapses and neurons in biological neural networks by altering M 5 Can change the magnitude of the synaptic strength, M 5 The smaller the resistance, the greater the synaptic strength.
The voltage module II comprises memristance M 3 Memristor M 4 Capacitance C 2 Resistance R 13 Operational amplifier OP 5 The synaptic module II comprises memristors M 6 Resistance R 15 Operational amplifier OP 6 Arithmetic unit ABM 2 Operational amplifier OP 7 Operational amplifier OP 8 Power supply V 6 And power supply V 7 The method comprises the steps of carrying out a first treatment on the surface of the Memristor M 3 K pole of (C) and memristance M 4 K-pole of (a) and operational amplifier OP 2 Is connected with the output end of the memristor M 3 Is of the A pole and memristance M 4 The A pole of (a) is connected with the operational amplifier OP 5 Is connected with the inverting input terminal of the operational amplifier OP 5 Is connected to the inverting input terminal of the operational amplifier OP 5 Is connected with a resistor R between the output ends of 13 Resistance R 13 A capacitor C is connected in parallel with 2 Operational amplifier OP 5 Respectively with memristor M 6 K pole of (a) mathematical operation unit ABM 2 IN of (2) 2 Input ends are connected with each other, memristor M 6 A pole of (a) and operational amplifier OP 6 Is connected with the inverting input terminal of the (c),operational amplifier OP 6 Is connected to the inverting input terminal of the operational amplifier OP 6 Is connected with a resistor R between the output ends of 15 Operational amplifier OP 6 Output terminal of (a) and mathematical operation unit ABM 2 IN of (2) 1 Input ends are connected, and the mathematical operation unit ABM 2 The OUT output ends of (1) are respectively connected with an operational amplifier OP 7 Is not connected with the normal phase input end of the operational amplifier OP 8 Is connected with the inverting input terminal of the operational amplifier OP 7 Is connected with the power supply V 6 Is connected with the positive electrode of the operational amplifier OP 7 The output ends of the (a) are respectively connected with the suppression signal judging module I and the suppression signal receiving and processing module II, and the operational amplifier OP 8 Is connected with the positive input end of the power supply V 7 Is connected with the positive electrode of the operational amplifier OP 8 The output end of the (a) is respectively connected with the promotion signal judging module I and the promotion signal receiving and processing module II; operational amplifier OP 5 Is not connected with the normal phase input end of the operational amplifier OP 6 Positive phase input terminal of (2) power supply V 6 Is connected with the negative electrode of the power supply V 7 The negative electrodes of the battery are grounded.
Memristance M, as shown by synaptic neuron II in FIG. 1 3 And memristance M 4 K pole of (a) and operational amplifier OP 2 Is connected with the output end of the input signal U 0 Voltage value of less than memristance M 1 And memristance M 2 At a threshold voltage of 0-30S, memristor M 3 And memristance M 4 Is kept unchanged, and is input with a signal U at 30-60S 0 Voltage value of (a) is greater than memristance M 3 And memristance M 4 Negative threshold voltage of memristor M 3 And memristance M 4 The resistance value of (2) is rapidly increased from 300 omega to 600 omega, and the memristor M is realized in 60-90S 3 The resistance value of (a) remains unchanged, input signal U 0 Voltage value of (a) is greater than memristance M 4 Positive threshold voltage of memristor M 4 The resistance of (2) decreases to 300 omega. Capacitor C 2 Resistance R 13 Operational amplifier OP 5 Is the inverse input terminal of (a) and memristor M 3 And memristance M 4 Is connected with the A pole of the (B) and the operational amplifier OP 5 The non-inverting input terminal of (C) is grounded, the capacitor C 2 Another end, resistance R 13 Another end, operational amplifier OP 5 Output terminal of (2)Memristance M 6 K poles of (C) are connected, memristor M is between 0 and 30s 6 The resistance value of (2) is reduced from 900 omega to 200 omega, and the memristor M is between 30 and 60S 5 The resistance value of (2) is increased from 200Ω to 1kΩ, and a specific simulation diagram is shown in fig. 4. Memristor M 6 A pole of (2) and a resistor R 15 And operational amplifier OP 6 Is connected with the inverting input terminal of the operational amplifier OP 6 The non-inverting input terminal of (2) is grounded, the resistor R 15 And an operational amplifier OP 6 Output terminal of (a) and mathematical operation unit ABM 2 An input end is connected with the mathematical operation unit ABM 2 The other end and the capacitor C 2 Another end, resistance R 13 Another end, operational amplifier OP 5 Is connected with the output end of ABM 2 The output value of (2) is-IN 2 /IN 1 *10＝M 6 100, arithmetic unit ABM 2 Output terminal of (a) and operational amplifier OP 7 Is connected with the non-inverting input terminal of the operational amplifier OP 7 Is connected with the power supply V 6 Is connected with the positive electrode of the operational amplifier OP 7 Corresponds to a threshold value of V 6 When OP 7 The voltage received at the non-inverting input of (a) is greater than V 5 At the time OP 17 Outputting 5V voltage when the received voltage is less than V 5 At the time, operational amplifier OP 7 Outputting 0v voltage and feeding the voltage back to the promotion module I; mathematical operation unit ABM 2 Output terminal of (a) and operational amplifier OP 8 Is connected to the inverting input terminal of (a) when OP 8 The voltage received at the inverting input of (a) is less than V 7 At the time OP 17 Outputting 5V voltage when the received voltage is greater than V 7 At the time, operational amplifier OP 8 And outputting 0v voltage and feeding the voltage back to the inhibition promotion module II. Synaptic neuron module for simulating synapses and neurons in biological neural networks by altering M 6 Can change the magnitude of the synaptic strength, M 6 The smaller the resistance, the greater the synaptic strength.
The inhibition signal judging module I comprises an AND gate D 2 Voltage-controlled switch S 3 Voltage pulse source V 3 And resistance R 16 The method comprises the steps of carrying out a first treatment on the surface of the The inhibition signal receiving and processing module I comprises memristors M 7 Transporting and transportingOperational amplifier OP 9 And resistance R 17 The method comprises the steps of carrying out a first treatment on the surface of the The suppression signal recovery module I comprises a voltage-controlled switch S 5 And resistance R 18 The method comprises the steps of carrying out a first treatment on the surface of the The AND gate D 2 The input end of (a) is respectively connected with a pulse power signal and an operational amplifier OP 7 Is connected with the output end of the AND gate D 2 Output terminal of (d) and voltage-controlled switch S 3 Is connected with the positive input terminal of the voltage-controlled switch S 3 Is grounded, and a voltage-controlled switch S 3 Respectively with memristance M 7 K pole, resistance R of (2) 16 Is connected with one end of a voltage-controlled switch S 3 Second contact of (2) and voltage pulse source V 3 Is connected with the positive electrode of the voltage pulse source V 3 Respectively with the resistor R 16 Is a voltage-controlled switch S 5 Is connected with the non-inverting input terminal of the voltage pulse source V 3 Is grounded, memristor M 7 A pole of (a) and operational amplifier OP 9 Is connected with the inverting input terminal of the operational amplifier OP 9 Is connected to the inverting input terminal of the operational amplifier OP 9 Is connected with a resistor R between the output ends of 17 Operational amplifier OP 9 Is grounded, and operational amplifier OP 9 Output terminal of (d) and resistor R 5 Is connected with the other end of the voltage-controlled switch S, outputs negative punishment inhibiting voltage 5 First contact of (a) and resistance R 18 Is connected with one end of a voltage-controlled switch S 5 Second contact of (2) and resistor R 5 Is connected with the other end of the resistor R 18 And voltage-controlled switch S 5 The inverting input terminals of which are grounded.
As shown in the inhibition module I of FIG. 1, the synaptic neuron module II outputs a signal U 2 And pulse power supply signal output signal U 6 Control inhibition signal judging module I outputs signal U when synapse neuron module II outputs signal U 2 Output signal U of pulse power supply signal 6 All output high level, AND gate D 2 The turn-on and inhibit signal judging module I starts to respond to make the voltage-controlled switch S 3 On output power V 3 The output end of the voltage-controlled switch is connected with a protection resistor R 16 Protection resistor R 16 Is a voltage-controlled switch S 3 Negative input terminal and voltage pulse source V 3 The negative electrodes are all grounded, and the voltage-controlled switch S 3 Is connected with memristance M 7 Is connected with the A pole of the voltage-controlled switch S 3 The output voltage value of one contact of (a) is smaller than memristance M 7 Memristor M 7 The resistance of (2) is maintained at 50Ω; when the voltage is controlled by the switch S 3 The output voltage of one contact of (a) is larger than memristance M 7 Memristor M 7 The resistance of (2) drops to 32Ω, as shown in FIG. 4, memristance M 7 K pole of (a) and operational amplifier OP 9 Is an inverting input terminal of (a) and a resistor R 17 Is connected to make the operational amplifier OP 9 Is output into the input signal as shown by V (R5) in fig. 3 for achieving a negative penalty in the reflection of the operational conditions. Voltage-controlled switch S 5 Is connected with the positive input end of the voltage pulse source V 3 Is connected with the negative pole of the voltage-controlled switch S 5 And a protection resistor R 18 Is connected with a protection resistor R 18 And voltage-controlled switch S 5 All negative input ends of (1) are grounded to enable memristor M 7 And the resistance value of (2) is recovered.
The suppression signal judging module II comprises an NMOS tube T 1 Resistance R 29 Power supply V 8 And power supply V 9 The method comprises the steps of carrying out a first treatment on the surface of the The inhibition signal receiving processing module II comprises memristor M 8 Capacitance C 3 Resistance R 19 Operational amplifier OP 10 SUM of voltages unit SUM 1 Operational amplifier OP 11 And power supply V 10 The method comprises the steps of carrying out a first treatment on the surface of the The NMOS tube T 1 Gate of (d) and operational amplifier OP 17 Is connected with the output end of NMOS tube T 1 The drain electrode of (a) is respectively connected with the resistor R 29 One end of (C) memristance M 8 The A pole of (C) is connected with the resistor R 29 Is connected with the other end of the power supply V 8 Is connected with the positive electrode of the power supply V 8 Is grounded with the negative electrode of NMOS tube T 1 Source of (d) and power supply V 9 Is connected with the positive electrode of the power supply V 9 Is grounded, memristor M 8 K pole of (a) and operational amplifier OP 10 Is connected with the inverting input terminal of the operational amplifier OP 10 Is connected to the inverting input terminal of the operational amplifier OP 10 Between the output terminals of (a)Is connected with a resistor R 19 Resistance R 19 A capacitor C is connected in parallel with 3 Operational amplifier OP 10 Is grounded, and operational amplifier OP 10 Output terminal of (a) and voltage summing unit SUM 1 Is connected to the first input terminal of the voltage summing unit SUM 1 Is connected to the second input terminal of the operational amplifier OP 7 Is connected with the output end of the voltage summation unit SUM 1 Output terminal of (a) and operational amplifier OP 11 Is connected with the inverting input terminal of the operational amplifier OP 11 Is connected with the positive input end of the power supply V 10 Is connected with the positive electrode of the operational amplifier OP 11 Output terminal of (d) and resistor R 7 Is connected to the other end of the power supply, and outputs a negative penalty suppression voltage for positive rewards, as shown by V (R7) in FIG. 3 10 The negative electrode of (2) is grounded.
As shown in the inhibition module II of FIG. 1, the synaptic neuron module I outputs a signal U 1 Control inhibition signal judging module II outputs signal U when synaptic neuron module I outputs signal U 1 When outputting high level, NMOS tube T 1 Output pass protection resistor R 29 Is a power supply V of (2) 8 Power supply V 8 Output low level, memristor M 8 A pole of (2) and NMOS transistor T 1 Is connected with a power supply V 8 Is lower than memristance M 8 As shown in FIG. 4, memristor M 8 The resistance of (2) is maintained at 1KΩ; when the synaptic neuron module II outputs a signal U 1 When outputting low level, NMOS tube T 1 Power supply V outputting high level 8 Greater than memristance M 8 Memristor M 8 The resistance value of (2) is rapidly reduced to 100 omega, and the memristor M 8 K pole of (a) and operational amplifier OP 9 An inverting input terminal of (a) and a resistor R 19 Connected with the capacitor C3, memristor M 8 K pole of (C) is respectively connected with capacitor C 3 One end of (1) resistor R 19 Is connected to one end of the operational amplifier OP 10 Is connected to the inverting input of the operational amplifier OP 10 Is grounded, and a voltage summing unit SUM 1 Respectively with the capacitor C 3 The other end of (C) and the resistor R 19 And an operational amplifier OP 10 Output phase of (2)Connected, the inhibitory signal of synaptic neuron II passes through voltage summation unit SUM 1 Is input to another input terminal of the operational amplifier OP 11 Is connected to the inverting input of the voltage summing unit SUM 1 Is connected with the output end of the power supply V 10 Positive electrode of (a) and operational amplifier OP 11 Is connected to the non-inverting input of the voltage summing unit SUM 1 Is greater than the power supply V 10 The voltage of (1) is an operational amplifier OP 11 Output-0.4 v voltage, if the SUM is a cell 1 Is smaller than the power supply V 10 The voltage of (1) is an operational amplifier OP 11 Output 0.2v voltage, OP 11 The output signal of the (a) is fed back to the input signal, and the negative punishment suppression function of the positive rewards is realized.
The promotion signal judging module I comprises an AND gate D 3 Voltage-controlled switch S 4 Voltage pulse source V 4 And resistance R 20 The method comprises the steps of carrying out a first treatment on the surface of the The signal receiving and processing module I comprises memristance M 9 Operational amplifier OP 12 And resistance R 21 The method comprises the steps of carrying out a first treatment on the surface of the The signal recovery promoting module I comprises a voltage-controlled switch S 6 And resistance R 22 The method comprises the steps of carrying out a first treatment on the surface of the The promotion signal judging module II comprises an NMOS tube T 2 Resistance R 30 Power supply V 11 And power supply V 12 The method comprises the steps of carrying out a first treatment on the surface of the The inhibition signal receiving and processing module II memristor M 10 Capacitance C 4 Resistance R 23 Operational amplifier OP 13 SUM of voltages unit SUM 2 NOT gate D 5 Operational amplifier OP 14 And power supply V 13 。
The AND gate D 3 Respectively NAND gate D at the input end of (a) 1 Output terminal of (a), operational amplifier OP 8 Is connected with the output end of the AND gate D 3 Output terminal of (d) and voltage-controlled switch S 4 Is connected with the positive input terminal of the voltage-controlled switch S 4 Is grounded, and a voltage-controlled switch S 4 Respectively with memristance M 9 K pole, resistance R of (2) 20 Is connected with one end of a voltage-controlled switch S 4 Second contact of (2) and voltage pulse source V 4 Is connected with the positive electrode of the voltage pulse source V 4 Respectively with the resistor R 20 Another of (2)Terminal voltage-controlled switch S 6 Is connected with the non-inverting input terminal of the voltage pulse source V 4 Is grounded, memristor M 9 A pole of (a) and operational amplifier OP 12 Is connected with the inverting input terminal of the operational amplifier OP 12 Is connected to the inverting input terminal of the operational amplifier OP 12 Is connected with a resistor R between the output ends of 21 Operational amplifier OP 12 Is grounded, and operational amplifier OP 12 Output terminal of (d) and resistor R 6 Is connected with the other end of the voltage-controlled switch S, outputs the promoting voltage of negative punishment to positive rewards 6 First contact of (a) and resistance R 22 Is connected with one end of a voltage-controlled switch S 6 Second contact of (2) and resistor R 6 Is connected with the other end of the resistor R 22 And voltage-controlled switch S 6 The inverting input terminals of which are grounded.
The NMOS tube T 2 Gate of (d) and operational amplifier OP 17 Is connected with the output end of NMOS tube T 2 The drain electrode of (a) is respectively connected with the resistor R 30 One end of (C) memristance M 10 The A pole of (C) is connected with the resistor R 30 Is connected with the other end of the power supply V 11 Is connected with the positive electrode of the power supply V 11 Is grounded with the negative electrode of NMOS tube T 2 Source of (d) and power supply V 12 Is connected with the positive electrode of the power supply V 12 Is grounded, memristor M 10 K pole of (a) and operational amplifier OP 13 Is connected with the inverting input terminal of the operational amplifier OP 13 Is connected to the inverting input terminal of the operational amplifier OP 13 Is connected with a resistor R between the output ends of 23 Resistance R 23 A capacitor C is connected in parallel with 4 Operational amplifier OP 13 Is grounded, and operational amplifier OP 13 Output terminal of (a) and voltage summing unit SUM 2 Is connected to the first input terminal of the voltage summing unit SUM 2 And a second input NAND gate D 5 Output terminals of (a) are connected with each other, not gate D 5 Input terminal of (a) and operational amplifier OP 8 Is connected with the output end of the voltage summation unit SUM 2 Output terminal of (a) and operational amplifier OP 14 Is connected with the inverting input terminal of the operational amplifier OP 14 Is connected with the positive input end of the power supply V 13 Is connected with the positive electrode of the operational amplifier OP 14 Output terminal of (d) and resistor R 8 Is connected with the other end of the power supply V 13 The negative electrode of (2) is grounded.
As shown in the facilitation module I of FIG. 1, the synaptic neuron module II outputs a signal U 4 And pulse power supply signal output signal U 8 Control promoting signal judging module I outputs signal U when synapse neuron module II outputs signal U 4 Output signal U of pulse power supply signal 8 All output high level, AND gate D 3 Conduction, the signal judging module II starts to respond to make the voltage-controlled switch S 4 On output power V 4 The output end of the voltage-controlled switch is connected with a protection resistor R 20 Protection resistor R 20 Is a voltage-controlled switch S 4 Negative input terminal and voltage pulse source V 4 The negative electrodes are all grounded, and the voltage-controlled switch S 4 Is connected with memristance M 9 Is connected with the pole A of (B), if the voltage-controlled switch S 4 The output voltage value of one contact of (a) is smaller than memristance M 9 As shown in FIG. 4, memristor M 9 The resistance of (2) is maintained at 50Ω; when the voltage is controlled by the switch S 4 The output voltage of one contact of (a) is larger than memristance M 9 Memristor M 7 The resistance value of (2) rises to 175 omega quickly, and the memristor M 9 K pole of (a) and operational amplifier OP 12 Is an inverting input terminal of (a) and a resistor R 21 Is connected to make the operational amplifier OP 12 The output voltage of (2) is output to the input signal as shown by V (R6) in fig. 3 to achieve a negative penalty that is a facilitation for positive excitation. Voltage-controlled switch S 6 Is connected with the positive input end of the voltage pulse source V 4 Is connected with the negative pole of the voltage-controlled switch S 6 And a protection resistor R 22 Is connected with a protection resistor R 22 And voltage-controlled switch S 6 All negative input ends of (1) are grounded to enable memristor M 9 And the resistance value of (2) is recovered. As shown in the facilitation module II of FIG. 1, the synaptic neuron module I outputs a signal U 5 Control inhibition signal judging module II outputs signal U when synaptic neuron module I outputs signal U 5 When outputting high level, NMOS tube T 2 Output pass protection resistor R 30 Is a power supply V of (2) 11 Power supply V 11 Output low level, memristor M 10 A pole of (2) and NMOS transistor T 2 Is connected with a power supply V 11 Is lower than memristance M 10 Memristor M 10 Is maintained at 1KΩ when the synaptic neuron module I outputs a signal U 5 When outputting low level, NMOS tube T 2 Power supply V outputting high level 12 Greater than memristance M 10 Memristor M 10 The resistance value of (2) is rapidly reduced to 100 omega, and a specific simulation diagram is shown in FIG. 4, and the memristor M 10 K pole of (a) and operational amplifier OP 13 An inverting input terminal of (a) and a resistor R 23 And capacitor C 4 Connected with memristor M 10 K pole of (C) is respectively connected with capacitor C 4 One end of (1) resistor R 23 Is connected to one end of the operational amplifier OP 13 Is connected to the inverting input of the operational amplifier OP 13 Is grounded, and a voltage summing unit SUM 2 Respectively with the capacitor C 4 The other end of (C) and the resistor R 23 And an operational amplifier OP 13 Is connected with the output end of the synapse neuron II, and the inhibition signal of the synapse neuron II passes through a NOT gate D 5 Connected to a voltage summing unit SUM 1 Is an operational amplifier OP 14 Is connected to the inverting input of the voltage summing unit SUM 2 Is connected with the output end of the power supply V 13 Positive electrode of (a) and operational amplifier OP 14 Is connected to the non-inverting input terminal of the voltage summing unit SUM 2 Is greater than the power supply V 13 The voltage of (1) is an operational amplifier OP 13 Output-0.6 v voltage, if the SUM is a cell 1 Is smaller than the power supply V 10 The voltage of (1) is an operational amplifier OP 11 Output-0.3 v voltage, OP 14 The output signal of (2) is fed back to the input signal, and a promoting voltage of the positive rewards is output, as shown by V (R8) in fig. 3, so that a promoting function is realized.
The voltage judging module comprises a PMOS tube T 3 Resistance R 24 Power supply V 15 Power supply V 16 NMOS tube T 4 Resistance R 25 Power supply V 17 Power supplyV 18 And gate D 4 Voltage-controlled switch S 7 Voltage pulse source V 14 Resistance R 26 SUM-voltage summing unit SUM 3 . The pulse power supply signal is respectively connected with the PMOS tube T 3 Gate of (D) and gate D 4 And a voltage-controlled switch S 7 Is connected with the positive input end of the PMOS tube T 3 The drain electrode of (a) is respectively connected with the resistor R 24 One end of NMOS tube T 4 The grid electrode of (C) is connected with the resistor R 24 Is connected with the other end of the power supply V 15 Is connected with the positive electrode of the power supply V 15 The negative electrode of the PMOS tube T is grounded 3 Source of (d) and power supply V 16 Is connected with the positive electrode of the power supply V 16 Is grounded with the negative electrode of NMOS tube T 4 The drain electrode of (a) is respectively connected with the resistor R 25 And gate D 4 Is connected with the input end of the resistor R 25 Is connected with the other end of the power supply V 17 Is connected with the positive electrode of the power supply V 17 Is grounded with the negative electrode of NMOS tube T 4 Source of (d) and power supply V 18 Is connected with the positive electrode of the power supply V 18 Is grounded; voltage-controlled switch S 7 Respectively with resistor R 26 One end of (a) and voltage summing unit SUM 3 Is connected to the first input terminal of the voltage-controlled switch S 7 Second contact of (2) and voltage pulse source V 14 Positive electrode of (a) is connected with a voltage-controlled switch S 7 Is connected with the inverting input terminal of the voltage pulse source V 14 Negative electrode of (2) and resistance R 26 The other ends of the two electrodes are grounded; AND gate D 4 Output terminal of (a) and voltage summing unit SUM 3 Is connected to the second input terminal of the voltage summing unit SUM 3 The output end of the voltage receiving and processing module is connected with the voltage receiving and processing module.
The voltage receiving processing module comprises memristor M 11 Current source I 1 Current source I 2 PMOS tube T 5 PMOS tube T 6 NMOS tube T 7 NMOS tube T 8 NMOS tube T 9 PMOS tube T 10 PMOS tube T 11 NMOS tube T 12 Resistance R 27 Power supply V 19 And power supply V 20 The method comprises the steps of carrying out a first treatment on the surface of the The voltage summation unit SUM 3 Respectively with memristor M 11 A pole, resistance R of (2) 27 Is connected with one end of memristor M 11 K pole of (C) is respectively connected with PMOS tube T 6 Source electrode of NMOS transistor T 12 The source electrodes of the PMOS tube T are connected 6 Gate of (c) and current source I 1 Is connected with the negative pole of the current source I 1 The positive electrode of (a) is respectively connected with the NMOS tube T 7 Source, power supply V 19 Positive electrode of (2) and NMOS transistor T 8 Is connected with the source of the power supply V 19 Is grounded at the negative electrode of the current source I 1 The negative electrode of (a) is respectively connected with the PMOS tube T 5 Drain electrode of PMOS tube T 5 The grid electrode of the PMOS tube T is connected with 5 Source and NMOS transistor T 9 The source electrodes of the NMOS transistor T are all grounded 9 Drain electrode of NMOS transistor T 9 Gate and NMOS transistor T of (2) 12 Are all connected with the grid of the current source I 2 Is connected with the positive electrode of the current source I 2 Respectively with the negative electrode of the power supply V 20 Positive electrode of PMOS tube T 10 Source electrode of (C) and PMOS tube T 11 Is connected with the source of the power supply V 20 The negative electrode of the PMOS tube T is grounded 10 Drain electrode of PMOS tube T 10 Gate and PMOS transistor T 11 The grid electrode of (C) is connected with NMOS tube T 12 The drain electrodes of the PMOS tube T are connected 11 The drain electrode of (a) is respectively connected with the resistor R 27 Is the other end of NMOS tube T 8 Is connected with the synaptic neuron module III, NMOS tube T 8 Gate, NMOS transistor T 7 Gate, NMOS transistor T 7 Drain electrodes of (C) and PMOS tube T 6 Is connected to the drain of the transistor.
As shown in the voltage control module of fig. 1, a pulse power signal is input into the signal U 6 To the voltage judging module, the PMOS tube T 3 And NMOS tube T 4 Corresponding to a logic gate, when the input signal U6 is at a low level, the PMOS transistor T 3 When the input signal U6 is at high level, the PMOS tube T outputs 0v 3 Is output-2.1 v through the NMOS tube T 4 When PMOS tube T 3 When the drain output of (2) is 0v, NMOS transistor T 4 The drain output of (1) is 0v, as the PMOS tube T 3 When the drain electrode output of the transistor is-2.1 v, the NMOS transistor T 4 Is 1v. Pulse power supply signal input signal U6 and NMOS tube T 4 Drain electrodes of (a) are respectively connected with AND gate D 4 Is connected with two input ends of AND gate D 3 Output ofThe signal outputs-1 v at low level and 1.2v at high level. By applying the third voltage control unit, the instantaneity in the reflection of the operation condition is realized, if the pigeon hears the noise, the yellow ball is not pecked in the first time, the generated negative penalty is larger than that of the instant yellow ball pecking, and even if the subsequent yellow ball pecking is carried out, the effect of eliminating the noise is not good after the instant yellow ball pecking, as shown by V (M) in fig. 5 12 (1) V (M) 12 (2)). Through a current source I 1 Current source I 2 PMOS tube T 5 PMOS tube T 6 NMOS tube T 7 NMOS tube T 8 NMOS tube T 9 PMOS tube T 10 PMOS tube T 11 NMOS tube T 12 Resistance R 27 Power supply V 19 And power supply V 20 The input-output ratio of the current mirror can be adjusted.
The synaptic neuron module III comprises memristors M 12 Resistance R 28 Operational amplifier OP 15 Arithmetic unit ABM 3 Power supply V 21 And operational amplifier OP 16 Resistance R 27 Is respectively connected with memristor M at the other end 12 K pole of (a) mathematical operation unit ABM 3 IN of (2) 2 Input ends are connected with each other, memristor M 12 A pole of (a) and operational amplifier OP 15 Is connected with the inverting input terminal of the operational amplifier OP 15 Is connected to the inverting input terminal of the operational amplifier OP 15 Is connected with a resistor R between the output ends of 28 Operational amplifier OP 15 Is grounded, and operational amplifier OP 15 Output terminal of (a) and mathematical operation unit ABM 3 IN of (2) 1 Input ends are connected, and the mathematical operation unit ABM 3 OUT output terminal of (a) and operational amplifier OP 16 Is connected with the non-inverting input terminal of the operational amplifier OP 16 Is connected with the power supply V 21 Is connected with the positive electrode of the power supply V 21 The negative electrode of (2) is grounded.
As shown in the synaptic neuron III of FIG. 1, the voltage control module outputs a signal U at 0-30S 12 Voltage value of less than memristance M 12 Memristor M 12 The resistance of (2) is maintained at 800 Ω30-60S, the voltage control module outputs a signal U 12 Voltage value of (a) is greater than memristance M 12 Positive threshold voltage of memristor M 5 The resistance of (2) decreases from 800 Ω to 200Ω. Memristor M 12 A pole of (2) and a resistor R 28 And operational amplifier OP 15 Is connected with the inverting input terminal of the operational amplifier OP 15 The non-inverting input terminal of (2) is grounded, the resistor R 28 And an operational amplifier OP 15 Output terminal of (a) and mathematical operation unit ABM 3 An input end is connected with the mathematical operation unit ABM 3 The other end outputs a signal U by the voltage control module 12 Is connected with ABM 3 The output value of (2) is-IN 2 /IN 1 *10＝M 12 100, arithmetic unit ABM 3 Output terminal of (a) and operational amplifier OP 16 Is connected with the non-inverting input terminal of the operational amplifier OP 16 Is connected with the power supply V 21 Is connected with the positive electrode of the power supply V 21 Is grounded at the negative electrode of the operational amplifier OP 16 Corresponds to a threshold value of V 21 When OP 16 The voltage received at the non-inverting input of (a) is less than V 21 At the time OP 16 Outputting 0V voltage when the received voltage is greater than V 5 At the time OP 17 A 5v voltage is output.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (4)
1. A memristive-based operational condition reflex circuit, which is characterized by comprising an input module, a voltage control module, a promotion module I, a promotion module II, a suppression module I, a suppression module II, a synaptic neuron module I, a synaptic neuron module II and a synaptic neuron module III; the input module is respectively connected with the pulse power supply signal, the promotion module I, the promotion module II, the inhibition module I, the inhibition module II, the synaptic neuron module I and the synaptic neuron module II, the synaptic neuron module II is respectively connected with the promotion module I, the promotion module II, the inhibition module I and the inhibition module II, and the synaptic neuron module I is respectively connected with the promotion module II and the inhibition module II; the pulse power supply signal is respectively connected with a voltage control module and a suppression module I, and the voltage control module is connected with a synaptic neuron module III;
the input module comprises a first voltage control unit, a second voltage control unit and an addition operation unit; the synaptic neuron module I comprises a voltage module I and a synaptic module I; the synaptic neuron module II comprises a voltage module II and a synaptic module II; the suppression module I comprises a suppression signal judging module I, a suppression signal receiving and processing module I and a suppression signal recovery module I; the suppression module II comprises a suppression signal judging module II and a suppression signal receiving and processing module II; the promotion module I comprises a promotion signal judgment module I, a promotion signal receiving and processing module I and a promotion signal recovery module I; the promotion module II comprises a promotion signal judgment module II and a promotion signal receiving processing module II; the voltage control module comprises a voltage judging module and a voltage receiving and processing module;
The input end of the first voltage-controlled unit is provided with a NAND gate D 1 Is connected with the output end of the NOT gate D 1 The input end of the voltage control unit is connected with a pulse power supply signal, the pulse power supply signal is respectively connected with the input end of the second voltage control unit, the inhibition signal judging module I and the voltage judging module, the voltage judging module is connected with the voltage receiving processing module, and the voltage receiving processing module is connected with the synaptic neuron module III; the output end of the first voltage control unit and the output end of the second voltage control unit are respectively connected with the input end of the addition operation unit; the output end of the addition unit is respectively connected with a promotion signal receiving processing module I, a promotion signal receiving processing module II, a suppression signal receiving processing module I, a suppression signal receiving processing module II, a voltage module I and a voltage module II, the voltage module I is connected with a synaptic module I, the synaptic module I is respectively connected with a promotion signal judging module II and a suppression signal judging module II, the voltage module II is connected with a synaptic module II, and the synaptic module II is respectively connected with a suppression signal judging module I, a suppression signal receiving processing module II,The promotion signal judging module I and the promotion signal receiving module II are connected; promotion signal judging module I respectively NAND gate D 1 The signal prompting judging module II is connected with the signal prompting receiving and processing module II; the suppression signal judging module I is respectively connected with the pulse power supply signal, the suppression signal receiving and processing module I and the suppression signal recovering module I; the suppression signal judging module II is connected with the suppression signal receiving and processing module II;
the first voltage control unit comprises a voltage control switch S 1 Power supply V 1 And resistance R 1 The method comprises the steps of carrying out a first treatment on the surface of the The second voltage control unit comprises a voltage control switch S 2 Power supply V 2 And resistance R 2 The method comprises the steps of carrying out a first treatment on the surface of the The addition unit comprises a resistor R 3 Resistance R 4 Resistance R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 Resistance R 11 Operational amplifier OP 1 And operational amplifier OP 2 ；
Voltage-controlled switch S 1 Non-inverting input of NAND gate D 1 Is connected with the output end of the voltage-controlled switch S 1 Respectively with the resistor R 1 One end of (1) resistor R 3 Is connected with one end of a voltage-controlled switch S 1 Second contact of (2) and power supply V 1 Is connected with the positive electrode of the power supply V 1 Negative electrode of (d), resistance R 1 And voltage-controlled switch S 1 The inverting input ends of the two are grounded;
voltage-controlled switch S 2 The positive input end of (2) is connected with a pulse power supply signal, and the voltage-controlled switch S 2 Respectively with resistor R 2 One end of (1) resistor R 4 Is connected with one end of a voltage-controlled switch S 2 Second contact of (2) and power supply V 2 Is connected with the positive electrode of the power supply V 2 Negative electrode of (d), resistance R 2 And voltage-controlled switch S 2 The inverting input ends of the two are grounded;
resistor R 3 Is another of (1)One end is respectively connected with the resistor R 5 One end of (1) resistor R 7 Is connected to one end of the operational amplifier OP 1 Is connected with the non-inverting input terminal of the resistor R 5 The other end of the resistor R is connected with the suppression signal receiving and processing module I 7 The other end of the signal receiving and processing module II is connected with the signal receiving and processing module II; resistor R 4 Respectively with resistor R at the other end 6 One end of (1) resistor R 8 Is connected to one end of the operational amplifier OP 1 Is connected with the non-inverting input terminal of the resistor R 6 The other end of the resistor R is connected with the promotion signal receiving processing module I 8 The other end of the signal receiving and processing module II is connected with an operational amplifier OP 1 Is not connected to the operational amplifier OP 1 Is connected with a resistor R between the output ends of 9 Operational amplifier OP 1 Output terminal of (d) and resistor R 10 Is connected with one end of resistor R 10 Is connected with the other end of the operational amplifier OP 2 Is connected with the inverting input terminal of the operational amplifier OP 2 A resistor R is connected between the inverting input terminal of the operational amplifier OP2 and the output terminal of the operational amplifier OP2 11 The output end of the operational amplifier OP2 is respectively connected with the voltage module I and the voltage module II, and the operational amplifier OP 2 Is connected to the non-inverting input terminal of the operational amplifier OP 1 The inverting input ends of the two are grounded;
the voltage module I comprises memristors M 1 Memristor M 2 Capacitance C 1 Resistance R 12 And operational amplifier OP 3 The synaptic module I comprises memristors M 5 Resistance R 14 Operational amplifier OP 4 Arithmetic unit ABM 1 Operational amplifier OP 17 And power supply V 5 The method comprises the steps of carrying out a first treatment on the surface of the The memristance M 1 K pole of (C) and memristance M 2 K-pole of (a) and operational amplifier OP 2 Is connected with the output end of the memristor M 1 Is of the A pole and memristance M 2 The A pole of (a) is connected with the operational amplifier OP 3 Is connected with the inverting input terminal of the operational amplifier OP 3 Is connected to the inverting input terminal of the operational amplifier OP 3 Is connected with a resistor between the output ends of R 12 Resistance R 12 A capacitor C is connected in parallel with 1 Operational amplifier OP 3 Respectively with memristor M 5 K pole of (a) mathematical operation unit ABM 1 IN of (2) 2 Input ends are connected with each other, memristor M 5 A pole of (a) and operational amplifier OP 4 Is connected with the inverting input terminal of the operational amplifier OP 4 Is connected to the inverting input terminal of the operational amplifier OP 4 Is connected with a resistor R between the output ends of 14 Operational amplifier OP 4 Output terminal of (a) and mathematical operation unit ABM 1 IN of (2) 1 Input ends are connected, and the mathematical operation unit ABM 1 OUT output terminal of (a) and operational amplifier OP 17 Is connected with the non-inverting input terminal of the operational amplifier OP 17 Is connected with the power supply V 5 Is connected with the positive electrode of the operational amplifier OP 17 The output end of the (a) is respectively connected with the suppression signal judging module II and the promotion signal judging module II; operational amplifier OP 3 Is not connected with the normal phase input end of the operational amplifier OP 4 Is connected with the positive input terminal of the power supply V 5 The cathodes of the electrodes are all grounded;
the voltage module II comprises memristance M 3 Memristor M 4 Capacitance C 2 Resistance R 13 Operational amplifier OP 5 The synaptic module II comprises memristors M 6 Resistance R 15 Operational amplifier OP 6 Arithmetic unit ABM 2 Operational amplifier OP 7 Operational amplifier OP 8 Power supply V 6 And power supply V 7 The method comprises the steps of carrying out a first treatment on the surface of the Memristor M 3 K pole of (C) and memristance M 4 K-pole of (a) and operational amplifier OP 2 Is connected with the output end of the memristor M 3 Is of the A pole and memristance M 4 The A pole of (a) is connected with the operational amplifier OP 5 Is connected with the inverting input terminal of the operational amplifier OP 5 Is connected to the inverting input terminal of the operational amplifier OP 5 Is connected with a resistor R between the output ends of 13 Resistance R 13 A capacitor C is connected in parallel with 2 Operational amplifier OP 5 Respectively with memristor M 6 K-pole, mathematical transport of (C)Computing unit ABM 2 IN of (2) 2 Input ends are connected with each other, memristor M 6 A pole of (a) and operational amplifier OP 6 Is connected with the inverting input terminal of the operational amplifier OP 6 Is connected to the inverting input terminal of the operational amplifier OP 6 Is connected with a resistor R between the output ends of 15 Operational amplifier OP 6 Output terminal of (a) and mathematical operation unit ABM 2 IN of (2) 1 Input ends are connected, and the mathematical operation unit ABM 2 The OUT output ends of (1) are respectively connected with an operational amplifier OP 7 Is not connected with the normal phase input end of the operational amplifier OP 8 Is connected with the inverting input terminal of the operational amplifier OP 7 Is connected with the power supply V 6 Is connected with the positive electrode of the operational amplifier OP 7 The output ends of the (a) are respectively connected with the suppression signal judging module I and the suppression signal receiving and processing module II, and the operational amplifier OP 8 Is connected with the positive input end of the power supply V 7 Is connected with the positive electrode of the operational amplifier OP 8 The output end of the (a) is respectively connected with the promotion signal judging module I and the promotion signal receiving and processing module II; operational amplifier OP 5 Is not connected with the normal phase input end of the operational amplifier OP 6 Positive phase input terminal of (2) power supply V 6 Is connected with the negative electrode of the power supply V 7 The cathodes of the electrodes are all grounded;
the inhibition signal judging module I comprises an AND gate D 2 Voltage-controlled switch S 3 Voltage pulse source V 3 And resistance R 16 The method comprises the steps of carrying out a first treatment on the surface of the The inhibition signal receiving processing module I comprises memristors M 7 Operational amplifier OP 9 And resistance R 17 The method comprises the steps of carrying out a first treatment on the surface of the The suppression signal recovery module I comprises a voltage-controlled switch S 5 And resistance R 18 The method comprises the steps of carrying out a first treatment on the surface of the The AND gate D 2 The input end of (a) is respectively connected with a pulse power signal and an operational amplifier OP 7 Is connected with the output end of the AND gate D 2 Output terminal of (d) and voltage-controlled switch S 3 Is connected with the positive input end of the voltage-controlled switch S 3 Is grounded, and a voltage-controlled switch S 3 Respectively with memristance M 7 K pole, resistance R of (2) 16 Is connected with one end of a voltage-controlled switch S 3 Is the second contact of (2)Point and voltage pulse source V 3 Is connected with the positive electrode of the voltage pulse source V 3 Respectively with the resistor R 16 Is a voltage-controlled switch S 5 Is connected with the non-inverting input terminal of the voltage pulse source V 3 Is grounded, memristor M 7 A pole of (a) and operational amplifier OP 9 Is connected with the inverting input terminal of the operational amplifier OP 9 Is connected to the inverting input terminal of the operational amplifier OP 9 Is connected with a resistor R between the output ends of 17 Operational amplifier OP 9 Is grounded, and operational amplifier OP 9 Output terminal of (d) and resistor R 5 Is connected with the other end of the voltage-controlled switch S 5 First contact of (a) and resistance R 18 Is connected with one end of a voltage-controlled switch S 5 Second contact of (2) and resistor R 5 Is connected with the other end of the resistor R 18 And voltage-controlled switch S 5 The inverting input ends of the two are grounded;
the suppression signal judging module II comprises an NMOS tube T 1 Resistance R 29 Power supply V 8 And power supply V 9 The method comprises the steps of carrying out a first treatment on the surface of the The inhibition signal receiving processing module II comprises memristor M 8 Capacitance C 3 Resistance R 19 Operational amplifier OP 10 SUM of voltages unit SUM 1 Operational amplifier OP 11 And power supply V 10 The method comprises the steps of carrying out a first treatment on the surface of the The NMOS tube T 1 Gate of (d) and operational amplifier OP 17 Is connected with the output end of NMOS tube T 1 The drain electrode of (a) is respectively connected with the resistor R 29 One end of (C) memristance M 8 The A poles of (2) are connected with each other, the resistor R 29 Is connected with the other end of the power supply V 8 Is connected with the positive electrode of the power supply V 8 Is grounded with the negative electrode of NMOS tube T 1 Source of (d) and power supply V 9 Is connected with the positive electrode of the power source V 9 Is grounded, memristor M 8 K pole of (a) and operational amplifier OP 10 Is connected with the inverting input terminal of the operational amplifier OP 10 Is connected to the inverting input terminal of the operational amplifier OP 10 Is connected with a resistor R between the output ends of 19， Resistor R 19 The upper part is connected with a capacitor in parallelC 3 Operational amplifier OP 10 Is grounded, and operational amplifier OP 10 Output terminal of (a) and voltage summing unit SUM 1 Is connected to the first input terminal of the voltage summing unit SUM 1 Is connected to the second input terminal of the operational amplifier OP 7 Is connected to the output terminal of the voltage summing unit SUM 1 Output terminal of (a) and operational amplifier OP 11 Is connected with the inverting input terminal of the operational amplifier OP 11 Is connected with the positive input end of the power supply V 10 Is connected with the positive electrode of the operational amplifier OP 11 Output terminal of (d) and resistor R 7 Is connected with the other end of the power supply V 10 Is grounded;
the promotion signal judging module I comprises an AND gate D 3 Voltage-controlled switch S 4 Voltage pulse source V 4 And resistance R 20 The method comprises the steps of carrying out a first treatment on the surface of the The signal receiving processing module I comprises memristance M 9 Operational amplifier OP 12 And resistance R 21 The method comprises the steps of carrying out a first treatment on the surface of the The signal recovery promoting module I comprises a voltage-controlled switch S 6 And resistance R 22 The method comprises the steps of carrying out a first treatment on the surface of the The promotion signal judging module II comprises an NMOS tube T 2 Resistance R 30 Power supply V 11 And power supply V 12 The method comprises the steps of carrying out a first treatment on the surface of the The inhibition signal receiving and processing module II memristor M 10 Capacitance C 4 Resistance R 23 Operational amplifier OP 13 SUM of voltages unit SUM 2 NOT gate D 5 Operational amplifier OP 14 And power supply V 13 ；
The AND gate D 3 Respectively NAND gate D at the input end of (a) 1 Output terminal of (a), operational amplifier OP 8 Is connected with the output end of the AND gate D 3 Output terminal of (d) and voltage-controlled switch S 4 Is connected with the positive input end of the voltage-controlled switch S 4 Is grounded, and a voltage-controlled switch S 4 Respectively with memristance M 9 K pole, resistance R of (2) 20 Is connected with one end of a voltage-controlled switch S 4 Is connected with the second contact of the voltage pulse source V 4 Is connected with the positive electrode of the voltage pulse source V 4 Respectively with the electricityR resistance 20 Is a voltage-controlled switch S 6 Is connected with the non-inverting input terminal of the voltage pulse source V 4 Is grounded, memristor M 9 A pole of (a) and operational amplifier OP 12 Is connected with the inverting input terminal of the operational amplifier OP 12 Is connected to the inverting input terminal of the operational amplifier OP 12 Is connected with a resistor R between the output ends of 21 Operational amplifier OP 12 Is grounded, and operational amplifier OP 12 Output terminal of (d) and resistor R 6 Is connected with the other end of the voltage-controlled switch S 6 First contact of (a) and resistance R 22 Is connected with one end of a voltage-controlled switch S 6 Second contact of (2) and resistor R 6 Is connected with the other end of the resistor R 22 And voltage-controlled switch S 6 The inverting input ends of the two are grounded;
the NMOS tube T 2 Gate of (d) and operational amplifier OP 17 Is connected with the output end of NMOS tube T 2 The drain electrode of (a) is respectively connected with the resistor R 30 One end of (C) memristance M 10 The A poles of (2) are connected with each other, the resistor R 30 Is connected with the other end of the power supply V 11 Is connected with the positive electrode of the power supply V 11 Is grounded with the negative electrode of NMOS tube T 2 Source of (d) and power supply V 12 Is connected with the positive electrode of the power supply V 12 Is grounded, memristor M 10 K pole of (a) and operational amplifier OP 13 Is connected with the inverting input terminal of the operational amplifier OP 13 Is connected to the inverting input terminal of the operational amplifier OP 13 Is connected with a resistor R between the output ends of 23 Resistance R 23 A capacitor C is connected in parallel with 4 Operational amplifier OP 13 Is grounded, and operational amplifier OP 13 Output terminal of (a) and voltage summing unit SUM 2 Is connected to the first input terminal of the voltage summing unit SUM 2 And a second input NAND gate D 5 Output terminals of (a) are connected with each other, not gate D 5 Input terminal of (a) and operational amplifier OP 8 Is connected with the output end of the voltage summation unit SUM 2 Output terminal of (a) and operational amplifier OP 14 Is connected to the inverting input terminal of (a)Connected to an operational amplifier OP 14 Is connected with the positive input end of the power supply V 13 Is connected with the positive electrode of the operational amplifier OP 14 Output terminal of (d) and resistor R 8 Is connected with the other end of the power supply V 13 The negative electrode of (2) is grounded.
2. The memristive-based operational conditional reflex circuit of claim 1, wherein the voltage determination module comprises a PMOS tube T 3 Resistance R 24 Power supply V 15 Power supply V 16 NMOS tube T 4 Resistance R 25 Power supply V 17 Power supply V 18 And gate D 4 Voltage-controlled switch S 7 Voltage pulse source V 14 Resistance R 26 SUM-voltage summing unit SUM 3 The method comprises the steps of carrying out a first treatment on the surface of the The pulse power supply signal is respectively connected with the PMOS tube T 3 Gate of (D) and gate D 4 And a voltage-controlled switch S 7 Is connected with the positive phase input end of the PMOS tube T 3 The drain electrode of (a) is respectively connected with the resistor R 24 One end of NMOS tube T 4 The grid electrode of (C) is connected with the resistor R 24 Is connected with the other end of the power supply V 15 Is connected with the positive electrode of the power supply V 15 The negative electrode of the PMOS tube T is grounded 3 Source of (d) and power supply V 16 Is connected with the positive electrode of the power supply V 16 Is grounded with the negative electrode of NMOS tube T 4 The drain electrode of (a) is respectively connected with the resistor R 25 And gate D 4 Is connected with the input end of the resistor R 25 Is connected with the other end of the power supply V 17 Is connected with the positive electrode of the power supply V 17 Is grounded with the negative electrode of the MOS tube T 4 Source of (d) and power supply V 18 Is connected with the positive electrode of the power supply V 18 Is grounded; voltage-controlled switch S 7 Respectively with resistor R 26 One end of (a) and voltage summing unit SUM 3 Is connected with the first input end of the voltage-controlled switch S 7 Second contact of (2) and voltage pulse source V 14 Positive electrode of (a) is connected with a voltage-controlled switch S 7 Is connected with the inverting input terminal of the voltage pulse source V 14 Negative electrode of (2) and resistance R 26 Is another of (1)One end is grounded; AND gate D 4 Output terminal of (a) and voltage summing unit SUM 3 Is connected to the second input terminal of the voltage summing unit SUM 3 The output end of the voltage receiving and processing module is connected with the voltage receiving and processing module.
3. The memristive-based operational conditional reflex circuit of claim 2, wherein the voltage receiving processing module comprises memristive M 11 Current source I 1 Current source I 2 PMOS tube T 5 PMOS tube T 6 NMOS tube T 7 NMOS tube T 8 NMOS tube T 9 PMOS tube T 10 PMOS tube T 11 NMOS tube T 12 Resistance R 27 Power supply V 19 And power supply V 20 The method comprises the steps of carrying out a first treatment on the surface of the The voltage summation unit SUM 3 Respectively with memristor M 11 A pole, resistance R of (2) 27 Is connected with one end of memristor M 11 K pole of (C) is respectively connected with PMOS tube T 6 Source electrode of NMOS transistor T 12 The source electrodes of the PMOS tube T are connected 6 Gate of (c) and current source I 1 Is connected with the negative pole of the current source I 1 The positive electrode of (a) is respectively connected with the NMOS tube T 7 Source, power supply V 19 Positive electrode of (2) and NMOS transistor T 8 Is connected with the source of the power supply V 19 Is grounded at the negative electrode of the current source I 1 The negative electrode of (a) is respectively connected with the PMOS tube T 5 Drain electrode of PMOS tube T 5 The grid electrode of the PMOS tube T is connected with 5 Source and NMOS transistor T 9 The source electrodes of the NMOS transistor T are all grounded 9 Drain electrode of NMOS transistor T 9 Gate and NMOS transistor T of (2) 12 Are all connected with the grid of the current source I 2 Is connected with the positive electrode of the current source I 2 Respectively with the power supplyV 20 Positive electrode of PMOS tube T 10 Source and of (2)PMOS tube T 11 Is connected with the source of the power supply V 20 The negative electrode of the PMOS tube T is grounded 10 Drain electrode of PMOS tube T 10 Gate and PMOS transistor T 11 The grid electrode of (C) is connected with NMOS tube T 12 Is connected to the drain electrode of the transistor,PMOS tube T 11 The drain electrode of (a) is respectively connected with the resistor R 27 Is the other end of NMOS tube T 8 Is connected with the synaptic neuron module III, NMOS tube T 8 Gate, NMOS transistor T 7 Gate, NMOS transistor T 7 Drain electrodes of (C) and PMOS tube T 6 Is connected to the drain of the transistor.
4. The memristive-based operational conditional reflex circuit of claim 3, wherein the synaptic neuron module III comprises a memristance M 12 Resistance R 28 Operational amplifier OP 15 Arithmetic unit ABM 3 Power supply V 21 And operational amplifier OP 16 Resistance R 27 Is respectively connected with memristor M at the other end 12 K pole of (a) mathematical operation unit ABM 3 IN of (2) 2 Input ends are connected with each other, memristor M 12 A pole of (a) and operational amplifier OP 15 Is connected with the inverting input terminal of the operational amplifier OP 15 Is connected to the inverting input terminal of the operational amplifier OP 15 Is connected with a resistor R between the output ends of 28 Operational amplifier OP 15 Is grounded, and operational amplifier OP 15 Output terminal of (a) and mathematical operation unit ABM 3 IN of (2) 1 Input ends are connected with a mathematical operation unit BM 3 OUT output terminal of (a) and operational amplifier OP 16 Is connected with the non-inverting input terminal of the operational amplifier OP 16 Is connected with the power supply V 21 Is connected with the positive electrode of the power supply V 21 The negative electrode of (2) is grounded.
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