CN113344194A - Operational conditioned reflex circuit based on memristor - Google Patents

Operational conditioned reflex circuit based on memristor Download PDF

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CN113344194A
CN113344194A CN202110599278.5A CN202110599278A CN113344194A CN 113344194 A CN113344194 A CN 113344194A CN 202110599278 A CN202110599278 A CN 202110599278A CN 113344194 A CN113344194 A CN 113344194A
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operational amplifier
voltage
power supply
resistance
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CN113344194B (en
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孙军伟
王洋洋
郭佳
杨建领
燕奕霖
单占江
肖萧
王英聪
王延峰
王妍
凌丹
刘鹏
方洁
黄春
余培照
李盼龙
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Zhengzhou University of Light Industry
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Abstract

The invention provides an operational conditioned reflex circuit based on memristance, which comprises an input module, a voltage control module, a promotion module I, a promotion module II, an inhibition module I, an inhibition module II, a synaptic neuron module I, a synaptic neuron module II and a synaptic neuron module III, wherein the input module is connected with the input module; the promotion module I realizes that the negative punishment of electric shock has a promotion effect on the positive punishment of food, the promotion module II realizes the positive punishment of food, the repetition rate of pigeon towards food is improved, the inhibition module I realizes the negative punishment of electric shock, the repetition rate of pigeon towards electric shock is reduced, and the inhibition module II realizes that the positive punishment of food has an inhibition effect on the negative punishment of electric shock; the synaptic neuron module I, II realizes operational conditioned reflex of the pigeon under different situations by connecting two groups of memristors in parallel. The invention realizes the process of the operational conditioned reflex, the promotion and inhibition relationship between the positive and negative, and the influence of instantaneity and satiety on the operational conditioned reflex.

Description

Operational conditioned reflex circuit based on memristor
Technical Field
The invention relates to the technical field of digital-analog circuits, in particular to an operational conditioned reflex circuit based on memristors, which is realized based on the idea of gold operational conditioned reflex.
Background
In 1971, the concept of memristance was proposed by professor zeita begonia of berkeley, university of california, usa, and the first working memristor was successfully developed in the HP laboratory of the usa in 2008. The characteristics of the memristor are very similar to synapses in biological nerves, and parts of functions of the brain can be simulated, so that the simulation memory learning of biological behaviors is carried out, and the circuit simulation of the biological memory behaviors is an extremely important part of the research of the memristor. The memristor presents a very potential application prospect in the aspects of nonvolatile storage, logic operation, novel calculation, storage fusion framework calculation, novel nerve morphology calculation and the like.
An actor Skinner provides an operational conditioned reflex theory system through experiments, a team in China also applies the operational conditioned reflex to training of dogs, and then Vollmer et al provides the influence of factors such as instantaneity and satiety on the operational conditioned reflex, but the influence is not realized through a circuit.
Disclosure of Invention
Aiming at the existing operational conditioned reflex theory, the invention provides an operational conditioned reflex circuit based on memristors, and the operational conditioned reflex process is realized through two groups of memristors which are connected in parallel in a positive and negative way; the promotion and inhibition relationship among different moods is realized through the promotion and inhibition circuit; by means of the voltage control circuit, the influence of immediacy and satiety on the operative conditioned reflex is achieved.
The technical scheme of the invention is realized as follows:
a memristor-based operational conditioned reflex circuit comprises an input module, a voltage control module, a promotion module I, a promotion module II, an inhibition module I, an inhibition module II, a synaptic neuron module I, a synaptic neuron module II and a synaptic neuron module III; the input module is respectively connected with a pulse power signal, a promoting module I, a promoting module II, an inhibiting module I, an inhibiting module II, a synaptic neuron module I and a synaptic neuron module II, the synaptic neuron module II is respectively connected with the promoting module I, the promoting module II, the inhibiting module I and the inhibiting module II, and the synaptic neuron module I is respectively connected with the promoting module II and the inhibiting module II; the pulse power supply signal is respectively connected with a voltage control module and an inhibition module I, and the voltage control module is connected with a synaptic neuron module III.
Preferably, the input module comprises a first voltage control unit, a second voltage control unit and an addition operation unit; the synaptic neuron module I comprises a voltage module I and a synaptic module I; the synaptic neuron module II comprises a voltage module II and a synaptic module II; the suppression module I comprises a suppression signal judgment module I, a suppression signal receiving and processing module I and a suppression signal recovery module I; the inhibition module II comprises an inhibition signal judgment module II and an inhibition signal receiving and processing module II; the promoting module I comprises a promoting signal judging module I, a promoting signal receiving and processing module I and a promoting signal restoring module I; the promoting module II comprises a promoting signal judging module II and a promoting signal receiving and processing module II; the voltage control module comprises a voltage judging module and a voltage receiving and processing module;
an input end NAND gate D of the first voltage control unit1Is connected to the output of the NOT gate D1The input end of the first voltage control unit is connected with a pulse power supply signal, the pulse power supply signal is respectively connected with the input end of the second voltage control unit, the inhibition signal judgment module I and the voltage judgment module, the voltage judgment module is connected with the voltage receiving and processing module, and the voltage receiving and processing module is connected with the synaptic neuron module III; the output end of the first voltage control unit and the output end of the second voltage control unit are respectively connected with the input end of the addition operation unit; the output end of the addition operation unit is respectively connected with a promoting signal receiving and processing module I, a promoting signal receiving and processing module II, an inhibiting signal receiving and processing module I, an inhibiting signal receiving and processing module II, a voltage module I and a voltage module II, wherein the voltage module I is connected with a synapse module I, the synapse module I is respectively connected with a promoting signal judging module II and an inhibiting signal judging module II, the voltage module II is connected with the synapse module II, and the synapse module II is respectively connected with an inhibiting signal judging module I, an inhibiting signal receiving and processing module II, a promoting signal judging module I and a promoting signal receiving module II; the promotion signal judgment module I is respectively an NAND gate D1The output end of the signal receiving and processing module I, the signal receiving and processing promotion module I and the signal recovery promotion module I are connected, and the signal judgment promotion module II is connected with the signal receiving and processing promotion module II; the suppression signal judgment module I is respectively connected with the pulse power supply signal, the suppression signal receiving and processing module I and the suppression signal recovery module I; and the suppression signal judgment module II is connected with the suppression signal receiving and processing module II.
Preferably, theThe first voltage control unit comprises a voltage control switch S1Power supply V1And a resistance R1(ii) a The second voltage control unit comprises a voltage controlled switch S2Power supply V2And a resistance R2(ii) a The addition unit includes a resistor R3Resistance R4Resistance R5Resistance R6Resistance R7Resistance R8Resistance R9Resistance R10Resistance R11Operational amplifier OP1And operational amplifier OP2；
Voltage-controlled switch S1Non-gate D of the positive input end1Is connected to the output terminal of the voltage-controlled switch S1Respectively with the resistor R1One terminal of (1), resistance R3Is connected to one end of a voltage-controlled switch S1Second contact of and power supply V1Is connected with the positive pole of the power supply V1Negative electrode of (2), resistance R1And the other end of the voltage-controlled switch S1The inverting input ends of the two-way switch are grounded;
voltage-controlled switch S2The positive phase input end of the voltage-controlled switch S is connected with a pulse power supply signal2Respectively with the resistor R2One terminal of (1), resistance R4Is connected to one end of a voltage-controlled switch S2Second contact of and power supply V2Is connected with the positive pole of the power supply V2Negative electrode of (2), resistance R2And the other end of the voltage-controlled switch S2The inverting input ends of the two-way switch are grounded;
resistance R3The other end of each of the resistors R and R is connected with5One terminal of (1), resistance R7And an operational amplifier OP1Is connected with the positive input end of the resistor R5The other end of the resistor R is connected with a suppression signal receiving and processing module I, and the resistor R7The other end of the signal receiving and processing module is connected with a suppression signal receiving and processing module II; resistance R4The other end of each of the resistors R and R is connected with6One terminal of (1), resistance R8And an operational amplifier OP1Is connected with the positive input end of the resistor R6Is connected with the signal receiving and processing facilitating module I, and a resistor R8Is connected with the promotion signal receiving and processing module II and is used for transmittingOperational amplifier OP1The non-inverting input terminal and the operational amplifier OP1Is connected with a resistor R between the output ends9An operational amplifier OP1Output terminal and resistor R10Is connected to one end of a resistor R10And the other end of (1) and an operational amplifier OP2Are connected to the inverting input terminal of an operational amplifier OP2And the operational amplifier OP2Is connected with a resistor R between the output ends11An operational amplifier OP2The output end of the operational amplifier is respectively connected with a voltage module I and a voltage module II, and the operational amplifier OP2And the non-inverting input terminal of the operational amplifier OP1The inverting input terminals of the two-way switch are all grounded.
Preferably, the voltage module I comprises a memristance M1Memory resistance M2Capacitor C1Resistance R12And operational amplifier OP3The synapse module I comprises a memristor M5Resistance R14Operational amplifier OP4Mathematical operation unit ABM1Operational amplifier OP17And a power supply V5(ii) a The memristor M1K pole and memristor M2Is connected with an operational amplifier OP2Is connected with the output end of the memory resistor M1A pole and memristor M2A pole of (1) is all connected with an operational amplifier OP3Are connected to the inverting input terminal of an operational amplifier OP3And the operational amplifier OP3Is connected with a resistor R between the output ends12Resistance R12A capacitor C is connected in parallel1An operational amplifier OP3Respectively with memristor M5K pole, mathematical operation unit ABM1IN of2Input end connected to memory resistor M5A pole of (1) and an operational amplifier OP4Are connected to the inverting input terminal of an operational amplifier OP4And the operational amplifier OP4Is connected with a resistor R between the output ends14An operational amplifier OP4Output end and mathematical operation unit ABM1IN of1Input ends are connected, and a mathematical operation unit ABM1OUT output terminal and operational amplifier OP17Are connected with the positive input end of the operational amplifierDevice OP17And the inverting input terminal of the power supply V5Is connected to the positive pole of an operational amplifier OP17The output end of the signal processing module is respectively connected with the suppression signal judgment module II and the promotion signal judgment module II; operational amplifier OP3Positive phase input terminal of, operational amplifier OP4Positive phase input terminal and power supply V5The cathodes of the two are all grounded.
Preferably, the voltage module II comprises a memristor M3Memory resistance M4Capacitor C2Resistance R13Operational amplifier OP5The synapse module II comprises a memristor M6Resistance R15Operational amplifier OP6Mathematical operation unit ABM2Operational amplifier OP7Operational amplifier OP8Power supply V6And a power supply V7(ii) a Memory resistance M3K pole and memristor M4Is connected with an operational amplifier OP2Is connected with the output end of the memory resistor M3A pole and memristor M4A pole of (1) is all connected with an operational amplifier OP5Are connected to the inverting input terminal of an operational amplifier OP5And the operational amplifier OP5Is connected with a resistor R between the output ends13Resistance R13A capacitor C is connected in parallel2An operational amplifier OP5Respectively with memristor M6K pole, mathematical operation unit ABM2IN of2Input end connected to memory resistor M6A pole of (1) and an operational amplifier OP6Are connected to the inverting input terminal of an operational amplifier OP6And the operational amplifier OP6Is connected with a resistor R between the output ends15An operational amplifier OP6Output end and mathematical operation unit ABM2IN of1Input ends are connected, and a mathematical operation unit ABM2Respectively with the operational amplifier OP7Positive phase input terminal of, operational amplifier OP8Are connected to the inverting input terminal of an operational amplifier OP7And the inverting input terminal of the power supply V6Is connected to the positive pole of an operational amplifier OP7The output end of the signal processing module is respectively connected with the suppression signal judgment module I and the suppression signal receiving processing module IIThen, an operational amplifier OP8Positive phase input terminal and power supply V7Is connected to the positive pole of an operational amplifier OP8The output end of the signal processing module is respectively connected with the promotion signal judgment module I and the promotion signal receiving processing module II; operational amplifier OP5Positive phase input terminal of, operational amplifier OP6Positive phase input terminal of, power supply V6Negative electrode of (2) and power supply V7The cathodes of the two are all grounded.
Preferably, the suppression signal judgment module I comprises an and gate D2Voltage controlled switch S3Voltage pulse source V3And a resistance R16(ii) a The suppression signal receiving and processing module I comprises a memristor M7Operational amplifier OP9And a resistance R17(ii) a The suppression signal recovery module I comprises a voltage-controlled switch S5And a resistance R18(ii) a The AND gate D2Respectively connected with the pulse power signal and the operational amplifier OP7Is connected with the output end of the AND gate D2Output terminal of and voltage-controlled switch S3Are connected with a positive input terminal of a voltage-controlled switch S3The inverting input terminal of the voltage-controlled switch S is grounded3Respectively with the memristor M7K pole, resistance R16Is connected to one end of a voltage-controlled switch S3Second contact of (2) and voltage pulse source V3Is connected with the positive pole of the voltage pulse source V3Respectively with the resistance R16Another end of (S), voltage controlled switch5Is connected with the positive phase input end of the voltage pulse source V3Negative pole of (1) is grounded, memory resistance M7A pole of (1) and an operational amplifier OP9Are connected to the inverting input terminal of an operational amplifier OP9And the operational amplifier OP9Is connected with a resistor R between the output ends17An operational amplifier OP9The non-inverting input terminal of (1) is grounded, and an operational amplifier OP9Output terminal and resistor R5Is connected to the other end of the voltage-controlled switch S5First contact of (3) and resistor R18Is connected to one end of a voltage-controlled switch S5Second contact of (3) and resistor R5Is connected to the other end of the resistor R18And the other end of the voltage-controlled switch S5Is the inverting input terminal ofAre all grounded;
the suppression signal judgment module II comprises an NMOS tube T1Resistance R29Power supply V8And a power supply V9(ii) a The suppression signal receiving and processing module II comprises a memristor M8Capacitor C3Resistance R19Operational amplifier OP10Voltage summing unit SUM1Operational amplifier OP11And a power supply V10(ii) a The NMOS tube T1Gate of and operational amplifier OP17Is connected with the output end of the NMOS tube T1Respectively with a resistor R29One end of (1), memristor M8Is connected with the A pole, and the resistance R29And the other end of (C) and a power supply V8Is connected with the positive pole of the power supply V8Is grounded, and an NMOS tube T1Source and power supply V9Is connected with the positive pole of the power supply V9Negative pole of (1) is grounded, memory resistance M8K pole and operational amplifier OP10Are connected to the inverting input terminal of an operational amplifier OP10And the operational amplifier OP10Is connected with a resistor R between the output ends19Resistance R19A capacitor C is connected in parallel3An operational amplifier OP10The non-inverting input terminal of (1) is grounded, and an operational amplifier OP10And the output and voltage summing unit SUM1Is connected to the first input terminal of the voltage summing unit SUM1Second input terminal of and operational amplifier OP7Are connected to the output of the voltage summing unit SUM1Output terminal of and operational amplifier OP11Are connected to the inverting input terminal of an operational amplifier OP11Positive phase input terminal and power supply V10Is connected to the positive pole of an operational amplifier OP11Output terminal and resistor R7Is connected to a power supply V10The negative electrode of (2) is grounded.
Preferably, the facilitation signal judgment module I comprises an and gate D3Voltage controlled switch S4Voltage pulse source V4And a resistance R20(ii) a The facilitation signal receiving processing module I comprises a memristor M9Operational amplifier OP12And a resistance R21(ii) a The module I packet for facilitating signal recoveryVoltage-controlled switch S6And a resistance R22(ii) a The promotion signal judgment module II comprises an NMOS tube T2Resistance R30Power supply V11And a power supply V12(ii) a Memristor M of suppression signal receiving and processing module II10Capacitor C4Resistance R23Operational amplifier OP13Voltage summing unit SUM2NOT gate D5Operational amplifier OP14And a power supply V13；
The AND gate D3Respectively input ends of the NAND gates D1Output terminal of (1), operational amplifier OP8Is connected with the output end of the AND gate D3Output terminal of and voltage-controlled switch S4Are connected with a positive input terminal of a voltage-controlled switch S4The inverting input terminal of the voltage-controlled switch S is grounded4Respectively with the memristor M9K pole, resistance R20Is connected to one end of a voltage-controlled switch S4Second contact of (2) and voltage pulse source V4Is connected with the positive pole of the voltage pulse source V4Respectively with the resistance R20Another end of (S), voltage controlled switch6Is connected with the positive phase input end of the voltage pulse source V4Negative pole of (1) is grounded, memory resistance M9A pole of (1) and an operational amplifier OP12Are connected to the inverting input terminal of an operational amplifier OP12And the operational amplifier OP12Is connected with a resistor R between the output ends21An operational amplifier OP12The non-inverting input terminal of (1) is grounded, and an operational amplifier OP12Output terminal and resistor R6Is connected to the other end of the voltage-controlled switch S6First contact of (3) and resistor R22Is connected to one end of a voltage-controlled switch S6Second contact of (3) and resistor R6Is connected to the other end of the resistor R22And the other end of the voltage-controlled switch S6The inverting input ends of the two-way switch are grounded;
the NMOS tube T2Gate of and operational amplifier OP17Is connected with the output end of the NMOS tube T2Respectively with a resistor R30One end of (1), memristor M10Is connected with the A pole, and the resistance R30And the other end of (C) and a power supply V11Is connected with the positive pole of the power supply V11Is grounded, and an NMOS tube T2Source and power supply V12Is connected with the positive pole of the power supply V12Negative pole of (1) is grounded, memory resistance M10K pole and operational amplifier OP13Are connected to the inverting input terminal of an operational amplifier OP13And the operational amplifier OP13Is connected with a resistor R between the output ends23Resistance R23A capacitor C is connected in parallel4An operational amplifier OP13The non-inverting input terminal of (1) is grounded, and an operational amplifier OP13And the output and voltage summing unit SUM2Is connected to the first input terminal of the voltage summing unit SUM2The second input end of the NAND gate D5Is connected to the output of the NOT gate D5And operational amplifier OP8Are connected to the output of the voltage summing unit SUM2Output terminal of and operational amplifier OP14Are connected to the inverting input terminal of an operational amplifier OP14Positive phase input terminal and power supply V13Is connected to the positive pole of an operational amplifier OP14Output terminal and resistor R8Is connected to a power supply V13The negative electrode of (2) is grounded.
Preferably, the voltage judging module comprises a PMOS transistor T3Resistance R24Power supply V15Power supply V16NMOS tube T4Resistance R25Power supply V17Power supply V18AND gate D4Voltage controlled switch S7Voltage pulse source V14Resistance R26SUM voltage summing unit SUM3；
The pulse power supply signal is respectively connected with the PMOS tube T3Grid and gate D4And a voltage-controlled switch S7Are connected with the positive phase input end of a PMOS tube T3Respectively with a resistor R24One end of (1), NMOS tube T4Is connected to the gate of the resistor R24And the other end of (C) and a power supply V15Is connected with the positive pole of the power supply V15The negative electrode of the PMOS tube T is grounded3Source and power supply V16Is connected with the positive pole of the power supply V16Is grounded at the negative electrodeNMOS transistor T4Respectively with a resistor R25One end of (D), and gate4Is connected to the input terminal of a resistor R25And the other end of (C) and a power supply V17Is connected with the positive pole of the power supply V17Is grounded, and an NMOS tube T4Source and power supply V18Is connected with the positive pole of the power supply V18The negative electrode of (2) is grounded; voltage-controlled switch S7Respectively with the resistor R26One terminal of (1), voltage summing unit SUM3Is connected to the first input terminal of the voltage-controlled switch S7Second contact of (2) and voltage pulse source V14Is connected to the positive pole of the voltage-controlled switch S7Voltage pulse source V14Negative electrode and resistance R26The other ends of the two are grounded; and gate D4And the output and voltage summing unit SUM3Is connected to the second input terminal of the voltage summing unit SUM3The output end of the voltage receiving and processing module is connected with the voltage receiving and processing module.
Preferably, the voltage receiving processing module comprises a memristor M11A current source I1A current source I2PMOS tube T5PMOS tube T6NMOS tube T7NMOS tube T8NMOS tube T9PMOS tube T10PMOS tube T11NMOS tube T12Resistance R27Power supply V19And a power supply V20(ii) a The voltage summing unit SUM3Respectively with memristor M11A pole of (1), a resistance R27Is connected with one end of a memristor M11K pole of (1) is respectively connected with PMOS tube T6Source electrode and NMOS tube T12Is connected with the source electrode of the PMOS tube T6Gate of and current source I1Is connected to the negative pole of a current source I1Respectively with the positive electrode of the NMOS transistor T7Source electrode, power supply V19Positive electrode and NMOS transistor T8Is connected to the source of the power supply V19Negative pole of (1) is grounded, current source I1Respectively with a PMOS transistor T5Drain electrode of (D), PMOS tube T5Is connected with the grid of the PMOS tube T5Source electrode and NMOS transistor T9The source electrodes of the NMOS transistors T are all grounded9Drain electrode of (1), NMOS tube T9Of a grid electrodeAnd NMOS transistor T12Gate of the transistor is connected with a current source I2Is connected to the positive pole of the current source I2Respectively connected with a power supply V20Positive electrode of PMOS transistor T10Source electrode and PMOS transistor T11Is connected to the source of the power supply V20The negative electrode of the PMOS tube T is grounded10Drain electrode of (D), PMOS tube T10Grid and PMOS transistor T11Grid of the NMOS transistor T12Is connected with the drain electrode of the PMOS tube T11Respectively with a resistor R27Another end of (1), NMOS tube T8Is connected with a synaptic neuron module III, and an NMOS tube T8Grid electrode and NMOS tube T7Grid electrode and NMOS tube T7Drain electrodes of the PMOS transistors T6Is connected to the drain of the transistor.
Preferably, the synaptic neuron module III comprises a memristor M12Resistance R28Operational amplifier OP15Mathematical operation unit ABM3Power supply V21And operational amplifier OP16Resistance R27The other end of the memory is respectively connected with a memory resistor M12K pole, mathematical operation unit ABM3IN of2Input end connected to memory resistor M12A pole of (1) and an operational amplifier OP15Are connected to the inverting input terminal of an operational amplifier OP15And the operational amplifier OP15Is connected with a resistor R between the output ends28An operational amplifier OP15The non-inverting input terminal of (1) is grounded, and an operational amplifier OP15Output end and mathematical operation unit ABM3IN of1Input ends are connected, and a mathematical operation unit ABM3OUT output terminal and operational amplifier OP16Are connected to the non-inverting input terminal of an operational amplifier OP16And the inverting input terminal of the power supply V21Is connected with the positive pole of the power supply V21The negative electrode of (2) is grounded.
Compared with the prior art, the invention has the following beneficial effects:
1) the invention realizes the operational conditioned reflex through the memristor circuit, and the frequency of the result in the future can be changed by giving different types of stimulation to the behavior result of the biological individual, thereby providing important significance for the intellectualization of the brain-like nerve.
2) The pigeon positive reward inhibition system can realize different reactions of the pigeons to the positive reward and the negative penalty under different states, and can realize the mutual promotion inhibition relationship between the positive reward and the negative penalty.
3) Through two groups of memristor positive and negative parallel circuits, the process of the operational conditioned reflex is realized, the promotion and inhibition relation among different emotions is realized, and the influence of instantaneity and satiety on the operational conditioned reflex is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of the present invention.
FIG. 2 is a diagram of simulation results in a specific environment of 0-90S, wherein 0-30S are diagrams of simulation results in a starved and noiseless environment, 30-60S are diagrams of simulation results in a starved and noisy environment, and 60-90S are diagrams of simulation results in a satiated and noisy environment.
FIG. 3 is a graph of simulation results of output voltages of the boost suppression module of the present invention.
FIG. 4 shows a memristor M of the present invention1、M2、M3、M4、M7、M8、M9And M10The simulation result diagram of (1).
FIG. 5 is a diagram of simulation results of the timeliness comparison of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
First, the functions realized by the present invention are described: in the theory of smin' S operative conditioned reflection, when in a hungry and noiseless environment, if the pigeon pecks red balls, food is obtained, which is a positive reward, increasing the repetition rate of the pigeon pecking red balls, and realizing positive enhancement in operative conditioned reflection, as shown in the 0-30S food graph in fig. 2; if the pigeon pecks the basketball, the pigeon is shocked, the shock is a negative punishment, the repetition rate of the pigeon pecking the basketball is reduced, and the positive punishment in the operational condition reflection is realized, as shown in a 0-30S shock diagram in fig. 2; if a pigeon pecks a yellow ball, the yellow ball represents the noise cancellation, and the repetition rate for the pigeon pecking the yellow ball is unchanged, as shown in the 0-30S noise cancellation diagram in fig. 2. When in a hungry and noisy environment, if the pigeon pecks red ball, food is obtained, which is a positive reward, increasing the repetition rate of the pigeon pecking red ball, as shown in the 30-60S food graph in fig. 2; if the pigeon pecks the basketball, the pigeon is shocked, the shock is a negative penalty, the repetition rate of the pigeon pecking the basketball is reduced, and the negative penalty in the operative condition reflection is realized, as shown in a 30-60S shock diagram in fig. 2; if the pigeon pecks yellow ball, the noise will be eliminated, and the repetition rate of the pigeon pecking yellow ball will be increased, as shown in the 30-60S noise elimination diagram in FIG. 2. When in a full and noisy environment, if the pigeon is eating red, there is no desire for food because the pigeon is in a full state, and the repetition rate for the pigeon to peck red is unchanged, as shown in the 60-90S food graph in fig. 2; if the pigeon pecks the basketball, the pigeon is shocked, and the shock is a negative penalty, which reduces the repetition rate of the pigeon pecking the basketball, as shown in the 60-90S shock diagram in fig. 2; if the pigeon pecks a ball, the noise is eliminated, increasing the repetition rate of the pigeon pecking a ball, and achieving escape in the negative enhancement in the operative condition reflection, as shown in the 60-90S noise elimination plot in fig. 2. If the pigeon pecks the green ball, the green ball is not a positive reward or negative punishment, the pigeon can be slowly forgotten, and the fading of the operative condition reflection is realized.
Under no use environment, pigeons achieve operational conditioned reflection by pecking balls of different colors; the satiety of the pigeons is analyzed through hunger and satiety states, and the instantaneity of the pigeons is analyzed through immediate actions.
As shown in fig. 1, an embodiment of the present invention provides an operational memristance-based conditioned reflex circuit, which includes an input module, a voltage control module, a promotion module I, a promotion module II, an inhibition module I, an inhibition module II, a synaptic neuron module I, a synaptic neuron module II, and a synaptic neuron module III; the input module is respectively connected with a pulse power signal, a promoting module I, a promoting module II, an inhibiting module I, an inhibiting module II, a synaptic neuron module I and a synaptic neuron module II, the synaptic neuron module II is respectively connected with the promoting module I, the promoting module II, the inhibiting module I and the inhibiting module II, and the synaptic neuron module I is respectively connected with the promoting module II and the inhibiting module II; the pulse power supply signal is respectively connected with a voltage control module and an inhibition module I, and the voltage control module is connected with a synaptic neuron module III. Realizing negative punished operational conditioned reflex by a suppression module I; the forward enhanced operational conditioned reflex is realized by the suppression module II; the promotion module I is used for realizing that the negative penalty has a promotion effect on positive excitation; and realizing that positive excitation has an inhibiting effect on negative punishment by the promoting module II.
The input module comprises a first voltage control unit, a second voltage control unit and an addition operation unit; the synaptic neuron module I comprises a voltage module I and a synaptic module I; the synaptic neuron module II comprises a voltage module II and a synaptic module II; the suppression module I comprises a suppression signal judgment module I, a suppression signal receiving and processing module I and a suppression signal recovery module I; the inhibition module II comprises an inhibition signal judgment module II and an inhibition signal receiving and processing module II; the promoting module I comprises a promoting signal judging module I, a promoting signal receiving and processing module I and a promoting signal restoring module I; the promoting module II comprises a promoting signal judging module II and a promoting signal receiving and processing module II; the voltage control module comprises a voltage judging module and a voltage receiving and processing module.
An input end NAND gate D of the first voltage control unit1Is connected to the output of the NOT gate D1The input end of the first voltage control unit is connected with a pulse power supply signal, the pulse power supply signal is respectively connected with the input end of the second voltage control unit, the inhibition signal judgment module I and the voltage judgment module, the voltage judgment module is connected with the voltage receiving and processing module, and the voltage receiving and processing module is connected with the synaptic neuron module III; the output end of the first voltage control unit and the output end of the second voltage control unit are respectively connected with the input end of the addition operation unit; the output end of the addition operation unit is respectively connected with a promoting signal receiving and processing module I, a promoting signal receiving and processing module II, an inhibiting signal receiving and processing module I, an inhibiting signal receiving and processing module II, a voltage module I and a voltage module II, wherein the voltage module I is connected with a synapse module I, the synapse module I is respectively connected with a promoting signal judging module II and an inhibiting signal judging module II, the voltage module II is connected with the synapse module II, and the synapse module II is respectively connected with an inhibiting signal judging module I, an inhibiting signal receiving and processing module II, a promoting signal judging module I and a promoting signal receiving module II; the promotion signal judgment module I is respectively an NAND gate D1The output end of the signal receiving and processing module I, the signal receiving and processing promotion module I and the signal recovery promotion module I are connected, and the signal judgment promotion module II is connected with the signal receiving and processing promotion module II; the suppression signal judgment module I is respectively connected with the pulse power supply signal, the suppression signal receiving and processing module I and the suppression signal recovery module I; and the suppression signal judgment module II is connected with the suppression signal receiving and processing module II.
The first voltage control unit comprises a voltage controlled switch S1Power supply V1And a resistance R1(ii) a The second voltage control unit comprises a voltage controlled switch S2Power supply V2And a resistance R2(ii) a The addition unit includes a resistor R3Resistance R4Resistance R5Resistance R6Resistance R7Resistance R8Resistance R9Resistance R10Resistance R11Operational amplifier OP1And operational amplifier OP2. The input signal is 4v at 0-30S and 60-90S, and at 30-60SThe input signal is-4 v.
Voltage-controlled switch S1Non-gate D of the positive input end1Is connected to the output terminal of the voltage-controlled switch S1Respectively with the resistor R1One terminal of (1), resistance R3Is connected to one end of a voltage-controlled switch S1Second contact of and power supply V1Is connected with the positive pole of the power supply V1Negative electrode of (2), resistance R1And the other end of the voltage-controlled switch S1The inverting input terminals of the two-way switch are all grounded.
Voltage-controlled switch S2The positive phase input end of the voltage-controlled switch S is connected with a pulse power supply signal2Respectively with the resistor R2One terminal of (1), resistance R4Is connected to one end of a voltage-controlled switch S2Second contact of and power supply V2Is connected with the positive pole of the power supply V2Negative electrode of (2), resistance R2And the other end of the voltage-controlled switch S2The inverting input terminals of the two-way switch are all grounded.
Resistance R3The other end of each of the resistors R and R is connected with5One terminal of (1), resistance R7And an operational amplifier OP1Is connected with the positive input end of the resistor R5The other end of the resistor R is connected with a suppression signal receiving and processing module I, and the resistor R7The other end of the signal receiving and processing module is connected with a suppression signal receiving and processing module II; resistance R4The other end of each of the resistors R and R is connected with6One terminal of (1), resistance R8And an operational amplifier OP1Is connected with the positive input end of the resistor R6Is connected with the signal receiving and processing facilitating module I, and a resistor R8Is connected with a signal receiving and processing facilitating module II, an operational amplifier OP1The non-inverting input terminal and the operational amplifier OP1Is connected with a resistor R between the output ends9An operational amplifier OP1Output terminal and resistor R10Is connected to one end of a resistor R10And the other end of (1) and an operational amplifier OP2Are connected to the inverting input terminal of an operational amplifier OP2And the operational amplifier OP2Is connected with a resistor R between the output ends11An operational amplifier OP2Output of (2)Its ends are respectively connected with voltage module I and voltage module II, and operational amplifier OP2And the non-inverting input terminal of the operational amplifier OP1The inverting input terminals of the two-way switch are all grounded.
The voltage module I comprises a memristor M1Memory resistance M2Capacitor C1Resistance R12And operational amplifier OP3The synapse module I comprises a memristor M5Resistance R14Operational amplifier OP4Mathematical operation unit ABM1Operational amplifier OP17And a power supply V5(ii) a The memristor M1K pole and memristor M2Is connected with an operational amplifier OP2Is connected with the output end of the memory resistor M1A pole and memristor M2A pole of (1) is all connected with an operational amplifier OP3Are connected to the inverting input terminal of an operational amplifier OP3And the operational amplifier OP3Is connected with a resistor R between the output ends12Resistance R12A capacitor C is connected in parallel1An operational amplifier OP3Respectively with memristor M5K pole, mathematical operation unit ABM1IN of2Input end connected to memory resistor M5A pole of (1) and an operational amplifier OP4Are connected to the inverting input terminal of an operational amplifier OP4And the operational amplifier OP4Is connected with a resistor R between the output ends14An operational amplifier OP4Output end and mathematical operation unit ABM1IN of1Input ends are connected, and a mathematical operation unit ABM1OUT output terminal and operational amplifier OP17Are connected to the non-inverting input terminal of an operational amplifier OP17And the inverting input terminal of the power supply V5Is connected to the positive pole of an operational amplifier OP17The output end of the signal processing module is respectively connected with the suppression signal judgment module II and the promotion signal judgment module II; operational amplifier OP3Positive phase input terminal of, operational amplifier OP4Positive phase input terminal and power supply V5The cathodes of the two are all grounded.
As shown in the synaptic neuron I in FIG. 1, the memristor M1And memory resistance M2K pole and operational amplifier OP2Is connected at 0-18S, the input signal U0Voltage value of less than memristor M1And memory resistance M2Threshold voltage of, memristor M1The resistance value of (1) is maintained at 300 omega, and the memory resistance M2Is maintained at 350 omega, and at 18-30S, the input signal U is0Voltage value of greater than memristor M1Positive threshold voltage of, memristor M1The resistance value of the resistor rapidly drops from 600 omega to 300 omega, and the memristor M2Is kept constant, at 30-60S, the input signal U is0Voltage value of greater than memristor M1Negative threshold voltage and memristor M2Positive threshold voltage of, memristor M1The resistance value of the resistor rises to 600 omega rapidly, and the memory resistance M2Decreases from 350 omega to 300 omega, at 60-90S the input signal U0Voltage value of less than memristor M1And memory resistance M2Threshold voltage of, memristor M1And memory resistance M2The resistance value of (a) remains unchanged. Capacitor C1Resistance R12Operational amplifier OP3Inverting input terminal and memristor M1And memory resistance M2Is connected to the A pole of the operational amplifier OP3The non-inverting input terminal of the capacitor C is grounded1Another terminal, resistance R12The other end, an operational amplifier OP3Output terminal and memristor M5K poles of (1) are connected, and the memristor M is between 0 and 30S5The resistance value of the resistor is reduced from 800 omega to 200 omega, and the memristor M is arranged between 30 and 60S5The resistance value of (1) rises from 200 Ω to 1K Ω, and a specific simulation diagram is shown in fig. 4. At memory resistance M5A pole and a resistor R14And operational amplifier OP4Are connected to the inverting input terminal of an operational amplifier OP4The non-inverting input end of the resistor R is grounded14And the other end of the operational amplifier OP4Output end and mathematical operation unit ABM1One input end is connected with a mathematical operation unit ABM1The other end and a capacitor C1Another terminal, resistance R12The other end, an operational amplifier OP3Are connected to the output of, ABM1Has an output value of-IN2/IN1*10＝M 5100, mathematical operation unit ABM1Output terminal of and operational amplifier OP17Are connected to the non-inverting input terminal of an operational amplifier OP17And the inverting input terminal of the power supply V5Is connected with the positive pole of the power supply V5Is grounded at the negative pole, and an operational amplifier OP17Corresponding to a threshold value of V5When OP is an activation function17The voltage received by the non-inverting input end is less than V5When is OP17outputting-5V voltage, when the received voltage is greater than V5When is OP17And 5v voltage is output and fed back to the promotion module II and the inhibition module II. The synaptic neuron module is used for simulating synapses and neurons in the biological neural network by changing M5Can change the magnitude of synaptic strength, M5The smaller the resistance value, the greater the synaptic strength.
The voltage module II comprises a memristor M3Memory resistance M4Capacitor C2Resistance R13Operational amplifier OP5The synapse module II comprises a memristor M6Resistance R15Operational amplifier OP6Mathematical operation unit ABM2Operational amplifier OP7Operational amplifier OP8Power supply V6And a power supply V7(ii) a Memory resistance M3K pole and memristor M4Is connected with an operational amplifier OP2Is connected with the output end of the memory resistor M3A pole and memristor M4A pole of (1) is all connected with an operational amplifier OP5Are connected to the inverting input terminal of an operational amplifier OP5And the operational amplifier OP5Is connected with a resistor R between the output ends13Resistance R13A capacitor C is connected in parallel2An operational amplifier OP5Respectively with memristor M6K pole, mathematical operation unit ABM2IN of2Input end connected to memory resistor M6A pole of (1) and an operational amplifier OP6Are connected to the inverting input terminal of an operational amplifier OP6And the operational amplifier OP6Is connected with a resistor R between the output ends15An operational amplifier OP6Output end and mathematical operation unit ABM2IN of1Input ends are connected, and a mathematical operation unit ABM2Respectively with the operational amplifier OP7Positive phase input terminal of, operational amplifier OP8Are connected to the inverting input terminal of an operational amplifier OP7And the inverting input terminal of the power supply V6Is connected to the positive pole of an operational amplifier OP7The output end of the operational amplifier is respectively connected with an inhibiting signal judging module I and an inhibiting signal receiving and processing module II, and the operational amplifier OP8Positive phase input terminal and power supply V7Is connected to the positive pole of an operational amplifier OP8The output end of the signal processing module is respectively connected with the promotion signal judgment module I and the promotion signal receiving processing module II; operational amplifier OP5Positive phase input terminal of, operational amplifier OP6Positive phase input terminal of, power supply V6Negative electrode of (2) and power supply V7The cathodes of the two are all grounded.
Memristor M as shown by synaptic neuron II in FIG. 13And memory resistance M4K pole and operational amplifier OP2Is connected to the output terminal of the input signal U0Voltage value of less than memristor M1And memory resistance M2At a threshold voltage of 0-30S, memristor M3And memory resistance M4Keeping unchanged, at 30-60S, inputting signal U0Voltage value of greater than memristor M3And memory resistance M4Negative threshold voltage of, memristor M3And memory resistance M4The resistance value of the resistor rapidly rises from 300 omega to 600 omega, and the memristor M is memorized at 60-90S3The resistance value of (1) is kept constant, and a signal U is input0Voltage value of greater than memristor M4Positive threshold voltage of, memristor M4The resistance value of (c) falls to 300 omega. Capacitor C2Resistance R13Operational amplifier OP5Inverting input terminal and memristor M3And memory resistance M4Is connected to the A pole of the operational amplifier OP5The non-inverting input terminal of the capacitor C is grounded2Another terminal, resistance R13The other end, an operational amplifier OP5Output terminal and memristor M6K poles of (1) are connected, and the memristor M is in 0-30s6The resistance value of the resistor is reduced from 900 omega to 200 omega, and the memristor M is arranged between 30 and 60S5The resistance value of (1) rises from 200 Ω to 1K Ω, and a specific simulation diagram is shown in fig. 4. Memory resistance M6A pole and a resistor R15And operational amplifier OP6Are connected to the inverting input terminal of an operational amplifier OP6The non-inverting input end of the resistor R is grounded15And the other end of the operational amplifier OP6Output end and mathematical operation unit ABM2One input end is connected with a mathematical operation unit ABM2The other end and a capacitor C2Another terminal, resistance R13The other end, an operational amplifier OP5Are connected to the output of, ABM2Has an output value of-IN2/IN1*10＝M6100, mathematical operation unit ABM2Output terminal of and operational amplifier OP7Are connected to the non-inverting input terminal of an operational amplifier OP7And the inverting input terminal of the power supply V6Is connected to the positive pole of an operational amplifier OP7Corresponding to a threshold value of V6When OP is an activation function7The voltage received by the non-inverting input end is more than V5When is OP17Outputting 5V voltage, when the received voltage is less than V5Time-lapse operational amplifier OP7Outputting 0v voltage, and feeding back the voltage to the promotion module I; mathematical operation unit ABM2Output terminal of and operational amplifier OP8When OP is connected to the inverting input terminal8The voltage received by the inverting input terminal is less than V7When is OP17Outputting 5V voltage, when the received voltage is larger than V7Time-lapse operational amplifier OP8And outputting 0v voltage, and feeding back the voltage to the inhibition promoting module II. The synaptic neuron module is used for simulating synapses and neurons in the biological neural network by changing M6Can change the magnitude of synaptic strength, M6The smaller the resistance value, the greater the synaptic strength.
The suppression signal judgment module I comprises an AND gate D2Voltage controlled switch S3Voltage pulse source V3And a resistance R16(ii) a The suppression signal receiving and processing module I comprises a memristor M7Operational amplifier OP9And a resistance R17(ii) a The suppression signal recovery module I comprises a voltage-controlled switch S5And a resistance R18(ii) a The AND gate D2Respectively connected with the pulse power signal and the operational amplifier OP7Is connected with the output end of the AND gate D2Output terminal of and voltage-controlled switch S3Of (1)Input terminals connected, voltage-controlled switch S3The inverting input terminal of the voltage-controlled switch S is grounded3Respectively with the memristor M7K pole, resistance R16Is connected to one end of a voltage-controlled switch S3Second contact of (2) and voltage pulse source V3Is connected with the positive pole of the voltage pulse source V3Respectively with the resistance R16Another end of (S), voltage controlled switch5Is connected with the positive phase input end of the voltage pulse source V3Negative pole of (1) is grounded, memory resistance M7A pole of (1) and an operational amplifier OP9Are connected to the inverting input terminal of an operational amplifier OP9And the operational amplifier OP9Is connected with a resistor R between the output ends17An operational amplifier OP9The non-inverting input terminal of (1) is grounded, and an operational amplifier OP9Output terminal and resistor R5Is connected with the other end of the voltage-controlled switch S to output a suppression voltage with a negative penalty5First contact of (3) and resistor R18Is connected to one end of a voltage-controlled switch S5Second contact of (3) and resistor R5Is connected to the other end of the resistor R18And the other end of the voltage-controlled switch S5The inverting input terminals of the two-way switch are all grounded.
As shown in the inhibition module I in FIG. 1, the synaptic neuron module II outputs a signal U2And the pulse power signal output signal U6A control inhibition signal judgment module I for outputting a signal U when a synaptic neuron module II outputs a signal U2And a pulse power signal output signal U6All output high level, then AND gate D2The conduction and suppression signal judgment module I starts to respond to enable the voltage-controlled switch S3Conducting output power supply V3The output end of the voltage-controlled switch is connected with a protective resistor R16Protection resistor R16Another end of (S), voltage controlled switch3Negative input terminal and voltage pulse source V3Voltage controlled switch S with grounded cathodes3One contact of (1) and memristor M7When the voltage-controlled switch S is connected3The output voltage value of one contact of the contact is less than the memristor M7Threshold voltage of, memristor M7The resistance value of (2) is maintained at 50 omega; when the voltage is controlled to switch S3The output voltage of one contact is larger than the memristor M7Threshold voltage of, memristor M7The resistance value of (1) is reduced to 32 omega, as shown in FIG. 4, the memristor M7K pole and operational amplifier OP9And the resistor R17Are connected to make the operational amplifier OP9Is output into the input signal, as shown at V (R5) in fig. 3, for implementing a negative penalty in the operative condition reflection. Voltage-controlled switch S5Positive input terminal and voltage pulse source V3Is connected to the negative pole of the voltage-controlled switch S5A contact of (2) and a protection resistor R18Connected to protect the resistor R18And the other end of the voltage-controlled switch S5All the negative input ends of the memory resistor M are grounded, so that the memory resistor M is connected7The resistance value of (c) is restored.
The suppression signal judgment module II comprises an NMOS tube T1Resistance R29Power supply V8And a power supply V9(ii) a The suppression signal receiving and processing module II comprises a memristor M8Capacitor C3Resistance R19Operational amplifier OP10Voltage summing unit SUM1Operational amplifier OP11And a power supply V10(ii) a The NMOS tube T1Gate of and operational amplifier OP17Is connected with the output end of the NMOS tube T1Respectively with a resistor R29One end of (1), memristor M8Is connected with the A pole, and the resistance R29And the other end of (C) and a power supply V8Is connected with the positive pole of the power supply V8Is grounded, and an NMOS tube T1Source and power supply V9Is connected with the positive pole of the power supply V9Negative pole of (1) is grounded, memory resistance M8K pole and operational amplifier OP10Are connected to the inverting input terminal of an operational amplifier OP10And the operational amplifier OP10Is connected with a resistor R between the output ends19Resistance R19A capacitor C is connected in parallel3An operational amplifier OP10The non-inverting input terminal of (1) is grounded, and an operational amplifier OP10And the output and voltage summing unit SUM1Is connected to the first input terminal of the voltage summing unit SUM1Second input terminal of and operational amplifier OP7Are connected to the output of the voltage summing unit SUM1Output terminal of and operational amplifier OP11Are connected to the inverting input terminal of an operational amplifier OP11Positive phase input terminal and power supply V10Is connected to the positive pole of an operational amplifier OP11Output terminal and resistor R7Is connected to output a positive reward for a negative penalty, as shown by V (R7) in figure 3, source V10The negative electrode of (2) is grounded.
As shown in the inhibition block II in FIG. 1, the synaptic neuron module I outputs a signal U1A control inhibition signal judgment module II for outputting a signal U when the synaptic neuron module I outputs a signal U1When outputting high level, NMOS transistor T1Output through protective resistor R29Power supply V8Power supply V8Output low level, memristor M8A pole and NMOS tube T1Connected, power supply V8Output signal of lower than memristor M8Threshold voltage of (2), as shown in FIG. 4, memristor M8The resistance value of (1) is maintained at 1K omega; when synaptic neuron module II outputs signal U1When outputting low level, NMOS transistor T1Power supply V outputting high level8Is greater than memristor M8Threshold voltage of, memristor M8The resistance value of the resistor is quickly reduced to 100 omega, and the memory resistance M8K pole and operational amplifier OP9The inverting input terminal and the resistor R of19Is connected with a capacitor C3 and has a memristor M8Respectively with a capacitor C3One terminal of (1), resistance R19And an operational amplifier OP10Are connected to the inverting input terminal of an operational amplifier OP10The non-inverting input terminal of the voltage summing unit SUM is grounded1Is respectively connected with the capacitor C3Another terminal of (1), a resistor R19And the other end of the operational amplifier OP10Is connected to the output of the first voltage summing unit SUM, and the inhibitory signal of the synaptic neuron II is passed through the voltage summing unit SUM1Is inputted to the other input terminal of the operational amplifier OP11And the voltage summing unit SUM1Is connected to the output terminal of the power supply V10Positive electrode of and operational amplifier OP11Are connected if the voltage is summedMeta SUM1Is greater than the power supply V10Of (2) an operational amplifier OP11Output-0.4 v voltage if unit SUM1Is less than the power supply V10Of (2) an operational amplifier OP11Output 0.2v voltage, OP11The output signal of the system is fed back to the input signal, and the function of inhibiting the negative punishment by the positive reward is realized.
The promotion signal judgment module I comprises an AND gate D3Voltage controlled switch S4Voltage pulse source V4And a resistance R20(ii) a The facilitation signal receiving processing module I comprises a memristor M9Operational amplifier OP12And a resistance R21(ii) a The facilitating signal recovery module I comprises a voltage controlled switch S6And a resistance R22(ii) a The promotion signal judgment module II comprises an NMOS tube T2Resistance R30Power supply V11And a power supply V12(ii) a Memristor M of suppression signal receiving and processing module II10Capacitor C4Resistance R23Operational amplifier OP13Voltage summing unit SUM2NOT gate D5Operational amplifier OP14And a power supply V13。
The AND gate D3Respectively input ends of the NAND gates D1Output terminal of (1), operational amplifier OP8Is connected with the output end of the AND gate D3Output terminal of and voltage-controlled switch S4Are connected with a positive input terminal of a voltage-controlled switch S4The inverting input terminal of the voltage-controlled switch S is grounded4Respectively with the memristor M9K pole, resistance R20Is connected to one end of a voltage-controlled switch S4Second contact of (2) and voltage pulse source V4Is connected with the positive pole of the voltage pulse source V4Respectively with the resistance R20Another end of (S), voltage controlled switch6Is connected with the positive phase input end of the voltage pulse source V4Negative pole of (1) is grounded, memory resistance M9A pole of (1) and an operational amplifier OP12Are connected to the inverting input terminal of an operational amplifier OP12And the operational amplifier OP12Is connected with a resistor R between the output ends21Transporting and transportingOperational amplifier OP12The non-inverting input terminal of (1) is grounded, and an operational amplifier OP12Output terminal and resistor R6Is connected to output a boost voltage for a positive reward with a negative penalty, a voltage controlled switch S6First contact of (3) and resistor R22Is connected to one end of a voltage-controlled switch S6Second contact of (3) and resistor R6Is connected to the other end of the resistor R22And the other end of the voltage-controlled switch S6The inverting input terminals of the two-way switch are all grounded.
The NMOS tube T2Gate of and operational amplifier OP17Is connected with the output end of the NMOS tube T2Respectively with a resistor R30One end of (1), memristor M10Is connected with the A pole, and the resistance R30And the other end of (C) and a power supply V11Is connected with the positive pole of the power supply V11Is grounded, and an NMOS tube T2Source and power supply V12Is connected with the positive pole of the power supply V12Negative pole of (1) is grounded, memory resistance M10K pole and operational amplifier OP13Are connected to the inverting input terminal of an operational amplifier OP13And the operational amplifier OP13Is connected with a resistor R between the output ends23Resistance R23A capacitor C is connected in parallel4An operational amplifier OP13The non-inverting input terminal of (1) is grounded, and an operational amplifier OP13And the output and voltage summing unit SUM2Is connected to the first input terminal of the voltage summing unit SUM2The second input end of the NAND gate D5Is connected to the output of the NOT gate D5And operational amplifier OP8Are connected to the output of the voltage summing unit SUM2Output terminal of and operational amplifier OP14Are connected to the inverting input terminal of an operational amplifier OP14Positive phase input terminal and power supply V13Is connected to the positive pole of an operational amplifier OP14Output terminal and resistor R8Is connected to a power supply V13The negative electrode of (2) is grounded.
As shown in the promotion block I in FIG. 1, the synaptic neuron block II outputs a signal U4And the pulse power signal output signal U8Control promotion messageA signal judgment module I for outputting a signal U when the synaptic neuron module II outputs a signal U4And a pulse power signal output signal U8All output high level, then AND gate D3Conducting to promote the signal judgment module II to start response and enable the voltage-controlled switch S4Conducting output power supply V4The output end of the voltage-controlled switch is connected with a protective resistor R20Protection resistor R20Another end of (S), voltage controlled switch4Negative input terminal and voltage pulse source V4Voltage controlled switch S with grounded cathodes4One contact of (1) and memristor M9Is connected if the voltage-controlled switch S is controlled4The output voltage value of one contact of the contact is less than the memristor M9Threshold voltage of (2), as shown in FIG. 4, memristor M9The resistance value of (2) is maintained at 50 omega; when the voltage is controlled to switch S4The output voltage of one contact is larger than the memristor M9Threshold voltage of, memristor M7Quickly rises to 175 omega, and the memory resistance M9K pole and operational amplifier OP12And the resistor R21Are connected to make the operational amplifier OP12Is output into the input signal, as shown at V (R6) in fig. 3, for achieving a negative penalty is a boost to a positive excitation. Voltage-controlled switch S6Positive input terminal and voltage pulse source V4Is connected to the negative pole of the voltage-controlled switch S6A contact of (2) and a protection resistor R22Connected to protect the resistor R22And the other end of the voltage-controlled switch S6All the negative input ends of the memory resistor M are grounded, so that the memory resistor M is connected9The resistance value of (c) is restored. As shown in the promotion block II in FIG. 1, the synaptic neuron module I outputs a signal U5A control inhibition signal judgment module II for outputting a signal U when the synaptic neuron module I outputs a signal U5When outputting high level, NMOS transistor T2Output through protective resistor R30Power supply V11Power supply V11Output low level, memristor M10A pole and NMOS tube T2Connected, power supply V11Output signal of lower than memristor M10Threshold voltage of, memristor M10When the synaptic neuron module I outputs a signal U, the resistance value of the synaptic neuron module I is maintained at 1K omega5When the low level is outputted, the voltage is outputted,NMOS tube T2Power supply V outputting high level12Is greater than memristor M10Threshold voltage of, memristor M10The resistance value of the resistor is rapidly reduced to 100 omega, a specific simulation diagram is shown in FIG. 4, and the memristor M10K pole and operational amplifier OP13The inverting input terminal and the resistor R of23And a capacitor C4Connected by memristor M10Respectively with a capacitor C4One terminal of (1), resistance R23And an operational amplifier OP13Are connected to the inverting input terminal of an operational amplifier OP13The non-inverting input terminal of the voltage summing unit SUM is grounded2Is respectively connected with the capacitor C4Another terminal of (1), a resistor R23And the other end of the operational amplifier OP13Is connected to the output of the first circuit, and the inhibitory signal of the synaptic neuron II passes through the NOT gate D5Connected to a voltage summing unit SUM1Of the other input terminal of the operational amplifier OP14And the voltage summing unit SUM2Is connected to the output terminal of the power supply V13Positive electrode of and operational amplifier OP14Are connected to the non-inverting input terminal of the voltage summing unit SUM2Is greater than the power supply V13Of (2) an operational amplifier OP13Output-0.6 v if the unit SUM1Is less than the power supply V10Of (2) an operational amplifier OP11Output-0.3 v voltage, OP14Outputs a negative penalty to the boost voltage for the positive reward, as shown at V (R8) in fig. 3, and performs the boost function.
The voltage judgment module comprises a PMOS tube T3Resistance R24Power supply V15Power supply V16NMOS tube T4Resistance R25Power supply V17Power supply V18AND gate D4Voltage controlled switch S7Voltage pulse source V14Resistance R26SUM voltage summing unit SUM3. The pulse power supply signal is respectively connected with the PMOS tube T3Grid and gate D4And a voltage-controlled switch S7Are connected with the positive phase input end of a PMOS tube T3Respectively with a resistor R24One end of (1), NMOS tube T4Is connected to the gate of the resistor R24And the other end of (C) and a power supply V15Is connected with the positive pole of the power supply V15The negative electrode of the PMOS tube T is grounded3Source and power supply V16Is connected with the positive pole of the power supply V16Is grounded, and an NMOS tube T4Respectively with a resistor R25One end of (D), and gate4Is connected to the input terminal of a resistor R25And the other end of (C) and a power supply V17Is connected with the positive pole of the power supply V17Is grounded, and an NMOS tube T4Source and power supply V18Is connected with the positive pole of the power supply V18The negative electrode of (2) is grounded; voltage-controlled switch S7Respectively with the resistor R26One terminal of (1), voltage summing unit SUM3Is connected to the first input terminal of the voltage-controlled switch S7Second contact of (2) and voltage pulse source V14Is connected to the positive pole of the voltage-controlled switch S7Voltage pulse source V14Negative electrode and resistance R26The other ends of the two are grounded; and gate D4And the output and voltage summing unit SUM3Is connected to the second input terminal of the voltage summing unit SUM3The output end of the voltage receiving and processing module is connected with the voltage receiving and processing module.
The voltage receiving and processing module comprises a memristor M11A current source I1A current source I2PMOS tube T5PMOS tube T6NMOS tube T7NMOS tube T8NMOS tube T9PMOS tube T10PMOS tube T11NMOS tube T12Resistance R27Power supply V19And a power supply V20(ii) a The voltage summing unit SUM3Respectively with memristor M11A pole of (1), a resistance R27Is connected with one end of a memristor M11K pole of (1) is respectively connected with PMOS tube T6Source electrode and NMOS tube T12Is connected with the source electrode of the PMOS tube T6Gate of and current source I1Is connected to the negative pole of a current source I1Respectively with the positive electrode of the NMOS transistor T7Source electrode, power supply V19Positive electrode and NMOS transistor T8OfPole phase connection, power supply V19Negative pole of (1) is grounded, current source I1Respectively with a PMOS transistor T5Drain electrode of (D), PMOS tube T5Is connected with the grid of the PMOS tube T5Source electrode and NMOS transistor T9The source electrodes of the NMOS transistors T are all grounded9Drain electrode of (1), NMOS tube T9Grid and NMOS transistor T12Gate of the transistor is connected with a current source I2Is connected to the positive pole of the current source I2Respectively connected with a power supply V20Positive electrode of PMOS transistor T10Source electrode and PMOS transistor T11Is connected to the source of the power supply V20The negative electrode of the PMOS tube T is grounded10Drain electrode of (D), PMOS tube T10Grid and PMOS transistor T11Grid of the NMOS transistor T12Is connected with the drain electrode of the PMOS tube T11Respectively with a resistor R27Another end of (1), NMOS tube T8Is connected with a synaptic neuron module III, and an NMOS tube T8Grid electrode and NMOS tube T7Grid electrode and NMOS tube T7Drain electrodes of the PMOS transistors T6Is connected to the drain of the transistor.
As shown in the voltage control block of FIG. 1, a pulsed power signal is input to signal U6To voltage judging module, PMOS tube T3And NMOS transistor T4Corresponding to a logic gate, when the input signal U6 is at low level, the PMOS transistor T3The drain of the PMOS transistor T outputs 0v, when the input signal U6 is high level3Is output by-2.1 v and then passes through an NMOS tube T4When PMOS transistor T3When the drain output of (3) is 0v, the NMOS tube T4When the drain of the PMOS transistor T outputs 0v3When the output of the drain electrode of the NMOS transistor is-2.1 v, the NMOS transistor T4The drain of (1) outputs 1 v. Pulse power supply signal input signal U6 and NMOS tube T4Respectively with an AND gate D4Is connected with the AND gate D3The output signal outputs-1 v at low level and 1.2v at high level. Instantaneity in operationally conditioned reflection is achieved by applying a third voltage control unit which generates a negative penalty greater than that of immediately pecking a ball if the pigeon does not peck the ball for the first time when he hears the noise, and which has no effect of immediately pecking the ball even if he subsequently pecks the ballThe noise elimination effect after the yellow ball is good, such as V (M) in figure 512(1) And V (M)12(2)). By means of a current source I1A current source I2PMOS tube T5PMOS tube T6NMOS tube T7NMOS tube T8NMOS tube T9PMOS tube T10PMOS tube T11NMOS tube T12Resistance R27Power supply V19And a power supply V20The input-output ratio can be adjusted by the aid of the current mirror.
The synaptic neuron module III comprises a memristor M12Resistance R28Operational amplifier OP15Mathematical operation unit ABM3Power supply V21And operational amplifier OP16Resistance R27The other end of the memory is respectively connected with a memory resistor M12K pole, mathematical operation unit ABM3IN of2Input end connected to memory resistor M12A pole of (1) and an operational amplifier OP15Are connected to the inverting input terminal of an operational amplifier OP15And the operational amplifier OP15Is connected with a resistor R between the output ends28An operational amplifier OP15The non-inverting input terminal of (1) is grounded, and an operational amplifier OP15Output end and mathematical operation unit ABM3IN of1Input ends are connected, and a mathematical operation unit ABM3OUT output terminal and operational amplifier OP16Are connected to the non-inverting input terminal of an operational amplifier OP16And the inverting input terminal of the power supply V21Is connected with the positive pole of the power supply V21The negative electrode of (2) is grounded.
As shown in FIG. 1 for synaptic neuron III, the voltage control module outputs signal U at 0-30S12Voltage value of less than memristor M12Threshold voltage of, memristor M12The resistance value of the voltage control module is maintained at 800 omega, and the voltage control module outputs a signal U within 30-60S12Voltage value of greater than memristor M12Positive threshold voltage of, memristor M5Decreases from 800 omega to 200 omega. At memory resistance M12A pole and a resistor R28And operational amplifier OP15Are connected to the inverting input terminal of an operational amplifier OP15Is grounded at the non-inverting input endResistance R28And the other end of the operational amplifier OP15Output end and mathematical operation unit ABM3One input end is connected with a mathematical operation unit ABM3The other end and the voltage control module output signal U12Connected, ABM3Has an output value of-IN2/IN1*10＝M12100, mathematical operation unit ABM3Output terminal of and operational amplifier OP16Are connected to the non-inverting input terminal of an operational amplifier OP16And the inverting input terminal of the power supply V21Is connected with the positive pole of the power supply V21Is grounded at the negative pole, and an operational amplifier OP16Corresponding to a threshold value of V21When OP is an activation function16The voltage received by the non-inverting input end is less than V21When is OP16Inputting 0V voltage, when the received voltage is greater than V5When is OP17Outputting 5v voltage.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. A memristance-based operational conditioned reflex circuit is characterized by comprising an input module, a voltage control module, a promotion module I, a promotion module II, an inhibition module I, an inhibition module II, a synaptic neuron module I, a synaptic neuron module II and a synaptic neuron module III; the input module is respectively connected with a pulse power signal, a promoting module I, a promoting module II, an inhibiting module I, an inhibiting module II, a synaptic neuron module I and a synaptic neuron module II, the synaptic neuron module II is respectively connected with the promoting module I, the promoting module II, the inhibiting module I and the inhibiting module II, and the synaptic neuron module I is respectively connected with the promoting module II and the inhibiting module II; the pulse power supply signal is respectively connected with a voltage control module and an inhibition module I, and the voltage control module is connected with a synaptic neuron module III.
2. The memristance-based operative conditional reflection circuit of claim 1, wherein the input module comprises a first voltage-controlled cell, a second voltage-controlled cell, and a summing unit; the synaptic neuron module I comprises a voltage module I and a synaptic module I; the synaptic neuron module II comprises a voltage module II and a synaptic module II; the suppression module I comprises a suppression signal judgment module I, a suppression signal receiving and processing module I and a suppression signal recovery module I; the inhibition module II comprises an inhibition signal judgment module II and an inhibition signal receiving and processing module II; the promoting module I comprises a promoting signal judging module I, a promoting signal receiving and processing module I and a promoting signal restoring module I; the promoting module II comprises a promoting signal judging module II and a promoting signal receiving and processing module II; the voltage control module comprises a voltage judging module and a voltage receiving and processing module;
an input end NAND gate D of the first voltage control unit1Is connected to the output of the NOT gate D1The input end of the first voltage control unit is connected with a pulse power supply signal, the pulse power supply signal is respectively connected with the input end of the second voltage control unit, the inhibition signal judgment module I and the voltage judgment module, the voltage judgment module is connected with the voltage receiving and processing module, and the voltage receiving and processing module is connected with the synaptic neuron module III; the output end of the first voltage control unit and the output end of the second voltage control unit are respectively connected with the input end of the addition operation unit; the output end of the addition operation unit is respectively connected with a promoting signal receiving and processing module I, a promoting signal receiving and processing module II, an inhibiting signal receiving and processing module I, an inhibiting signal receiving and processing module II, a voltage module I and a voltage module II, wherein the voltage module I is connected with a synapse module I, the synapse module I is respectively connected with a promoting signal judging module II and an inhibiting signal judging module II, the voltage module II is connected with the synapse module II, and the synapse module II is respectively connected with an inhibiting signal judging module I, an inhibiting signal receiving and processing module II, a promoting signal judging module I and a promoting signal receiving module II; the promotion signal judgment module I is respectively an NAND gate D1The output end of the signal receiving and processing module I, the signal receiving and processing promotion module I and the signal recovery promotion module I are connected, and the signal judgment promotion module II is connected with the signal receiving and processing promotion module II; suppression signal judging moduleThe block I is respectively connected with a pulse power signal, a suppression signal receiving and processing module I and a suppression signal recovery module I; and the suppression signal judgment module II is connected with the suppression signal receiving and processing module II.
3. The memristance-based operative conditionally reflective circuit of claim 2, wherein the first voltage-controlled cell comprises a voltage-controlled switch S1Power supply V1And a resistance R1(ii) a The second voltage control unit comprises a voltage controlled switch S2Power supply V2And a resistance R2(ii) a The addition unit includes a resistor R3Resistance R4Resistance R5Resistance R6Resistance R7Resistance R8Resistance R9Resistance R10Resistance R11Operational amplifier OP1And operational amplifier OP2；
Voltage-controlled switch S1Non-gate D of the positive input end1Is connected to the output terminal of the voltage-controlled switch S1Respectively with the resistor R1One terminal of (1), resistance R3Is connected to one end of a voltage-controlled switch S1Second contact of and power supply V1Is connected with the positive pole of the power supply V1Negative electrode of (2), resistance R1And the other end of the voltage-controlled switch S1The inverting input ends of the two-way switch are grounded;
voltage-controlled switch S2The positive phase input end of the voltage-controlled switch S is connected with a pulse power supply signal2Respectively with the resistor R2One terminal of (1), resistance R4Is connected to one end of a voltage-controlled switch S2Second contact of and power supply V2Is connected with the positive pole of the power supply V2Negative electrode of (2), resistance R2And the other end of the voltage-controlled switch S2The inverting input ends of the two-way switch are grounded;
resistance R3The other end of each of the resistors R and R is connected with5One terminal of (1), resistance R7And an operational amplifier OP1Is connected with the positive input end of the resistor R5The other end of the resistor R is connected with a suppression signal receiving and processing module I, and the resistor R7The other end of (2) and a suppressorThe number receiving processing module II is connected; resistance R4The other end of each of the resistors R and R is connected with6One terminal of (1), resistance R8And an operational amplifier OP1Is connected with the positive input end of the resistor R6Is connected with the signal receiving and processing facilitating module I, and a resistor R8Is connected with a signal receiving and processing facilitating module II, an operational amplifier OP1The non-inverting input terminal and the operational amplifier OP1Is connected with a resistor R between the output ends9An operational amplifier OP1Output terminal and resistor R10Is connected to one end of a resistor R10And the other end of (1) and an operational amplifier OP2Are connected to the inverting input terminal of an operational amplifier OP2And the operational amplifier OP2Is connected with a resistor R between the output ends11An operational amplifier OP2The output end of the operational amplifier is respectively connected with a voltage module I and a voltage module II, and the operational amplifier OP2And the non-inverting input terminal of the operational amplifier OP1The inverting input terminals of the two-way switch are all grounded.
4. The memristive-based operative conditionally reflective circuit of claim 3, wherein the voltage block I comprises a memristance M1Memory resistance M2Capacitor C1Resistance R12And operational amplifier OP3The synapse module I comprises a memristor M5Resistance R14Operational amplifier OP4Mathematical operation unit ABM1Operational amplifier OP17And a power supply V5(ii) a The memristor M1K pole and memristor M2Is connected with an operational amplifier OP2Is connected with the output end of the memory resistor M1A pole and memristor M2A pole of (1) is all connected with an operational amplifier OP3Are connected to the inverting input terminal of an operational amplifier OP3And the operational amplifier OP3Is connected with a resistor R between the output ends12Resistance R12A capacitor C is connected in parallel1An operational amplifier OP3Respectively with memristor M5K pole, mathematical operation unit ABM1IN of2Input end connected to memory resistor M5A pole of (1) and an operational amplifier OP4Are connected to the inverting input terminal of an operational amplifier OP4And the operational amplifier OP4Is connected with a resistor R between the output ends14An operational amplifier OP4Output end and mathematical operation unit ABM1IN of1Input ends are connected, and a mathematical operation unit ABM1OUT output terminal and operational amplifier OP17Are connected to the non-inverting input terminal of an operational amplifier OP17And the inverting input terminal of the power supply V5Is connected to the positive pole of an operational amplifier OP17The output end of the signal processing module is respectively connected with the suppression signal judgment module II and the promotion signal judgment module II; operational amplifier OP3Positive phase input terminal of, operational amplifier OP4Positive phase input terminal and power supply V5The cathodes of the two are all grounded.
5. The memristive-based operative conditionally reflective circuit of claim 4, wherein the voltage module II comprises a memristor M3Memory resistance M4Capacitor C2Resistance R13Operational amplifier OP5The synapse module II comprises a memristor M6Resistance R15Operational amplifier OP6Mathematical operation unit ABM2Operational amplifier OP7Operational amplifier OP8Power supply V6And a power supply V7(ii) a Memory resistance M3K pole and memristor M4Is connected with an operational amplifier OP2Is connected with the output end of the memory resistor M3A pole and memristor M4A pole of (1) is all connected with an operational amplifier OP5Are connected to the inverting input terminal of an operational amplifier OP5And the operational amplifier OP5Is connected with a resistor R between the output ends13Resistance R13A capacitor C is connected in parallel2An operational amplifier OP5Respectively with memristor M6K pole, mathematical operation unit ABM2IN of2Input end connected to memory resistor M6A pole of (1) and an operational amplifier OP6Is connected with the inverting input terminalAn operational amplifier OP6And the operational amplifier OP6Is connected with a resistor R between the output ends15An operational amplifier OP6Output end and mathematical operation unit ABM2IN of1Input ends are connected, and a mathematical operation unit ABM2Respectively with the operational amplifier OP7Positive phase input terminal of, operational amplifier OP8Are connected to the inverting input terminal of an operational amplifier OP7And the inverting input terminal of the power supply V6Is connected to the positive pole of an operational amplifier OP7The output end of the operational amplifier is respectively connected with an inhibiting signal judging module I and an inhibiting signal receiving and processing module II, and the operational amplifier OP8Positive phase input terminal and power supply V7Is connected to the positive pole of an operational amplifier OP8The output end of the signal processing module is respectively connected with the promotion signal judgment module I and the promotion signal receiving processing module II; operational amplifier OP5Positive phase input terminal of, operational amplifier OP6Positive phase input terminal of, power supply V6Negative electrode of (2) and power supply V7The cathodes of the two are all grounded.
6. The memristance-based operative conditioned reflex circuit according to claim 5, wherein the inhibit signal determination module I comprises an AND gate D2Voltage controlled switch S3Voltage pulse source V3And a resistance R16(ii) a The suppression signal receiving and processing module I comprises a memristor M7Operational amplifier OP9And a resistance R17(ii) a The suppression signal recovery module I comprises a voltage-controlled switch S5And a resistance R18(ii) a The AND gate D2Respectively connected with the pulse power signal and the operational amplifier OP7Is connected with the output end of the AND gate D2Output terminal of and voltage-controlled switch S3Are connected with a positive input terminal of a voltage-controlled switch S3The inverting input terminal of the voltage-controlled switch S is grounded3Respectively with the memristor M7K pole, resistance R16Is connected to one end of a voltage-controlled switch S3Second contact of (2) and voltage pulse source V3Is connected with the positive pole of the voltage pulse source V3Of the negative electrodeRespectively associated with the resistor R16Another end of (S), voltage controlled switch5Is connected with the positive phase input end of the voltage pulse source V3Negative pole of (1) is grounded, memory resistance M7A pole of (1) and an operational amplifier OP9Are connected to the inverting input terminal of an operational amplifier OP9And the operational amplifier OP9Is connected with a resistor R between the output ends17An operational amplifier OP9The non-inverting input terminal of (1) is grounded, and an operational amplifier OP9Output terminal and resistor R5Is connected to the other end of the voltage-controlled switch S5First contact of (3) and resistor R18Is connected to one end of a voltage-controlled switch S5Second contact of (3) and resistor R5Is connected to the other end of the resistor R18And the other end of the voltage-controlled switch S5The inverting input ends of the two-way switch are grounded;
the suppression signal judgment module II comprises an NMOS tube T1Resistance R29Power supply V8And a power supply V9(ii) a The suppression signal receiving and processing module II comprises a memristor M8Capacitor C3Resistance R19Operational amplifier OP10Voltage summing unit SUM1Operational amplifier OP11And a power supply V10(ii) a The NMOS tube T1Gate of and operational amplifier OP17Is connected with the output end of the NMOS tube T1Respectively with a resistor R29One end of (1), memristor M8Is connected with the A pole, and the resistance R29And the other end of (C) and a power supply V8Is connected with the positive pole of the power supply V8Is grounded, and an NMOS tube T1Source and power supply V9Is connected with the positive pole of the power supply V9Negative pole of (1) is grounded, memory resistance M8K pole and operational amplifier OP10Are connected to the inverting input terminal of an operational amplifier OP10And the operational amplifier OP10Is connected with a resistor R between the output ends19Resistance R19A capacitor C is connected in parallel3An operational amplifier OP10The non-inverting input terminal of (1) is grounded, and an operational amplifier OP10And the output and voltage summing unit SUM1Is connected to the first input terminal of the voltage summing unit SUM1Second input terminal of and operational amplifier OP7Are connected to the output of the voltage summing unit SUM1Output terminal of and operational amplifier OP11Are connected to the inverting input terminal of an operational amplifier OP11Positive phase input terminal and power supply V10Is connected to the positive pole of an operational amplifier OP11Output terminal and resistor R7Is connected to a power supply V10The negative electrode of (2) is grounded.
7. The memristance-based operative conditioned reflex circuit according to claim 5, wherein the facilitation signal judgment module I comprises an AND gate D3Voltage controlled switch S4Voltage pulse source V4And a resistance R20(ii) a The facilitation signal receiving processing module I comprises a memristor M9Operational amplifier OP12And a resistance R21(ii) a The facilitating signal recovery module I comprises a voltage controlled switch S6And a resistance R22(ii) a The promotion signal judgment module II comprises an NMOS tube T2Resistance R30Power supply V11And a power supply V12(ii) a Memristor M of suppression signal receiving and processing module II10Capacitor C4Resistance R23Operational amplifier OP13Voltage summing unit SUM2NOT gate D5Operational amplifier OP14And a power supply V13；
The AND gate D3Respectively input ends of the NAND gates D1Output terminal of (1), operational amplifier OP8Is connected with the output end of the AND gate D3Output terminal of and voltage-controlled switch S4Are connected with a positive input terminal of a voltage-controlled switch S4The inverting input terminal of the voltage-controlled switch S is grounded4Respectively with the memristor M9K pole, resistance R20Is connected to one end of a voltage-controlled switch S4Second contact of (2) and voltage pulse source V4Is connected with the positive pole of the voltage pulse source V4Respectively with the resistance R20Another end of (S), voltage controlled switch6Is connected with the positive phase input end of the voltage pulse source V4Negative pole of (1) is grounded, memory resistance M9A pole and operational amplifierAmplifier OP12Are connected to the inverting input terminal of an operational amplifier OP12And the operational amplifier OP12Is connected with a resistor R between the output ends21An operational amplifier OP12The non-inverting input terminal of (1) is grounded, and an operational amplifier OP12Output terminal and resistor R6Is connected to the other end of the voltage-controlled switch S6First contact of (3) and resistor R22Is connected to one end of a voltage-controlled switch S6Second contact of (3) and resistor R6Is connected to the other end of the resistor R22And the other end of the voltage-controlled switch S6The inverting input ends of the two-way switch are grounded;
the NMOS tube T2Gate of and operational amplifier OP17Is connected with the output end of the NMOS tube T2Respectively with a resistor R30One end of (1), memristor M10Is connected with the A pole, and the resistance R30And the other end of (C) and a power supply V11Is connected with the positive pole of the power supply V11Is grounded, and an NMOS tube T2Source and power supply V12Is connected with the positive pole of the power supply V12Negative pole of (1) is grounded, memory resistance M10K pole and operational amplifier OP13Are connected to the inverting input terminal of an operational amplifier OP13And the operational amplifier OP13Is connected with a resistor R between the output ends23Resistance R23A capacitor C is connected in parallel4An operational amplifier OP13The non-inverting input terminal of (1) is grounded, and an operational amplifier OP13And the output and voltage summing unit SUM2Is connected to the first input terminal of the voltage summing unit SUM2The second input end of the NAND gate D5Is connected to the output of the NOT gate D5And operational amplifier OP8Are connected to the output of the voltage summing unit SUM2Output terminal of and operational amplifier OP14Are connected to the inverting input terminal of an operational amplifier OP14Positive phase input terminal and power supply V13Is connected to the positive pole of an operational amplifier OP14Output terminal and resistor R8Is connected to a power supply V13The negative electrode of (2) is grounded.
8. The memristor-based operative conditioned reflex circuit according to any one of claims 2 to 7, wherein the voltage judging module comprises a PMOS tube T3Resistance R24Power supply V15Power supply V16NMOS tube T4Resistance R25Power supply V17Power supply V18AND gate D4Voltage controlled switch S7Voltage pulse source V14Resistance R26SUM voltage summing unit SUM3；
The pulse power supply signal is respectively connected with the PMOS tube T3Grid and gate D4And a voltage-controlled switch S7Are connected with the positive phase input end of a PMOS tube T3Respectively with a resistor R24One end of (1), NMOS tube T4Is connected to the gate of the resistor R24And the other end of (C) and a power supply V15Is connected with the positive pole of the power supply V15The negative electrode of the PMOS tube T is grounded3Source and power supply V16Is connected with the positive pole of the power supply V16Is grounded, and an NMOS tube T4Respectively with a resistor R25One end of (D), and gate4Is connected to the input terminal of a resistor R25And the other end of (C) and a power supply V17Is connected with the positive pole of the power supply V17Is grounded, and an NMOS tube T4Source and power supply V18Is connected with the positive pole of the power supply V18The negative electrode of (2) is grounded; voltage-controlled switch S7Respectively with the resistor R26One terminal of (1), voltage summing unit SUM3Is connected to the first input terminal of the voltage-controlled switch S7Second contact of (2) and voltage pulse source V14Is connected to the positive pole of the voltage-controlled switch S7Voltage pulse source V14Negative electrode and resistance R26The other ends of the two are grounded; and gate D4And the output and voltage summing unit SUM3Is connected to the second input terminal of the voltage summing unit SUM3The output end of the voltage receiving and processing module is connected with the voltage receiving and processing module.
9. The memristance-based operative bar of claim 8A voltage receiving processing module comprising a memristor M11A current source I1A current source I2PMOS tube T5PMOS tube T6NMOS tube T7NMOS tube T8NMOS tube T9PMOS tube T10PMOS tube T11NMOS tube T12Resistance R27Power supply V19And a power supply V20(ii) a The voltage summing unit SUM3Respectively with memristor M11A pole of (1), a resistance R27Is connected with one end of a memristor M11K pole of (1) is respectively connected with PMOS tube T6Source electrode and NMOS tube T12Is connected with the source electrode of the PMOS tube T6Gate of and current source I1Is connected to the negative pole of a current source I1Respectively with the positive electrode of the NMOS transistor T7Source electrode, power supply V19Positive electrode and NMOS transistor T8Is connected to the source of the power supply V19Negative pole of (1) is grounded, current source I1Respectively with a PMOS transistor T5Drain electrode of (D), PMOS tube T5Is connected with the grid of the PMOS tube T5Source electrode and NMOS transistor T9The source electrodes of the NMOS transistors T are all grounded9Drain electrode of (1), NMOS tube T9Grid and NMOS transistor T12Gate of the transistor is connected with a current source I2Is connected to the positive pole of the current source I2Respectively connected with a power supply V20Positive electrode of PMOS transistor T10Source electrode and PMOS transistor T11Is connected to the source of the power supply V20The negative electrode of the PMOS tube T is grounded10Drain electrode of (D), PMOS tube T10Grid and PMOS transistor T11Grid of the NMOS transistor T12Is connected with the drain electrode of the PMOS tube T11Respectively with a resistor R27Another end of (1), NMOS tube T8Is connected with a synaptic neuron module III, and an NMOS tube T8Grid electrode and NMOS tube T7Grid electrode and NMOS tube T7Drain electrodes of the PMOS transistors T6Is connected to the drain of the transistor.
10. The memristive-based operative conditioned reflex circuit of claim 9, wherein the synaptic neuron module III comprising a memristor M12Resistance R28Operational amplifier OP15Mathematical operation unit ABM3Power supply V21And operational amplifier OP16Resistance R27The other end of the memory is respectively connected with a memory resistor M12K pole, mathematical operation unit ABM3IN of2Input end connected to memory resistor M12A pole of (1) and an operational amplifier OP15Are connected to the inverting input terminal of an operational amplifier OP15And the operational amplifier OP15Is connected with a resistor R between the output ends28An operational amplifier OP15The non-inverting input terminal of (1) is grounded, and an operational amplifier OP15Output end and mathematical operation unit ABM3IN of1Input ends are connected, and a mathematical operation unit ABM3OUT output terminal and operational amplifier OP16Are connected to the non-inverting input terminal of an operational amplifier OP16And the inverting input terminal of the power supply V21Is connected with the positive pole of the power supply V21The negative electrode of (2) is grounded.
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