CN116894470A - Neural functional circuit for simulating animal operability conditional reflex - Google Patents
Neural functional circuit for simulating animal operability conditional reflex Download PDFInfo
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Abstract
The invention relates to the technical field of nerve function circuits, in particular to a nerve function circuit for simulating animal operability condition reflex, which comprises the following steps of simulating the use of food to conduct reward training on animals through a food training circuit, and triggering the animal operability condition reflex; wherein, food training circuit includes: the food voltage control module, the food synaptic neuron module, the pull rod voltage control module and the pull rod synaptic module are electrically connected; the food voltage control module performs delay control, simulates a food reward signal to delay the time of the pull rod signal, and outputs voltage to control the food synaptic neuron module; the food synapse neuron module simulates the influence of food on the action of the pull rod, and outputs voltage to control the pull rod synapse module; the pull rod voltage control module outputs voltage to control the pull rod synaptic module; the pull rod synapse module simulates a biological pull rod behavior. The invention solves the problem that the prior circuit does not consider the influence of rewarding delay behavior on the biological learning speed.
Description
Technical Field
The invention relates to the technical field of nerve functional circuits, in particular to a nerve functional circuit for simulating animal operability conditional reflex.
Background
Memristors are emerging nanoscale electronic devices, are widely applied to the fields of information storage, logic operation, neural networks, biological behavior simulation and the like, and have huge application prospects. Memristors are nonvolatile and can be used for simulating biological synapses so as to construct a neural functional circuit and realize biological learning and memory functions.
Operative conditional reflex is a process and method of behavior modification caused by stimulus, which affects the probability of behavior occurrence after rewarding or punishing the behavior, and synaptic plasticity establishes a link between stimulus and behavior, so that an organism can adjust its behavior according to stimulus. Some scholars have proposed memrist-based operative conditional reflex circuits, but do not consider the impact of rewarding delay behavior on the speed of bio-learning, and the present invention proposes a neuro-functional circuit that addresses these issues.
Disclosure of Invention
Aiming at the defects of the prior art, the invention realizes the analysis of the biological learning speed under different delay rewards by changing the time of the reward delay behavior; by changing the intensity of the stimulus, the analysis of the learning speed by the intensity of the stimulus is realized.
The technical scheme adopted by the invention is as follows: a nerve functional circuit for simulating animal operability condition reflex, which simulates the use of food to conduct rewarding training on animals through a food training circuit and triggers the animal operability condition reflex; wherein,,
the food training circuit includes: the food voltage control module, the food synaptic neuron module, the pull rod voltage control module and the pull rod synaptic module are electrically connected;
the food voltage control module performs delay control, simulates a food reward signal to delay the time of the pull rod signal, and outputs voltage to control the food synaptic neuron module;
the food synapse neuron module simulates the influence of food on the action of the pull rod, and outputs voltage to control the pull rod synapse module;
the pull rod voltage control module outputs voltage to control the pull rod synaptic module;
the pull rod synapse module simulates a biological pull rod behavior.
Further, the method further comprises the following steps: simulating punishment training on animals by using electric shock through an electric shock training circuit, and triggering the operational conditional reflex of the animals; wherein,,
the electric shock training circuit includes: a weak stimulation synaptic neuron module, a strong stimulation synaptic neuron module and a button synaptic die electrically connected in sequence;
the weak stimulation synaptic neuron module simulates the influence of weak stimulation on the reflection of biological operability conditions and outputs voltage to control the button synaptic module;
the strong stimulation synaptic neuron module simulates the influence of strong stimulation on the biological operability condition reflex, and the output voltage controls the button synaptic module;
the button synapse module simulates the biological button behavior.
Further, the food voltage control module includes: level conversion module I, level conversion module II and memristor M 4 Arithmetic unit ABM 2 Arithmetic unit ABM 3 And a resistor R7; wherein the level conversion module I comprises a PMOS tube P 5 -P 7 NMOS tube N 5 -N 7 PMOS tube P 5 And NMOS tube N 5 The common grid electrode of the PMOS tube P is connected with the food input voltage 5 And NMOS tube N 5 Is connected with the common drain electrode of the PMOS tube P 6 And NMOS tube N 6 Is connected with the common grid electrode of the PMOS tube P 6 And NMOS tube N 6 Is connected with the common drain electrode of the PMOS tube P 7 And NMOS tube N 7 Is connected with the common grid electrode of the PMOS tube P 7 And NMOS tube N 7 Is a common drain of memristor M 4 Connecting; the level conversion module II comprises: PMOS tube P 8 -P 10 NMOS tube N 8 -N 10 Memristor M 4 The output end of (a) is respectively connected with the resistor R7 and the PMOS tube P 8 And NMOS tube N 8 Is connected with the common grid electrode of the PMOS tube P 8 And NMOS tube N 8 The source of (a) is respectively connected with the mathematical operation unit ABM 2 Sum mathematical operation unit ABM 3 Is connected with the output end of the PMOS tube P 8 And NMOS tube N 8 Is connected with the common drain electrode of the PMOS tube P 9 And NMOS tube N 9 Is connected with the common grid electrode of the PMOS tube P 9 And NMOS tube N 9 Is connected with the common drain electrode of the PMOS tube P 10 And NMOS tube N 10 Is connected with common gate of (C)And (5) connecting.
Further, the food synaptic neuron module comprises: operational amplifier U 1 -U 5 Memristor M 1 -M 2 Arithmetic unit ABM 4 Resistance R 8 -R 14 And a voltage-controlled switch S 1 Resistance R 9 One end of (2) and a voltage-controlled switch S 1 3 rd pin of (d) is connected with resistor R 8 And resistance R 9 Parallel connected resistor R 10 Sum operational amplifier U 1 Is connected with the reverse input terminal of the resistor R 10 AND operation amplifier U 1 Output terminal and resistor R 11 One end of (1) is connected to a resistor R 11 Respectively with the other end of the operational amplifier U 2 Is the inverting input terminal of (1) and resistor R 12 Connected, operational amplifier U 2 Output terminal of (a) and memristor M 1 Connecting, memristor M 1 Respectively with the output end of the operational amplifier U 3 Is the inverting input terminal of (1) and resistor R 13 Connected, operational amplifier U 3 Respectively with memristor M 2 Sum mathematical operation unit ABM 4 Is connected with one input end of the memristor M 2 Respectively with resistor R 14 Sum operational amplifier U 4 Is connected with the inverting input terminal of the operational amplifier U 4 Output terminal of (a) and mathematical operation unit ABM 4 The other input end of (a) is connected with a mathematical operation unit ABM 4 Output terminal of (a) and operational amplifier U 5 Is connected with the inverting input terminal of the operational amplifier U 5 Output terminal of (d) and voltage-controlled switch S 1 Is connected to the 1 st pin.
Further, the pull rod voltage control module includes: operational amplifier U 6 -U 7 Resistance R 1 -R 5 PMOS tube P 1 -P 2 NMOS tube N 1 -N 2 PMOS tube P 1 And NMOS tube N 1 The common grid electrode of the PMOS transistor is connected with the pull rod input voltage 1 And NMOS tube N 1 Is connected with the common drain electrode of the PMOS tube P 2 And NMOS tube N 2 Is connected with the common grid electrode of the PMOS tube P 2 And NMOS tube N 2 Is connected with the common drain of the resistor R 1 Connection, resistance R 1 And resistance R 2 Respectively with resistorsR 3 Sum operational amplifier U 6 Is connected with the reverse input terminal of the resistor R 3 And the other end of the (B) and the operational amplifier U 6 Output terminal of (d) and resistor R 4 One end of (1) is connected to a resistor R 4 And the other end of (2) is connected with resistor R 5 One end of (a) and an operational amplifier U 7 Is connected with the reverse input terminal of the resistor R 5 And the other end of the (B) and the operational amplifier U 7 Is connected with the output end of the power supply.
Further, the pull rod synapse module comprises: memristor M 3 Operational amplifier U 8 -U 9 Arithmetic unit ABM 1 And resistance R 6 Operational amplifier U 8 Respectively with memristor M 3 And resistance R 6 One end of (a) is connected with the memristor M 3 The other end of (a) and a mathematical operation unit ABM 1 Is connected with one input end of the resistor R 6 And the other end of the (B) and the operational amplifier U 8 Output terminal of (a) and mathematical operation unit ABM 1 The other input end of (a) is connected with a mathematical operation unit ABM 1 Output terminal of (a) and operational amplifier U 9 Is connected to the inverting input of (a).
Further, the weak stimulation synaptic neuron module comprises: PMOS tube P 11 -P 12 NMOS tube N 11 -N 12 Memristor M 6 Operational amplifier U 10 -U 11 Resistance R 15 -R 17 PMOS tube P 11 And NMOS tube N 11 Common grid, PMOS tube P 11 And NMOS tube N 1 Is connected with the common drain electrode of the PMOS tube P 12 And NMOS tube N 12 Is connected with the common grid electrode of the PMOS tube P 12 And NMOS tube N 12 Is a common drain of memristor M 6 One end of (a) is connected with the memristor M 6 Respectively with the other end of the operational amplifier U 10 Is the inverting input terminal of (1) and resistor R 15 One end of (1) is connected to a resistor R 15 Respectively with the other end of the operational amplifier U 10 Output terminal of (d) and resistor R 16 One end of (1) is connected to a resistor R 16 Respectively with resistor R at the other end 17 And an operational amplifier U 11 Is connected with the reverse input terminal of the resistor R 17 And the other end of the (B) and the operational amplifier U 11 Is connected with the output end of the power supply.
Further, the intense stimulation of synaptic neuron modules comprises: PMOS tube P 13 -P 14 NMOS tube N 13 -N 14 Memristor M 7 Operational amplifier U 12 Operational amplifier U 13 Arithmetic unit ABM 5 Voltage control voltage source evalu 1 Resistance R 19 And resistance R 24 PMOS tube P 13 And NMOS tube N 13 Common grid, PMOS tube P 13 And NMOS tube N 13 Is connected with the common drain electrode of the PMOS tube P 14 And NMOS tube N 14 Is connected with the common grid electrode of the PMOS tube P 14 And NMOS tube N 14 Is a common drain of memristor M 7 Sum mathematical operation unit ABM 5 Is connected with one input end of the memristor M 7 Respectively with the output end of the operational amplifier U 13 Is the inverting input terminal of (1) and resistor R 24 One end of (1) is connected to a resistor R 24 Respectively with the other end of the operational amplifier U 13 Output of (a) and mathematical operation unit ABM 5 Is connected with the other input end of the mathematical operation unit ABM 5 Output terminal of (a) and operational amplifier U 12 Is connected with the inverting input terminal of the operational amplifier U 12 Is connected to the output terminal of the voltage control voltage source evalu 1 Is connected with one input end of a voltage control voltage source EVALUE 1 And a resistor R 19 And (5) connection.
Further, the button synapse neuron module comprises: operational amplifier U 14 -U 17 Memristor M 5 Arithmetic unit ABM 6 Resistance R 18 Resistance R 20 -R 23 Resistance R 18 One end of (a) is respectively connected with the resistor R 20 Sum operational amplifier U 14 Is connected with the reverse input terminal of the resistor R 20 Respectively with the other end of the operational amplifier U 14 Output terminal of (d) and resistor R 21 One end of (1) is connected to a resistor R 21 Respectively with resistor R at the other end 22 And an operational amplifier U 15 Is connected with the reverse input terminal of the resistor R 22 Respectively with the other end of the operational amplifier U 15 Output of (2), memristor M 5 Is the input of (2)Inlet end and mathematical operation unit ABM 6 Is connected with one input end of the memristor M 5 Respectively with the other end of the operational amplifier U 16 Is the inverting input terminal of (1) and resistor R 23 One end of (1) is connected to a resistor R 23 Respectively with the other end of the operational amplifier U 16 Output of (a) and mathematical operation unit ABM 6 Is connected with the other input end of the mathematical operation unit ABM 6 Output terminal of (a) and operational amplifier U 17 Is connected to the inverting input of (a).
The invention has the beneficial effects that:
1. by changing the time of the reward delay behavior, the analysis of the biological learning speed under different delay rewards is realized;
2. by changing the intensity of the stimulus, the analysis of the learning speed by the intensity of the stimulus is realized;
3. the influence of satiety on the reflection of biological operability conditions is simulated;
4. the time for rewarding delay behavior can be controlled by changing input voltage, so that the delay time is better adjusted, and a new idea is provided for the design of the neural functional circuit.
Drawings
FIG. 1 is a circuit diagram of a food training circuit of the present invention;
fig. 2 is a circuit diagram of shock training of the present invention;
FIG. 3 is a block diagram of a food voltage control module of the food training circuit;
FIG. 4 is a schematic diagram of a food synaptic neuron of the food training circuit;
FIG. 5 is a block diagram of a pull rod voltage control module of the food training circuit;
FIG. 6 is a schematic diagram of a pull rod synapse module of a food training circuit;
FIG. 7 is a block diagram of weak stimulation synaptic neurons of a shock training circuit;
FIG. 8 is a schematic diagram of a strong stimulation synaptic neuron of the shock training circuit;
FIG. 9 is a block diagram of a button synapse of a shock training circuit;
FIG. 10 is a graph showing simulation results of the food signal delay pull rod signal 0s of the food training section of the present invention;
FIG. 11 is a graph showing simulation results of the food signal delay pull rod signal 2s of the food training section of the present invention;
FIG. 12 is a graph showing simulation results of a food training portion food signal delay pull rod signal of 10.5s according to the present invention;
FIG. 13 is a graph of simulation results under weak stimulation conditions of the shock training section of the present invention;
FIG. 14 is a graph showing simulation results under strong stimulation conditions in the electric shock training section of the present invention;
fig. 15 is a graph showing the results of simulation of the strong stimulation at different times in the electric shock training section of the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings and examples, which are simplified schematic illustrations showing only the basic structure of the invention and thus showing only those constructions that are relevant to the invention.
As shown in fig. 1 and 2, a neural functional circuit that simulates operative conditioned reflex of an animal comprises: food training circuitry and shock training circuitry, wherein,
the food training circuit includes: the food voltage control module, the food synaptic neuron module, the pull rod voltage control module and the pull rod synaptic module are electrically connected in sequence,
the food voltage control module performs delay control, simulates a food reward signal to delay the time of the pull rod signal, and outputs voltage to control the food synaptic neuron module;
the food synapse neuron module simulates the influence of food on the action of the pull rod, and outputs voltage to control the pull rod synapse module;
the pull rod voltage control module outputs voltage to control the pull rod synaptic module;
the pull rod synaptic module simulates the action of a biological pull rod;
the output end of the pull rod synapse module is an output signal end I, food training is to control the time provided by food delay through the food voltage control module, the longer the time delay provided by the food delay is, the longer the training process time is, and when the food delay time is too long, food and the pull rod cannot form associative memory.
The electric shock training circuit includes: a weak stimulation synaptic neuron module, a strong stimulation synaptic neuron module and a button synaptic die electrically connected in sequence, wherein,
the weak stimulation synaptic neuron module simulates the influence of weak stimulation on the reflection of biological operability conditions and outputs voltage to control the button synaptic module;
the strong stimulation synaptic neuron module simulates the influence of strong stimulation on the biological operability condition reflex, and the output voltage controls the button synaptic module;
the button synapse module simulates the biological button behavior;
the output end of the button synapse module is an output signal end II, and the electric shock training is performed by controlling the weak stimulation synapse neuron module and the strong stimulation synapse neuron module, so that the training speed is higher as the weak stimulation times are more in the same time, and the training can be rapidly completed when the strong stimulation is generated.
The food voltage control module of fig. 3 includes: level conversion module I, level conversion module II and memristor M 4 Arithmetic unit ABM 2 Arithmetic unit ABM 3 And a resistor R7; wherein the level conversion module I comprises a PMOS tube P 5 PMOS tube P 6 PMOS tube P 7 NMOS tube N 5 NMOS tube N 6 And NMOS tube N 7 Forming a voltage comparator; food input signal V Food product The amplitude of the voltage is 0V and 2V, the voltage with the amplitude of 0V and 2V can be converted into the voltage with the amplitude of 4V and 4V through the level conversion module I, and the output of the level conversion module I is V N7 The method comprises the steps of carrying out a first treatment on the surface of the The level conversion module II comprises a PMOS tube P 8 PMOS tube P 9 PMOS tube P 10 NMOS tube N 8 NMOS tube N 9 NMOS tube N 10 Forming a voltage comparator; PMOS tube P 8 The threshold voltage of the NMOS transistor N is-3.251V 8 Is 4.02V;
ABM 2 the expression of (2) is:
V OUT1 ＝ V IN1 - 0.1*V IN2 (1)
ABM 3 the expression of (2) is:
V OUT2 ＝ V IN1 + 0.1*V IN2 (2)
ABM 2 middle V IN1 3.751V, ABM 3 Middle V IN1 is-3.52V, ABM 2 And ABM 3 Middle V IN2 Are all delay voltages V T When the delay time is 0s, ABM 2 Is 3.751V, ABM 3 The output of (2) is-3.52V, when the input of the level conversion module II is V R7 When the output voltage is more than 0.5V, the output voltage is-4V, and the input voltage of the level conversion module II R7 The output voltage is 4V when the voltage is smaller than 0.5V, and different delay time V is set T Can change the output voltage V N10 Is a pulse width of (2); r is R 7 Output V of level conversion module I is voltage dividing resistor N7 Memristor M can be changed 4 Thereby changing the output voltage V of the level conversion module I N7 Is a function of the magnitude of (a).
As shown in fig. 4, the food synaptic neuron module comprises: operational amplifier U 1 Operational amplifier U 2 Operational amplifier U 3 Operational amplifier U 4 Operational amplifier U 5 Memristor M 1 Memristor M 2 Arithmetic unit ABM 4 Resistance R 8 -R 14 And a voltage-controlled switch S 1 The method comprises the steps of carrying out a first treatment on the surface of the Resistor R 8 Resistance R 9 Resistance R 10 Sum operational amplifier U 1 Forms an adder, a resistor R 11 Resistance R 12 Sum operational amplifier U 2 Forming an inverter; when the operational amplifier U 3 The output of the output terminal of (a) is larger than that of the memristor M 2 Memristor M at positive threshold of (2) 2 The resistance of (2) decreases; mathematical operation unit ABM 4 The outputs of (2) are:
Vout ＝ -V IN2 / V IN1 ＝ M 2 /1000 (3)
operational amplifier U 5 Functioning as a comparator, when memristor M 2 When the resistance of (a) is reduced to 400 omega, ABM 4 The output voltage is less than 0.4V, and the output voltage is amplified by an operational amplifier U 5 Outputting a high level; voltage-controlled switch S 1 When the voltage difference between the 1 st pin and the 2 nd pin is larger than 0V, the 3 rd pin and the 4 th pin are connected, and the power supply V 20 Adding to memristor M through adder circuit and inverter circuit 1 The method comprises the steps of carrying out a first treatment on the surface of the Operational amplifier U 4 Resistance R 14 And memristance M 2 Forms an inverse amplifying circuit when memristor M 2 When the resistance of (a) is changed, the operational amplifier U is changed 4 Is set, the output voltage of which is set.
As shown in fig. 5, the pull rod voltage control module includes: operational amplifier U 6 Operational amplifier U 7 Resistance R 1 -R 5 PMOS tube P 1 PMOS tube P 2 NMOS tube N 1 And NMOS tube N 2 The method comprises the steps of carrying out a first treatment on the surface of the Resistor R 1 Resistance R 2 Resistance R 3 Sum operational amplifier U 6 Forms an adder, a resistor R 4 Resistance R 5 Sum operational amplifier U 7 Forms an inverter, a PMOS tube P 1 PMOS tube P 2 NMOS tube N 1 And NMOS tube N 2 Constitute voltage comparator, pull rod signal V Pull rod The magnitudes of (2) are 0V and 2V, the magnitudes are changed to-0.2V and 3V respectively by a voltage comparator, and the voltage is outputted by an adder and an inverter.
As shown in fig. 6, the pull-rod synaptic module includes a memristor M 3 Operational amplifier U 8 Operational amplifier U 9 Arithmetic unit ABM 1 And resistance R 6 The method comprises the steps of carrying out a first treatment on the surface of the Mathematical operation unit ABM 1 The outputs of (2) are:
Vout ＝ -V IN2 / V IN1 ＝ M 2 /1000 (4)
operational amplifier U 9 Functioning as a comparator, when memristor M 3 When the resistance of (a) is reduced to 700 omega, ABM 1 The output voltage is less than 0.7V, and the output voltage is amplified by an operational amplifier U 9 Outputting a high level; operational amplifier U 8 Resistance R 6 And memristance M 3 Forms an inverse amplifying circuit when memristor M 2 When the resistance of (a) is changed, the operational amplifier U is changed 4 Is set, the output voltage of which is set.
As shown in fig. 7, the weakly stimulated synaptic neuron module comprises: PMOS tube P 11 PMOS tube P 12 NMOS tube N 11 NMOS tube N 12 Memristor M 6 Operational amplifier U 10 Operational amplifier U 11 Resistance R 15 -R 17 The method comprises the steps of carrying out a first treatment on the surface of the PMOS tube P 11 PMOS tube P 12 NMOS tube N 11 NMOS tube N 12 Composition comparator V Electric shock The amplitude of the memristor M is changed into-0.2V and 2V respectively through a comparator 6 The resistance value of (2) changes when the applied voltage is larger or smaller than the threshold voltage, thereby resulting in a change in output, resistance R 16 Resistance R 17 Sum operational amplifier U 11 Form an inverter, an operational amplifier U 10 Is passed through an inverter U 11 Output, output voltage is V W 。
As shown in fig. 8, the intense stimulation synaptic neuron module comprises: PMOS tube P 13 PMOS tube P 14 NMOS tube N 13 NMOS tube N 14 Memristor M 7 Operational amplifier U 12 Operational amplifier U 13 Arithmetic unit ABM 5 Voltage control voltage source evalu 1 Resistance R 19 And resistance R 24 The method comprises the steps of carrying out a first treatment on the surface of the PMOS tube P 13 PMOS tube P 14 NMOS tube N 13 NMOS tube N 14 A comparator for judging if the intensity of the applied voltage reaches the strong stimulation standard by adjusting the PMOS tube P 13 And NMOS tube N 13 The threshold of the source voltage control comparator of (c) may be set to a minimum voltage that simulates a strong stimulus; the output of the mathematical operation unit ABM5 is:
Vout ＝ -V IN2 / V IN1 ＝ M 7 /1000 (5)
operational amplifier U 12 Functioning as a comparator, when memristor M 7 When the resistance of (a) is reduced to 700 omega, ABM 4 The output voltage is less than 0.7V, and the output voltage is amplified by an operational amplifier U 12 Outputting a high level; voltage control voltage source evalu 1 The output of (a) is 0V and 5V, when the voltage is controlled by the voltage source EVALUE 1 When the voltage difference between IN+ and IN-is greater than 10V, outputting 5V, otherwiseOutput 0V, voltage control voltage source EVALUE 1 Output V of (2) S To strongly stimulate the output of the synaptic neuron module.
As shown in fig. 9, the button synaptic neuron module comprises: operational amplifier U 14 Operational amplifier U 15 Operational amplifier U 16 Operational amplifier U 17 Memristor M 5 Arithmetic unit ABM 6 Resistance R 18 Resistance R 20 -R 23 The method comprises the steps of carrying out a first treatment on the surface of the Resistor R 18 Resistance R 20 Sum operational amplifier U 14 Forms an adder, a resistor R 21 Resistance R 22 Sum operational amplifier U 15 An inverter is formed to weakly stimulate the output V of the synaptic neuron W And output V of the strong stimulation synaptic neuron S Voltage addition, inverting the voltage through an inverter, and a mathematical operation unit ABM 6 The outputs of (2) are:
Vout ＝ -V IN2 / V IN1 ＝ M 5 /1000 (6)
operational amplifier U 17 Functioning as a comparator, when memristor M 7 When the resistance value of (a) rises to 5kΩ, ABM 6 The output voltage is greater than 5V, and the output voltage is amplified by an operational amplifier U 17 A high level is output.
FIGS. 10-12 are graphs of simulation results of the food training circuit signal delay pull rod signals 0s, 2s, and 10.5s of the present invention; wherein V is Pull rod Input voltage of pull rod voltage control module, V Food product Is the input voltage of the food voltage control module, V COM2 For the output voltage of level-shifting block II, V U3 Is memristor M 2 Input voltage of negative terminal M 2 For memristance M 2 Resistance change of V U7 For the output voltage of the pull-rod voltage control module, M 3 For memristance M 3 Resistance change of V OUT1 Is an output voltage signal of the food training circuit. As can be seen from the figure, the stage I is a learning stage, the stage II is a learning stage, and the stage III is a strengthening stage; in phase I, memristor M 3 The resistance value of the strain is continuously reduced, the organism finishes learning in the stage I, V OUT1 To a high level; II stage removal of foodSignal V Food product Memristor M 3 The resistance value of (V) is kept unchanged OUT1 Still at high level, indicating successful training; III stage of reapplying food signal V Food product Memristor M 3 The resistance value of (C) is reduced again, and the V is the V OUT1 A high level is output.
FIGS. 13-15 are diagrams showing simulation results of the shock training circuit of the present invention, V Electric shock To electric shock input signal, V M6 Is memristor M 6 Voltage applied across M 6 For memristance M 6 Resistance change of V M7 Is memristor M 7 Voltage applied across M 7 For memristance M 7 Resistance change of V M5 Is memristor M 5 Voltage applied across M 5 For memristance M 5 Resistance change of V OUT2 Is an output voltage signal of the shock training circuit. When weak stimulus is input, the strength of the weak stimulus is too small to activate the strong stimulus neuron, and the memristor M is used for stimulating the strong stimulus neuron 7 The voltage at two ends is-0.2V which is larger than the memristor M 7 Memristor M 7 The resistance value of (2) remains unchanged, memristor M 5 The resistance value of (1) slowly rises, when the memristor M 5 When the resistance value of (C) rises to 5kΩ, V OUT2 A high level is output. When strong stimulus is input, the strong stimulus neuron is activated, and the memristor M 7 The voltage across it is greater than memristor M 7 Memristor M 7 The resistance value drops, so that the memristor M 5 Voltage V at two ends M5 Less than a negative threshold voltage, memristor M 5 As the resistance value of memristor M rises 5 When the resistance value of (C) rises to 5kΩ, V OUT2 A high level is output.
With the above-described preferred embodiments according to the present invention as an illustration, the above-described descriptions can be used by persons skilled in the relevant art to make various changes and modifications without departing from the scope of the technical idea of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.
Claims (9)
1. A neural functional circuit for simulating animal operability condition reflex, which is characterized in that the animal is simulated to be rewarded and trained by using food through a food training circuit, and animal operability condition reflex is triggered; wherein,,
the food training circuit includes: the food voltage control module, the food synaptic neuron module, the pull rod voltage control module and the pull rod synaptic module are electrically connected;
the food voltage control module performs delay control, simulates a food reward signal to delay the time of the pull rod signal, and outputs voltage to control the food synaptic neuron module;
the food synapse neuron module simulates the influence of food on the action of the pull rod, and outputs voltage to control the pull rod synapse module;
the pull rod voltage control module outputs voltage to control the pull rod synaptic module;
the pull rod synapse module simulates a biological pull rod behavior.
2. The neuro-functional circuit for simulating operative conditioned reflex in an animal of claim 1, further comprising: simulating punishment training on animals by using electric shock through an electric shock training circuit, and triggering the operational conditional reflex of the animals; wherein,,
the electric shock training circuit includes: a weak stimulation synaptic neuron module, a strong stimulation synaptic neuron module and a button synaptic module electrically connected in sequence;
the weak stimulation synaptic neuron module simulates the influence of weak stimulation on the reflection of biological operability conditions and outputs voltage to control the button synaptic module;
the strong stimulation synaptic neuron module simulates the influence of strong stimulation on the biological operability condition reflex, and the output voltage controls the button synaptic module;
the button synapse module simulates the biological button behavior.
3. The neural functional circuit of claim 1, wherein the food voltage control module comprises: level conversion module I and level conversionModule II, memristor M 4 Arithmetic unit ABM 2 Arithmetic unit ABM 3 And a resistor R7; wherein the level conversion module I comprises a PMOS tube P 5 -P 7 NMOS tube N 5 -N 7 PMOS tube P 5 And NMOS tube N 5 The common grid electrode of the PMOS tube P is connected with the food input voltage 5 And NMOS tube N 5 Is connected with the common drain electrode of the PMOS tube P 6 And NMOS tube N 6 Is connected with the common grid electrode of the PMOS tube P 6 And NMOS tube N 6 Is connected with the common drain electrode of the PMOS tube P 7 And NMOS tube N 7 Is connected with the common grid electrode of the PMOS tube P 7 And NMOS tube N 7 Is a common drain of memristor M 4 Connecting; the level conversion module II comprises: PMOS tube P 8 -P 10 NMOS tube N 8 -N 10 Memristor M 4 The output end of (a) is respectively connected with the resistor R7 and the PMOS tube P 8 And NMOS tube N 8 Is connected with the common grid electrode of the PMOS tube P 8 And NMOS tube N 8 The source of (a) is respectively connected with the mathematical operation unit ABM 2 Sum mathematical operation unit ABM 3 Is connected with the output end of the PMOS tube P 8 And NMOS tube N 8 Is connected with the common drain electrode of the PMOS tube P 9 And NMOS tube N 9 Is connected with the common grid electrode of the PMOS tube P 9 And NMOS tube N 9 Is connected with the common drain electrode of the PMOS tube P 10 And NMOS tube N 10 Is connected to the common gate of (c).
4. The neural functional circuit of claim 1, wherein the food synaptic neuron module comprises: operational amplifier U 1 -U 5 Memristor M 1 -M 2 Arithmetic unit ABM 4 Resistance R 8 -R 14 And a voltage-controlled switch S 1 Resistance R 9 One end of (2) and a voltage-controlled switch S 1 3 rd pin of (d) is connected with resistor R 8 And resistance R 9 Parallel connected resistor R 10 Sum operational amplifier U 1 Is connected with the reverse input terminal of the resistor R 10 AND operation amplifier U 1 Output terminal and resistor R 11 One end of (1) is connected to a resistor R 11 Respectively with the other end of the operational amplifier U 2 Is the inverting input terminal of (1) and resistor R 12 Connected, operational amplifier U 2 Output terminal of (a) and memristor M 1 Connecting, memristor M 1 Respectively with the output end of the operational amplifier U 3 Is the inverting input terminal of (1) and resistor R 13 Connected, operational amplifier U 3 Respectively with memristor M 2 Sum mathematical operation unit ABM 4 Is connected with one input end of the memristor M 2 Respectively with resistor R 14 Sum operational amplifier U 4 Is connected with the inverting input terminal of the operational amplifier U 4 Output terminal of (a) and mathematical operation unit ABM 4 The other input end of (a) is connected with a mathematical operation unit ABM 4 Output terminal of (a) and operational amplifier U 5 Is connected with the inverting input terminal of the operational amplifier U 5 Output terminal of (d) and voltage-controlled switch S 1 Is connected to the 1 st pin.
5. The neuro-functional circuit for simulating operational conditioned reflex of an animal of claim 1, wherein the pull rod voltage control module comprises: operational amplifier U 6 -U 7 Resistance R 1 -R 5 PMOS tube P 1 -P 2 NMOS tube N 1 -N 2 PMOS tube P 1 And NMOS tube N 1 The common grid electrode of the PMOS transistor is connected with the pull rod input voltage 1 And NMOS tube N 1 Is connected with the common drain electrode of the PMOS tube P 2 And NMOS tube N 2 Is connected with the common grid electrode of the PMOS tube P 2 And NMOS tube N 2 Is connected with the common drain of the resistor R 1 Connection, resistance R 1 And resistance R 2 Respectively with resistor R 3 Sum operational amplifier U 6 Is connected with the reverse input terminal of the resistor R 3 And the other end of the (B) and the operational amplifier U 6 Output terminal of (d) and resistor R 4 One end of (1) is connected to a resistor R 4 And the other end of (2) is connected with resistor R 5 One end of (a) and an operational amplifier U 7 Is connected with the reverse input terminal of the resistor R 5 And the other end of the (B) and the operational amplifier U 7 Is connected with the output end of the power supply.
6. According to claim 1A rod synapse module comprising: memristor M 3 Operational amplifier U 8 -U 9 Arithmetic unit ABM 1 And resistance R 6 Operational amplifier U 8 Respectively with memristor M 3 And resistance R 6 One end of (a) is connected with the memristor M 3 The other end of (a) and a mathematical operation unit ABM 1 Is connected with one input end of the resistor R 6 And the other end of the (B) and the operational amplifier U 8 Output terminal of (a) and mathematical operation unit ABM 1 The other input end of (a) is connected with a mathematical operation unit ABM 1 Output terminal of (a) and operational amplifier U 9 Is connected to the inverting input of (a).
7. The neural functional circuit of claim 2, wherein the weak stimulation synaptic neuron module comprises: PMOS tube P 11 -P 12 NMOS tube N 11 -N 12 Memristor M 6 Operational amplifier U 10 -U 11 Resistance R 15 -R 17 PMOS tube P 11 And NMOS tube N 11 Common grid, PMOS tube P 11 And NMOS tube N 1 Is connected with the common drain electrode of the PMOS tube P 12 And NMOS tube N 12 Is connected with the common grid electrode of the PMOS tube P 12 And NMOS tube N 12 Is a common drain of memristor M 6 One end of (a) is connected with the memristor M 6 Respectively with the other end of the operational amplifier U 10 Is the inverting input terminal of (1) and resistor R 15 One end of (1) is connected to a resistor R 15 Respectively with the other end of the operational amplifier U 10 Output terminal of (d) and resistor R 16 One end of (1) is connected to a resistor R 16 Respectively with resistor R at the other end 17 And an operational amplifier U 11 Is connected with the reverse input terminal of the resistor R 17 And the other end of the (B) and the operational amplifier U 11 Is connected with the output end of the power supply.
8. A neuro-functional circuit for simulating operative conditioned reflex in an animal according to claim 2, whereinThus, the intense stimulation of synaptic neuron modules includes: PMOS tube P 13 -P 14 NMOS tube N 13 -N 14 Memristor M 7 Operational amplifier U 12 Operational amplifier U 13 Arithmetic unit ABM 5 Voltage control voltage source evalu 1 Resistance R 19 And resistance R 24 PMOS tube P 13 And NMOS tube N 13 Common grid, PMOS tube P 13 And NMOS tube N 13 Is connected with the common drain electrode of the PMOS tube P 14 And NMOS tube N 14 Is connected with the common grid electrode of the PMOS tube P 14 And NMOS tube N 14 Is a common drain of memristor M 7 Sum mathematical operation unit ABM 5 Is connected with one input end of the memristor M 7 Respectively with the output end of the operational amplifier U 13 Is the inverting input terminal of (1) and resistor R 24 One end of (1) is connected to a resistor R 24 Respectively with the other end of the operational amplifier U 13 Output of (a) and mathematical operation unit ABM 5 Is connected with the other input end of the mathematical operation unit ABM 5 Output terminal of (a) and operational amplifier U 12 Is connected with the inverting input terminal of the operational amplifier U 12 Is connected to the output terminal of the voltage control voltage source evalu 1 Is connected with one input end of a voltage control voltage source EVALUE 1 And a resistor R 19 And (5) connection.
9. The neural functional circuit of claim 2, wherein the button synaptic neuron module comprises: operational amplifier U 14 -U 17 Memristor M 5 Arithmetic unit ABM 6 Resistance R 18 Resistance R 20 -R 23 Resistance R 18 One end of (a) is respectively connected with the resistor R 20 Sum operational amplifier U 14 Is connected with the reverse input terminal of the resistor R 20 Respectively with the other end of the operational amplifier U 14 Output terminal of (d) and resistor R 21 One end of (1) is connected to a resistor R 21 Respectively with resistor R at the other end 22 And an operational amplifier U 15 Is connected with the reverse input terminal of the resistor R 22 The other end of (a) is respectively connected with the transportCalculation amplifier U 15 Output of (2), memristor M 5 Input terminal of (a) and mathematical operation unit ABM 6 Is connected with one input end of the memristor M 5 Respectively with the other end of the operational amplifier U 16 Is the inverting input terminal of (1) and resistor R 23 One end of (1) is connected to a resistor R 23 Respectively with the other end of the operational amplifier U 16 Output of (a) and mathematical operation unit ABM 6 Is connected with the other input end of the mathematical operation unit ABM 6 Output terminal of (a) and operational amplifier U 17 Is connected to the inverting input of (a).
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