CN210488595U

CN210488595U - Synapse bionic circuit for realizing diversified STDP learning rule based on memristor

Info

Publication number: CN210488595U
Application number: CN201921384401.6U
Authority: CN
Inventors: 叶葱; 张鑫; 夏天; 刘昕怡; 刘炎欣
Original assignee: Hubei University
Current assignee: Hubei University
Priority date: 2019-08-25
Filing date: 2019-08-25
Publication date: 2020-05-08
Anticipated expiration: 2029-08-25

Abstract

The utility model relates to a synapse bionic circuit based on memristor realization diversified STDP learning rule, which comprises an enhancing module, an inhibiting module and a memristive synapse module, wherein the enhancing module and the inhibiting module respectively comprise two input ends and an output end, the two input ends receive a front neuron signal pre and a rear neuron signal post, and the output ends are connected with the memristive synapse module; when the current neuron signal pre arrives before the post neuron signal post, the enhancement module works, the inhibition module stops running, and the enhancement module outputs direct current levels with different widths according to the input time difference of the two signals; when the post neuron signal post arrives before the pre neuron signal, the inhibition module works, the enhancement module stops running, and the inhibition module outputs direct current levels with different widths according to the input time difference of the two signals; the memristor synapse module correspondingly inhibits memristor conductance weights according to direct-current levels with different widths, so that corresponding parameters for simulating and realizing the STDP learning function are changed, and the application range is wide.

Description

Synapse bionic circuit for realizing diversified STDP learning rule based on memristor

Technical Field

The utility model relates to a neural network integrated circuit field, concretely relates to synapse bionic circuit based on recall and hinder ware and realize diversified STDP learning rule.

Background

With the advent of the artificial intelligence era, the data information processing amount and the calculation complexity are increased sharply, the framework system of the traditional computer is suffering from severe challenges, and a novel calculation mechanism for realizing the integration of calculation and storage is at the forefront. The human brain has an interactively connected complex neural network, and the highly developed parallel computing capability and learning and memory functions of the human brain bring inspiration for the development of people on brain-like chips. In the brain, neurons are the basic building blocks of neural networks, and neurosynaptic is the basis for connections between neurons. The change of the shape, function and working efficiency of the synapse, namely synapse plasticity plays an important role in information transmission, processing and storage among neurons in a neural network, and is also an important basis of the learning ability of the human brain. Therefore, in order to realize a bionic chip which is similar to the brain and uses a neural network for information transmission and storage, it is the first task to construct an artificial synapse circuit.

In 2008, a hewlett packard laboratory developed a first titanium oxide-based thin film memristor physical model, and confirmed the inference about the existence of a fourth basic circuit element, namely a memristor, except for a resistor, a capacitor and an inductor, which was proposed by professor zelndica's begonia in 1971. The memristor has unique performances of nonlinearity, passivity, power-off non-volatility and the like. When both ends of the memristor are stimulated by the same pulse as the nerve synapse, the conductance change of the memristor is similar to the change situation of the synapse weight, so that the memristor is considered to be an ideal device for developing and simulating the artificial nerve synapse. In recent years, in order to better explain the learning and memory functions of biological brain, a pulse time dependent plasticity (STDP) learning rule is proposed, which is a mechanism for regulating synaptic strength in brain through the relative time of presynaptic and postsynaptic pulses, and is a theoretical basis for learning and self-adapting external interference of biological neural network. Therefore, one typically builds artificial synapse circuits with memristors and implements the STDP learning rules. In order to explore the research of brain-like bionic chips, predecessors simulated synapses by building COMS integrated circuits to realize STDP learning rules, but most synapse circuits have the problems of overlarge power consumption and harsh input signal waveforms and are difficult to regulate. To solve these problems, researchers have begun to build synaptic circuits built based on memristors and implement STDP learning functions. However, when the time difference between the pre-neuron signal and the post-neuron signal is taken as the abscissa and the conductance weight of the synaptic module is taken as the ordinate, different biological neurons may work in different quadrants, for example, a biological visual nerve works in

quadrants

1 and 3, and a muscle nerve works in

quadrants

1 and 2, and an artificial synaptic circuit built based on a memristor is the same as a traditional cmos synaptic circuit, and has the problems of single analog type and unsatisfactory fitting effect.

SUMMERY OF THE UTILITY MODEL

The utility model discloses to the technical problem who exists among the prior art, provide and realize diversified STDP study rule's synapse bionic circuit based on recalling the resistance ware. The utility model discloses a synapse circuit compares in the president can only simulate the synapse bionic circuit of an STDP study rule, can simulate the diversified STDP study function of different positions synapses such as organism visual nerve, muscle nerve. Meanwhile, the input signal of the circuit abandons the traditional complex and difficult-to-adjust double-spike pulse waveform and adopts a simple and easy-to-adjust direct current pulse waveform, so that the input condition is not harsh any more. The circuit also has the capability of adjusting the STDP learning rule, changes the variation of the synaptic weight under the same excitation by changing the set regulation voltage, further changes the corresponding parameters for simulating and realizing the STDP learning function, can be used for simulating the synaptic STDP learning rule under different environments, has wider application range, and has greater development potential in the aspect of artificial intelligence bionics.

The utility model provides an above-mentioned technical problem's technical scheme as follows:

a synapse bionic circuit for realizing diversified STDP learning rules based on a memristor comprises an enhancing module, an inhibiting module and a memristor synapse module,

the enhancing module comprises two input ends and an output end, the two input ends of the enhancing module are respectively used for receiving a pre neuron signal pre and a post neuron signal post, and the output end of the enhancing module is connected with the memristive synapse module;

the inhibition module comprises two input ends and an output end, the two input ends of the inhibition module are respectively used for receiving a pre neuron signal pre and a post neuron signal post, and the output end of the inhibition module is connected with the memristive synapse module;

when the pre-neuron signal pre reaches the synaptic bionic circuit before the post-neuron signal post, the enhancing module works, the inhibiting module stops running, and the enhancing module outputs direct current levels with different widths to the memristive synaptic module according to the input time difference between the pre-neuron signal pre and the post-neuron signal post;

when the post-neuron signal post reaches the synaptic bionic circuit before the pre-neuron signal pre, the inhibition module works, the enhancement module stops running, and the inhibition module outputs direct current levels with different widths to the memristive synaptic module according to the input time difference between the post-neuron signal post and the pre-neuron signal pre;

the memristive synapse module correspondingly suppresses memristor Rm conductance weights according to the direct current levels of different widths.

On the basis of the technical scheme, the utility model discloses can also do following improvement.

Preferably, the enhancement module includes an inverter U1, a nand gate U2, an electronic switch P1, a resistor R1, a capacitor C1, a first analog switch, a resistor R2, a capacitor C2, a voltage comparator U5, and a resistor R3, an output of the inverter U1 is connected to one input of the nand gate U2, another input of the nand gate U2 receives the pre-neuron signal pre, and an output of the nand gate U2The control electrode of the electronic switch tube P1 is connected, the input end of the electronic switch tube P1 is connected with a power supply voltage, the output end of the electronic switch tube P1 is connected with one end of the first analog switch, the control end of the first analog switch receives the post neuron signal post, the other end of the first analog switch is connected with the equidirectional input end of the voltage comparator U5, and the reverse input end of the voltage comparator U5 is connected with a regulation voltage V_thThe output end of the voltage comparator U5 is connected with the memristive synapse module, one end of the resistor R3 is connected with a power supply input end of the voltage comparator U5 in parallel to be connected with a power supply, and the other end of the resistor R3 is connected with the output end of the voltage comparator U5; the resistor R1 and the capacitor C1 are connected between the output end of the electronic switch tube P1 and the ground in parallel, and the resistor R2 and the capacitor C2 are connected between the equidirectional input end of the voltage comparator U5 and the ground in parallel.

Preferably, the suppression module includes an inverter U3, a nand gate U4, an electronic switch tube P2, a resistor R4, a capacitor C3, a second analog switch, a resistor R5, a capacitor C4, a voltage comparator U6, and a resistor R6, an input terminal of the inverter U3 is connected to an output terminal of the electronic switch tube P1, an output terminal of the inverter U3 is connected to one input terminal of the nand gate U4, another input terminal of the nand gate U4 receives the post neuron signal post, an output terminal of the nand gate U4 is connected to a control terminal of the electronic switch tube P2, an input terminal of the electronic switch tube P2 is connected to a supply voltage, output terminals of the electronic switch tube P2 are respectively connected to an input terminal of the inverter U1 and one terminal of the second analog switch, a control terminal of the second analog switch receives the pre neuron signal, and another terminal of the second analog switch is connected to a non-inverting input terminal of the voltage comparator U6, the reverse input end of the voltage comparator U6 is connected with a regulation voltage V_thThe output end of the voltage comparator U6 is connected with the memristive synapse module, one end of the resistor R6 is connected with a power supply input end of the voltage comparator U6 in parallel to be connected with a power supply, and the other end of the resistor R6 is connected with the output end of the voltage comparator U6; the resistor R4 and the capacitor C3 are connected in parallel at the input of the electronic switch tube P2The resistor R5 and the capacitor C4 are connected between the output end and the ground in parallel between the same-direction input end of the voltage comparator U6 and the ground.

Preferably, the memristive synapse module comprises a first memristive synapse submodule, a second memristive synapse submodule, a third memristive synapse submodule, and a fourth memristive synapse submodule; when the time difference delta T between the input of the pre neuron signal pre and the input of the post neuron signal post into the memristive synapse module is used as an abscissa and the conductance weight of the memristor Rm is used as an ordinate,

the first memristive synapse submodule works in

quadrants

1 and 3 and is used for simulating the neural activity working in

quadrants

1 and 3;

the second memristive synapse submodule works in

quadrants

2 and 4 and is used for simulating the neural activity working in

quadrants

2 and 4;

the third memristive synapse submodule works in

quadrants

1 and 2 and is used for simulating the neural activity working in

quadrants

1 and 2;

the fourth memristive synapse submodule operates in

quadrants

3 and 4 and is used for simulating neural activity operating in

quadrants

3 and 4.

Preferably, the first memristive synapse module comprises a memristor Rm and a third analog switch, the third analog switch comprises at least four channels, the output end of the boost module is connected with the control end of a first channel of the third analog switch and the control end of a fourth channel of the third analog switch, one end of the first channel of the third analog switch is connected with an external power supply, the other end of the first channel of the third analog switch is connected with the positive electrode of the memristor Rm, the negative electrode of the memristor Rm is connected with one end of the fourth channel of the third analog switch, and the other end of the fourth channel of the third analog switch is grounded; the output end of the suppression module is connected with the control end of the second channel of the third analog switch and the control end of the third channel of the third analog switch, one end of the second channel of the third analog switch is connected with an external power supply, the other end of the second channel of the third analog switch is connected with the negative electrode of the memristor Rm, the positive electrode of the memristor Rm is connected with one end of the third channel of the third analog switch, and the other end of the third channel of the third analog switch is grounded.

Preferably, the second memristive synapse module comprises a memristor Rm and a fourth analog switch, the fourth analog switch comprises at least four channels, the output end of the boost module is connected with the control end of a first channel of the fourth analog switch and the control end of a fourth channel of the fourth analog switch, one end of the first channel of the fourth analog switch is connected with an external power supply, the other end of the first channel of the fourth analog switch is connected with the negative electrode of the memristor Rm, the positive electrode of the memristor Rm is connected with one end of the fourth channel of the fourth analog switch, and the other end of the fourth channel of the fourth analog switch is grounded; the output end of the suppression module is connected with the control end of the second channel of the fourth analog switch and the control end of the third channel of the fourth analog switch, one end of the second channel of the fourth analog switch is connected with an external power supply, the other end of the second channel of the fourth analog switch is connected with the anode of the memristor Rm, the cathode of the memristor Rm is connected with one end of the third channel of the fourth analog switch, and the other end of the third channel of the fourth analog switch is grounded.

Preferably, the third memristive synapse sub-module comprises a memristor Rm and a fifth analog switch, the fifth analog switch comprises at least two channels, the output end of the boost module is connected with the control end of a first channel of the fifth analog switch, one end of the first channel of the fifth analog switch is connected with an external power supply, the other end of the first channel of the fifth analog switch is connected with the anode of the memristor Rm, and the cathode of the memristor Rm is grounded; the output end of the suppression module is connected with the control end of a second channel of the fifth analog switch, one end of the second channel of the fifth analog switch is connected with an external power supply, and the other end of the second channel of the fifth analog switch is connected with the anode of the memristor Rm.

Preferably, the fourth memristive synapse sub-module comprises a memristor Rm and a sixth analog switch, the sixth analog switch comprises at least two channels, the output end of the boost module is connected with the control end of a first channel of the sixth analog switch, one end of the first channel of the sixth analog switch is connected with an external power supply, the other end of the first channel of the sixth analog switch is connected with the negative electrode of the memristor Rm, and the positive electrode of the memristor Rm is grounded; the output end of the suppression module is connected with the control end of the second channel of the sixth analog switch, one end of the second channel of the sixth analog switch is connected with an external power supply, and the other end of the second channel of the sixth analog switch is connected with the negative electrode of the memristor Rm.

The utility model has the advantages that: the utility model discloses a synapse circuit compares in the president can only simulate the synapse bionic circuit of an STDP study rule, can simulate the diversified STDP study function of different positions synapses such as organism visual nerve, muscle nerve. Meanwhile, the input signal of the circuit abandons the traditional complex and difficult-to-adjust double-spike pulse waveform and adopts a simple and easy-to-adjust direct current pulse waveform, so that the input condition is not harsh any more. The circuit also has the capability of adjusting the STDP learning rule, changes the variation of the synaptic weight under the same excitation by changing the set regulation voltage, further changes the corresponding parameters for simulating and realizing the STDP learning function, can be used for simulating the synaptic STDP learning rule under different environments, has wider application range, and has greater development potential in the aspect of artificial intelligence bionics.

Drawings

FIG. 1 is a schematic view of the overall structure of the present invention;

FIG. 2a is a diagram of a memristive synapse module according to a first embodiment of the present disclosure;

FIG. 2b is a block diagram of a memristive synapse module in accordance with a third embodiment of the present disclosure;

FIG. 2c is a block diagram of a memristive synapse module in accordance with a second embodiment of the present invention;

FIG. 2d is a block diagram of a memristive synapse module in accordance with a fourth embodiment of the present disclosure;

fig. 3 is a simulated time domain waveform diagram when four input signals of different conditions are respectively input in the first embodiment of the present invention;

fig. 4 is a line graph of the percentage of change in conductance of the memristor when the input pulse time difference Δ T is changed in steps of 1 millisecond according to the first embodiment of the present invention;

fig. 5 is a line graph of the percentage of change in conductance of the memristor when the input pulse time difference Δ T is changed in steps of 1 millisecond in the third embodiment of the present invention;

fig. 6 is a line graph of the percentage of change in conductance of the memristor when the input pulse time difference Δ T is changed in steps of 1 millisecond in the second embodiment of the present invention;

fig. 7 is a line graph of the percentage of change in conductance of the memristor when the input pulse time difference Δ T is changed in steps of 1 millisecond in the fourth embodiment of the present invention;

FIG. 8 shows an embodiment of the present invention in which the input pulse time difference Δ T is changed in1 ms by steps, and the memristor is controlled by different control voltages V_thPercentage change in conductance plot below.

Detailed Description

The principles and features of the present invention are described below in conjunction with the following drawings, the examples given are only intended to illustrate the present invention and are not intended to limit the scope of the present invention.

A synaptic biomimetic circuit for implementing diversified STDP learning rules based on memristors as shown in FIG. 1 comprises an enhancing module, an inhibiting module and a memristive synapse module,

As shown in fig. 1, the enhancing module and the inhibiting module are independent from each other and operate alternately, the enhancing module and the inhibiting module both have two input ends and one output end, and the output ends of the enhancing module and the inhibiting module are connected with the two input ends of the memristive synapse module, so that a complete memristive synapse bionic circuit is formed.

In this embodiment, the enhancement module includes an inverter U1, a nand gate U2, an electronic switch P1, a resistor R1, a capacitor C1, a first analog switch, a resistor R2, a capacitor C2, a voltage comparator U5, a resistor R3, the input end of the inverter U1 is marked as a point b, the output end of the inverter U1 is connected with one input end of the NAND gate U2, the other input end of the NAND gate U2 receives the pre neuron signal pre, the output end of the NAND gate U2 is connected with the control electrode of the electronic switch tube P1, the input end of the electronic switch tube P1 is connected with a supply voltage, the output end of the electronic switch tube P1 is connected with one end of the first analog switch, the control end of the first analog switch receives the post neuron signal post, the other end of the first analog switch is connected with the equidirectional input end of the voltage comparator U5, and the reverse input end of the voltage comparator U5 is connected with a regulation voltage V._thThe output end of the voltage comparator U5 is connected with the memristive synapse module, one end of the resistor R3 is connected with a power supply input end of the voltage comparator U5 in parallel to be connected with a power supply, and the other end of the resistor R3 is connected with the output end of the voltage comparator U5; the resistor R1 and the capacitor C1 are connected in parallel between the output end of the electronic switch tube P1 and the ground, and the node where the output ends of the resistor R1, the capacitor C1 and the electronic switch tube P1 are connected is marked as a point aThe resistor R2 and the capacitor C2 are connected in parallel between the equidirectional input end of the voltage comparator U5 and the ground, and are used for receiving charges transmitted from the capacitor C1, wherein the capacitance value of C2 should be much smaller than that of C1, the capacitance value of C2 is 1uF, the resistance value of R2 is 15k, the resistance value of R1 is 1k, and the capacitance value of C1 is 10 uF.

The first analog switch is realized by an analog switch chip ADG442, and comprises four-channel single-pole single-throw switches, and the on-off of each single-pole single-throw switch is controlled by a control end. The electronic switch tube P1 adopts a PMOS tube, the grid of the electronic switch tube P1 is connected with the output end of the NAND gate U2, the source of the electronic switch tube P1 is connected with a +5V power supply, and the drain of the electronic switch tube P1 is connected with the S1 pin of the analog switch chip ADG442, a resistor R1 and a capacitor C1; the pin D1 of the ADG442 is connected with the positive input end of the voltage comparator U5, the pin IN1 of the ADG442 is connected with the post neuron signal post, the pin VSS-15V, VDD of the ADG442 is connected with +15V, and the pins GND, S4, D4 and IN4 are all grounded. Voltage comparator U5 is implemented with LM 393. The power supply input end of LM393 terminates +5V power supply, and its GND pin is ground.

In this embodiment, the suppressing module includes an inverter U3, a nand gate U4, an electronic switch tube P2, a resistor R4, a capacitor C3, a second analog switch, a resistor R5, a capacitor C4, a voltage comparator U6, and a resistor R6, an input end of the inverter U3 is denoted as a point a, an input end of the inverter U3 is connected to a point a in the boosting module, an output end of the inverter U3 is connected to one input end of the nand gate U4, the other input end of the nand gate U4 receives the post neuron signal post, an output end of the nand gate U4 is connected to a control electrode of the electronic switch tube P2, an input end of the electronic switch tube P2 is connected to a supply voltage, an output end of the electronic switch tube P2 is connected to one end of the second analog switch, a control end of the second analog switch receives the pre neuron signal, and the other end of the second analog switch is connected to a unidirectional input end of the voltage comparator U6, the reverse input end of the voltage comparator U6 is connected with a regulation voltage V_thThe output end of the voltage comparator U6 is connected with the memristive synapse module, one end of the resistor R6 is connected with a power supply in parallel with the power supply input end of the voltage comparator U6, and the other end of the resistor R6 is connected with a power supplyOne end of the voltage comparator U6 is connected with the output end of the voltage comparator U6; the resistor R4 and the capacitor C3 are connected in parallel between the output end of the electronic switch tube P2 and the ground, the connection node of the resistor R4, the capacitor C3 and the output end of the electronic switch tube P2 is marked as a point b, and the point b of the suppression module is connected with the point b of the boost module, namely the point b of the suppression module is connected with the input end of the inverter U1. The resistor R5 and the capacitor C4 are connected in parallel between the equidirectional input end of the voltage comparator U6 and the ground and are used for receiving charges transmitted from the capacitor C3, wherein the capacitance value of C4 is far smaller than that of C3, the capacitance value of C4 is 1uF, the resistance value of R5 is 15k, the resistance value of R4 is 1k, and the capacitance value of C3 is 10 uF.

The second analog switch is realized by multiplexing an analog switch chip ADG442 used by the first analog switch, and comprises four-channel single-pole single-throw switches, and the on-off of each single-pole single-throw switch is controlled by a control end. The first analog switch uses the first channel (S1, D1) and the fourth channel (S4, D4) of the ADG442 chip, the second analog switch uses the third channel (S3, D3) and the second channel (S2, D2) of the ADG442 chip, the pin IN3 controls the on-off of the third channel (S3, D3), and the pin IN2 controls the on-off of the second channel (S2, D2).

The electronic switch tube P2 adopts a PMOS tube, the grid of the electronic switch tube P2 is connected with the output end of the NAND gate U4, the source of the electronic switch tube P2 is connected with a +5V power supply, and the drain of the electronic switch tube P2 is connected with a D3 pin of an analog switch chip ADG442, a resistor R4 and a capacitor C3; the pin S3 of the ADG442 is connected to the positive input terminal of the voltage comparator U6, the pin IN3 of the ADG442 is connected to the pre-neuron signal pre, the pin VSS of the ADG442 is connected to-15V, VDD and +15V, and the pins GND, S2, D2 and IN2 are all grounded. Voltage comparator U6 is implemented with LM 393. The power supply input end of LM393 is connected with the +5V power supply, the GND pin of the LM393 is grounded, and the resistor R6 is connected between Vcc and the output end of the voltage comparator U6.

When the current neuron signal pre reaches the synapse bionic circuit of the embodiment before the post neuron signal post, the enhancing module outputs pulse levels with different widths at the output end of the enhancing module according to the time difference of the input pre neuron signal pre before the post neuron signal post, and the larger the time difference is, the larger the pulse width isThe wider. When the current neuron signal pre reaches the synapse bionic circuit before the post neuron signal post, the pre neuron signal pre is at a high level, the post neuron signal post is at a low level, the NAND gate U4 in the inhibition module is locked by the low level of the post neuron signal post, the NAND gate U4 outputs a high level, and at the moment, the gate-source voltage U2 of the PMOS tube P2_GSGreater than the turn-on voltage U_GS(th)When the PMOS transistor P2 enters the cut-off region, the +5V power supply cannot charge the C3, and the b point in the suppression module is kept at a low potential, so that the suppression module does not operate. When the current neuron signal pre reaches the input high level, the point b in the enhancement module outputs the high level through the inverter U1, the two input ends of the NAND gate U2 are both high level, and the output end of the NAND gate U2 outputs the low level. Gate source voltage U of PMOS pipe P1_GSLess than the turn-on voltage U_GS(th)The PMOS tube P1 is conducted, the +5V direct-current power supply charges the capacitor C1, the conduction duration of the PMOS tube P1 is the pulse width of the neuron signal pre before the input signal, when the current neuron signal pre is ended and returns to the low level, the capacitor C1 ends charging, and then the capacitor C1 starts discharging through the resistor R1. When the post neuron signal post arrives, the 1 pin IN1 of the ADG422 goes high, the single-pole single-throw analog switch (pin S1 and pin D1) between the 2 and 3 pins is turned on, the capacitor C1 with a large capacitance value starts to charge the capacitor C2 with a small capacitance value, and since the capacitance value of the capacitor C2 is far smaller than that of the capacitor C1, the capacitor C2 charges the charge before the post neuron signal post returns to low potential and the first analog switch is turned off. And the maximum voltage charged by the capacitor C2 is the same as the voltage of the capacitor C1 at the time of turning on the first analog switch, and since the capacitor C1 is continuously discharged before, the voltage of the capacitor C1 is continuously decreased, so that the earlier the time when the post neuron signal post arrives, that is, the smaller the time difference between the pre neuron signal and the post neuron signal post, the larger the maximum voltage charged by the capacitor C2 is. After the post neuron signal post returns to the low level, the capacitor C2 starts to discharge through the resistor R2, and since the resistance value of the resistor R2 and the capacitance value of the capacitor C2 are fixed, the discharge time of the capacitor C2 is proportional to the maximum voltage value reached by charging the capacitor C2. The resistor R2 and the capacitor C2 are connected in parallel to the same-direction input end and the reverse-direction input end of the voltage comparator U5Is connected to a regulated voltage V_thWhen the capacitor C2 is full of charge, the output end of the voltage comparator U5 outputs high level, and when the voltage of the capacitor C2 is discharged to V_thWhen the voltage is lower, the voltage comparator U5 outputs low level; the smaller the time difference between the input signal front neuron signal pre and the input signal back neuron signal post is, the higher the initial discharge voltage of the capacitor C2 is, and the wider the output direct-current level width of the output end of the voltage comparator U5 is; or by changing the regulating voltage V_thThe comparison threshold of the voltage comparator U5 is adjusted, so that the output level width is changed, and V is obtained under the condition that the time difference between two input signals is not changed_thThe smaller the dc pulse width output by the voltage comparator U5. A resistor R3 is connected between Vcc of the voltage comparator U5 and the output terminal, and serves as a pull-up resistor to enable the voltage comparator U5 (i.e., LM393) to operate normally.

The circuit structure and the working principle of the inhibition module are basically the same as those of the enhancement module, the current neuron signal pre reaches the synapse bionic circuit after the post neuron signal post, the inhibition module outputs pulse levels with different widths at the output end according to the time difference of the input post neuron signal post before the pre neuron signal, and the pulse width is wider when the time difference is larger. When the post neuron signal post reaches the synaptic bionic circuit before the pre neuron signal pre, the post neuron signal post is at a high level, the pre neuron signal pre is at a low level, the low level of the pre neuron signal pre locks the NAND gate U2 in the enhancement module, the NAND gate U2 outputs a high level, and at the moment, the U of the PMOS tube P1 is at a high level_GSGreater than U_GS(th)When the PMOS transistor P1 enters the cut-off region, the +5V power supply cannot charge the capacitor C1, and the point a of the enhancement module remains at a low voltage. When the post neuron signal post reaches a high level, the point a in the enhancement module is connected with the input end of the inverter U3, a high level is output through the inverter U3, the two input ends of the NAND gate U4 are both high levels, and the NAND gate U4 outputs a low level. Gate source voltage U of PMOS pipe P2_GSLess than the turn-on voltage U_GS(th)The PMOS tube P2 is conducted, the capacitor C3 is charged by the +5V direct-current power supply, the conduction duration of the PMOS tube P2 is the pulse width of the input signal post-neuron signal post, and when the post-neuron signal post signal is ended and returns to the low level, the capacitor C3 is endedAfter which the capacitor C3 begins to discharge through resistor R4. Until the pre-neuron signal pre arrives, the 9 pin (i.e., the IN3 pin) of the ADG422 goes high, the single-pole single-throw analog switch between the 10 and 11 pins (i.e., the D3 pin and the S3 pin) is turned on, the capacitor C3 with a larger capacitance value starts to charge the capacitor C4 with a smaller capacitance value, and since the capacitance value of the capacitor C4 is much smaller than that of the capacitor C3, the capacitor C3 charges the charge before the pre-neuron signal pre returns to a low level and the second analog switch (i.e., the D3 pin and the S3 pin) is turned off. And the maximum voltage charged by the capacitor C4 is the same as the voltage of the capacitor C3 at the turn-on time of the second analog switch, and since the capacitor C3 is continuously discharged before, the voltage of the capacitor C3 is continuously decreased, so the earlier the time when the front neuron signal pre arrives, that is, the smaller the time difference between the rear neuron signal post and the front neuron signal pre is, the larger the maximum voltage charged by the capacitor C4 is. After the pre-neuron signal pre returns to the low level, the capacitor C4 starts to discharge through the resistor R5, and since the resistance of the resistor R5 and the capacitance of the capacitor C4 are fixed, the discharge time of the capacitor C4 is proportional to the maximum voltage value reached by charging the capacitor C4. The resistor R5 and the capacitor C4 are connected in parallel to the equidirectional input end of the voltage comparator U6(LM393), and the reverse input end is connected to the regulated voltage V_thWhen the capacitor C4 is full of charge, the output end of the voltage comparator U6 outputs high level, and when the voltage of the capacitor C4 discharges to the regulation voltage V_thIn the following, the voltage comparator U6 outputs a low level, and the smaller the time difference between the neuron signal post after the input signal and the neuron signal pre before, the higher the initial discharge voltage of the capacitor C4, and the wider the output dc level width of the output terminal of the voltage comparator U6; or by changing the regulating voltage V_thThe comparison threshold of the voltage comparator U6 is adjusted, so that the output level width is changed, and the voltage V is regulated and controlled under the condition that the time difference between two input signals is not changed_thThe smaller the dc pulse width output by the voltage comparator U6. A resistor R6 is connected between Vcc of the voltage comparator U6 and the two terminals of the output terminal, and serves as a pull-up resistor to enable the voltage comparator U6(LM393) to work normally.

In this embodiment, the memristive synapse module comprises a first memristive synapse submodule, a second memristive synapse submodule, a third memristive synapse submodule, and a fourth memristive synapse submodule; when the time difference delta T between the input of the pre neuron signal pre and the input of the post neuron signal post into the memristive synapse module is used as an abscissa and the conductance weight of the memristor Rm is used as an ordinate,

the first memristive synapse submodule works in

quadrants

1 and 3 and is used for simulating the neural activity working in

quadrants

1 and 3, such as simulating the activity of the visual nerve of a living body;

the second memristive synapse submodule works in

quadrants

2 and 4 and is used for simulating the neural activity working in

quadrants

2 and 4;

the third memristive synapse submodule operates in

quadrants

1 and 2 and is used for simulating neural activity operating in

quadrants

1 and 2, such as simulating the activity of muscle nerves of an organism;

the fourth memristive synapse submodule operates in

quadrants

3 and 4 and is used for simulating neural activity operating in

quadrants

3 and 4.

The memristive synapse module is connected with the enhancing module and the inhibiting module through a selection switch and is used for controlling the first memristive synapse submodule, the second memristive synapse submodule, the third memristive synapse submodule and the fourth memristive synapse submodule to be connected respectively.

The first embodiment is as follows:

the embodiment uses a selection switch to switch on the connection between the boosting module, the suppressing module and the first memristive synapse submodule on the basis of the main scheme. When the time difference Δ T between the pre neuron signal pre and the post neuron signal post is taken as an abscissa and the conductance weight of the memristor Rm is taken as an ordinate, the first memristor synapse submodule circuit of the embodiment is used for realizing the STDP learning rule that the learning function is located in the 1, 3 quadrants.

In this embodiment, the first memristive synapse module includes a memristor Rm and a third analog switch, the third analog switch includes at least four channels, an output end of the boost module is connected to a control end of a first channel of the third analog switch and a control end of a fourth channel of the third analog switch, one end of the first channel of the third analog switch is connected to a power supply, the other end of the first channel of the third analog switch is connected to an anode of the memristor Rm, a cathode of the memristor Rm is connected to one end of the fourth channel of the third analog switch, and the other end of the fourth channel of the third analog switch is grounded; the output end of the suppression module is connected with the control end of the second channel of the third analog switch and the control end of the third channel of the third analog switch, one end of the second channel of the third analog switch is connected with a power supply, the other end of the second channel of the third analog switch is connected with the negative electrode of the memristor Rm, the positive electrode of the memristor Rm is connected with one end of the third channel of the third analog switch, and the other end of the third channel of the third analog switch is grounded.

Specifically, as shown in fig. 2a, the third analog switch is implemented by using an analog switch chip ADG442, which includes four controllable single-pole single-throw switch channels. The GND pin of ADG442 is grounded, VSS is connected to-15V, and VDD is connected to + 15V. IN the first memristive synapse submodule, an output end of a voltage comparator U5 of an enhancement module is respectively connected with an IN1 pin and an IN4 pin of an ADG442, and is used for controlling a single-pole single-throw switch composed of a D1 pin and an S1 pin and a single-pole single-throw switch composed of a D4 pin and an S4 pin, a D1 pin of the ADG442 is connected with an external power supply, and the external power supply adopts +2V voltage for the consideration and the biological STDP learning function to be closer; the S1 pin of the ADG442 is connected with the anode of the memristor Rm; the pin S4 is grounded, and the pin D4 is connected with the negative electrode of the memristor Rm. IN the first memristive synapse submodule, the output end of a voltage comparator U6 of an inhibition module is respectively connected with an IN2 pin and an IN3 pin of an ADG442, and is used for controlling a single-pole single-throw switch composed of a D2 pin and an S2 pin and a single-pole single-throw switch composed of a D3 pin and an S3 pin, the D2 pin is connected with an external power supply, and the external power supply adopts +2V voltage for being closer to an STDP learning function of a living being considered; the pin S2 is connected with the negative electrode of the memristor Rm; the pin S3 is grounded, and the pin D3 is connected with the anode of the memristor Rm.

When the time difference Δ T between the pre neuron signal pre and the post neuron signal post is taken as an abscissa and the conductance weight of the memristor Rm is taken as an ordinate, the first memristive synapse submodule circuit of the embodiment is used for realizing the STDP learning rule that the learning function is located in the 1, 3 quadrants, the current neuron signal pre reaches the input end of the synapse bionic circuit before the post neuron signal post, and the enhancing module outputs the direct current levels with different widths to the memristive synapse module according to the time difference Δ T between the arrival of the two neuron signals. When the memristive synapse module circuit of the embodiment is adopted, a direct-current level transmitted from the boost module is input to pins 1 and 8 (namely pins IN1 and IN 4) of an ADG442 of the memristive synapse module, a single-pole single-throw analog switch (composed of a pin D1 and a pin S1) of the first channel and a single-pole single-throw analog switch (composed of a pin D4 and a pin S4) of the fourth channel are turned on, and since the suppression module stops working, pins 9 and 16 (namely a pin IN3 and a pin IN 2) connected with the suppression module are at a low potential, a single-pole single-throw analog switch (composed of a pin D2 and a pin S2) of the second channel on the right side and a single-pole single-throw analog switch (composed of a pin D3 and a pin S3) of the third channel are IN an off state. The current generated by the +2V direct-current power supply is transmitted to the anode of the memristor Rm through the single-pole single-throw analog switch (composed of a pin D1 and a pin S1) of the first channel, and then flows to a zero potential point from the cathode of the memristor Rm through the single-pole single-throw analog switch (composed of a pin D4 and a pin S4) of the fourth channel to form a closed loop, so that the conductance of the memristor Rm is increased. The wider the direct current level generated by the enhancing module is, namely the larger the time difference between the input signal front neuron signal pre and the input signal back neuron signal post is, the larger the conductance increase of the memristor Rm is; when the post neuron signal post reaches the input end of the synapse bionic circuit before the pre neuron signal, the suppression module outputs direct current levels with different widths to the memristive synapse module according to the arrival time difference delta T of the post neuron signal post and the pre neuron signal pre, the direct current levels transmitted by the suppression module are input to 9 pins and 16 pins (namely an IN3 pin and an IN2 pin) of the ADG442, a single-pole single-throw analog switch (composed of a D2 pin and an S2 pin) of a second channel on the right side and a single-pole single-throw analog switch (composed of a D3 pin and an S3 pin) of a third channel are conducted, because the enhancement module stops working, the pins 1 and 8 (namely the pin IN1 and the pin IN 4) connected with the enhancement module are at low potential, and the single-pole single-throw analog switch (composed of the pin D1 and the pin S1) of the first channel and the single-pole single-throw analog switch (composed of the pin D4 and the pin S4) of the fourth channel on the left side are IN an off state. The current generated by the +2V direct-current power supply is transmitted to the cathode of the memristor Rm through the single-pole single-throw analog switch (composed of a pin D2 and a pin S2) of the second channel, and then flows to a zero potential point from the anode of the memristor Rm through the single-pole single-throw analog switch (composed of a pin D3 and a pin S3) of the third channel to form a closed loop, so that the conductance of the memristor Rm is reduced. The wider the direct current level generated by the suppression module is, namely the larger the time difference delta T between the neuron signal post after the input signal and the neuron signal pre before is, the larger the conductance reduction of the memristor Rm is.

Fig. 3 is a diagram of PSPICE simulated time domain waveforms when four input signals under different conditions are respectively input after the memristive synapse module of the present embodiment is accessed to the enhancing module and the inhibiting module. As shown in fig. 3, four cases, namely, 1 ms of a pre-neuron signal pre leading and post-neuron signal post, 8 ms of a pre-neuron signal pre leading and post-neuron signal post, 1 ms of a pre-neuron signal pre lagging and post-neuron signal post, and 8 ms of a pre-neuron signal pre lagging and post-neuron signal post are input to output pulses respectively, so that four different cases that the pre-neuron signal and the post-neuron signal reach synapses successively are simulated. When the input front neuron signal pre arrives 1 millisecond before the input rear neuron signal post, the resistance value of the memristor Rm can be observed to be reduced from 11K to 10.3K; until the second pair of pre-pulse neuron signals pre arrives 8 milliseconds before the post neuron signals post, the resistance value of the memristor Rm is reduced from 10.3K to 9.9K; when the third pair of pre-pulse neuron signals pre arrives 1 millisecond later than the post-pulse neuron signals post, the resistance value of the memristor Rm rises to 10.6K; and finally, when the fourth pair of pre-pulse neuron signals pre lags behind the post-neuron signal post for 8 milliseconds, the resistance value of the memristor Rm rises to 11K again. The method is the same as the STDP learning rule of biological synapses, when a current neuron signal pre reaches a synapse bionic circuit before a back neuron signal post, the conductance weight of a memristor Rm rises, and the smaller the time difference delta T between the front neuron signal pre and the back neuron signal post, the more obvious the conductance rise of the memristor Rm is; when the current neuron signal pre reaches the synapse bionic circuit after the post neuron signal post, the conductance weight of the memristor Rm is reduced, and the smaller the time difference delta T between the post neuron signal post and the pre neuron signal pre is, the more obvious the conductance of the memristor Rm is reduced.

To further simulate the bionic characteristics of the biological synapse STDP learning rule, as shown in fig. 4, in this embodiment, a pre-neuron signal pre and a post-neuron signal post with a time difference Δ T varying in1 ms step by step are respectively input, and the percentages of conductance changes of the memristor Rm under corresponding conditions are recorded and connected in a line by a dot, as shown in fig. 4, it can be observed that the measured oscillogram is similar to the 1, 3-quadrant STDP learning function oscillogram of the biological synapse, and the simulation effect is good and has good bionic characteristics.

To further expand the application range of the first memristive synapse submodule circuit, fig. 8 shows that at different regulated voltages V_thNext, taking this embodiment as an example, a line graph of the percentage of change in conductance of the memristor Rm when the input pulse time difference Δ T changes in steps of 1 millisecond is shown. Regulating voltage V_thThe lower the threshold voltage is, the longer the time from the discharge voltage of the capacitor C2 and the capacitor C4 to the threshold value is, and the wider the output level width of the boost module and/or the suppression module is, so that V is compared with V at the same input pulse time difference DeltaT_thThe smaller the memristor Rm conductance change percentage, the larger. Thus, according to the actual situation, different V can be adjusted_thThe memristive synaptic electrical circuit is employed.

Example two:

the embodiment uses a selection switch to switch on the connection between the boosting module, the suppressing module and the second memristive synapse submodule on the basis of the main scheme. When the time difference Δ T between the pre neuron signal pre and the post neuron signal post is taken as an abscissa and the conductance weight of the memristor Rm is taken as an ordinate, the second memristor synapse submodule circuit of the embodiment is used for realizing the STDP learning rule that the learning function is located in2, 4 quadrants.

In this embodiment, the second memristive synapse module includes a memristor Rm and a fourth analog switch, the fourth analog switch includes at least four channels, an output end of the boost module is connected to a control end of a first channel of the fourth analog switch and a control end of a fourth channel of the fourth analog switch, one end of the first channel of the fourth analog switch is connected to a power supply, the other end of the first channel of the fourth analog switch is connected to a negative electrode of the memristor Rm, an anode of the memristor Rm is connected to one end of the fourth channel of the fourth analog switch, and the other end of the fourth channel of the fourth analog switch is grounded; the output end of the suppression module is connected with the control end of the second channel of the fourth analog switch and the control end of the third channel of the fourth analog switch, one end of the second channel of the fourth analog switch is connected with a power supply, the other end of the second channel of the fourth analog switch is connected with the anode of the memristor Rm, the cathode of the memristor Rm is connected with one end of the third channel of the fourth analog switch, and the other end of the third channel of the fourth analog switch is grounded.

As shown in fig. 2c, the fourth analog switch is implemented by using an analog switch chip ADG442, which includes four controllable single-pole single-throw switch channels. The GND pin of ADG442 is grounded, VSS is connected to-15V, and VDD is connected to + 15V. IN the memristive synapse module, the output end of a voltage comparator U5 of an enhancement module is respectively connected with an IN1 pin and an IN4 pin of an ADG442, and is used for controlling a single-pole single-throw switch composed of a D1 pin and an S1 pin and a single-pole single-throw switch composed of a D4 pin and an S4 pin, the D1 pin of the ADG442 is connected with an external power supply, and the external power supply adopts +2V voltage for the consideration and the biological STDP learning function to be closer; the S1 pin of the ADG442 is connected with the negative electrode of the memristor Rm; the pin S4 is grounded, and the pin D4 is connected with the anode of the memristor Rm. IN the second memristive synapse submodule, the output end of a voltage comparator U6 of an inhibition module is respectively connected with an IN2 pin and an IN3 pin of an ADG442, and is used for controlling a single-pole single-throw switch composed of a D2 pin and an S2 pin and a single-pole single-throw switch composed of a D3 pin and an S3 pin, the D2 pin is connected with an external power supply, and the external power supply adopts +2V voltage for being closer to an STDP learning function of a living being considered; the pin S2 is connected with the anode of the memristor Rm; the pin S3 is grounded, and the pin D3 is connected with the negative electrode of the memristor Rm.

The second memristive synapse submodule of the present embodiment is substantially identical to the first memristive synapse submodule of the first embodiment in terms of circuit structure and operation principle, and the second memristive synapse submodule of the present embodiment is obtained by placing the memristor Rm in the first memristive synapse submodule of the first embodiment in a reversed polarity, so that the simulated synapse function of the second memristive synapse submodule of the present embodiment is opposite to that of the first memristive synapse submodule of the first embodiment. In this embodiment, a pre neuron signal pre and a post neuron signal post, which have time differences Δ T varying in1 millisecond steps, are respectively input, and the percentage of conductance change of the memristor Rm under corresponding conditions is recorded and connected in parallel to form a line, as shown in fig. 6, it can be observed that the measured oscillogram is similar to the 2, 4-quadrant STDP learning function oscillogram of the biological synapse, the simulation effect is good, and the simulation characteristic is good.

Example three:

the embodiment uses a selection switch to switch on the connection between the boosting module, the suppressing module and the third memristive synapse submodule on the basis of the main scheme. When the time difference Δ T between the pre neuron signal pre and the post neuron signal post is taken as an abscissa and the conductance weight of the memristor Rm is taken as an ordinate, the third memristor synapse submodule circuit of the embodiment is used for realizing the STDP learning rule that the learning function is located in the 1, 2 quadrants.

In this embodiment, the third memristive synapse sub-module includes a memristor Rm and a fifth analog switch, the fifth analog switch includes at least two channels, an output end of the boost module is connected to a control end of a first channel of the fifth analog switch, one end of the first channel of the fifth analog switch is connected to a power supply, the other end of the first channel of the fifth analog switch is connected to an anode of the memristor Rm, and a cathode of the memristor Rm is grounded; the output end of the suppression module is connected with the control end of the second channel of the fifth analog switch, one end of the second channel of the fifth analog switch is connected with a power supply, and the other end of the second channel of the fifth analog switch is connected with the anode of the memristor Rm.

As shown IN fig. 2b, the fifth analog switch is implemented by using one analog switch chip ADG442, which includes four controllable single-pole single-throw switch channels, IN this embodiment, only two of the controllable single-pole single-throw switch channels are used, and all pins (i.e., the IN2 pin, the S2 pin, the D2 pin, the IN3 pin, the S3 pin, and the D3 pin) of the other two controllable single-pole single-throw switch channels are grounded. The GND pin of ADG442 is grounded, VSS is connected to-15V, and VDD is connected to + 15V. IN a third memristive synapse submodule, an output end of a voltage comparator U5 of an enhancement module is connected with an IN1 pin of an ADG442 and used for controlling a single-pole single-throw switch composed of a D1 pin and an S1 pin, the D1 pin of the ADG442 is connected with an external power supply, the external power supply adopts +2V voltage for considering the closer approach to an STDP learning function of a living being, and an S1 pin of the ADG442 is connected with the anode of a memristor Rm; IN a third memristive synapse submodule, the output end of a voltage comparator U6 of an inhibition module is connected with an IN4 pin of an ADG442 and used for controlling a single-pole single-throw switch composed of a D4 pin and an S4 pin, the S4 pin is connected with an external power supply, the external power supply is closer to an STDP learning function of organisms IN consideration, the voltage of +2V is adopted by the external power supply, and the D4 pin is connected with the anode of a memristor Rm; the negative electrode of the memristor Rm is grounded.

In this embodiment, the STDP learning rule that the learning function is located in the 1, 2 quadrants is implemented, the current neuron signal pre reaches the input end of the synapse bionic circuit before the post neuron signal post, and the enhancing module outputs the direct current levels with different widths to the third memristive synapse submodule according to the time difference Δ T between the arrival of the current neuron signal pre and the arrival of the post neuron signal post. IN this embodiment, the dc level transmitted from the boost module is input to the 1 pin (i.e., the IN1 pin) of the ADG442, the single-pole single-throw analog switch (composed of the D1 pin and the S1 pin) of the first channel of the fifth analog switch is turned on, and the current generated by the +2V dc power source is transmitted to the positive electrode of the memristor Rm through the single-pole single-throw analog switch (composed of the D1 pin and the S1 pin) of the first channel of the fifth analog switch, and then flows from the negative electrode of the memristor Rm to the zero potential point, so as to form a closed loop, thereby increasing the conductance of the memristor Rm. The wider the direct current level generated by the enhancing module is, namely the larger the time difference delta T between the pre neuron signal and the post neuron signal of the input signal is, the larger the conductance increase of the memristor Rm is; when the post neuron signal post reaches the input end of the synapse bionic circuit before the pre neuron signal, the suppression module outputs direct current levels with different widths to the memristive synapse module according to the arrival time difference delta T of the post neuron signal post and the pre neuron signal pre, the direct current level transmitted by the suppression module is input to 8 pins (namely an IN4 pin) of the ADG442, a single-pole single-throw analog switch (composed of a D4 pin and an S4 pin) of a second channel of the fifth analog switch is conducted, current generated by a +2V direct current power supply is transmitted to the positive pole of the memristor Rm through the single-pole single-throw analog switch (composed of the D4 pin and the S4 pin) of the second channel of the fifth analog switch, and then flows from the negative pole of the memristor Rm to a zero potential point, so that the conductance of the memristor Rm rises. The wider the direct current level generated by the suppression module, namely the larger the time difference between the neuron signal post after the input signal and the neuron signal pre before, the larger the conductance increase of the memristor Rm. In order to further simulate the bionic characteristics of the biological synapse STDP learning rule, in this embodiment, a pre-neuron signal pre and a post-neuron signal post with a time difference Δ T varying in1 millisecond step are respectively input, and the percentage of conductance change of the memristor Rm under the corresponding condition is recorded and connected in parallel to form a line, as shown in fig. 5, it can be observed that the measured oscillogram is similar to the oscillogram of the

biological synapse

1, 2 quadrant STDP learning function, the simulation effect is good, and the simulation characteristic is good.

Example four:

the embodiment uses a selection switch to switch on the connection between the boosting module, the suppressing module and the fourth memristive synapse submodule on the basis of the main scheme. When the time difference Δ T between the pre neuron signal pre and the post neuron signal post is taken as an abscissa and the conductance weight of the memristor Rm is taken as an ordinate, the fourth memristor synapse submodule circuit of the embodiment is used for realizing the STDP learning rule that the learning function is located in the 3, 4 quadrants.

In this embodiment, the fourth memristive synapse sub-module comprises a memristor Rm and a sixth analog switch, the sixth analog switch comprises at least two channels, the output end of the boost module is connected with the control end of a first channel of the sixth analog switch, one end of the first channel of the sixth analog switch is connected with a power supply, the other end of the first channel of the sixth analog switch is connected with the negative electrode of the memristor Rm, and the positive electrode of the memristor Rm is grounded; the output end of the suppression module is connected with the control end of the second channel of the sixth analog switch, one end of the second channel of the sixth analog switch is connected with a power supply, and the other end of the second channel of the sixth analog switch is connected with the negative electrode of the memristor Rm.

As shown IN fig. 2D, the sixth analog switch is implemented by using one analog switch chip ADG442, which includes four controllable single-pole single-throw switch channels, IN this embodiment, only two of the controllable single-pole single-throw switch channels are used, and all pins (i.e., the IN2 pin, the S2 pin, the D2 pin, the IN3 pin, the S3 pin, and the D3 pin) of the other two controllable single-pole single-throw switch channels are grounded. The GND pin of ADG442 is grounded, VSS is connected to-15V, and VDD is connected to + 15V. IN a fourth memristive synapse submodule, an output end of a voltage comparator U5 of an enhancement module is connected with an IN1 pin of an ADG442 and used for controlling a single-pole single-throw switch composed of a D1 pin and an S1 pin, the D1 pin of the ADG442 is connected with an external power supply, the external power supply adopts +2V voltage for considering the closer approach to an STDP learning function of organisms, and an S1 pin of the ADG442 is connected with the negative electrode of a memristor Rm; IN a fourth memristive synapse submodule, the output end of a voltage comparator U6 of an inhibition module is connected with an IN4 pin of an ADG442 and used for controlling a single-pole single-throw switch composed of a D4 pin and an S4 pin, the S4 pin is connected with an external power supply, the external power supply is closer to an STDP learning function of organisms IN consideration, the voltage of +2V is adopted by the external power supply, and the D4 pin is connected with the negative electrode of a memristor Rm; the positive electrode of the memristor Rm is grounded.

The circuit structure and the operation principle of the fourth memristive synapse submodule of the present embodiment are substantially the same as those of the third memristive synapse submodule of the third embodiment, and the fourth memristive synapse submodule of the present embodiment is obtained by reversely placing the memristors Rm in the third memristive synapse submodule of the third embodiment, so that the synaptic function simulated by the fourth memristive synapse submodule of the present embodiment is opposite to that simulated by the third memristive synapse submodule of the third embodiment. In this embodiment, a pre neuron signal pre and a post neuron signal post, which have time differences Δ T varying in1 millisecond steps, are respectively input, and the percentage of conductance change of the memristor Rm under corresponding conditions is recorded and connected in parallel to form a line, as shown in fig. 7, it can be observed that the measured oscillogram is similar to the oscillogram of the 3, 4-quadrant STDP learning function of the biological synapse, the simulation effect is good, and the simulation characteristic is good.

The utility model discloses a synapse bionic circuit compares in the president can only simulate the synapse bionic circuit of an STDP learning rule, and the diversified STDP learning function of different positions synapses such as simulation organism visual nerve, muscle nerve is selected to the accessible select switch. Meanwhile, the input signal of the circuit abandons the traditional complex and difficult-to-adjust double-spike pulse waveform and adopts a simple and easy-to-adjust direct current pulse waveform, so that the input condition is not harsh any more. The circuit also has the capability of adjusting the STDP learning rule, changes the variation of the synaptic weight under the same excitation by changing the set regulation voltage, further changes the corresponding parameters for simulating and realizing the STDP learning function, can be used for simulating the synaptic STDP learning rule under different environments, has wider application range, and has greater development potential in the aspect of artificial intelligence bionics.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.

Claims

1. A synapse bionic circuit for realizing diversified STDP learning rules based on a memristor is characterized by comprising an enhancing module, an inhibiting module and a memristor synapse module,

when the front neuron signal pre arrives before the rear neuron signal post, the enhancement module works, the inhibition module stops running, and the enhancement module outputs direct current levels with different widths according to the input time difference between the front neuron signal pre and the rear neuron signal post;

when the post-neuron signal post arrives before the pre-neuron signal pre, the inhibition module works, the enhancement module stops running, and the inhibition module outputs direct current levels with different widths according to the input time difference between the post-neuron signal post and the pre-neuron signal pre;

the memristive synapse module correspondingly suppresses memristor conductance weights according to the direct current levels of different widths.

2. The synaptic biomimetic circuit for realizing diversified STDP learning rules based on memristors as claimed in claim 1, wherein the enhancing module comprises an inverter U1, a NAND gate U2, an electronic switch tube P1, a resistor R1, a capacitor C1, a first analog switch, a resistor R2, a capacitor C2, a voltage comparator U5 and a resistor R3, wherein an output of the inverter U1 is connected to one input of the NAND gate U2, another input of the NAND gate U2 receives the pre-neuron signal, an output of the NAND gate U2 is connected to a control electrode of the electronic switch tube P1, an input of the electronic switch tube P1 is connected to a supply voltage, an output of the electronic switch tube P1 is connected to one end of the first analog switch, a control end of the first analog switch receives the post-neuron signal post, another end of the first analog switch is connected to a same-direction input of the voltage comparator U5, the reverse input end of the voltage comparator U5 is connected with a regulation voltage Vth, the output end of the voltage comparator U5 is connected with the memristive synapse module, one end of the resistor R3 is connected with the power input end of the voltage comparator U5 in parallel to be connected with a power supply, and the other end of the resistor R3 is connected with the output end of the voltage comparator U5; the resistor R1 and the capacitor C1 are connected between the output end of the electronic switch tube P1 and the ground in parallel, and the resistor R2 and the capacitor C2 are connected between the equidirectional input end of the voltage comparator U5 and the ground in parallel.

3. The synaptic biomimetic circuit for realizing diversified STDP learning rules based on memristors as claimed in claim 2, wherein the suppressing module comprises an inverter U3, a NAND gate U4, an electronic switch tube P2, a resistor R4, a capacitor C3, a second analog switch, a resistor R5, a capacitor C4, a voltage comparator U6 and a resistor R6, an input terminal of the inverter U3 is connected to an output terminal of the electronic switch tube P1, an output terminal of the inverter U3 is connected to one input terminal of the NAND gate U4, the other input terminal of the NAND gate U4 receives the post-neuron signal post, an output terminal of the NAND gate U4 is connected to a control terminal of the electronic switch tube P2, an input terminal of the electronic switch tube P2 is connected to a supply voltage, and output terminals of the electronic switch tube P2 are respectively connected to an input terminal of the inverter U1 and one terminal of the second analog switch, the control end of the second analog switch receives the pre-neuron signal pre, the other end of the second analog switch is connected with the equidirectional input end of the voltage comparator U6, the inverted input end of the voltage comparator U6 is connected with a regulation voltage Vth, the output end of the voltage comparator U6 is connected with the memristive synapse module, one end of the resistor R6 is connected with the power supply input end of the voltage comparator U6 in parallel to be connected with a power supply, and the other end of the resistor R6 is connected with the output end of the voltage comparator U6; the resistor R4 and the capacitor C3 are connected between the output end of the electronic switch tube P2 and the ground in parallel, and the resistor R5 and the capacitor C4 are connected between the equidirectional input end of the voltage comparator U6 and the ground in parallel.

4. The synaptic biomimetic circuit to implement diverse STDP learning rules based on memristors of claim 3, wherein the memristive synapse module comprises a first memristive synapse submodule, a second memristive synapse submodule, a third memristive synapse submodule, a fourth memristive synapse submodule; when the time difference delta T between the input of the pre neuron signal pre and the input of the post neuron signal post into the memristive synapse module is used as an abscissa and the conductance weight of the memristor Rm is used as an ordinate,

the first memristive synapse submodule works in quadrants 1 and 3 and is used for simulating the neural activity working in quadrants 1 and 3;

the second memristive synapse submodule works in quadrants 2 and 4 and is used for simulating the neural activity working in quadrants 2 and 4;

the third memristive synapse submodule works in quadrants 1 and 2 and is used for simulating the neural activity working in quadrants 1 and 2;

the fourth memristive synapse submodule operates in quadrants 3 and 4 and is used for simulating neural activity operating in quadrants 3 and 4.

5. The synaptic biomimetic circuit for implementing diversified STDP learning rules based on memristors according to claim 4, wherein the first memristive synapse submodule comprises a memristor Rm and a third analog switch, the third analog switch comprises at least four channels, an output end of the boost module is connected with a control end of a first channel of the third analog switch and a control end of a fourth channel of the third analog switch, one end of the first channel of the third analog switch is connected with an external power supply, the other end of the first channel of the third analog switch is connected with an anode of the memristor Rm, a cathode of the memristor Rm is connected with one end of the fourth channel of the third analog switch, and the other end of the fourth channel of the third analog switch is grounded; the output end of the suppression module is connected with the control end of the second channel of the third analog switch and the control end of the third channel of the third analog switch, one end of the second channel of the third analog switch is connected with an external power supply, the other end of the second channel of the third analog switch is connected with the negative electrode of the memristor Rm, the positive electrode of the memristor Rm is connected with one end of the third channel of the third analog switch, and the other end of the third channel of the third analog switch is grounded.

6. The synaptic biomimetic circuit for implementing diversified STDP learning rules based on memristors according to claim 4, wherein the second memristive synapse module comprises a memristor Rm and a fourth analog switch, the fourth analog switch comprises at least four channels, an output end of the boost module is connected with a control end of a first channel of the fourth analog switch and a control end of a fourth channel of the fourth analog switch, one end of the first channel of the fourth analog switch is connected with an external power supply, the other end of the first channel of the fourth analog switch is connected with a negative electrode of the memristor Rm, an anode of the memristor Rm is connected with one end of a fourth channel of the fourth analog switch, and the other end of the fourth channel of the fourth analog switch is grounded; the output end of the suppression module is connected with the control end of the second channel of the fourth analog switch and the control end of the third channel of the fourth analog switch, one end of the second channel of the fourth analog switch is connected with an external power supply, the other end of the second channel of the fourth analog switch is connected with the anode of the memristor Rm, the cathode of the memristor Rm is connected with one end of the third channel of the fourth analog switch, and the other end of the third channel of the fourth analog switch is grounded.

7. The synaptic biomimetic circuit for implementing diversified STDP learning rules based on memristors according to claim 4, wherein the third memristive synapse submodule comprises a memristor Rm and a fifth analog switch, the fifth analog switch comprises at least two channels, the output end of the boost module is connected with the control end of a first channel of the fifth analog switch, one end of the first channel of the fifth analog switch is connected with an external power supply, the other end of the first channel of the fifth analog switch is connected with the positive electrode of the memristor Rm, and the negative electrode of the memristor Rm is grounded; the output end of the suppression module is connected with the control end of a second channel of the fifth analog switch, one end of the second channel of the fifth analog switch is connected with an external power supply, and the other end of the second channel of the fifth analog switch is connected with the anode of the memristor Rm.

8. The synaptic biomimetic circuit for implementing diversified STDP learning rules based on memristors according to claim 4, wherein the fourth memristive synapse submodule comprises a memristor Rm and a sixth analog switch, the sixth analog switch comprises at least two channels, the output end of the boost module is connected with the control end of a first channel of the sixth analog switch, one end of the first channel of the sixth analog switch is connected with an external power supply, the other end of the first channel of the sixth analog switch is connected with the negative electrode of the memristor Rm, and the positive electrode of the memristor Rm is grounded; the output end of the suppression module is connected with the control end of the second channel of the sixth analog switch, one end of the second channel of the sixth analog switch is connected with an external power supply, and the other end of the second channel of the sixth analog switch is connected with the negative electrode of the memristor Rm.