CN114757345A

CN114757345A - Memristor association memory neural network circuit and control method thereof

Info

Publication number: CN114757345A
Application number: CN202210259889.XA
Authority: CN
Inventors: 杨乐; 丁芝侠; 李赛; 张�浩
Original assignee: Huazhong Agricultural University; Wuhan Institute of Technology
Current assignee: Huazhong Agricultural University; Wuhan Institute of Technology
Priority date: 2022-03-16
Filing date: 2022-03-16
Publication date: 2022-07-15

Abstract

The invention relates to a memristor associative memory neural network circuit and a control method thereof, wherein the memristor associative memory neural network circuit comprises: including the logical output circuit that connects gradually, including the synaptic electrical circuit of memristor cross array to and the neuron circuit who is connected with synaptic electrical circuit electricity, wherein: the logic output circuit generates a control voltage after receiving the unconditional stimulation signal and/or the conditional stimulation signal; the synaptic circuit is triggered by the control voltage to adjust the resistance value of the memristor in the memristor cross array, so that an associative memory function and/or an associative output function are realized; and the neuron circuit outputs an analog voltage signal for representing correlation information according to the regulated memristor resistance value in the memristor cross array. Meanwhile, a forgetting function along with time is realized through the timing voltage output circuit. The method and the device correlate the corresponding information by means of associative memory, are expected to be applied to the field of intelligent robots, and improve the service experience of the intelligent robots.

Description

Memristor association memory neural network circuit and control method thereof

Technical Field

The invention belongs to the technical field of emerging circuits, and particularly relates to a memristor associative memory neural network circuit and a control method thereof.

Background

The human brain has billions of neurons, each of which communicates with others through thousands of synapses. The human brain can complete various fine and complicated works quickly and efficiently, and the overall power consumption is less than 20 watts. Therefore, the memristor neural network circuit is used for simulating the mechanism and the function of the human brain, the performance of the hardware circuit far surpassing that of the existing computer can be realized, and the performance of the circuit is greatly improved. In conclusion, how to effectively utilize the memristive neural network circuit to improve the circuit performance becomes a key difficulty in the technical field of emerging circuits.

In the prior art, an expert team designs a circuit capable of simulating the behavior of a physical memristor by using a microcontroller and an A/D converter, and the circuit is applied to a memristor associative memory neural network circuit to serve as a synaptic circuit to realize corresponding functions; the learners also design a corresponding neural network circuit by taking the memristor as a synaptic circuit based on the excellent characteristics of the memristor according to associative memory, but the utilization rate of the memristor is very low, and only the memristor on the diagonal line of the crossed array can be effectively utilized; a corresponding memristive neural network circuit is designed to simulate Pavlov associative memory and a corresponding forgetting process, but discrete memristive devices are utilized, so that the expansion performance is poor, and high-density integration is difficult to realize. In short, in the existing research or published patent, the utilization degree of the circuit is not high, the density of the whole information storage is not enough, and the high-density integrated manufacturing is difficult to realize, so that the performance of the whole memristive associative memory neural network circuit has certain defects. Therefore, how to design a high-performance memristive associative memory neural network circuit is an urgent problem to be solved.

Disclosure of Invention

In view of the above, there is a need for a memristive associative memory neural network circuit and a control method thereof, which are used to overcome the problems of the prior art that the circuit utilization rate of the memristive associative memory neural network circuit is not high and the density of the whole information storage is not sufficient.

In order to solve the above technical problem, the present invention provides a memristive associative memory neural network circuit, including a logic output circuit, a synapse circuit, and a neuron circuit electrically connected to the synapse circuit in sequence, wherein the synapse circuit includes a memristor crossbar array, wherein:

the logic output circuit generates a control voltage after receiving the unconditional stimulus signal and/or the conditional stimulus signal; the synaptic circuit is triggered by the control voltage to adjust the resistance value of the memristor in the memristor cross array, so that an associative memory function and/or an associative output function are realized; and the neuron circuit outputs an analog voltage signal for representing correlation information according to the regulated memristor resistance value in the memristor cross array.

Further, the logic output circuit comprises a logic conversion circuit and a voltage selection output circuit which are electrically connected in sequence, wherein:

the logic conversion circuit comprises a first NOT gate and an OR gate, the conditional stimulus signal is connected to the input end of the first NOT gate, the unconditional stimulus signal is connected to the first input end of the OR gate, and the output end of the NOT gate is connected to the second input end of the OR gate.

Further, the voltage selection output circuit comprises a first analog switch and a second analog switch, an output end of the or gate is electrically connected to a control end of the first analog switch, a first input end of the first analog switch is connected to a first voltage, and a second input end of the first analog switch is connected to a second voltage; the output end of the NOT gate is electrically connected to the control end of the second analog switch, and the first input end of the second analog switch is connected to a third voltage and the second input end of the second analog switch is connected to a fourth voltage.

Further, the memristor crossbar array in the synaptic circuit includes M row signal lines, N column signal lines, the row signal lines and the column signal lines crossing each other but not directly connected, wherein each row signal line and each column signal line are connected together at a cross point through a circuit unit including a memristor.

Further, the control voltage includes a first control voltage signal output by the first analog switch and a second control voltage signal output by the second analog switch, and the circuit unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a memristor, where:

one end of the first MOS tube is electrically connected to the row signal line and used for receiving the first control voltage signal, and the other end of the first MOS tube is electrically connected to the anode of the memristor;

one end of the second MOS tube is connected to one end of the first MOS tube, and the other end of the second MOS tube is connected to the negative electrode of the memristor;

one end of the third MOS tube is connected to the anode of the memristor, and the other end of the third MOS tube is connected to the column signal line;

one end of the fourth MOS tube is connected to the cathode of the memristor, and the other end of the fourth MOS tube is connected to the column signal line;

the control end of the first MOS tube, the control end of the second MOS tube, the control end of the third MOS tube and the control end of the fourth MOS tube are respectively electrically connected to a first shunt point, and the first shunt point is used for receiving the second control voltage signal.

Further, the neuron circuit is electrically connected to a column signal line in the synapse circuit, the neuron circuit comprising an operational amplifier and a neuron resistance, wherein:

one end of the neuron resistor is electrically connected to the inverting input end of the operational amplifier, and the other end of the neuron resistor is electrically connected to the output end of the operational amplifier;

the inverting input end of the operational amplifier is electrically connected to the column signal line, the non-inverting input end of the operational amplifier is grounded, and the output end of the operational amplifier outputs the analog voltage signal.

Further, the memristive associative memory neural network circuit further comprises a timing voltage output circuit electrically connected to the synapse circuit, the timing voltage output circuit comprising a clock pulse source, a binary counter, a monostable flip-flop, a second not gate, an and gate, a third analog switch, a fourth analog switch, wherein:

the clock pulse source is electrically connected to the binary counter and used for outputting a pulse signal to the binary counter;

the binary counter is electrically connected to the monostable flip-flop and is used for outputting a logic indication level to the monostable flip-flop when the pulse signal is counted to a preset value;

the conditional stimulus signal is connected to the input end of a second NOT gate, the output end of the second NOT gate is connected to the first input end of an AND gate, the monostable trigger is connected to the second input end of the AND gate, and the AND gate is electrically connected to the control end of the third analog switch and the control end of the fourth analog switch respectively;

a first input end of the third analog switch is connected to a fifth voltage, a second input end of the third analog switch is set to be in a high-impedance state, and an output end of the third analog switch is electrically connected to the row signal line in the synapse circuit;

the first input end of the fourth analog switch is connected with a sixth voltage, the second input end of the fourth analog switch is set to be in a high-resistance state, and the output end of the fourth analog switch is electrically connected to a first shunt point in a circuit unit of the synapse circuit.

The invention also provides a control method of the memristor associative memory neural network circuit, which is based on the memristor associative memory neural network circuit and comprises the following steps:

carrying out logic transformation on the received unconditional stimulation signals and/or conditional stimulation signals through a logic output circuit to generate control voltage;

adjusting the resistance value of a memristor in a memristor cross array under the triggering of the control voltage through a synapse circuit to realize an associative memory function and/or an associative output function;

and outputting an analog voltage signal for representing the correlation information according to the regulated resistance value of the memristor in the memristor cross array through a neuron circuit.

Further, the generating of the control voltage by logically converting the received unconditional stimulus signal and/or conditional stimulus signal by the logic output circuit includes:

when the unconditional stimulation signal and the conditional stimulation signal are both in high level, logic judgment is carried out through a logic conversion circuit, the result of the logic judgment is input to a voltage selection output circuit, a first control voltage signal output by a first analog switch and a second control voltage signal output by a second analog switch in the voltage selection output circuit form a first voltage combination, wherein the first voltage combination is used for triggering the synapse circuit to realize the associative memory function, and the storage of the associated information is completed;

when the unconditional stimulation signal is at a low level and the conditional stimulation signal is at a high level, performing logic judgment through a logic conversion circuit, inputting a result of the logic judgment to the voltage selection output circuit, wherein the first control voltage signal and the second control voltage signal form a second voltage combination, and the second voltage combination is used for triggering the synapse circuit to realize a correlation output function;

when the unconditional stimulus signal and the conditional stimulus signal are both at low level, or the unconditional stimulus signal is at high level and the conditional stimulus signal is at low level, the logic conversion circuit is used for carrying out logic judgment, the result of the logic judgment is input to the voltage selection output circuit, the first control voltage signal and the second control voltage signal form a third voltage combination and a fourth voltage combination, wherein the third voltage combination and the fourth voltage combination do not trigger the synapse circuit to realize the associative memory function or the associative output function.

Further, the adjusting, by the synaptic circuit, the memristor resistance values in the memristor crossbar array under the triggering of the control voltage to realize an associative memory function and/or an associative output function includes:

when the synaptic circuit receives the first voltage combination, a first MOS tube and a fourth MOS tube in a circuit unit of the synaptic circuit are conducted, a second MOS tube and a third MOS tube in the circuit unit of the synaptic circuit are disconnected, and when a first control voltage signal is larger than a threshold voltage of a memristor, the resistance value of the memristor is continuously reduced, so that an associative memory function is realized;

when the synapse circuit receives the second voltage combination, the first MOS transistor and the fourth MOS transistor are conducted, the second MOS transistor and the third MOS transistor are disconnected, and when a first control voltage signal is smaller than a threshold voltage of the memristor, the resistance value of the memristor is kept unchanged, so that a correlation output function is realized;

when the synapse circuit receives the third voltage combination or the fourth voltage combination, the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are all disconnected;

wherein the outputting, by the neuron circuit, an analog voltage signal for representing correlation information according to the adjusted memristor resistance in the memristor crossbar array includes:

determining synaptic weight according to the ratio of neuron resistance to the regulated memristor resistance;

determining the analog voltage signal according to the synaptic weight and the first control voltage signal.

Further, the control method further comprises:

when the unconditional stimulation signal and the conditional stimulation signal are both in a high level, or the unconditional stimulation signal is in a low level and the conditional stimulation signal is in a high level, a third analog switch and a fourth analog switch in the timing voltage output circuit output a high-impedance state;

when the unconditional stimulation signal and the conditional stimulation signal are both in a low level, or the unconditional stimulation signal is in a high level and the conditional stimulation signal is in a low level, if the timing voltage output circuit times to a preset time, a third control voltage signal output by the third analog switch and a fourth control voltage signal output by the fourth analog switch form a fifth voltage combination, so that the associated information is forgotten along with the time, and the duration of the fifth voltage combination can be adjusted and the forgetting rate along with the time can be changed by changing the device parameters in the monostable trigger circuit;

when the synapse circuit receives the fifth voltage combination, a second MOS tube and a third MOS tube in a circuit unit of the synapse circuit are connected, a first MOS tube and a fourth MOS tube in the circuit unit of the synapse circuit are disconnected, and when a third control voltage signal is larger than a threshold voltage of a memristor, the resistance value of the memristor is continuously increased, so that a function of forgetting associated information along with time is realized.

Compared with the prior art, the invention has the beneficial effects that: in the memristor associative memory neural network circuit, corresponding logic conversion is carried out on the unconditional stimulation signal and the conditional stimulation signal through a set logic output circuit to form a control voltage for triggering a synaptic circuit; through setting a synapse circuit, adjusting the resistance value of a memristor by using a memristor cross array in the synapse circuit under the action of different control voltages, realizing association of associative memory information, or outputting the memorized association information; corresponding associated information is output by the neuron circuit, and the associated information is represented by analog voltage signals output by the neurons. And under the control of the timing voltage output circuit, the stored related information can realize a forgetting function along with time. In the related control method, firstly, corresponding logic judgment is carried out on the unconditional stimulation signal and the conditional stimulation signal, and corresponding control voltage is formed by using the result of the logic judgment; then, after different voltage combinations are formed by different control voltages, resistance value changes of memristors in the memristor cross array are adjusted, and association of data and extraction of associated information are achieved by combining the characteristic that a synaptic circuit is flexible and controllable; finally, the analog voltage signal is output to represent the size of the data volume, represent different information and effectively indicate the change of the associated information. In addition, after the preset time is timed, the timing voltage output circuit generates a corresponding voltage combination to control the reverse change of the memristance to realize the forgetting function. Also, the forgetting rate can be set to a different value. In conclusion, the invention not only uses the memristor cross array as a carrier, increases the integration level of the circuit and the density of memory information storage, but also has good expandability. Analog signals output by the neurons are also used for expressing different information and indicating the change of the associated information, so that the method has a good effect.

Drawings

FIG. 1 is a schematic structural diagram of an embodiment of a memristive associative memory neural network circuit according to the present disclosure;

FIG. 2 is a schematic diagram of a logic output circuit of FIG. 1 according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating an embodiment of the synaptic electrical circuit of FIG. 1 according to the present invention;

FIG. 4 is a schematic diagram of an embodiment of the neuron circuit of FIG. 1 according to the present invention;

FIG. 5 is a schematic diagram of an embodiment of the clocked voltage output circuit of FIG. 1 according to the present invention;

FIG. 6 is a schematic diagram of a specific system architecture of an embodiment of a memristive associative memory neural network circuit according to the present disclosure;

FIG. 7 is a schematic diagram of a specific circuit structure of an embodiment of a memristive associative memory neural network circuit according to the present disclosure;

fig. 8 is a schematic flow chart illustrating a control method of a memristive associative memory neural network circuit according to an embodiment of the present disclosure.

Detailed Description

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention and not to limit the scope of the invention.

In the description of the present invention, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to imply that the number of technical features indicated is significant. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. Further, "plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the described embodiments can be combined with other embodiments.

The invention provides a memristor associative memory neural network circuit and a control method thereof.

Before the description of the embodiments, the related words are paraphrased:

memristor: a memory resistor (Memristor) is a circuit device that represents the relationship between magnetic flux and electric charge. A memristor has a dimension of resistance, but unlike resistance, the resistance of a memristor is determined by the charge flowing through it. Therefore, the charge quantity flowing through the memristor can be known by measuring the resistance value of the memristor, so that the memristor has the function of memorizing the charge; it should be noted that, in 2008, professor chua zaila (leon.o.chua) of china theoretically proposes a memristor for the first time from the viewpoint of symmetry of basic parameters of a circuit. The Hewlett packard laboratory firstly manufactures physical devices of the memristor in 2008, and development of memristor research is greatly promoted. When a corresponding voltage is applied to two ends of the memristor, the memristance changes. When there is no voltage across the memristor, the resistance of the memristor remains unchanged. The resistance value change of the memristor can be well matched with the synaptic weight change in the neural network, so that the memristor is used as the synaptic circuit, the number of used electronic devices can be reduced, and the working performance of the synaptic circuit can be improved. Therefore, the memristor neural network circuit has a very good application prospect;

associative memory: is an important biological learning mechanism and has been verified in pavlov associative memory experiments. Pavlov associative memory experiments showed that dogs can establish conditioned reflex between ringing and salivation through associative learning, the experimental process is as follows: under initial conditions, the dogs were only fed (unconditioned stimulation) and were allowed to salivate, while the dogs were not allowed to salivate by ringing alone (conditioned stimulation). Then, the dog is rung while feeding it, and the dog learns through the association between food and bell, forming a conditioned reflex between bell and salivation. After the learning process is over, the dog alone rings and it will secrete saliva. Associative memory was also verified in experiments such as gill contraction reflex of sea hares, blink reflex of rabbits, and the like. Two inputs are contained in the associative memory: unconditional stimulation, conditional stimulation. In the initial stage, the synaptic weight corresponding to the conditional stimulus is small. A learning phase, wherein the synaptic weight is continuously increased along with the association learning;

based on the description of the technical terms, in the prior art, the circuit structure of the memristive associative memory neural network circuit is not based on the memristive crossbar array, and high-density integrated manufacturing cannot be realized; the control of the circuit units in the memristor cross array is complex, and each circuit unit cannot be independently and flexibly controlled; meanwhile, the existing memristor associative memory neural network circuit can only represent the existence or nonexistence of output, and does not use analog quantity to represent the data quantity, so that the existing memristor associative memory neural network circuit lacks good circuit performance. Therefore, the invention aims to provide a high-performance novel memristive associative memory neural network circuit.

Specific examples are described in detail below, respectively:

an embodiment of the present invention provides a memristive associative memory neural network circuit, and referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of the memristive associative memory neural network circuit provided by the present invention, and includes a logic output circuit 101, a synaptic circuit 102 including a memristor crossbar array, and a neuron circuit 103 electrically connected to the synaptic circuit, which are electrically connected in sequence, where:

the logic output circuit 101 generates a control voltage after receiving the unconditional stimulation signal and/or the conditional stimulation signal; the synaptic circuit 102 regulates the resistance of the memristor in the memristor crossbar array under the triggering of the control voltage, so as to realize an associative memory function and/or an associative output function; the neuron circuit 103 outputs an analog voltage signal for representing correlation information according to the adjusted memristor resistance value in the memristor crossbar array.

In the embodiment of the invention, in a memristor associative memory neural network circuit, a logic output circuit is arranged to perform corresponding logic conversion on an unconditional stimulation signal and a conditional stimulation signal to form a control voltage for triggering a synaptic circuit; through setting a synapse circuit, adjusting the resistance value of a memristor by using a memristor cross array in the synapse circuit under the action of different control voltages, realizing association of associative memory information, or outputting the memorized association information; corresponding associated information is output by the neuron circuit, and the associated information is represented by analog voltage signals output by the neurons. It should be noted that the circuit is not completely implemented according to the mechanism of biopavlov associative memory, but the working mode is reasonably adjusted according to the application requirements of the circuit on the basis of the basic mechanism of pavlov associative memory, so that the circuit is a novel memristive associative memory neural network circuit.

As a preferred embodiment, referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of the logic output circuit in fig. 1 provided by the present invention, where the logic output circuit includes a logic converting circuit and a voltage selecting output circuit electrically connected in sequence, where:

In the embodiment of the invention, the first NOT gate and the first OR gate are used for carrying out effective logic judgment on the unconditional stimulation signal (US) and the conditional stimulation signal (CS).

In a specific embodiment of the present invention, and with reference to FIG. 2, the conditional stimulus signal (CS) is coupled to an input of a NOT-gate U1, an output of the NOT-gate U1 is coupled to a second input of an OR-gate U2, and the unconditional stimulus signal (US) is coupled to a first input of an OR-gate U2.

As a preferred embodiment, still referring to fig. 2, the voltage selection output circuit includes a first analog switch and a second analog switch, an output terminal of the or gate is electrically connected to a control terminal of the first analog switch, and a first input terminal of the first analog switch is connected to a first voltage and a second input terminal of the first analog switch is connected to a second voltage; the output end of the NOT gate is electrically connected to the control end of the second analog switch, and the first input end of the second analog switch is connected to a third voltage and the second input end of the second analog switch is connected to a fourth voltage.

In the embodiment of the invention, the voltage selection output circuit outputs different voltage combinations, namely control voltages by utilizing the first analog switch and the second analog switch under the triggering of the logic signal.

In a specific embodiment of the present invention, as seen in FIG. 2, the output terminal of the NOT gate U1 is connected to the control terminal of the second analog switch S2, and the output terminal of the OR gate U2 is connected to the control terminal of the first analog switch S1. The first input terminal of the first analog switch S1 is connected to a voltage of 1V, and the second input terminal of the first analog switch S1 is connected to a voltage of 0.4V. A first input terminal of the second analog switch S2 is connected to a voltage of 0.5V, and a second input terminal of the second analog switch S2 is connected to a voltage of-2V.

As a preferred embodiment, referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment of the synapse circuit in fig. 1 provided by the present invention, where the memristor crossbar array in the synapse circuit includes M row signal lines and N column signal lines, the row signal lines and the column signal lines are crossed but not directly connected to each other, and each row signal line and each column signal line are connected together at a cross point through a circuit unit including memristors.

In the embodiment of the invention, based on the cross array structure, the synaptic circuit is involved, and each circuit unit can be flexibly, effectively and independently controlled. Here, M and N are preferably equal values.

As a preferred embodiment, still referring to fig. 3, the control voltage includes a first control voltage signal output by the first analog switch and a second control voltage signal output by the second analog switch, and the circuit unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a memristor, where:

In the embodiment of the invention, the 4T1M memristor cross array structure (one memristor and four MOS tubes) is used as a synaptic circuit, so that each circuit unit of 4T1M can be flexibly controlled, corresponding functions are realized, each circuit unit is applied, and the storage density of information is improved.

In a specific embodiment of the present invention, the circuit unit 4T1M includes: the transistor comprises a first MOS transistor T1, a second MOS transistor T2, a third MOS transistor T3, a fourth MOS transistor T4 and a memristor Rm 1. The connection mode is shown in fig. 3, and is not described in detail here.

As a preferred embodiment, referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of the neuron circuit in fig. 1 provided by the present invention, the neuron circuit is electrically connected to the column signal lines in the synapse circuit, the neuron circuit includes an operational amplifier and a neuron resistor, wherein:

In the embodiment of the invention, the neuron circuit is used for representing the size of the data volume by using the analog voltage, representing different information and indicating the change of the associated information, thereby having good effect.

As a preferred embodiment, referring to fig. 5, fig. 5 is a schematic structural diagram of an embodiment of the timing voltage output circuit in fig. 1 provided in the present invention, the memristive associative memory neural network circuit further includes a timing voltage output circuit electrically connected to the synapse circuit, the timing voltage output circuit includes a clock pulse source, a binary counter, a monostable flip-flop, a second not gate, an and gate, a third analog switch, and a fourth analog switch, where:

the conditional stimulus signal is connected to the input end of a second NOT gate, the output end of the second NOT gate is connected to the first input end of an AND gate, the monostable trigger is connected to the second input end of the AND gate, and the AND gate is respectively and electrically connected to the control end of the third analog switch and the control end of the fourth analog switch;

In the embodiment of the invention, a timing voltage output circuit is utilized, and the forgetting speed along with the time can be adjusted at will by the circuit.

In an embodiment of the invention, referring to fig. 5, the above-mentioned clocked voltage output circuit includes a binary counter, a monostable flip-flop, a second not gate U3, an and gate U4, a third analog switch S3, and a fourth analog switch S4;

the output end of the binary counter is connected to the input end of the monostable trigger, and when the counter reaches a preset count value, the monostable trigger is triggered. The condition stimulus CS11 is connected to the input terminal of the second NOT gate U3, the output terminal of the second NOT gate U3 is connected to the first input terminal of the AND gate U4, the output terminal of the monostable flip-flop is connected to the second input terminal of the AND gate U4, the output terminal of the AND gate U4 is connected to the control terminal of the third switch S3, and the output terminal of the AND gate U4 is also connected to the control terminal of the fourth switch S4;

the first input end of the third switch S3 is connected with 1V voltage, the second input end of the third switch S3 is set to be in a high-impedance state, and the output end of the third switch S3 is connected with the row signal line of the 4T1M memristive crossbar array. A first input end of the fourth switch S4 is connected with 2V voltage, a second input end of the fourth switch S4 is set to be in a high-impedance state, and an output end of the fourth switch S4 is connected with control ends of four MOS (metal oxide semiconductor) tubes of a circuit unit in the 4T1M memristive crossbar array;

it should be noted that the first analog switch S1 to the fourth analog switch S4 are all alternative analog switches.

A specific structure of the memristive associative memory neural network circuit is described in detail below with reference to fig. 6 and 7, where fig. 6 is a schematic diagram of a specific system structure of an embodiment of the memristive associative memory neural network circuit provided by the present invention, fig. 7 is a schematic diagram of a specific circuit structure of an embodiment of the memristive associative memory neural network circuit provided by the present invention, and a specific structure of the memristive associative memory neural network circuit is as follows:

as shown in fig. 6, the unconditional stimulus signal and the conditional stimulus signal are converted by the logic conversion circuit to generate the control signal of the voltage selection output circuit. And different control signals connect and output different voltage combinations at the input end of the voltage selection output circuit. And controlling the circuit units in the 4T1M memristor crossbar array to work in different states to realize an associative memory function or an associated information output function. Moreover, the timing voltage output circuit outputs a corresponding voltage combination after a certain time according to a set forgetting rate along with time, and controls the circuit units in the 4T1M cross array to realize forgetting and updating of associated data;

it should be noted that fig. 7 proposes a novel 4T1M memristive crossbar array structure as a synaptic circuit, which can flexibly control each 4T1M unit to implement a corresponding function. All circuit units in the memristor cross array are applied, and the storage density of information is improved. The memristor associative memory neural network circuit realizes storage of associated information and extraction of the associated information by performing logic transformation on unconditional stimulation signals and conditional stimulation signals and combining the characteristic of flexibility and controllability of a 4T1M synaptic circuit. The memristor association memory neural network circuit realizes a forgetting function along with time through the timing voltage output circuit, and can randomly adjust the forgetting rate. The neurons of the memristive associative memory neural network output corresponding analog voltages which represent the amount of related information.

The embodiment of the present invention provides a control method of a memristive associative memory neural network circuit, and with reference to fig. 8, fig. 8 is a schematic flowchart of an embodiment of the control method of the memristive associative memory neural network circuit provided by the present invention, and the memristive associative memory neural network circuit based on the memristors includes steps S801 to S803, where:

in step S801, the logic output circuit performs logic conversion on the received unconditional stimulus signal and/or conditional stimulus signal to generate a control voltage;

in step S802, by using a synapse circuit, under the trigger of the control voltage, adjusting a resistance value of a memristor in a memristor crossbar array, so as to implement an associative memory function and/or an associative output function;

in step S803, an analog voltage signal representing the correlation information is output by the neuron circuit according to the adjusted memristor resistance in the memristor crossbar array.

In the embodiment of the invention, firstly, corresponding logic judgment is carried out on the unconditional stimulation signal and the conditional stimulation signal, and corresponding control voltage is formed by using the result of the logic judgment; then, after different control voltages form different voltage combinations, a memristor cross array in a synaptic circuit is triggered, the resistance value change of the memristor is adjusted, and therefore the storage of the associated information and the extraction of the associated information are achieved by combining the flexible and controllable characteristics of the synaptic circuit; finally, the analog voltage signal is output to represent the size of the data volume, represent different information and effectively indicate the change of the associated information.

As a preferred embodiment, the control voltage includes a first control voltage signal output by a first analog switch and a second control voltage signal output by a second analog switch, and the step S802 specifically includes:

when the unconditional stimulus signal and the conditional stimulus signal are both at a low level, or the unconditional stimulus signal is at a high level and the conditional stimulus signal is at a low level, the logic conversion circuit is used for carrying out logic judgment, the result of the logic judgment is input to the voltage selection output circuit, the first control voltage signal and the second control voltage signal form a third voltage combination and a fourth voltage combination, and neither the third voltage combination nor the fourth voltage combination triggers the synapse circuit to realize an associative memory function or an associative output function.

In the embodiment of the invention, the signal output of different voltage combinations is realized through the logic conversion circuit and the voltage selection output circuit, and different triggers to the synapse circuit are realized.

In a specific embodiment of the present invention, as seen in fig. 2, the unconditional stimulus signal is represented by US, the conditional stimulus signal is represented by CS, the logic conversion circuit is composed of a not gate U1 and an or gate U2, CS is connected to an input terminal of the not gate U1, an output terminal of the not gate U1 is connected to a second input terminal of the or gate U2, and US is connected to a second input terminal of the or gate U2, wherein:

when the unconditional stimulation signal and the conditional stimulation signal are both in low level or the unconditional stimulation signal is in high level and the conditional stimulation signal is in low level, the memristive associative memory neural network circuit does not generate any output for the two input combination states. The two states have no specific functional meaning for the memristive associative memory neural network circuit;

when the unconditional stimulus and the conditional stimulus signals are high level at the same time, the memristive associative memory neural network circuit enters an associative learning stage;

when the unconditional stimulus is a low level and the conditional stimulus is a high level, the memristor associative memory neural network circuit outputs corresponding associated information;

the voltage selection output circuit is composed of a first analog switch S1 and a second analog switch S2. The output of the NOT gate in the logic conversion circuit is connected to the control terminal sc2 of the second analog switch S2, and the output of the OR gate in the logic conversion circuit is connected to the control terminal sc1 of the first analog switch S1. The first input terminal of the first analog switch S1 is connected to a voltage of 1V, and the second input terminal of the first analog switch S1 is connected to a voltage of 0.4V. A first input terminal of the second analog switch S2 is connected to a voltage of 0.5V, and a second input terminal of the second analog switch S2 is connected to a voltage of-2V. If the control terminal sc1 of the first analog switch S1 is high, the output voltage of the first analog switch S1 is 1V. If the control terminal sc1 of the first analog switch S1 is at a low level, the output voltage of the first analog switch S1 is 0.4V. If the control terminal sc2 of the second analog switch S2 is high, the output voltage of the second analog switch S2 is 0.5V. If the control terminal sc2 of the second analog switch S2 is at a low level, the output voltage of the second analog switch S2 is-2V. Accordingly, to implement the functionality described above. The relationship between the inputs and outputs of the logic conversion circuit and the voltage selection output is shown in table 1 below:

TABLE 1

In table 1, US and CS have different logic combinations, sc1 represents the output of the or gate in the logic conversion circuit, and sc2 represents the output of the not gate in the logic conversion circuit. Vim represents the output of the first analog switch S1 and Vc represents the output of the second analog switch S2. The voltage selection output circuit outputs different voltage combinations and is connected to the 4T1M memristor crossover array to complete corresponding functions.

As a preferred embodiment, the step S803 specifically includes:

when the synapse circuit receives the second voltage combination, the first MOS tube and the fourth MOS tube are conducted, the second MOS tube and the third MOS tube are disconnected, and when the first control voltage signal is smaller than the threshold voltage of the memristor, the resistance value of the memristor is kept unchanged, and the correlation output function is realized;

when the synapse circuit receives the third voltage combination or the fourth voltage combination, the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are all disconnected.

In the embodiment of the invention, the 4T1M memristive crossbar array is triggered by different circuit combinations to realize different functions.

In a specific embodiment of the present invention, in conjunction with fig. 3, a 4T1M memristive crossbar array is shown in fig. 3, which is a 4 × 4 memristive crossbar array, each circuit unit in the array is of the same structure, and the circuit units are connected to corresponding row signal lines and column signal lines. The working principle of the 4T1M memristive crossbar array is described below by taking the circuit cell M11 as an example:

wherein, circuit unit M11 includes: the transistor comprises a first MOS transistor T1, a second MOS transistor T2, a third MOS transistor T3, a fourth MOS transistor T4 and a memristor Rm 1. One end of the first MOS transistor T1 is connected to the row signal line H1 for receiving an input signal. The other end of the first MOS transistor T1 is connected to the anode of the memristor Rm 1; one end of the second MOS transistor T2 is connected to one end of the first MOS transistor T1, i.e., the row signal line H1, and receives an input signal. The other end of the second MOS transistor T2 is connected to the negative electrode of the memristor Rm 1. One end of the third MOS transistor T3 is connected to the positive electrode of the memristor Rm1, and the other end of the third MOS transistor T3 is connected to the column signal line L1; one end of the fourth MOS transistor T4 is connected to the cathode of the memristor Rm1, and the other end of the fourth MOS transistor T4 is connected to the column signal line L1; the gates of the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3 and the fourth MOS transistor T4 are connected together and controlled by a control signal Vc 11. In the circuit unit M11, the first MOS transistor T1 and the fourth MOS transistor T4 are P-type MOS transistors, and the second MOS transistor T2 and the third MOS transistor T3 are N-type MOS transistors. In the memristive associative memory neural network circuit, the threshold voltage of a P-type MOS tube is set to be-0.6V, and the threshold voltage of an N-type MOS tube is set to be 0.6V. And the corresponding memristors are voltage-controlled memristors, and the corresponding negative and positive threshold voltages are set to-0.5V and 0.5V. Here, the AIST model is taken as an example to describe a designed circuit, but the circuit design is not limited to the AIST model, and other voltage-controlled threshold memristor models are also applicable to the memristor associative memory neural network circuit. The AIST memristor model is described as follows:

i_off，i_on，i₀is a constant, D is the length of the memristor, u_vIs the average ion mobility, R, in the memristor_OFFAnd R_ONRespectively representing maximum and minimum memristances, x (t) representing the length of the doped region, V_T+，V_T-Respectively representing positive and negative threshold voltages, f (x (t)) is a window function;

for the 4T1M circuit unit M11, if the voltage combination output by the voltage selection output circuit is Vim1 with voltage 1V and Vc11 with voltage 0.5V, the voltage connected between the first MOS transistor T1 and one end of the second MOS transistor T2 is 1V. Accordingly, the voltage between the gate and the source of the first and second MOS transistors T1 and T2 is-0.5V. Since the first MOS transistor T1 is a P-type MOS transistor, the gate-source voltage of-0.5V is greater than the threshold voltage of the first MOS transistor T1, so that the first MOS transistor T1 is turned off. Since the second MOS transistor T2 is an N-type MOS transistor, the gate-source voltage of-0.5V is less than the threshold voltage of the second MOS transistor T2, so the second MOS transistor T2 is turned off. The voltage on column line L1 is 0V due to the virtual short effect of the operational amplifier. Therefore, the voltages between the gates and the sources of the third MOS transistor T3 and the fourth MOS transistor T4 are 0.5V. Since the third MOS transistor T3 is an N-type MOS transistor, the gate-source voltage of 0.5V is less than the threshold voltage of the third MOS transistor T3, so the third MOS transistor T3 is turned off. Since the fourth MOS transistor T4 is a P-type MOS transistor, the gate-source voltage of 0.5V is greater than the threshold voltage of the fourth MOS transistor T4, so the fourth MOS transistor T4 is turned off. Therefore, in this state, the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4 are all in the off state, so that the circuit unit M11 is disconnected from other circuits, and the operation of other circuits is not affected.

For the 4T1M circuit unit M11, if the voltage combination output by the voltage selection output circuit is Vim1 with voltage 1V and Vc11 with voltage-2V, the voltage connected between the first MOS transistor T1 and one end of the second MOS transistor T2 is 1V. Accordingly, the voltages between the gates and the sources of the first and second MOS transistors T1 and T2 are-3V. Since the first MOS transistor T1 is a P-type MOS transistor, the gate-source voltage of-3V is less than the threshold voltage of the first MOS transistor T1, so the first MOS transistor T1 is turned on. Since the second MOS transistor T2 is an N-type MOS transistor, the gate-source voltage of-3V is less than the threshold voltage of the second MOS transistor T2, so the second MOS transistor T2 is turned off. The voltage on column line L1 is 0V due to the virtual short effect of the operational amplifier. Therefore, the voltages between the gates and the sources of the third and fourth MOS transistors T3 and T4 are-2V. Since the third MOS transistor T3 is an N-type MOS transistor, the gate-source voltage of-2V is lower than the threshold voltage of the third MOS transistor T3, so that the third MOS transistor T3 is turned off. Since the fourth MOS transistor T4 is a P-type MOS transistor, the gate-source voltage of-2V is less than the threshold voltage of the fourth MOS transistor T4, so the fourth MOS transistor T4 is turned on. Therefore, in this state, a current flows from Vim1 to the column line L1 through the first MOS transistor T1 and the fourth MOS transistor T4, forming a current path. Since the voltage of Vim1 is greater than the memristor's threshold voltage, the memristor's resistance continues to decrease in this state.

For the 4T1M circuit unit M11, if the combination of the voltages output by the voltage selection output circuit is Vim1 with a voltage of 0.4V and Vc11 with a voltage of-2V, the voltage connected between the first MOS transistor T1 and one end of the second MOS transistor T2 is 0.4V. Accordingly, the voltage between the gate and the source of the first and second MOS transistors T1 and T2 is-2.4V. Since the first MOS transistor T1 is a P-type MOS transistor, the gate-source voltage of-2.4V is less than the threshold voltage of the first MOS transistor T1, so the first MOS transistor T1 is turned on. Since the second MOS transistor T2 is an N-type MOS transistor, the gate-source voltage of-2.4V is less than the threshold voltage of the second MOS transistor T2, so the second MOS transistor T2 is turned off. The voltage on column line L1 is 0V due to the virtual short effect of the operational amplifier. Therefore, the voltages between the gates and the sources of the third and fourth MOS transistors T3 and T4 are-2V. Since the third MOS transistor T3 is an N-type MOS transistor, the gate-source voltage of-2V is less than the threshold voltage of the third MOS transistor T3, so the third MOS transistor T3 is turned off. Since the fourth MOS transistor T4 is a P-type MOS transistor, the gate-source voltage of-2V is less than the threshold voltage of the fourth MOS transistor T4, so the fourth MOS transistor T4 is turned on. Therefore, in this state, a current flows from Vim1 to the column line L1 through the first MOS transistor T1 and the fourth MOS transistor T4, forming a current path. Since the voltage of Vim1 is less than the memristor's threshold voltage, the memristor's resistance remains unchanged in this state. In this state, the memristor resistance remains unchanged, but has a corresponding current path, so that relevant information stored in the synaptic circuit can be output to the corresponding neuron circuit.

It should be noted that, as can be seen from the above description, due to the flexible and controllable circuit cells in the 4T1M memristive crossbar array, disconnection of the circuit cells, change of memristances of the circuit cells, and output of corresponding associated information can be achieved through corresponding voltages. The 4T1M cells in the memristive crossbar array have the same structure, so their control circuits and modes are the same.

As a preferred embodiment, the step S803 further includes:

determining synaptic weight according to the ratio of the neuron resistance to the regulated memristor resistance;

In the embodiment of the invention, the output of the analog voltage signal is effectively carried out by using the neuron resistor and the operational amplifier.

In a specific embodiment of the present invention, as seen in fig. 4, all the neuron circuits are identical in structure, and each neuron circuit includes an operational amplifier and a resistor. The non-inverting terminal of the operational amplifier is grounded, the column line of the 4T1M memristor crossbar array is connected to the inverting terminal of the operational amplifier, one end of the resistor is also connected to the inverting terminal of the operational amplifier, and the other end of the resistor is connected to the output terminal of the operational amplifier to form a feedback structure. Assuming that only the circuit cell M11 in the 4T1M memristive crossbar array has a current path, connected to the corresponding column signal line L1, and the corresponding input voltage Vim1 is 0.4V, the corresponding neuron-circuit output voltage Vo1 can be expressed as:

according to the above equation, the corresponding synaptic weight w11 can be expressed as:

according to the formula, the smaller the resistance value of the memristor is, the larger the value of the synaptic weight is; therefore, when the input voltage Vim1 is 0.4V, the magnitude of the related information can be represented by an analog voltage signal output from the neuron circuit.

As a preferred embodiment, the step S803 further includes:

when the unconditional stimulation signal and the conditional stimulation signal are both in low level, or the unconditional stimulation signal is in high level and the conditional stimulation signal is in low level, if the timing voltage output circuit is timed to preset time, the corresponding control voltage combination is connected to the synapse circuit, and the forgetting function along with time is realized.

In the embodiment of the invention, the timing voltage output circuit is used for controlling the time of accessing the corresponding voltage combination into the memristor cross array, and the corresponding forgetting rate is changed.

In an embodiment of the invention, referring to fig. 5, a structural diagram of the clocked voltage output circuit is shown in fig. 5, which includes a binary counter, a monostable flip-flop, a second not gate U3, an and gate U4, a third analog switch S3, and a fourth analog switch S4. The function of the timing voltage output circuit is to realize the forgetting process of the memristor association memory neural network circuit along with time. For the patent of the invention, the forgetting process is that after the timing circuit times to a set time, the corresponding voltage combination is controlled to be connected into the memristor cross array, the resistance value of the corresponding memristor is increased, and the corresponding synapse weight is reduced. The increasing amount of the resistance value of the memristor is determined by the time when the corresponding voltage combination is accessed to the memristor cross array, so that the corresponding forgetting rate can be changed by controlling the time when the corresponding voltage combination is accessed to the memristor cross array;

the output end of the binary counter is connected to the input end of the monostable trigger, and when the counter reaches a preset counting value, the monostable trigger is triggered. The condition stimulus CS11 is connected to the input terminal of a second NOT gate U3, the output terminal of the second NOT gate U3 is connected to the first input terminal of an AND gate U4, the output terminal of a monostable trigger is connected to the second input terminal of an AND gate U4, the output terminal of an AND gate U4 is connected to the control terminal of a third switch S3, and the output terminal of an AND gate U4 is also connected to the control terminal of a fourth switch S4;

the first input end of the third analog switch S3 is connected with 1V voltage, the second input end of the third analog switch S3 is set to be in a high-impedance state, and the output end of the third analog switch S3 is connected with the row signal line of the 4T1M memristive crossbar array. A first input end of the fourth analog switch S4 is connected with 2V voltage, a second input end of the fourth analog switch S4 is set to be in a high-resistance state, and an output end of the fourth analog switch S4 is connected with control ends of four MOS (metal oxide semiconductor) tubes of a circuit unit in the 4T1M memristor crossbar array;

the condition stimulus CS11 is connected to the input terminal of the second NOT gate U3, and the output terminal of the second NOT gate U3 is connected to the first input terminal of the AND gate U4. If the conditional stimulus CS11 is high, the second not gate U3 outputs a low level, at which time the and gate U4 is locked. The output of the monostable flip-flop is connected to the second input of the and gate U4, and the and gate U4 always outputs a low level regardless of whether the second input of the and gate U4 is high or low. If the conditional stimulus CS11 is low, the second not gate U3 outputs a high level, at which time the and gate U4 is opened. The output of the and gate U4 follows the level change of the second input terminal.

When the condition stimulus CS11 is at a low level, if the binary counter reaches a corresponding timing time, the monostable trigger circuit is triggered, and the monostable trigger circuit outputs a pulse. The high level duration of the pulse can be realized by adjusting the parameters of the resistor and the capacitor in the monostable trigger circuit. The and gate U4 outputs a pulse, and when the pulse is at a high level, the output voltage Vim1 of the third analog switch S3 is 1V, and the output voltage Vc11 of the fourth analog switch S4 is 2V;

when the voltage combination is connected to the circuit unit M11, the voltage connected to one end of the first MOS transistor T1 and the second MOS transistor T2 is 1V. Accordingly, the voltage between the gate and the source of the first MOS transistor T1 and the second MOS transistor T2 is 1V. Since the first MOS transistor T1 is a P-type MOS transistor, the gate-source voltage of 1V is greater than the threshold voltage of the first MOS transistor T1, so the first MOS transistor T1 is turned off. Since the second MOS transistor T2 is an N-type MOS transistor, the gate-source voltage of 1V is greater than the threshold voltage of the second MOS transistor T2, so that the second MOS transistor T2 is turned on. The voltage on column line L1 is 0V due to the virtual short effect of the operational amplifier. Therefore, the voltages between the gates and the sources of the third MOS transistor T3 and the fourth MOS transistor T4 are 2V. Since the third MOS transistor T3 is an N-type MOS transistor, the gate-source voltage of 2V is greater than the threshold voltage of the third MOS transistor T3, so that the third MOS transistor T3 is turned on. Since the fourth MOS transistor T4 is a P-type MOS transistor, the gate-source voltage of 2V is greater than the threshold voltage of the fourth MOS transistor T4, so the fourth MOS transistor T4 is turned off. Therefore, in this state, a current flows from Vim1 to the column line L1 through the second MOS transistor T2 and the third MOS transistor T3, forming a current path. Since the voltage of Vim1 is greater than the memristor's threshold voltage, the memristor's resistance increases in this state, indicating that the synaptic weight is decreasing. The increment of the memristor resistance value can be changed by adjusting the parameters of the monostable trigger circuit and adjusting the time of the voltage combination accessing the memristor cross array, so that the forgetting rate along with the time is changed. After the output of the monostable flip-flop circuit becomes low, the output voltage of the third analog switch S3 and the output voltage of the fourth analog switch S4 become high impedance state, and the operation of the circuit unit M11 is not affected.

The technical solution of the present invention is more clearly illustrated below with reference to a specific application scenario, and the 4 × 4T1M cross array given in the above embodiment outputs the corresponding correlation information of the fruit, and the specific application principle is as follows:

in the memristive associative memory neural network circuit, the unconditional stimulation signal US represents the corresponding parameter information of the fruit: freshness, mouthfeel, texture, edible date. The conditional stimulus signal CS represents 'visually recognized fruit' or 'picture of fruit name recognized'; the input of the conditional stimulation can be realized through a corresponding pre-neural network;

in the embodiment, the 4T1M memristive crossbar array of 4 x 4 comprises four circuit units in each row, which respectively represent four characteristics of freshness, taste, texture and edible date of a fruit. For example, four circuit units in the first row in the memristive crossbar array respectively represent four characteristics of freshness, taste, texture and edible date of apples. The second row, the third row and the fourth row in the memristive cross array respectively represent four characteristics of pears, grapes and oranges. For each circuit unit in the 4T1M memristive crossbar array of 4 × 4 in the embodiment, a corresponding logic conversion circuit, a voltage selection output circuit and a timing output circuit are provided;

when the corresponding unconditional stimulation signal and the conditional stimulation signal are simultaneously in a high level, the corresponding circuit unit enters an associative memory stage. The resistance of the memristor in the circuit unit is reduced, and the synaptic weight is increased. The association between 'visually recognized fruit' or 'picture of recognized fruit name' and freshness, taste, texture, edible date of the fruit is established through associative memory. And storing the freshness, taste, texture and edible date information of the fruits into a memristor association memory neural network. Because each circuit unit has a separate control circuit, each circuit unit can individually perform associative memory to store corresponding association information. All circuit units in the 4T1M memristive crossbar array of 4 x 4 can store corresponding associated information at the same time;

after the associated information is stored in the memristive associative memory neural network circuit through associative learning, if the unconditional stimulus signal is at a low level and the conditional stimulus signal is at a high level, the corresponding circuit unit outputs the associated information. When the associated information is output, according to the sequence of identifying the fruit visually or identifying the picture of the fruit name, the associated information of the fruit which is identified firstly is output, and then the associated information of the second fruit is output. Four characteristics of freshness, taste, texture and edible date of a fruit are stored in corresponding synaptic circuits, and when the fruit is identified, a voltage of 0.4V is input into a 4T1M memristor crossbar array. Since each characteristic of four fruits is quantized in a different memristor resistance variation range, the corresponding Am1, Am2, Am3 and Am4 neuron circuits output analog voltages in the corresponding ranges, and the associated information of the corresponding characteristics of the fruits is represented. For example, the freshness characteristic of an apple is quantized to a memristance within 20k Ω -35k Ω, the freshness characteristic of a pear is quantized to a memristance within 35k Ω -50k Ω, the freshness characteristic of a grape is quantized to a memristance within 50k Ω -65k Ω, and the freshness characteristic of an orange is quantized to a memristance within 65k Ω -80k Ω. Thus, when the corresponding fruit is identified, the Am1 neuron will output a voltage within the corresponding range, indicating the corresponding correlation signature. Similarly, the mouthfeel, texture and edible date can also represent corresponding related information through analog voltages output by Am2, Am3 and Am4 neuron circuits. Meanwhile, each characteristic can be further adjusted to be in a different voltage range by adjusting the resistances R1, R2, R3 and R4 in the neural circuits of Am1, Am2, Am3 and Am 4;

when the timing voltage output circuit reaches the preset time, the memristor associative memory neural network enters a forgetting stage along with the time. Because each circuit unit in the 4T1M memristive crossbar array is provided with an independent control circuit, the changes of freshness, taste, texture and edible date of the fruits along with the time can be reflected in a targeted and detailed manner according to the different characteristics of the four characteristics of each fruit along with the time. When the timing voltage output circuit reaches the set timing time, the corresponding voltage combination is connected to the 4T1M cross array, and the duration of the control signal of each circuit unit can be adjusted, so that the increase amount of the resistance value of the memristor, namely the reduction amount of the synaptic weight, is changed, and different forgetting rates over time are obtained.

The invention discloses a memristor associative memory neural network circuit and a control method thereof, wherein in the memristor associative memory neural network circuit, a logic output circuit is arranged to perform corresponding logic conversion on a non-conditional stimulus signal and a conditional stimulus signal to form a control voltage for triggering a synaptic circuit; through setting a synaptic circuit, the resistance value of a memristor in the synaptic circuit is adjusted under the action of different control voltages by utilizing the memristor cross array, so that association of associative memory information is realized, or the memorized association information is output; corresponding associated information is output by the neuron circuit, and the associated information is represented by analog voltage signals output by the neurons. In the related control method, firstly, corresponding logic judgment is carried out on the unconditional stimulation signal and the conditional stimulation signal, and corresponding control voltage is formed by using the result of the logic judgment; then, after different control voltages form different circuit combinations, a memristor cross array in a synaptic circuit is triggered to change, and the resistance value change of the memristor is adjusted, so that the association of data and the extraction of associated information are realized by combining the flexible and controllable characteristics of the synaptic circuit; finally, the analog voltage signal is output to represent the size of the data volume, represent different information and effectively indicate the change of the associated information.

The technical scheme of the invention provides a novel 4T1M cross array and a corresponding voltage combination strategy which can be applied to a memristive associative memory neural network. Furthermore, in order to realize the connection between the unconditional stimulation signals, the conditional stimulation signals and the voltage combination strategy, a logic conversion circuit and a voltage selection output circuit are designed. Moreover, a timing voltage output circuit is designed to realize a forgetting process along with time, and the forgetting rate can be flexibly adjusted through the circuit design. In conclusion, the technical scheme of the invention not only uses the memristor cross array as a carrier, but also increases the integration level of the circuit and the density of memory information storage. The analog signals output by the neurons are also used for expressing different information and indicating the change of the associated information, thereby having good effect. It should be further explained that, according to the voice recognition and picture processing results of the pre-neural network, the memristive neural network circuit is used to obtain corresponding associated information, a human-computer interaction system for extracting fruit associated information can be constructed, and the human-computer interaction system is used in the field of intelligent robots to improve the service experience of the intelligent robots.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Claims

1. A memristive associative memory neural network circuit, comprising a logic output circuit, a synaptic circuit, and a neuron circuit electrically connected in sequence, the synaptic circuit comprising a memristor crossbar array, wherein:

the logic output circuit generates a control voltage after receiving the unconditional stimulation signal and/or the conditional stimulation signal; the synaptic circuit is triggered by the control voltage to adjust the resistance value of the memristor in the memristor cross array, so that an associative memory function and/or an associative output function are realized; and the neuron circuit outputs an analog voltage signal for representing correlation information according to the regulated memristor resistance value in the memristor cross array.

2. The memristive associative memory neural network circuit according to claim 1, wherein the logic output circuit comprises a logic transformation circuit and a voltage selection output circuit which are electrically connected in sequence, wherein:

3. The memristive associative memory neural network circuit according to claim 2, wherein the voltage selection output circuit comprises a first analog switch and a second analog switch, the output end of the or gate is electrically connected to the control end of the first analog switch, and the first input end of the first analog switch is connected to a first voltage and the second input end of the first analog switch is connected to a second voltage; the output end of the NOT gate is electrically connected to the control end of the second analog switch, and the first input end of the second analog switch is connected to a third voltage and the second input end of the second analog switch is connected to a fourth voltage.

4. The memristive associative memory neural network circuit of claim 1, wherein the memristor crossbar array in the synapse circuit comprises M row signal lines, N column signal lines, the row and column signal lines crossing each other but not directly connected, wherein each row signal line and each column signal line are connected together at a cross-point by a circuit unit comprising memristors.

5. The memristive associative memory neural network circuit according to claim 4, wherein the control voltage comprises a first control voltage signal output by a first analog switch and a second control voltage signal output by a second analog switch, the circuit unit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a memristor, wherein:

6. The memristive associative memory neural network circuit of claim 1, wherein the neuron circuit is electrically connected to a column signal line in the synapse circuit, the neuron circuit comprising an operational amplifier and a neuron resistance, wherein:

7. The memristive associative memory neural network circuit of claim 1, further comprising a clocked voltage output circuit electrically connected to the synapse circuit, the clocked voltage output circuit comprising a source of clock pulses, a binary counter, a monostable flip-flop, a second not gate, an and gate, a third analog switch, a fourth analog switch, wherein:

the conditional stimulus signal is connected to the input end of a second NOT gate, and the output end of the second NOT gate is connected to the first input end of the AND gate; the monostable trigger is connected to a second input end of the AND gate; the AND gate is electrically connected to the control end of the third analog switch and the control end of the fourth analog switch respectively;

8. A control method of a memristive associative memory neural network circuit, the control method being based on the memristive associative memory neural network circuit according to any one of claims 1 to 7, and the control method comprising:

carrying out logic conversion on the received unconditional stimulation signals and/or conditional stimulation signals through a logic output circuit to generate control voltage;

9. The method for controlling a memristive associative memory neural network circuit according to claim 8, wherein the control voltage comprises a first control voltage signal output by a first analog switch and a second control voltage signal output by a second analog switch, and the logic output circuit logically converts the received unconditional stimulus signal and/or the conditional stimulus signal to generate the control voltage, comprising:

when the unconditional stimulation signal and the conditional stimulation signal are both high level, carrying out logic judgment through a logic conversion circuit, inputting a logic judgment result to a voltage selection output circuit, wherein a first control voltage signal output by a first analog switch and a second control voltage signal output by a second analog switch in the voltage selection output circuit form a first voltage combination, and the first voltage combination is used for triggering the synapse circuit to realize an associative memory function and complete the storage of associated information;

10. The method for controlling the memristive associative memory neural network circuit according to claim 9, wherein the adjusting the memristor resistance values in the memristor crossbar array under the triggering of the control voltage through the synaptic circuit to realize the associative memory function and/or the associative output function comprises:

11. The control method of the memristive associative memory neural network circuit of any one of claims 7 to 10, further comprising:

when the unconditional stimulation signal and the conditional stimulation signal are both at a high level, or the unconditional stimulation signal is at a low level and the conditional stimulation signal is at a high level, a third analog switch and a fourth analog switch in the timing voltage output circuit output a high-resistance state;

when the synapse circuit receives the fifth voltage combination, the second MOS tube and the third MOS tube in the circuit unit of the synapse circuit are conducted, the first MOS tube and the fourth MOS tube in the circuit unit of the synapse circuit are disconnected, and when a third control voltage signal is larger than the threshold voltage of the memristor, the resistance value of the memristor is continuously increased, so that a function of forgetting associated information along with time is realized.