CN116436440B - SOI stacked transistor voltage swing balancing circuit and power amplifier - Google Patents

SOI stacked transistor voltage swing balancing circuit and power amplifier Download PDF

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CN116436440B
CN116436440B CN202310425470.1A CN202310425470A CN116436440B CN 116436440 B CN116436440 B CN 116436440B CN 202310425470 A CN202310425470 A CN 202310425470A CN 116436440 B CN116436440 B CN 116436440B
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transistor
capacitor
circuit
input
resistor
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CN116436440A (en
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张志浩
龙俊明
章国豪
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Guangdong University of Technology
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Guangdong University of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/32—Balance-unbalance networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention discloses an SOI stacked transistor voltage swing balance circuit and a power amplifier, which comprise an input matching network, an input balun circuit, a core differential amplifying circuit, an output matching network and an input balun circuit, wherein the output end of the input matching network is connected with the input end of the core differential amplifying circuit, the output end of the core differential amplifying circuit is connected with the output matching network and the input end of the input balun circuit, the input end of the input matching network and the input balun circuit receives radio frequency signals, and the output end of the output matching network and the input balun circuit is connected with load impedance. By using the invention, the correction of voltage stress and phase can be realized by utilizing differential waveform symmetry, thereby improving power output and efficiency. The invention is used as a voltage swing balance circuit and a power amplifier of an SOI stacked transistor, and can be widely applied to the technical field of power amplification of transistor stacking.

Description

SOI stacked transistor voltage swing balancing circuit and power amplifier
Technical Field
The invention relates to the technical field of power amplification of transistor stacking, in particular to an SOI stacked transistor voltage swing balancing circuit and a power amplifier.
Background
According to the international standards organization 3GPP standard, the 5G frequency band is divided into two ranges, FR1 (Sub-6 GHz) and FR2 (millimeter wave). The millimeter wave frequency band provides a faster and wider physical transmission channel, the transmission performance is obviously superior to that of Sub-6GHz, meanwhile, the frequency spectrum resources of the Sub-6GHz frequency band are tense, the problem of frequency spectrum crowding must be fundamentally solved, the frequency spectrum crowding must be expanded from the physical channel, the frequency band extends towards the millimeter wave direction with higher frequency band, the full potential of 5G communication is released, a Power Amplifier (PA) is one of key units in a wireless communication link, the function of the PA is to amplify a modulation signal carrying useful information to a certain power and radiate the modulation signal through an antenna, and the output capacity, linearity and efficiency of a transmitter are determined by a power amplifier to a great extent. In the face of 5G millimeter wave communication, a power amplifier is required to have higher power, higher efficiency, better linearity, larger bandwidth, high reliability and lower cost, the power amplifier needs to output high enough power to meet the communication requirement and the enough signal coverage, however, for a CMOS device, the output power is limited due to low current capacity and small withstand voltage, so that the power boosting method must be considered when the CMOS device is used for realizing the radio frequency front end, the transistor stacking technology is a compact and efficient power boosting method, the maximum voltage bearable at two ends of a drain source of a single transistor is lower due to the characteristics of the CMOS device, therefore, if only a single transistor is adopted as a power unit, the maximum output power is limited by the voltage swing capability, and due to the limitation of the process, breakdown voltage is limited between a gate-substrate, a gate-source and a gate-drain, so that the gate source and the gate drain of the top transistor are subjected to high voltage pressure, and the breakdown voltage is further caused, and the reliability of the gate source and the drain has great influence on the working reliability of a circuit is generated.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide an SOI stacked transistor voltage swing balancing circuit and a power amplifier, which can improve power output and efficiency by using differential waveform symmetry to implement voltage stress and phase correction.
The first technical scheme adopted by the invention is as follows: the SOI stacked transistor voltage swing balance circuit comprises an input matching network, an input balun circuit, a core differential amplifying circuit, an output matching network and an input balun circuit, wherein the output end of the input matching network is connected with the input end of the core differential amplifying circuit, the output end of the core differential amplifying circuit is connected with the output matching network and the input end of the input balun circuit, the input matching network receives radio frequency signals from the input end of the input balun circuit, and the output end of the output matching network is connected with load impedance:
the input matching network and the input balun circuit comprise an input matching circuit, a first transformer circuit and an RC bias network circuit;
the input matching circuit is used for receiving radio frequency signals;
the first transformer circuit converts a single-ended signal output by the input matching circuit into a differential signal and couples the differential signal to the input end of the core differential amplifying circuit;
the RC bias network circuit provides bias voltage for the bottom transistor in the core differential amplifying circuit to work;
the core differential amplifying circuit comprises a first four-transistor stacking unit, a first capacitor series circuit, a second four-transistor stacking unit and a second capacitor series circuit;
the first four-transistor stacking unit and the second four-transistor stacking unit are used for improving the voltage swing of the transistor and enhancing the power output capability of the transistor;
the first capacitor series circuit and the second capacitor series circuit are used for adjusting the phase difference between the first four-transistor stacking unit and the second four-transistor stacking unit and reducing the voltage pressure of the transistor grid electrode;
the output matching network and the input balun circuit comprise an output matching network circuit and a second transformer circuit;
the second transformer circuit is used for receiving the output signal of the core differential amplifying circuit and converting the output signal into a single-ended signal;
the output matching network circuit is used for receiving the single-ended signal output by the second transformer circuit and transmitting the single-ended signal to the load impedance.
Further, the input matching network and the input balun circuit comprise a transformer TF1, a capacitor C1 and a resistor R1, wherein the transformer TF1 is a first transformer circuit, and the capacitor C1 and the resistor R1 form an RC bias network circuit.
Further, in the input matching network and the input balun circuit, the input end of the transformer TF1 is connected to the output end of the input matching circuit, the output end of the transformer TF1 is connected to the first end of the capacitor C1 and the first end of the resistor R1, the second end of the capacitor C1 is grounded, and the second end of the resistor R1 is connected to the V Bias1 。
Further, the core differential amplifying circuit includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and a resistor R7, wherein the transistor M1, the transistor M2, the transistor M3, the transistor M4, the capacitor C2, the capacitor C3, the capacitor C4 constitute a first transistor stack unit, the transistor M5, the transistor M6, the transistor M7, the transistor M8, the capacitor C5, the capacitor C6, the capacitor C7, the resistor R5, the resistor R6 and the resistor R7 constitute a second transistor stack unit, the capacitor C8, the capacitor C9 and the capacitor C10 constitute a capacitor C11, and a capacitor C13, and a series circuit.
Further, in the core differential amplifying circuit, the gate of the transistor M1 and the gate of the transistor M5 are respectively connected to the output terminal of the transformer TF1, the source of the transistor M1 and the source of the transistor M5 are respectively connected to the ground, the gate of the transistor M1 is connected to the first terminal of the capacitor C11, the drain of the transistor M1 is respectively connected to the source of the transistor M2, the gate of the transistor M2 is respectively connected to the second terminal of the capacitor C8, the first terminal of the capacitor C9, the second terminal of the capacitor C2 and the second terminal of the resistor R2, the drain of the transistor M2 is respectively connected to the second terminal of the capacitor C9, the first terminal of the capacitor C10, the second terminal of the capacitor C3 and the second terminal of the resistor R3, the gate of the transistor M4 is respectively connected to the second terminal of the capacitor C10, the second terminal of the capacitor C4 and the second terminal of the resistor C4, the drain of the transistor M6 is respectively connected to the first terminal of the capacitor C5, the drain of the transistor M6 is connected to the second terminal of the capacitor C5, the gate of the transistor M5 is respectively connected to the second terminal of the capacitor C5, the gate of the transistor M5 is connected to the second terminal of the capacitor C5, the gate of the transistor M4 is connected to the capacitor C3, the drain of the capacitor C4 is connected to the capacitor C3 is connected to the source of the capacitor C3, the capacitor is connected to the capacitor C3 is connected to the source of the capacitor C3, the capacitor is connected to the source of the capacitor is connected to the capacitor 3 is connected to the sourceA source electrode of the transistor M7 is connected with a second end of the capacitor C12, a first end of the capacitor C13, a first end of the capacitor C6 and a first end of the resistor R6 respectively, a drain electrode of the transistor M7 is connected with a source electrode of the transistor M8, a gate electrode of the transistor M8 is connected with a second end of the capacitor C13, a first end of the capacitor C7 and a first end of the resistor R7 respectively, a drain electrode of the transistor M8 is connected with an output matching network and an input end of a second transformer circuit in the input balun circuit, a first end of the capacitor C2, a first end of the capacitor C3, a first end of the capacitor C4, a second end of the capacitor C5, a second end of the capacitor C6 and a second end of the capacitor C7 are grounded, a first end of the resistor R2 and a second end of the resistor R5 are grounded Bias2 A first end of the resistor R3 and a second end of the resistor R6 are connected with V Bias3 A first end of the resistor R4 and a second end of the resistor R7 are connected with V Bias4 。
Further, the output matching network and the input balun circuit comprise a transformer TF2, wherein the transformer TF2 is a second transformer circuit.
Further, in the output matching network and the input balun circuit, the input end of the transformer TF2 is connected with the core differential amplifying circuit, the output end of the transformer TF2 is connected with the input end of the output matching network circuit, and the output end of the output matching network circuit is connected with the load impedance.
The second technical scheme adopted by the invention is as follows: a power amplifier comprising an SOI stacked transistor voltage swing balancing circuit as described above.
The circuit and the device have the beneficial effects that: the invention inputs signals from an input end through an input matching network and an input balun circuit, converts single-ended signals into double-ended differential signals through the input balun, inputs the double-ended differential signals into a core differential amplifying circuit for amplification by the differential amplifying circuit, two paths of the differential amplifying circuit work with a phase difference of 180 degrees, at the moment, two transistor stacking structures of the differential amplifying unit conduct and amplify in turn, current and voltage on stacked nodes can be regarded as symmetrical relation, the first differential structure is introduced to improve the power output capacity of the whole power amplifier, and the second differential structure utilizes the waveform symmetry of the differential to realize voltage stress and phase correction, and then inputs the voltage stress and the phase correction to the output matching network and the input balun circuit, obtains the swing amplitude of an output signal at an output balun TF2 and converts the swing amplitude of the output signal to a single-ended output signal to a load.
Drawings
FIG. 1 is a schematic diagram of a voltage swing balancing circuit for SOI stacked transistors according to the present invention;
fig. 2 is a schematic diagram of a conventional power amplifier structure of a transistor stack;
FIG. 3 is a schematic diagram of a conventional stacked transistor waveform phase difference;
FIG. 4 is a schematic diagram of the inter-transistor delay phase and capacitive charge current waveforms of the present invention;
fig. 5 is a schematic diagram of waveforms of a stacked cell of the present invention.
Detailed Description
The invention will now be described in further detail with reference to the drawings and to specific examples. The step numbers in the following embodiments are set for convenience of illustration only, and the order between the steps is not limited in any way, and the execution order of the steps in the embodiments may be adaptively adjusted according to the understanding of those skilled in the art.
As shown in fig. 2, due to the characteristics of the CMOS device, the maximum voltage swing bearable at both ends of the drain and source of a single transistor is low, so if only a single transistor is used as a power unit, the maximum output power will be limited by the voltage swing capability, the transistor stacking technology can overcome the voltage swing limitation of a single transistor, and N transistors can theoretically bear n×v M Wherein V is M Maximum voltage swing that can be tolerated by a single transistor;
however, due to process limitations, not only is the voltage limit present at the drain-source port, but there is also a breakdown voltage limit between the gate-substrate, gate-source, gate-drain of the transistor. When the number of stacked transistors increases, the top transistor gate will be biased at V D ＝(N-1)×V DS +V GS In the case of high power supply, V DS The grid of the top tube will be at a higher electrical levelThe voltage level is higher between the drain-substrate and the gate-drain, and in addition, when the power amplifier is in high power operation, the voltage swing is larger, and the source-drain voltage of the transistor is pulled down to a lower level (about NXV) knee ) The gate source and the gate drain of the top transistor are subjected to very high voltage, so that the gate source and the gate drain are broken down, and the reliability of the circuit is greatly influenced; in addition, as the working frequency increases, such as millimeter wave frequency band, the parasitic parameters of the transistor have great influence on the design of the circuit, parasitic capacitance exists between different ports of the transistor, and the gate-source capacitance C gs The phase difference of current-voltage waveforms among the stacked transistors can be caused, and when the phase difference is large to a certain extent, the voltage-current synthesis of the output end can be influenced, and finally the output power and the efficiency of the power amplifier are influenced;
the current transistor stack mainstream scheme is as follows:
(1) A transistor stack with a gate capacitance;
transistor stack technology initially biases the common gate transistor at a fixed voltage, however, this fixed bias is extremely prone to gate breakdown for the top transistor when subjected to high swings, as the number of transistor stacks increases, the power supply must also increase, the top transistor will be exposed to higher voltage stress, and this effect will therefore deteriorate as the number of transistor stacks increases, severely limiting the number of transistor stacks and their reliability. For this phenomenon, a gate capacitor is introduced into the common gate tube, so that the three ends of the gate, the source and the drain of the transistor can swing in the same swing trend, thus slowing down the voltage pressure between different ports to a certain extent, improving the reliability and also improving the limitation of the stacking quantity of the transistor to a certain extent. However, this approach reduces the voltage stress without addressing the effect of transistor parasitic capacitance, C gs The waveform phase difference is formed between different transistors, the symmetry of the stacked transistor structure is broken, the phase change caused by parasitic capacitance reduces the output drain-source voltage swing of the whole power amplifier, and the efficiency is reduced.
(2) Tuning a node;
due to C gs The leakage of parasitic capacitance and the phase difference are caused, so that a method is needed to compensate the leakage, wherein one compensation method is to compensate an LC series circuit, the LC series circuit is introduced at the junction of the stacked transistors, the equivalent capacitance value at the junction can be reduced or adjusted to a proper level, the swing phase difference between different transistors is in a proper range, the voltage swing synthesis of the output end is optimized, the efficiency and the output power are improved, however, the low-loss inductance is difficult to realize on the chip, so that the influence of the inductance on the power cannot be ignored, and in addition, the area of the inductance is huge, the chip area is greatly increased by introducing the compensation network, and the manufacturing cost is further improved.
To sum up, the stacked transistor technology must overcome the amplitude and phase balance of the voltage swing, however, the existing methods have some drawbacks in terms of performance, implementation difficulty and cost, so the swing balance of the transistor stack is important for improving the performance.
Referring to fig. 1, the invention provides an SOI stacked transistor voltage swing balancing circuit, which comprises an input matching network and an input balun circuit, a core differential amplifying circuit, an output matching network and an input balun circuit, wherein the output end of the input matching network and the input balun circuit is connected with the input end of the core differential amplifying circuit, the output end of the core differential amplifying circuit is connected with the output matching network and the input end of the input balun circuit, the input end of the input matching network and the input balun circuit receives radio frequency signals, and the output end of the output matching network and the input balun circuit is connected with load impedance:
the input matching network and the input balun circuit comprise an input matching circuit, a first transformer circuit and an RC bias network circuit; the input matching circuit is used for receiving radio frequency signals; the first transformer circuit converts a single-ended signal output by the input matching circuit into a differential signal and couples the differential signal to the input end of the core differential amplifying circuit; the RC bias network circuit provides bias voltage for the bottom transistor in the core differential amplifying circuit to work;
specifically, the input matching network and the input balun circuit comprise a transformer TF1, a capacitor C1 and a resistor R1, wherein the transformer TF1 is a first transformer circuit, the capacitor C1 and the resistor R1 form an RC bias network circuit, in the input matching network and the input balun circuit, an input end of the transformer TF1 is connected with an output end of the input matching circuit, an output end of the transformer TF1 is respectively connected with a first end of the capacitor C1 and a first end of the resistor R1, a second end of the capacitor C1 is grounded, and a second end of the resistor R1 is connected with V Bias1 ；
Further, the input matching circuit and the transformer TF1 are responsible for matching the input impedance of the amplifying circuit to a 50Ω input impedance terminal, so as to realize impedance matching;
the transformer TF1 is responsible for coupling the signal of the power input to the input of the differential power amplifier: firstly, converting a single-ended signal into a differential signal, and providing a differential input signal of an amplifier; secondly, a certain impedance transformation effect is realized, so that the use amount of passive devices input into a matching network can be reduced to a certain extent; the third is that the RC bias network can be connected through a center tap to provide bias voltages for the bottom transistors M1 and M5 of the two transistor stack units;
the capacitor C1 and the resistor R1 are bias circuit networks of the input end, the resistor R1 is a ballast resistor for receiving bias voltage, and a certain stability of the transistor can be provided; the capacitor C1 is a filter capacitor, and provides bias voltages for the bottom transistor M1 and the transistor M5 of the two transistor stack unit through a center tap connected to the transformer TF 1.
The core differential amplifying circuit comprises a first four-transistor stacking unit, a first capacitor series circuit, a second four-transistor stacking unit and a second capacitor series circuit; the first four-transistor stacking unit and the second four-transistor stacking unit are used for improving the voltage swing of the transistor and enhancing the power output capability of the transistor; the first capacitor series circuit and the second capacitor series circuit are used for adjusting the phase difference between the first four-transistor stacking unit and the second four-transistor stacking unit and reducing the voltage pressure of the transistor grid electrode;
specifically, the core differential amplifying circuit includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, and a resistor R7, wherein the transistor M1, the transistor M2, the transistor M3, the transistor M4, the capacitor C2, the capacitor C3, the capacitor C4 constitute a first transistor stack unit, the transistor M5, the transistor M6, the transistor M7, the transistor M8, the capacitor C5, the capacitor C6, the capacitor C7, the resistor R5, the resistor R6, and the resistor R7 constitute a second transistor stack unit, the capacitor C8, the capacitor C9, and the capacitor C10 constitute a first capacitor series circuit, in the core differential amplifying circuit, a first capacitor series circuit is formed by a capacitor C11, a capacitor C12 and a capacitor C13, wherein a grid electrode of a transistor M1 and a grid electrode of a transistor M5 are respectively connected with an output end of a transformer TF1, a source electrode of the transistor M1 and a source electrode of the transistor M5 are connected with each other and grounded, a grid electrode of the transistor M1 is connected with a first end of a capacitor C11, a drain electrode of the transistor M1 is connected with a source electrode of a transistor M2, a grid electrode of the transistor M2 is respectively connected with a second end of a capacitor C8, a first end of a capacitor C9, a second end of a capacitor C2 and a second end of a resistor R2, a drain electrode of the transistor M2 is connected with a source electrode of a transistor M3, a grid electrode of the transistor M3 is respectively connected with a second end of the capacitor C9, a first end of the capacitor C10, a second end of the capacitor C3 and a second end of the resistor R3, a drain electrode of the transistor M3 is connected with a source electrode of the transistor M4, the grid electrode of the transistor M4 is respectively connected with the second end of the capacitor C10, the second end of the capacitor C4 and the second end of the resistor R4, the drain electrode of the transistor M4 is connected with the output matching network and the input end of the second transformer circuit in the input balun circuit, the grid electrode of the transistor M5 is connected with the first end of the capacitor C8, the drain electrode of the transistor M5 is connected with the source electrode of the transistor M6, the grid electrode of the transistor M6 is respectively connected with the second end of the capacitor C11, the first end of the capacitor C12, the first end of the capacitor C5 and the first end of the resistor R5, the drain electrode of the transistor M6The gate of the transistor M7 is connected with the second end of the capacitor C12, the first end of the capacitor C13, the first end of the capacitor C6 and the first end of the resistor R6 respectively, the drain of the transistor M7 is connected with the source of the transistor M8, the gate of the transistor M8 is connected with the second end of the capacitor C13, the first end of the capacitor C7 and the first end of the resistor R7 respectively, the drain of the transistor M8 is connected with the output matching network and the input end of the second transformer circuit in the input balun circuit, the first end of the capacitor C2, the first end of the capacitor C3, the first end of the capacitor C4, the second end of the capacitor C5, the second end of the capacitor C6 and the second end of the resistor C7 are grounded, the first end of the resistor R2 and the second end of the resistor R5 are connected with the second end V Bias2 A first end of the resistor R3 and a second end of the resistor R6 are connected with V Bias3 A first end of the resistor R4 and a second end of the resistor R7 are connected with V Bias4 ；
Further, the first four-transistor stacking unit and the second four-transistor stacking unit are implemented by differential connection of two four-transistor stacking units, wherein the transistor M1, the transistor M2, the transistor M3 and the transistor M4 are one unit, the transistor M5, the transistor M6, the transistor M7 and the transistor M8 are one unit, the two four-transistor stacking units are in differential working states, and the working states of the two four-transistor stacking units have a phase difference of 180 degrees;
the transistors M2, M3, M4, M6, M7 and M8 are stacked transistors, so as to improve the voltage swing of the power unit and enhance the power output capability. The grid electrode is connected with an RC bias network, and R is a power supply resistor; c is the gate capacitance, which provides the ability of the gate voltage to follow the swing, while the impedance seen from the source of each transistor can be considered asWherein C is gs The capacitor C can also adjust node impedance for parasitic capacitance of the gate source, balance voltage swing of each transistor and prevent breakdown of the device caused by overlarge swing of one transistor;
the capacitor C8, the capacitor C9, the capacitor C10, the capacitor C11, the capacitor C12 and the capacitor C13 are serial capacitor circuits of two stacked units respectively, and the purpose is to slow down the voltage pressure of a grid electrode and adjust the phase difference between different stacked transistors at the same time;
as shown in fig. 3, for the conventional common stacked transistor waveform phase difference, the following analysis (taking the transistor M1, the transistor M2, the transistor M3, and the transistor M4 as examples) is performed, after the signal is input to the gate of the transistor M1, the transistor M1 is turned on, the drain-source current is increased, the drain-source voltage is reduced, the drain-source voltage behavior of the transistor M1 and the input voltage can be regarded as no phase difference, and the drain voltage of the transistor M1 (the source of the transistor M2) is reduced, the gate-source voltage of the transistor M2 is increased, so that the transistor M2 is gradually turned on in the process, and the phase difference is caused in the processTransistor M3 and transistor M4 are the same, and therefore will cause +.>Is a phase difference of (2);
the key point of the invention is that, by means of the property of inverting differential signals, because the swing trend of the transistor M5 is the same as that of the transistor M2, the transistor M3 and the transistor M4, and a phase difference exists, the gates of the transistor M5, the transistor M2, the transistor M3 and the transistor M4 are coupled by introducing a capacitor series circuit, firstly, the gate of the stacked transistor can follow the output voltage swing to a greater extent, secondly, the switching delay phase difference of the stacked transistor is reduced, the power output and the efficiency are improved, secondly, the power output capability of the whole power amplifier is improved by introducing a differential structure, and secondly, the correction of voltage stress and phase is realized by utilizing the waveform symmetry of the differential structure.
The output matching network and the input balun circuit comprise an output matching network circuit and a second transformer circuit; the second transformer circuit is used for receiving the output signal of the core differential amplifying circuit and converting the output signal into a single-ended signal; the output matching network circuit is used for receiving the single-ended signal output by the second transformer circuit and transmitting the single-ended signal to the load impedance;
specifically, the output matching network and the input balun circuit comprise a transformer TF2, wherein the transformer TF2 is a second transformer circuit, in the output matching network and the input balun circuit, the input end of the transformer TF2 is connected with the core differential amplifying circuit, the output end of the transformer TF2 is connected with the input end of the output matching network circuit, and the output end of the output matching network circuit is connected with the load impedance;
further, the transformer TF2 is responsible for coupling the differential output of the power amplifier unit to the load: one is to implement conversion of differential signals to single-ended signals; secondly, a certain impedance transformation effect is realized, and the use amount of passive devices of an output matching network can be reduced to a certain extent; thirdly, the power supply voltage VDD can be connected through the center tap to supply power for the two stacked transistor units, and as the differential signals of the center tap are equivalent short-circuit ends, a choke coil with huge volume is not needed for power supply of the VDD, so that the area is saved;
the output matching circuit and the transformer TF2 are responsible for converting a 50Ω output impedance terminal into an optimal power output impedance of the power amplifier, so as to realize optimal power output matching of the power amplifier.
In summary, the workflow of the circuit of the present invention is as follows:
the circuit structure of the invention is mainly divided into three modules, namely an input matching network, an input balun TF1, an output matching network, an input balun TF2 and a core differential amplifying circuit; after the signal is input from the input end, the single-ended signal is converted into a double-ended differential signal through the input balun for the differential amplifying circuit to amplify; the two paths of the differential circuit work with a phase difference of 180 degrees, signals are amplified and output to the balun TF2, the TF2 further converts the signals from double ends to single ends, and the signals are synthesized to single-ended signals and then transmitted to a load;
the working principle of the core differential amplifying circuit is that after signals are input from an input end, single-ended signals are converted into double-ended differential signals through an input balun and amplified by the differential amplifying circuit, two paths of the differential amplifying circuit work with a phase difference of 180 degrees, at the moment, two transistor stacking structures of the differential amplifying unit are conducted and amplified in turn, and current and voltage on stacking nodes can be regarded as symmetrical relation, for example, when a grid electrode of a transistor M1 acquires high voltage, a transistor stacking unit of an upper half stacking branch, namely a first four transistor stacking unit, is increased due to the current of a transistor opening passage, and the voltage of an output end is pulled down; the opposite grid electrode of the transistor M2 acquires low voltage, the transistor stacking unit of the upper half stacking branch is increased due to the increase of the transistor on-channel current, and the voltage of the output end is pulled up, so that the swing of an output signal is acquired at the position of the output balun TF2 and is converted into a single-ended output signal to a load;
further, referring to fig. 4, the transistor gates can follow the output voltage swing to a greater extent, for example, the transistor M2, transistor M3 and transistor M4 gates, as shown in fig. 5, the swing trend can be simply regarded as V DS,M2 、V DS,M3 、V DS,M4 As can be seen from the figure, when the transistor M1 is at a low level, the transistor M2 is at a high level, and although the gates of the transistor M2, the transistor M3 and the transistor M4 are connected to the gate capacitance of the ground, the gate capacitance is the same as the flow direction of the capacitance series circuit, so that the equivalent voltage swing of the gates of the transistor M2, the transistor M3 and the transistor M4 is raised, the VGD voltage difference is reduced, and the gate-drain breakdown is reduced;
for reducing the switching delay phase difference of stacked transistors, when V DS,M2 、V DS,M3 、V DS,M4 With the phase difference being turned off, the gate voltage of the transistor M2 decreases, and the voltage difference of the capacitor series circuit increases, so that more current is drawn from the transistors M2, M3 and M4, respectively, to accelerate the turn-off of the transistors M2, M3 and M4, thereby the phase differenceThe power output and efficiency are improved.
Another aspect provides a power amplifier comprising an SOI stacked transistor voltage swing balancing circuit as described in any one of the possible designs of the first aspect;
in another aspect, the working process, working details and technical effects of the SOI stacked transistor voltage swing balancing circuit in the power amplifier provided in this embodiment may be referred to the above first aspect or any one of the possible designs of the first aspect, and will not be repeated herein.
While the preferred embodiment of the present invention has been described in detail, the invention is not limited to the embodiment, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the invention, and these modifications and substitutions are intended to be included in the scope of the present invention as defined in the appended claims.

Claims (6)

1. The SOI stacked transistor voltage swing balance circuit is characterized by comprising an input matching network, an input balun circuit, a core differential amplifying circuit, an output matching network and an input balun circuit, wherein the output end of the input matching network is connected with the input end of the core differential amplifying circuit, the output end of the core differential amplifying circuit is connected with the output matching network and the input end of the input balun circuit, the input end of the input matching network and the input balun circuit receives radio frequency signals, and the output end of the output matching network and the input balun circuit is connected with load impedance:
the input matching network and the input balun circuit comprise an input matching circuit, a first transformer circuit and an RC bias network circuit;
the input matching circuit is used for receiving radio frequency signals;
the first transformer circuit converts a single-ended signal output by the input matching circuit into a differential signal and couples the differential signal to the input end of the core differential amplifying circuit;
the RC bias network circuit provides bias voltage for the bottom transistor in the core differential amplifying circuit to work;
the core differential amplifying circuit comprises a first four-transistor stacking unit, a first capacitor series circuit, a second four-transistor stacking unit and a second capacitor series circuit;
the first four-transistor stacking unit and the second four-transistor stacking unit are used for improving the voltage swing of the transistor and enhancing the power output capability of the transistor;
the first capacitor series circuit and the second capacitor series circuit are used for adjusting the phase difference between the first four-transistor stacking unit and the second four-transistor stacking unit and reducing the voltage pressure of the transistor grid electrode;
the output matching network and the input balun circuit comprise an output matching network circuit and a second transformer circuit;
the second transformer circuit is used for receiving the output signal of the core differential amplifying circuit and converting the output signal into a single-ended signal;
the output matching network circuit is used for receiving the single-ended signal output by the second transformer circuit and transmitting the single-ended signal to the load impedance;
the input matching network and the input balun circuit comprise a transformer TF1, a capacitor C1 and a resistor R1, wherein the transformer TF1 is a first transformer circuit, and the capacitor C1 and the resistor R1 form an RC bias network circuit; the resistor R1 is a ballast resistor for receiving bias voltage, so that the stability of the transistor is improved; the capacitor C1 is a filter capacitor and provides bias voltage for the transistor M1 and the transistor M5 through a center tap connected to the transformer TF 1;
the core differential amplifying circuit comprises a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and a resistor R7, wherein the transistor M1, the transistor M2, the transistor M3, the transistor M4, the capacitor C2, the capacitor C3, the capacitor C4 form a first four-transistor stack unit, the transistor M5, the transistor M6, the transistor M7, the transistor M8, the capacitor C5, the capacitor C6, the capacitor C7, the resistor R5, the resistor R6 and the resistor R7 form a second four-transistor stack unit, the capacitor C8, the capacitor C9 and the capacitor C10 form a capacitor C11, and a capacitor C11, which are connected in series.
2. The circuit of claim 1, wherein in the input matching network and the input balun circuit, an input terminal of the transformer TF1 is connected to an output terminal of the input matching circuit, an output terminal of the transformer TF1 is connected to a first terminal of a capacitor C1 and a first terminal of a resistor R1, a second terminal of the capacitor C1 is grounded, and a second terminal of the resistor R1 is connected to V Bias1 。
3. The SOI stacked transistor voltage swing balancing circuit according to claim 2, wherein in the core differential amplifying circuit, the gate of the transistor M1, the gate of the transistor M5 are respectively connected to the output terminal of the transformer TF1, the source of the transistor M1 and the source of the transistor M5 are respectively connected to ground, the gate of the transistor M1 is connected to the first terminal of the capacitor C11, the drain of the transistor M1 is respectively connected to the source of the transistor M2, the gate of the transistor M2 is respectively connected to the second terminal of the capacitor C8, the first terminal of the capacitor C9, the second terminal of the capacitor C2 and the second terminal of the resistor R2, the drain of the transistor M2 is respectively connected to the second terminal of the capacitor C9, the first terminal of the capacitor C10, the second terminal of the capacitor C3 and the second terminal of the resistor R3, the drain of the transistor M3 is respectively connected to the first terminal of the capacitor C4, the first terminal of the transistor C6, the drain of the transistor C6 is respectively connected to the first terminal of the capacitor C6, the first terminal of the capacitor C6 and the second terminal of the resistor R5, the drain of the transistor M6 is respectively connected to the first terminal of the capacitor C6, the gate of the transistor M6 is connected to the second terminal of the capacitor C6, the first terminal of the capacitor C6 and the second terminal of the resistor R5 is respectively connected to the second terminal of the capacitor C6, the drain of the capacitor M6 is connected to the second terminal of the capacitor C6, the drain of the transistor M7 and the transistor M8The grid electrode of the transistor M8 is respectively connected with the second end of the capacitor C13, the first end of the capacitor C7 and the first end of the resistor R7, the drain electrode of the transistor M8 is connected with the output matching network and the input end of the second transformer circuit in the input balun circuit, the first end of the capacitor C2, the first end of the capacitor C3, the first end of the capacitor C4, the second end of the capacitor C5, the second end of the capacitor C6 and the second end of the capacitor C7 are grounded, the first end of the resistor R2 and the second end of the resistor R5 are connected with the input end of the second transformer circuit in the balun circuit Bias2 A first end of the resistor R3 and a second end of the resistor R6 are connected with V Bias3 A first end of the resistor R4 and a second end of the resistor R7 are connected with V Bias4 。
4. The SOI stacked transistor voltage swing balancing circuit of claim 1, wherein the output matching network and input balun circuit comprises a transformer TF2, wherein the transformer TF2 is a second transformer circuit.
5. The SOI stacked transistor voltage swing balancing circuit of claim 4, wherein in the output matching network and input balun circuit, the input of the transformer TF2 is connected to the core differential amplifying circuit, the output of the transformer TF2 is connected to the input of the output matching network circuit, and the output of the output matching network circuit is connected to the load impedance.
6. A power amplifier comprising an SOI stacked transistor voltage swing balancing circuit as claimed in any one of claims 1 to 5.
CN202310425470.1A 2023-04-20 2023-04-20 SOI stacked transistor voltage swing balancing circuit and power amplifier Active CN116436440B (en)

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Publication number Priority date Publication date Assignee Title
CN113037223A (en) * 2021-03-31 2021-06-25 广东工业大学 Broadband differential radio frequency power amplifier with second harmonic suppression
WO2021196404A1 (en) * 2020-03-30 2021-10-07 南京汇君半导体科技有限公司 Low phase deviation digital-controlled radio frequency attenuator
CN113783538A (en) * 2021-09-13 2021-12-10 东南大学 CMOS low noise amplifier
CN114759889A (en) * 2022-03-08 2022-07-15 西安电子科技大学 High-gain power amplifier circuit of pseudo-differential Cascode structure of W wave band
CN218772017U (en) * 2022-11-14 2023-03-28 成都市时代速信科技有限公司 Differential stacked power amplifier and radio frequency transmission circuit
CN115913154A (en) * 2023-02-08 2023-04-04 深圳飞骧科技股份有限公司 Microwave power amplifier and microwave chip

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021196404A1 (en) * 2020-03-30 2021-10-07 南京汇君半导体科技有限公司 Low phase deviation digital-controlled radio frequency attenuator
CN113037223A (en) * 2021-03-31 2021-06-25 广东工业大学 Broadband differential radio frequency power amplifier with second harmonic suppression
CN113783538A (en) * 2021-09-13 2021-12-10 东南大学 CMOS low noise amplifier
CN114759889A (en) * 2022-03-08 2022-07-15 西安电子科技大学 High-gain power amplifier circuit of pseudo-differential Cascode structure of W wave band
CN218772017U (en) * 2022-11-14 2023-03-28 成都市时代速信科技有限公司 Differential stacked power amplifier and radio frequency transmission circuit
CN115913154A (en) * 2023-02-08 2023-04-04 深圳飞骧科技股份有限公司 Microwave power amplifier and microwave chip

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