CN114759889A - High-gain power amplifier circuit of pseudo-differential Cascode structure of W wave band - Google Patents
High-gain power amplifier circuit of pseudo-differential Cascode structure of W wave band Download PDFInfo
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- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
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- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
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Abstract
The invention relates to a high-gain power amplifier circuit with a pseudo-differential Cascode structure of a W wave band, which comprises: the input balun, the plurality of stages of amplifying circuit units and the output balun are connected in sequence, wherein the input balun and the output balun both adopt a balun structure of a single-coil laminated transformer; the amplifying circuit unit adopts a pseudo-differential cascode structure. According to the high-gain power amplifier circuit with the W-band pseudo-differential Cascode structure, the amplifying circuit unit adopts a pseudo-differential Cascode (Cascode) amplifying structure, so that a differential mode signal can be amplified, a common mode signal can be inhibited, the output voltage swing of the amplifier can be improved, the influence of parasitic inductance of a bonding wire on a power amplifier can be reduced, meanwhile, the differential structure can reduce the interference of the power amplifier on other circuits, and the power amplifier can still have high gain under the attenuation of the W-band signal.
Description
Technical Field
The invention belongs to the technical field of microwave integrated circuits, and particularly relates to a high-gain power amplifier circuit with a pseudo-differential Cascode structure in a W wave band.
Background
With the development of modern science and technology, people enter the information age, higher requirements are put forward on the speed and the information capacity of communication, the traditional low-frequency band communication cannot meet the requirements of people, meanwhile, the microwave low-frequency band frequency spectrum resources are in a very short supply, and the mutual interference is serious, so that people have to look at higher frequency development. The W wave band belongs to the millimeter wave frequency band, and compared with the microwave low frequency band, the W wave band has certain improvement on information transmission speed and information transmission capacity.
The power amplifier is used as an important component of a transmitter of a communication system, the performance of the power amplifier directly plays a decisive role in the performance of the whole communication system, generally, the power amplifier is positioned at the tail end of the transmitter of the whole communication system, signals pass through a modem, a mixer and a filter, and are amplified to certain power through the power amplifier and then transmitted through an antenna. Therefore, how to improve the output power of the power amplifier, the performance indexes such as the working bandwidth and the efficiency are very important for the performance of the whole transmitter.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a high gain power amplifier circuit with a pseudo-differential Cascode structure in a W-band. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a high-gain power amplifier circuit with a pseudo-differential Cascode structure of a W wave band, which comprises: the transformer comprises an input balun, a plurality of stages of amplifying circuit units and an output balun which are connected in sequence, wherein the input balun and the output balun both adopt a balun structure of a single-coil laminated transformer; the amplifying circuit unit adopts a pseudo-differential cascode amplifying structure.
In one embodiment of the present invention, the amplifying circuit unit includes a first input matching network, a second input matching network, a first common emitter transistor, a second common emitter transistor, a first input bias resistor, a second input bias resistor, a first common base transistor, a second common base transistor, a first interconnection inductor, a second interconnection inductor, a first bias decoupling capacitor, a second bias decoupling capacitor, a first bias resistor, a second bias resistor, a first output matching network, and a second output matching network,
the output end of the first input matching network is respectively connected with the base electrode of the first common emitter transistor and the first end of the first input bias resistor;
the output end of the second input matching network is respectively connected with the base electrode of the second common emitter transistor and the first end of the second input bias resistor;
the second end of the first input bias resistor and the second end of the second input bias resistor are both connected with a first bias voltage;
the emitter of the first common emitter transistor and the emitter of the second common emitter transistor are both connected with the ground terminal;
the collector of the first common emitter transistor is connected with the first end of the first interconnection inductor, and the collector of the second common emitter transistor is connected with the first end of the second interconnection inductor;
an emitter of the first common base transistor is connected with a second end of the first interconnection inductor, a base is respectively connected with a first end of the first bias decoupling capacitor and a first end of the first bias resistor, and a collector is connected with an input end of the first output matching network;
an emitter of the second common base transistor is connected with a second end of the second interconnection inductor, a base is respectively connected with a first end of the second bias decoupling capacitor and a first end of the second bias resistor, and a collector is connected with an input end of the second output matching network;
the second end of the first bias decoupling capacitor and the second end of the second bias decoupling capacitor are both connected with the grounding terminal, and the second end of the first bias resistor and the second end of the second bias resistor are both connected with a second bias voltage;
the input end of the first output matching network and the input end of the second output matching network are both connected with a power supply voltage.
In an embodiment of the present invention, a single end of the input balun is used as an input end to input a signal, and a differential end is used as an output end to connect an input end of a first input matching network and an input end of a second input matching network of the amplifying circuit unit of the first stage, respectively;
the differential end of the output balun is used as an input end and is respectively connected with the output end of the first output matching network and the output end of the second output matching network of the last-stage amplifying circuit unit, and the single end is used as an output end to output an amplified signal;
the output ends of the two output matching networks of the previous stage in the two adjacent stages of amplifying circuit units are correspondingly connected with the input ends of the two input matching networks of the next stage.
In one embodiment of the invention, the first input matching network and the second input matching network are of the type L-matching network, Π -matching network, or T-matching network; the first output matching network and the second output matching network are of an L-type matching network, a pi-type matching network or a T-type matching network.
In an embodiment of the present invention, the T-type matching network includes a first matching capacitor, a second matching capacitor, and a first matching inductor, wherein a first end of the first matching capacitor is used as an input end, a second end of the first matching capacitor is respectively connected to a first end of the second matching capacitor and a first end of the first matching inductor, a second end of the second matching capacitor is used as an output end, and a second end of the first matching inductor is connected to the ground end;
the L-shaped matching network comprises a second matching inductor and a third matching capacitor, the first end of the second matching inductor is connected with the power supply voltage, the second end of the second matching inductor is connected with the first end of the third matching capacitor, the first end of the third matching capacitor is used as an input end, and the second end of the third matching capacitor is used as an output end.
In one embodiment of the present invention, the first input matching network and the second input matching network are of the type of the T-type matching network, and the first output matching network and the second output matching network are of the type of the L-type matching network;
and the output matching network of the previous stage in the two adjacent stages of amplifying circuit units shares a matching capacitor with the input matching network of the next stage correspondingly connected with the output matching network.
In an embodiment of the present invention, the first interconnection inductor, the second interconnection inductor, the first matching inductor and the second matching inductor all adopt an octagonal spiral structure.
In one embodiment of the invention, the primary coil and the secondary coil of the balun structure both adopt an octagonal spiral structure.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the high-gain power amplifier circuit with the pseudo-differential Cascode structure, the amplifying circuit unit adopts a pseudo-differential Cascode (Cascode) amplifying structure, so that a differential mode signal can be amplified, a common mode signal can be inhibited, the output voltage swing of the amplifier is improved, the influence of parasitic inductance of a bonding wire on a power amplifier is reduced, meanwhile, the differential structure can reduce the interference of the power amplifier on other circuits, and the power amplifier can still have high gain under the signal attenuation of a W wave band;
2. the high-gain power amplifier circuit with the W-band pseudo-differential Cascode structure still has good performance when the frequency is very high, and the indexes of the output power, the gain, S21, S22, stability coefficient and the like can reach a certain level;
3. according to the high-gain power amplifier circuit with the W-band pseudo-differential Cascode structure, the input balun and the output balun are both designed manually, the layout area is effectively saved, the loss in a 92-96GHz working frequency band is about 1.7dB, the phase imbalance is less than 7 degrees, and the high-gain power amplifier circuit has good working performance.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are specifically described below with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic structural diagram of a conventional power amplifier circuit according to an embodiment of the present invention;
fig. 2 is a block diagram of a high-gain power amplifier circuit with a pseudo-differential Cascode structure in a W-band according to an embodiment of the present invention;
fig. 3a is a schematic circuit diagram of a T-type matching network according to an embodiment of the present invention;
fig. 3b is a schematic circuit diagram of an L-type matching network according to an embodiment of the present invention;
fig. 4a is a schematic structural diagram of a spiral inductor according to an embodiment of the present invention;
FIG. 4b is a diagram showing a simulation result of the inductance of a spiral inductor according to an embodiment of the present invention;
fig. 4c is a diagram illustrating a simulation result of an inductance Q value of a spiral inductor according to an embodiment of the present invention;
fig. 5a is a schematic structural diagram of a balun structure provided in an embodiment of the present invention;
fig. 5b is a diagram of a simulation result of a balun structure according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a high-gain power amplifier circuit with a pseudo-differential Cascode structure in a W-band in three-stage cascade connection according to an embodiment of the present invention;
fig. 7 is a diagram of simulation results of the amplifier circuit of fig. 6 provided by an embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, a high gain power amplifier circuit with a pseudo-differential Cascode structure in W-band according to the present invention will be described in detail with reference to the accompanying drawings and the detailed description.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a conventional power amplifier circuit according to an embodiment of the present invention, where the conventional power amplifier circuit adopts a multi-stage cascode structure, and an operating frequency band is 92 GHz-96 GHz, but in the operating frequency band, a gain and a power of the power amplifier circuit cannot meet actual application requirements at the present stage. In order to improve the performance of a power amplifier circuit in a W-band, this embodiment provides a high-gain power amplifier circuit in a pseudo-differential Cascode structure in a W-band, please refer to fig. 2, fig. 2 is a schematic diagram of a block diagram structure of a high-gain power amplifier circuit in a pseudo-differential Cascode structure in a W-band according to an embodiment of the present invention, as shown in fig. 2, the high-gain power amplifier circuit in a pseudo-differential Cascode structure in a W-band in this embodiment includes an input balun 1, a plurality of stage amplification circuit units 2, and an output balun 3, which are sequentially connected, where the input balun 1 and the output balun 3 both adopt a balun structure of a single-turn stacked transformer; the amplifier circuit unit 2 has a pseudo-differential Cascode (Cascode) amplification structure.
Specifically, the amplifying circuit unit 2 includes a first input matching network 201, a second input matching network 202, a first common emitter transistor 203, a second common emitter transistor 204, a first input bias resistor 205, a second input bias resistor 206, a first common base transistor 207, a second common base transistor 208, a first interconnection inductor 209, a second interconnection inductor 210, a first bias decoupling capacitor 211, a second bias decoupling capacitor 212, a first bias resistor 213, a second bias resistor 214, a first output matching network 215, and a second output matching network 216.
Wherein, the output terminal of the first input matching network 201 is connected to the base of the first common emitter transistor 203 and the first terminal of the first input bias resistor 205 respectively; the output end of the second input matching network 202 is respectively connected with the base of the second common emitter transistor 204 and the first end of the second input bias resistor 206; a second terminal of the first input bias resistor 205 and a second terminal of the second input bias resistor 206 are both connected to a first bias voltage Vbias 1.
The emitter of the first common-emitter transistor 203 and the emitter of the second common-emitter transistor 204 are both connected to the ground GND; the collector of the first common-emitter transistor 203 is connected to a first terminal of a first interconnection inductance 209 and the collector of the second common-emitter transistor 204 is connected to a first terminal of a second interconnection inductance 210.
The emitter of the first common base transistor 207 is connected to the second terminal of the first interconnecting inductor 209, the base is connected to the first terminal of the first bias decoupling capacitor 211 and the first terminal of the first bias resistor 213, respectively, and the collector is connected to the input terminal of the first output matching network 215; the emitter of the second common base transistor 208 is connected to the second terminal of the second interconnecting inductor 210, the base is connected to the first terminal of the second bias decoupling capacitor 212 and the first terminal of the second bias resistor 214, respectively, and the collector is connected to the input of the second output matching network 216.
The second terminal of the first bias decoupling capacitor 211 and the second terminal of the second bias decoupling capacitor 212 are both connected to the ground GND, and the second terminal of the first bias resistor 213 and the second terminal of the second bias resistor 214 are both connected to the second bias voltage Vbias 2; the input terminal of the first output matching network 215 and the input terminal of the second output matching network 216 are both connected to the power supply voltage VDD.
Further, a single end of the input balun 1 is used as an input signal of the input end, and a differential end is used as an output end and is respectively connected with the input end of the first input matching network 201 and the input end of the second input matching network 202 of the first-stage amplification circuit unit 2; a differential end of the output balun 3 is used as an input end and is respectively connected with an output end of the first output matching network 215 and an output end of the second output matching network 216 of the last-stage amplification circuit unit 2, and a single end is used as an output end to output an amplified signal; the output ends of the two output matching networks (215 and 216) of the previous stage in the amplifying circuit units 2 of the adjacent two stages are correspondingly connected to the input ends of the two input matching networks (201 and 202) of the next stage.
It should be noted that, in this embodiment, the amplifying circuit unit 2 of the last stage adopts maximum output power matching, and the amplifying circuit units 2 of the first stage and the intermediate stage both adopt conjugate matching.
In the pseudo-differential Cascode (Cascode) amplification structure of the embodiment, a tail current source in the differential structure is removed, and an emitter of the common emitter transistor is directly grounded to form a pseudo-differential structure, so that the output voltage swing is not limited by the tail current source, and the output power of the power amplifier is improved.
Further, the use of interconnection inductors (209 and 210) between the collectors of the common emitter transistors (203 and 204) and the emitters of the common base transistors (207 and 208) can form a pi-type network with parasitic capacitance, which can significantly improve the stability of the circuit. With the bias decoupling capacitors (211 and 212), parasitic inductances between the bases of the common base transistors (207 and 208) and a dc bias provided by the power supply voltage VDD can be coupled, and thus, a high gain for the W band can be achieved.
Further, optionally, the types of the first input matching network 201 and the second input matching network 202 are an L-type matching network, a Π -type matching network, or a T-type matching network; optionally, the first output matching network 215 and the second output matching network 216 are of the type L-matching network, Π -matching network, or T-matching network.
Referring to fig. 3a and fig. 3b in combination, fig. 3a is a schematic circuit structure diagram of a T-type matching network according to an embodiment of the present invention; fig. 3b is a schematic circuit structure diagram of an L-type matching network according to an embodiment of the present invention. As shown in fig. 3a, the T-type matching network includes a first matching capacitor 4, a second matching capacitor 5, and a first matching inductor 6, wherein a first end of the first matching capacitor 4 is used as an input end, a second end of the first matching capacitor 4 is respectively connected to a first end of the second matching capacitor 5 and a first end of the first matching inductor 6, a second end of the second matching capacitor 5 is used as an output end, and a second end of the first matching inductor 6 is connected to a ground GND.
As shown in fig. 3b, the L-shaped matching network includes a second matching inductor 7 and a third matching capacitor 8, a first end of the second matching inductor 7 is connected to the power voltage VDD, a second end of the second matching inductor is connected to a first end of the third matching capacitor 8, the first end of the third matching capacitor 8 is used as an input end, and the second end of the third matching capacitor 8 is used as an output end.
In the present embodiment, the types of the first input matching network 201 and the second input matching network 202 are T-type matching networks, and the types of the first output matching network 215 and the second output matching network 216 are L-type matching networks; the output matching network (215/216) of the previous stage in the two adjacent stages of amplifying circuit units 2 shares a matching capacitance with the input matching network (201/202) of the next stage connected thereto.
The input matching networks (201 and 202) of the embodiment of the invention adopt T-shaped matching networks, thereby improving the freedom degree of design and more flexibly controlling the bandwidth. The output matching networks (215 and 216) adopt L-shaped matching networks, so that the influence of unnecessary passive devices on the power and the loss of the circuit can be reduced while the narrow-band bandwidth is ensured. In addition, the complexity of the circuit structure can be reduced by sharing the matching capacitance between the output matching network (215 and 216) of the previous stage and the input matching network (201 and 202) of the subsequent stage.
It should be noted that, in this embodiment, the first interconnection inductor 209, the second interconnection inductor 210, the first matching inductor 6, and the second matching inductor 7 all adopt an octagonal spiral structure. The octagonal spiral structure adopts the inductor layout and the S parameter which are independently designed, the metal used by the inductor is the top layer thick metal provided in the preparation process, the area of the layout is effectively saved, and the Q value of the inductor is improved to a certain extent. Referring to fig. 4a to fig. 4c, fig. 4a is a schematic structural diagram of a spiral inductor according to an embodiment of the present invention; FIG. 4b is a diagram illustrating a simulation result of the inductance of a spiral inductor according to an embodiment of the present invention; fig. 4c is a graph of a simulation result of the inductance Q value of the spiral inductor according to the embodiment of the present invention, as shown in the figure, when the inner diameter of the inductor is 39.46 μm, the line width is 4 μm, and the inductance Q value is 23.4 and the inductance value is 92.3pH at the operating center frequency of 94 GHz.
Further, in this embodiment, the balun structure of the single-turn stacked transformer adopted by the input balun 1 and the output balun 3 is formed by adopting an autonomously designed single-turn stacked transformer; the primary coil of the transformer balun is composed of top layer metal, and the secondary coil is composed of secondary top layer metal. The primary coil and the secondary coil of the balun structure are of octagonal spiral structures, and layout area can be effectively saved. Referring to fig. 5a and fig. 5b in combination, fig. 5a is a schematic structural diagram of a balun structure according to an embodiment of the present invention; fig. 5b is a simulation result diagram of a balun structure according to an embodiment of the present invention. As shown in the figure, the balun structure of this embodiment has an inner diameter of 66 μm in a single turn, a coil width of 6 μm, a primary-secondary inductance ratio of about 1, and a loss of about 1.7dB in an operating frequency band of 92-96GHz, and has good operating performance.
It should be noted that the manufacturing process of the high-gain power amplifier circuit with the pseudo-differential Cascode structure in the W-band may be implemented by any one of the existing processes, such as a III-V semiconductor process, a gallium arsenide (GaAs) process, an indium phosphide (InP) process, and the like.
In this embodiment, the process of manufacturing the high-gain power amplifier circuit of the pseudo-differential Cascode structure in the W band employs a 130nm SiGe BiCMOS process (silicon germanium (SiGe)). Since Ge has a larger lattice constant than Si, and thus SiGe has a smaller energy band than Si and a larger energy band than Ge, the reduction of the energy band increases the mobility of carriers, and thus the cutoff frequency of SiGe is much higher than Si. At the same time, doping with Si also provides the same level of integration as silicon-based processes, so the cost of SiGe processes is much less than processes such as III-V compounds. The working frequency band of the high-gain power amplifier circuit with the W-band pseudo-differential Cascode structure prepared by the process comprises the following steps: 92 GHz-96 GHz, and the central frequency point is 94 GHz.
Further, taking the amplifying circuit unit 2 including three-stage cascade as an example, a specific circuit principle and effect of the high-gain power amplifier circuit of the pseudo differential Cascode structure of the W band of the present embodiment will be described.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a three-stage cascaded W-band high-gain power amplifier circuit with a pseudo-differential Cascode structure according to an embodiment of the present invention. As shown in the figure, the first and second,
for the first stage of amplification:
two paths of input matching networks of the first-stage differential Cascode power amplification circuit are subjected to conjugate matching by a T-shaped matching network consisting of input matching capacitors C1 and C2, an input matching inductor L1, input matching capacitors C3 and C4 and an input matching inductor L2, so that the better performance of the circuit is ensured.
Specifically, after being connected with a single end of the input balun 1, the input signal IN is output by differential ends of the input balun 1, and then the input signal IN + and the input signal IN-are output, one end of the input matching capacitor C1 is connected with the radio frequency input signal IN +, the other end of the input matching capacitor C1 is connected with one end of the input matching inductor L1 IN parallel, the input matching capacitor C2 is connected IN series, the other end of the input matching inductor L1 is grounded, and the other end of the input matching capacitor C2 is connected with a bias circuit IN parallel and used for providing the optimal current density for the common emitter transistor Q1. One end of the input matching capacitor C3 is connected with the radio frequency input signal IN-, and the other end is connected with one end of the input matching inductor L2 IN parallel, and is connected with the input matching capacitor C4 IN series, the other end of the input matching inductor L2 is grounded, and the other end of the input matching capacitor C4 is connected with a bias circuit IN parallel, and is used for providing the optimal current density for the common emitter transistor Q3.
An interconnection inductor Lm1 is connected in series between the collector of the common emitter transistor Q1 and the emitter of the common base transistor Q2; the interconnection inductor Lm1 can form a pi-shaped network with the parasitic capacitance between the common emitter transistor Q1 and the common base transistor Q2, thereby improving the stability of the first-stage amplifying circuit. An interconnection inductor Lm2 is connected in series between the collector of the common emitter transistor Q3 and the emitter of the common base transistor Q4; the interconnection inductor Lm2 can form a pi-shaped network with the parasitic capacitance between the common emitter transistor Q3 and the common base transistor Q4, thereby improving the stability of the first-stage amplifying circuit.
The base of the common base transistor Q2 is connected with one end of a bias decoupling capacitor C5, and the other end of the bias decoupling capacitor C5 is grounded; the base of the common base transistor Q2 is also connected to one end of a bias resistor R3, and the other end of the bias resistor R3 is connected to a bias voltage Vbias2 to ensure the optimal current density of the common base transistor Q2. The bias decoupling capacitor C5 is used to couple the parasitic inductance between the base of the common base transistor Q2 and the dc bias. The base of the common base transistor Q4 is connected with one end of a bias decoupling capacitor C6, and the other end of the bias decoupling capacitor C6 is grounded; the base of the common base transistor Q4 is also connected to one end of a bias resistor R4, and the other end of the bias resistor R4 is connected to a bias voltage Vbias2 to ensure the optimal current density of the common base transistor Q4. The bias decoupling capacitor C6 is used to couple the parasitic inductance between the base of the common base transistor Q4 and the dc bias.
The collectors of the common base transistors Q2 and Q4 are respectively connected with two output matching networks of the first-stage amplifying circuit. The output matching network connected with the collector of the common base transistor Q2 consists of an output matching inductor L3 and an output matching capacitor C8, and the output matching network connected with the collector of the common base transistor Q4 consists of an output matching inductor L4 and an output matching capacitor C7, so that the output impedance of the circuit can be ensured to be conjugate matched with the input impedance of the second-stage amplifying circuit, and the circuit has enough gain.
Specifically, the collector of the common base transistor Q2 is connected to one end of an output matching inductor L3 and one end of an output matching capacitor C8, the other end of the output matching inductor L3 is connected to the power supply voltage VDD, and the other end of the output matching capacitor C8 is used as a signal output end. The collector of the common base transistor Q4 is connected to one end of an output matching inductor L4 and an output matching capacitor C7, the other end of the output matching inductor L4 is connected to the power supply voltage VDD, and the other end of the output matching capacitor C7 is used as a signal output end.
For the second stage amplification circuit:
in the two-way input matching network of the second-stage differential Cascode power amplifying circuit, one input matching network consists of an input matching capacitor C8 (namely, an output matching capacitor C8 in one output matching network of the first-stage amplifying circuit), an input matching inductor L6 and an input matching inductor C10 to form a T-shaped matching network, and the other input matching network consists of an input matching capacitor C7 (namely, an output matching capacitor C7 in the other output matching network of the first-stage amplifying circuit), an input matching inductor L5 and an input matching inductor C9 to form a T-shaped matching network. Therefore, the input impedances of the two paths in the second-stage amplifying circuit can be respectively subjected to conjugate matching with the output impedances of the two paths in the first-stage amplifying circuit, and the optimal matching between circuit stages is ensured.
Specifically, the input matching capacitor C8 is connected in parallel with one end of the input matching inductor L6, and is connected in series with the input matching capacitor C10, the other end of the input matching inductor L6 is grounded, and the other end of the input matching capacitor C10 is connected with a bias circuit, and is used for providing the optimal current density for the common emitter transistor Q5; the input matching capacitor C7 is connected in parallel with one end of the input matching inductor L5, connected in series with the input matching capacitor C9, the other end of the input matching inductor L5 is grounded, and the other end of the input matching capacitor C9 is connected with a bias circuit for providing the optimal current density for the common emitter transistor Q7.
The emitter of the common emitter transistor Q5 is directly grounded, an interconnection inductor Lm3 is connected between the collector of the common emitter transistor Q5 and the emitter of the common base transistor Q6 in series, and the interconnection inductor Lm3 is used for forming an n-type network with parasitic capacitance between the common emitter transistor Q5 and the common base transistor Q6. The emitter of the common-emitter transistor Q7 is directly grounded, an interconnection inductor Lm4 is connected between the collector of the common-emitter transistor Q7 and the emitter of the common-base transistor Q8 in series, and the interconnection inductor Lm4 is used for forming an n-type network with parasitic capacitance between the common-emitter transistor Q7 and the common-base transistor Q8, so that the stability of the second-stage amplifying circuit is improved.
The base of the common base transistor Q6 is connected with one end of a bias decoupling capacitor C11, and the other end of the bias decoupling capacitor C11 is grounded; the base of the common base transistor Q6 is also connected to one end of a bias resistor R7, and the other end of the bias resistor R7 is connected to a bias voltage Vbias2 to provide a bias voltage to ensure the optimal current density of the common base transistor Q6. The bias decoupling capacitor C11 is used to couple the parasitic inductance between the base of the common base transistor Q6 and the dc bias. The base of the common base transistor Q8 is connected with one end of a bias decoupling capacitor C12, and the other end of the bias decoupling capacitor C12 is grounded; the base of the common base transistor Q8 is also connected to one end of a bias resistor R8, and the other end of the bias resistor R8 is connected to a bias voltage Vbias2 to provide a bias voltage to ensure the optimal current density of the common base transistor Q8. The bias decoupling capacitor C12 is used to couple the parasitic inductance between the base of the common base transistor Q8 and the dc bias.
The collectors of the common base transistors Q8 and Q6 are respectively connected with the two output matching networks of the second-stage amplifying circuit. The output matching network of one path consists of an output matching inductor L7 and an output matching capacitor C14; the output matching network of the other path consists of an output matching inductor L8 and an output matching capacitor C13, so that the output impedance of the two paths of the second-stage amplifying circuit can be ensured to be matched with the input impedance of the two paths of the last-stage amplifying circuit in a conjugate mode, and the circuit has enough gain.
Specifically, the collector of the common-base transistor Q6 is connected to one end of an output matching inductor L7 and one end of an output matching capacitor C14, the other end of the output matching inductor L7 is connected to the power supply voltage VDD, and the other end of the output matching capacitor C14 is used as a signal output end of a Cascode structure. The collector of the common base transistor Q8 is connected to one end of an output matching inductor L8 and an output matching capacitor C13, the other end of the output matching inductor L8 is connected to the power supply voltage VDD, and the other end of the output matching capacitor C13 is used as the signal output end of another Cascode structure.
For the third stage of amplification circuit:
in the third stage of differential Cascode power amplification circuit: the input matching network of one path consists of an input matching capacitor C13 (namely, an output matching capacitor C13 in the output matching network of the second-stage amplification circuit), an input matching inductor L9 and an input matching capacitor C15 to form a T-shaped matching network, and the input matching network of the other path consists of an input matching capacitor C14 (namely, an output matching capacitor C14 in the output matching network of the other path in the second-stage amplification circuit), an input matching inductor L10 and an input matching capacitor C16 to form a T-shaped matching network which is used for carrying out conjugate matching with the output impedance of the second-stage amplification circuit, so that the optimal matching between circuit stages is ensured.
Specifically, the input matching capacitor C13 is connected in parallel to one end of the input matching inductor L9, and connected in series to the input matching capacitor C15, the other end of the input matching inductor L9 is grounded, and the other end of the input matching capacitor C15 is connected to a bias circuit for providing the optimal current density to the common emitter transistor Q10. The input matching capacitor C14 is connected in parallel with one end of the input matching inductor L10, connected in series with the input matching capacitor C16, the other end of the input matching inductor L10 is grounded, and the other end of the input matching capacitor C16 is connected with a bias circuit for providing the optimal current density for the common emitter transistor Q12.
The emitters of the common emitter transistors Q9 and Q11 are directly grounded. An interconnection inductor Lm5 is connected in series between the collector of the common emitter transistor Q9 and the emitter of the common base transistor Q10; the interconnection inductor Lm5 is used for forming a pi-shaped network with a parasitic capacitor between the common emitter transistor Q9 and the common base transistor Q10; an interconnection inductor Lm6 is connected in series between the collector of the common emitter transistor Q11 and the emitter of the common base transistor Q12; the interconnection inductor Lm6 is used to form a pi-type network with the parasitic capacitance between the common emitter transistor Q11 and the common base transistor Q12, thereby improving the stability of the third stage amplifying circuit.
The base of the common base transistor Q10 is connected with one end of a bias decoupling capacitor C17, and the other end of the bias decoupling capacitor C17 is grounded; the base of the common base transistor Q10 is also connected to one end of a resistor R11 in the bias circuit, and the other end of the bias resistor R11 is connected to a bias voltage Vbias2 to provide a bias voltage to ensure the optimal current density of the common base transistor Q10. The bias decoupling capacitor C17 is used to couple the parasitic inductance between the base of the common base transistor Q10 and the dc bias. The base of the common base transistor Q12 is connected with one end of a bias decoupling capacitor C18, and the other end of the bias decoupling capacitor C18 is grounded; the base of the common base transistor Q12 is also connected to one end of a resistor R12 in the bias circuit, and the other end of the bias resistor R12 is connected to a bias voltage Vbias2 to provide a bias voltage to ensure the optimal current density of the common base transistor Q12. The bias decoupling capacitor C18 is used to couple the parasitic inductance between the base of the common base transistor Q12 and the dc bias.
The collectors of the common base transistors Q10 and Q12 are respectively connected with two output matching networks of the third-stage differential Cascode power amplifier circuit. The output matching network of one path is composed of an output matching inductor L11 and an output matching capacitor C20, and the output matching network of the other path is composed of an output matching inductor L12 and an output matching capacitor C19. The circuit is used for ensuring that the output impedance of the circuit can be matched with the input impedance in a conjugate mode, and the circuit has enough gain.
Specifically, the collector of the common base transistor Q10 is connected to one end of an output matching inductor L11 and one end of an output matching capacitor C20, the other end of the output matching inductor L11 is connected to the power supply voltage VDD, and the other end of the output matching capacitor C20 is used as a signal output end. The collector of the common base transistor Q12 is connected to one end of an output matching inductor L12 and an output matching capacitor C19, the other end of the output matching inductor L12 is connected to the power supply voltage VDD, and the other end of the output matching capacitor C19 is used as a signal output terminal. The third stage amplifying circuit is used as the last stage amplifying circuit, two paths of output signals of the third stage amplifying circuit are connected with the differential end of the output balun 3, and the differential signals are converted into single-ended output signals through the output balun 3.
In this embodiment, a three-stage pseudo differential Cascode power amplifier circuit structure is adopted, so that the power amplifier can still have a high gain under the attenuation of a W-band signal. And the T-shaped input matching network is adopted to realize good input matching and improve the linearity of the circuit. The parasitic capacitance between the common emitter transistor and the common base transistor can form a pi-shaped network by adopting the interconnection inductor, so that the stability of the power amplifying circuit is improved. With the bias decoupling capacitor, the parasitic inductance between the base of the common base transistor and the dc bias provided by VDD can be coupled.
Furthermore, the input matching network adopts a T-shaped matching network, the output matching network adopts an L-shaped matching network, the matching flexibility can be improved, and the influence of unnecessary passive devices on the noise power and the gain of the circuit is reduced while the narrow-band bandwidth is ensured. In addition, the capacitance of the radio frequency path also has the function of blocking direct current, and the inductance connected with the power supply simultaneously serves as a high-frequency choke coil.
Further, in order to verify the specific performance of the high-gain power amplifier circuit with the pseudo-differential Cascode structure in the W-band of the present embodiment, optimization tuning and corresponding performance simulation are performed. Table 1 shows the results of optimizing the parameter values of the elements of the high-gain power amplifier circuit having the pseudo-differential Cascode structure in the W band, which is the three-stage cascade shown in fig. 6.
TABLE 1 optimization of component parameter values
| Component | Numerical value |
| L1/L2 | 74.9pH |
| L3/L4 | 55pF |
| L5/L6 | 102.7pH |
| L7/L8 | 55pH |
| L9/L10 | 64.9pF |
| L11/L12 | 45pH |
| C1/C3 | 71.0fF |
| C2/C4 | 100fF |
| C5/C6 | 86.4fF |
| C7/C8 | 74.5fF |
| C9/C10 | 26.3fF |
| C11/C12 | 120fF |
| C13/C14 | 86fF |
| C15/C16 | 22.1fF |
| C17/C18 | 115.8fF |
| C19/C20 | 76.5fF |
| R1/R2 | 3kΩ |
| R3/R4 | 17kΩ |
| R5/R6 | 4kΩ |
| R7/R8 | 18kΩ |
| R9/R10 | 2kΩ |
| R11/R12 | 10kΩ |
| Lm1/Lm2/Lm3 | 10pH |
Fig. 7 shows simulation results of the high-gain power amplifier circuit with pseudo-differential Cascode structure in W band cascaded in three stages according to this embodiment in 90GHz to 100GHz, where fig. 7 is a simulation result diagram of the amplifier circuit in fig. 6 according to this embodiment of the present invention. It should be noted that the simulation result of fig. 7 is a post-simulation result, parasitic parameters of all transistors used in the circuit are extracted in the Cadence IC617 by using a PEX tool, and the rest passive parts are electromagnetically simulated by using an electromagnetic simulation tool Momentum, and the result obtained by the combined simulation method is closer to the real result during chip testing.
Wherein, the graph (a) in fig. 7 is a gain simulation result, and the ordinate axis of the ordinate axis represents the gain; (b) the graph is an output power simulation result, and the axis of the ordinate axis represents the output power; (c) the figure is a stability coefficient simulation result, and the coordinate axis of the vertical axis represents a stability coefficient kf; (d) the graph shows the simulation results of S parameters, and respectively shows four curves of S11, S12, S21 and S22, and the ordinate axis represents the S parameter values.
As can be seen from the diagrams (a) and (b) in fig. 7, in the operating frequency band, when the high-gain power amplifier circuit in the W band operates at the center frequency of 94GHz, the test results include: psat 10.14dBm Power Gain 30.72 dB.
As can be seen from the graph (c) in fig. 7, the high frequency stability coefficient of the circuit is greater than 1, and the circuit is absolutely stable.
As can be seen from the graph (d) in FIG. 7, in the 92G-96GHz operating frequency range, the input reflection coefficient S11 is less than-13 dB, the isolation between the input port and the output port S12 is less than-40 dB, the isolation of the circuit is good, the output reflection coefficient S22 is less than-10 dB, the input and the output are well matched, and S21 is more than 29dB in the range, so that the gain is high.
The results of comparing the optimum performance of the conventional power amplifier circuit shown in fig. 1 and the amplifier circuit of fig. 6 are shown in table 2.
TABLE 2 comparison of the main performance of two power amplifier circuits
Compared with the traditional power amplifier circuit, the high-gain power amplifier circuit with the W-band differential Cascode structure provided by the embodiment of the invention has higher gain and power in the W-band of 92 GHz-96 GHz, improves the isolation degree, obviously improves the stability of the circuit and has more obvious performance advantages.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (8)
1. A W-band pseudo-differential Cascode-structured high-gain power amplifier circuit, comprising: the transformer comprises an input balun (1), a plurality of stages of amplifying circuit units (2) and an output balun (3) which are connected in sequence, wherein the input balun (1) and the output balun (3) both adopt a balun structure of a single-coil laminated transformer; the amplifying circuit unit (2) adopts a pseudo-differential cascode amplifying structure.
2. The W-band pseudo-differential Cascode-structured high-gain power amplifier circuit according to claim 1, wherein said amplifier circuit unit (2) comprises a first input matching network (201), a second input matching network (202), a first common emitter transistor (203), a second common emitter transistor (204), a first input bias resistor (205), a second input bias resistor (206), a first common base transistor (207), a second common base transistor (208), a first interconnection inductor (209), a second interconnection inductor (210), a first bias decoupling capacitor (211), a second bias decoupling capacitor (212), a first bias resistor (213), a second bias resistor (214), a first output matching network (215), and a second output matching network (216),
the output end of the first input matching network (201) is respectively connected with the base of the first common emitter transistor (203) and the first end of the first input bias resistor (205);
the output end of the second input matching network (202) is respectively connected with the base of the second common emitter transistor (204) and the first end of the second input bias resistor (206);
a second end of the first input bias resistor (205) and a second end of the second input bias resistor (206) are both connected to a first bias voltage (Vbias 1);
the emitter of the first common emitter transistor (203) and the emitter of the second common emitter transistor (204) are both connected to the Ground (GND);
the collector of the first common emitter transistor (203) is connected with the first end of the first interconnection inductor (209), and the collector of the second common emitter transistor (204) is connected with the first end of the second interconnection inductor (210);
the emitter of the first common base transistor (207) is connected with the second end of the first interconnection inductor (209), the base stages are respectively connected with the first end of the first bias decoupling capacitor (211) and the first end of the first bias resistor (213), and the collector electrode is connected with the input end of the first output matching network (215);
the emitter of the second common base transistor (208) is connected with the second end of the second interconnection inductor (210), the base is respectively connected with the first end of the second bias decoupling capacitor (212) and the first end of the second bias resistor (214), and the collector is connected with the input end of the second output matching network (216);
a second end of the first bias decoupling capacitor (211) and a second end of the second bias decoupling capacitor (212) are both connected to the Ground (GND), and a second end of the first bias resistor (213) and a second end of the second bias resistor (214) are both connected to a second bias voltage (Vbias 2);
the input end of the first output matching network (215) and the input end of the second output matching network (216) are both connected with a power supply Voltage (VDD).
3. The high gain power amplifier circuit of pseudo-differential Cascode structure in W-band according to claim 2, characterized in that a single end of said input balun (1) is used as input terminal for input signal, and a differential terminal is used as output terminal for connecting respectively an input terminal of a first input matching network (201) and an input terminal of a second input matching network (202) of said amplifying circuit unit (2) of the first stage;
the differential end of the output balun (3) is used as an input end and is respectively connected with the output end of a first output matching network (215) and the output end of a second output matching network (216) of the amplification circuit unit (2) at the last stage, and a single end is used as an output end to output an amplified signal;
the output ends of the two output matching networks of the previous stage in the amplifying circuit units (2) of the two adjacent stages are correspondingly connected with the input ends of the two input matching networks (201) of the next stage.
4. The W-band pseudo-differential Cascode-structured high-gain power amplifier circuit according to claim 2, wherein said first input matching network (201) and said second input matching network (202) are of the type of an L-type matching network, a Π -type matching network, or a T-type matching network; the first output matching network (215) and the second output matching network (216) are of the type L, Π, or T.
5. The W-band pseudo-differential Cascode-structured high-gain power amplifier circuit according to claim 4, wherein said T-type matching network comprises a first matching capacitor (4), a second matching capacitor (5) and a first matching inductor (6), wherein a first end of said first matching capacitor (4) is used as an input end, a second end of said first matching capacitor (4) is respectively connected to a first end of said second matching capacitor (5) and a first end of said first matching inductor (6), a second end of said second matching capacitor (5) is used as an output end, and a second end of said first matching inductor (6) is connected to said ground end (GND);
the L-shaped matching network comprises a second matching inductor (7) and a third matching capacitor (8), wherein the first end of the second matching inductor (7) is connected with the power supply Voltage (VDD), the second end of the second matching inductor is connected with the first end of the third matching capacitor (8), the first end of the third matching capacitor (8) serves as an input end, and the second end of the third matching capacitor serves as an output end.
6. The W-band pseudo-differential Cascode-structured high-gain power amplifier circuit according to claim 5, wherein said first input matching network (201) and said second input matching network (202) are of the type of said T-type matching network, and said first output matching network (215) and said second output matching network (216) are of the type of said L-type matching network;
and the output matching network of the previous stage in the adjacent two stages of amplifying circuit units (2) shares a matching capacitor with the input matching network of the next stage correspondingly connected with the output matching network.
7. The W-band pseudo-differential Cascode-structured high-gain power amplifier circuit according to claim 5, wherein said first interconnection inductance (209), said second interconnection inductance (210), said first matching inductance (6) and said second matching inductance (7) each adopt an octagonal spiral structure.
8. The W-band pseudo-differential Cascode-structured high-gain power amplifier circuit according to claim 1, wherein said primary coil and said secondary coil of said balun structure are each in an octagonal spiral structure.
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| CN116436440A (en) * | 2023-04-20 | 2023-07-14 | 广东工业大学 | SOI stacked transistor voltage swing balancing circuit and power amplifier |
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