WO2023273456A1

WO2023273456A1 - Balance circuit and single-ended-to-differential amplifier

Info

Publication number: WO2023273456A1
Application number: PCT/CN2022/084019
Authority: WO
Inventors: 曹松松
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2021-06-29
Filing date: 2022-03-30
Publication date: 2023-01-05
Also published as: CN115549630A

Abstract

Provided in the present disclosure is a balance circuit, comprising a balun sub-circuit. The balance circuit further comprises a first auxiliary balance circuit and a second auxiliary balance circuit. The first auxiliary balance circuit comprises a first auxiliary inductor and a first auxiliary capacitor, wherein a first end of the first auxiliary inductor is electrically connected to an intermediate node of a differential output end of the balun sub-circuit, and a second end of the first auxiliary inductor is electrically connected to a first electrode of the first auxiliary capacitor; and a second electrode of the first auxiliary capacitor is configured to be grounded, and the first electrode of the first auxiliary capacitor is also configured to input a first bias signal. The second auxiliary balance circuit comprises a second auxiliary inductor and a second auxiliary capacitor, wherein a first end of the second auxiliary inductor is electrically connected to the intermediate node of the differential output end of the balun sub-circuit, and a second end of the second auxiliary inductor is electrically connected to a first electrode of the second auxiliary capacitor; and a second electrode of the second auxiliary capacitor is configured to be grounded. Further provided in the present disclosure is a single-ended-to-differential amplifier.

Description

Balanced circuits and single-ended-to-differential amplifiers

Cross References to Related Applications

This application claims priority to Patent Application No. 202110726747.5 filed with the China Patent Office on June 29, 2021, the entire contents of which are hereby incorporated by reference.

technical field

The present disclosure relates to, but is not limited to, the field of testing of communication devices.

Background technique

In the 5G millimeter-wave transceiver circuit and phased array system, the low-noise amplifier, as a key component of the receiving front-end, needs to have excellent noise figure and broadband amplification characteristics.

At present, a wide-band, low-noise, and high-balance low-noise amplifier has become the pursuit of this field.

Contents of the invention

The present disclosure provides a balanced circuit and a single-ended-to-differential amplifier.

As a first aspect of the present disclosure, a balancing circuit is provided, the balancing circuit includes a balun sub-circuit, wherein the balancing circuit further includes a first auxiliary balancing circuit and a second auxiliary balancing circuit; the first auxiliary The balance circuit includes a first auxiliary inductance and a first auxiliary capacitor, the first end of the first auxiliary inductance is electrically connected to the intermediate node of the differential output end of the balun sub-circuit, and the second end of the first auxiliary inductance is connected to the The first pole of the first auxiliary capacitor is electrically connected, the second pole of the first auxiliary capacitor is configured to be grounded, and the first pole of the first auxiliary capacitor is also configured to input a first bias signal; The two auxiliary balancing circuits include a second auxiliary inductance and a second auxiliary capacitor, the first end of the second auxiliary inductance is electrically connected to the intermediate node of the differential output end of the balun sub-circuit, and the second auxiliary inductance The terminal is electrically connected to the first pole of the second auxiliary capacitor, and the second pole of the second auxiliary capacitor is configured to be grounded.

As a second aspect of the present disclosure, a single-ended-to-differential amplifier is provided. The single-ended-to-differential amplifier includes an input-stage matching circuit, a single-ended amplifying circuit, a balancing circuit, a differential amplifying circuit, and an output-stage matching circuit, wherein, The balanced circuit is any one of the balanced circuits described herein, the output end of the single-ended amplifier circuit is electrically connected to the single-ended input end of the balun sub-circuit, and the differential of the balun sub-circuit The output terminal is electrically connected to the differential input terminal of the differential amplifier circuit.

Description of drawings

FIG. 1 is an exemplary circuit diagram of a balancing circuit provided by the present disclosure;

FIG. 2 is a block diagram of a single-ended-to-differential amplifier provided by the present disclosure;

3 is a circuit diagram of a single-ended-to-differential amplifier provided by the present disclosure;

Fig. 4 is an exemplary circuit diagram of a single-ended amplifier circuit;

5 is an exemplary circuit diagram of a differential amplifier circuit;

6 is an exemplary circuit diagram of an input stage matching circuit;

FIG. 7 is an exemplary circuit diagram of an output stage matching circuit.

detailed description

In order for those skilled in the art to better understand the technical solution of the present disclosure, the balanced circuit and the single-end-to-differential circuit provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the case of no conflict, each embodiment and each feature in the embodiment of the present disclosure can be combined with each other.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that when the terms "comprising" and/or "consisting of" are used in this specification, the presence of said features, integers, steps, operations, elements and/or components is specified, but not excluded. Add one or more other features, integers, steps, operations, elements, components and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art and the present disclosure, and will not be interpreted as having idealized or excessive formal meanings, Unless expressly so limited herein.

As a first aspect of the present disclosure, as shown in FIG. 1 , a balancing circuit 100 is provided, the balancing circuit 100 includes a balun (balun) sub-circuit 130, wherein the balancing circuit 100 also includes a first auxiliary balancing circuit 110 and the second auxiliary balancing circuit 120 .

The first auxiliary balancing circuit 110 includes a first auxiliary inductance L5 and a first auxiliary capacitor C9, the first end of the first auxiliary inductance L5 is electrically connected to the intermediate node of the differential output end of the balun sub-circuit 130, and the first end of the first auxiliary inductance L5 The two terminals are electrically connected to the first pole of the first auxiliary capacitor C9, the second pole of the first auxiliary capacitor C9 is configured to be grounded, and the first pole of the first auxiliary capacitor C9 is also configured to input the first bias signal ibias1.

The second auxiliary balancing circuit 120 includes a second auxiliary inductance L4 and a second auxiliary capacitor C8, the first end of the second auxiliary inductance L4 is electrically connected to the intermediate node of the differential output end of the balun sub-circuit 130, and the first end of the second auxiliary inductance L4 The two terminals are electrically connected to the first pole of the second auxiliary capacitor C8, and the second pole of the second auxiliary capacitor C8 is configured to be grounded.

In the balancing circuit provided in the present disclosure, in addition to the balun sub-circuit 130 for balancing, there are also two auxiliary balancing circuits (respectively the first auxiliary balancing circuit 110 and the second auxiliary balancing circuit 120), which The two auxiliary balancing circuits are tuning circuits including capacitors and inductors connected in series, which can improve the balancing performance of the entire balancing circuit, and further improve the balancing performance of the single-end-to-differential amplifier circuit including the balancing circuit.

As an exemplary embodiment, the first auxiliary inductance L5 and the second auxiliary inductance L4 can be made with a microstrip line structure, thereby improving the grounding performance of the first auxiliary balanced circuit and the second auxiliary balanced circuit, and improving the performance of the balanced circuit. Balance performance.

As shown in FIG. 2 , when the balance circuit is used in a single-ended-to-differential amplifier, it is arranged between the single-ended amplifier circuit 300 and the differential amplifier circuit 400 .

As shown in FIG. 3 and FIG. 4 , the single-ended amplifier circuit 300 is a cascode amplifier circuit, including a cas tube and a gm tube. As shown in the figure, the first pole of the cas tube is electrically connected to the grid of the cas tube, and is formed as the output terminal out of the single-ended amplifier circuit 300, and the grid of the gm tube is electrically connected to the signal input terminal in of the single-ended to differential amplifier. Connected, the second pole of the gm tube is grounded through the inductor L3.

As shown in FIG. 3 and FIG. 5 , the differential amplifier circuit 400 is a cascode differential amplifier circuit, including p (positive) cascode amplifier circuits and n (negative) cascode amplifier circuits.

P-way cascode amplifying circuit includes p-way cas tube cas_p and p-way gm tube gm_p, the first pole of p-way cas tube is formed as p-way differential output terminal of differential amplifier circuit, and the gate of p-way cas tube is used to access the gate Pole bias voltage Vb. The gate of the p-channel gm transistor is electrically connected to one end of the differential signal output end of the balance circuit 100 , and the second pole of the p-channel gm transistor is grounded through the inductor L6 .

The n-way cascode amplifying circuit includes n-way cas transistors cas_n and n-way gm transistors gm_n, and the first poles of the n-way cas transistors are formed as n-way differential output terminals of the differential amplifier circuit. The gates of the n-way gm transistors are electrically connected to the other end of the differential signal output end of the balance circuit, and the second poles of the n-way gm transistors are grounded through the inductor L7.

The balance circuit 100 is an intermediate stage matching circuit between the single-ended amplifier circuit 300 and the differential amplifier circuit 400 , which not only converts the single-ended signal into a differential signal, but also improves the balance performance.

In addition, the output terminal of the balance circuit 100 is connected to the grid of the p-way gm transistor and the grid of the n-way gm transistor of the differential amplifier circuit 400, which provides a grid terminal bias for the grid terminal of the differential amplifier circuit 400, thereby improving The integration level of the single-ended-to-differential amplifier.

In the present disclosure, the specific structure of the balun sub-circuit 130 is not particularly limited. As shown in FIG. 1 , the balun sub-circuit 130 includes a single-ended-to-differential balun 131 . Both the first auxiliary balancing circuit 110 and the second auxiliary balancing circuit 120 are electrically connected to the single-ended-to-differential balun 131 .

In order to further filter out noise, in an exemplary embodiment, the balancing circuit 100 may further include a bypass capacitor group 140, and the bypass capacitor group includes at least one bypass capacitor. The first pole of the bypass capacitor is grounded, and the second pole of the bypass capacitor is electrically connected to the high-level signal input terminal avdd of the balun sub-circuit 130 .

The AC grounding of the bypass capacitor can implement DC bias (DC bias) on the output end of the single-ended amplifier circuit 300, so that the balanced circuit has two functions of a matching network and a DC bias, thereby simplifying the single-ended amplifier circuit 300. Circuit structure of end-to-differential amplifier.

In the present disclosure, there is no special limitation on the number of bypass capacitors in the bypass capacitor bank. In the embodiment shown in FIG. 1 , the bypass capacitor group includes three bypass capacitors, which are respectively a bypass capacitor C5 , a bypass capacitor C6 , and a bypass capacitor C7 .

As mentioned above, the balun sub-circuit includes a single-ended-to-differential balun. In order to further realize a low-noise single-ended-to-differential amplifier, in an example implementation, the balun sub-circuit 130 may also include a first common mode The filter capacitor C3 and the second common-mode filter capacitor C4, the first common-mode filter capacitor C3 is connected in parallel to the single-ended input side of the single-ended to differential balun, and the second common-mode filter capacitor C4 is connected in parallel to the single-ended to differential balun len's differential output side.

In order to better optimize the balancing performance of the balancing circuit 100 , in an exemplary embodiment, the first auxiliary balancing circuit 110 and the second auxiliary balancing circuit 120 are symmetrical about the middle node of the differential output terminal of the balun sub-circuit 130 .

As a second aspect of the present disclosure, a single-ended-to-differential amplifier is provided. As shown in FIG. 2 and FIG. , a differential amplifier circuit 400 and an output stage matching circuit 500. Wherein, the balance circuit 100 is the above-mentioned balance circuit provided in the first aspect of the present disclosure, the output end of the single-ended amplifier circuit 300 is electrically connected to the single-end input end of the balun sub-circuit 130, and the differential output end of the balun sub-circuit 130 It is electrically connected with the differential input terminal of the differential amplifier circuit 400 .

In the present disclosure, the input end of the input stage matching circuit 200 is electrically connected to the general input end of the single-end-to-differential amplifier, and is configured to filter the single-end signal to be converted.

The input end of the single-ended amplifying circuit 300 is electrically connected to the output end of the input-stage matching circuit 200 , configured to amplify the signal output from the input-stage matching circuit 200 to the single-ended amplifying circuit 300 .

The balancing circuit 100 functions as a matching network and is configured to convert the single-ended amplified signal output by the single-ended amplifying circuit 300 into a differential signal.

The differential amplifier circuit 400 is configured to further amplify the differential signal output by the balancing circuit 100 .

The output stage matching circuit 500 is configured to perform further matching processing on the differential signal output by the differential amplifier circuit 400, so as to obtain a signal whose power matches the load.

As mentioned above, the balance circuit 100 includes the first auxiliary balance circuit 110 and the second auxiliary balance circuit 120, which can improve the balance performance of the balance circuit, and further improve the balance performance of the single-ended-to-differential amplifier.

In the present disclosure, the specific structure of the input stage matching circuit 200 is not specifically limited. As an exemplary implementation, as shown in FIG. 6, the input stage matching circuit 200 includes a series capacitor C1, a parallel inductor L1, and a series inductor L2, and the first pole of the series capacitor C1 is connected to the input terminal of the single-ended-to-differential amplifier. In is electrically connected, the second pole of the series capacitor C1 is electrically connected to the first terminal of the parallel inductor L1, the second terminal of the parallel inductor L1 is electrically connected to the second bias signal input terminal ibias2, and the first terminal of the series inductor L2 is electrically connected to the series The second pole of the capacitor C1 is electrically connected, and the second end of the series inductor L2 is electrically connected to the input end of the single-ended amplifier circuit 300 .

In addition to receiving the single-ended signal to be amplified, the series capacitor C1 can also isolate the DC signal. The series capacitor C1, the parallel inductor L1, and the series inductor L2 form a T-shaped bandpass matching network (also a third-order bandpass structure), which can realize broadband noise matching and broadband input impedance matching.

In order to realize the grounding of the parallel inductor L1, in an exemplary embodiment, the input stage matching circuit 200 may further include a grounding capacitor C2, the first pole of the grounding capacitor C2 is electrically connected to the second end of the parallel inductor L1, and the grounding capacitor C2 The second pole is grounded.

In this disclosure, the structure of the output stage matching circuit 500 is not particularly limited. In the embodiment shown in FIG. 7 , the output stage matching circuit 500 includes an output differential transformer (transformer) 501, a first differential matching capacitor C12, The second differential matching capacitor C13, the differential input terminal of the output differential transformer 501 is electrically connected to the output terminal of the differential amplifier circuit 400, the first differential matching capacitor C12 is connected in parallel with the output differential transformer 501 at the differential input terminal of the output stage matching circuit 500, and the second Two differential matching capacitors C13 are connected in parallel with the output differential transformer 501 at the differential output terminal of the output stage matching circuit 500 .

In order to provide a more stable output signal, in an example implementation, the output stage matching circuit 500 may further include a first decoupling capacitor C10 and a second decoupling capacitor C11, one end of the first decoupling capacitor C10 is grounded, and the The other end of the first decoupling capacitor C10 is electrically connected to the input differential tap of the output differential transformer 501, one end of the second decoupling capacitor C11 is grounded, and the other end of the second decoupling capacitor C11 is connected to the input differential tap of the output differential transformer 501. electrical connection.

In order to further expand the bandwidth of the single-ended-to-differential amplifier, in an exemplary embodiment, the output stage matching circuit 500 further includes a parallel resistor R1, and the parallel resistor R1 is connected in parallel with the first differential matching capacitor C12 at the input end of the output stage matching circuit 500 . By setting the parallel resistor R1, the Q value of the matching circuit can be reduced, thereby expanding the bandwidth of the single-ended-to-differential amplifier and improving the gain flatness of the single-ended-to-differential amplifier.

In order to isolate the DC component of the differential output of the single-ended-to-differential amplifier, in an exemplary embodiment, the output stage matching circuit 400 further includes a first DC blocking capacitor C14 and a second DC blocking capacitor C15 .

The first pole of the first DC blocking capacitor C14 is electrically connected to the first pole of the second differential matching capacitor C13, and the second pole of the first DC blocking capacitor C14 is electrically connected to the p output terminal out_p of the differential output terminal of the output stage matching circuit 500 .

The first pole of the second DC blocking capacitor C15 is electrically connected to the second pole of the second differential matching capacitor C13, and the second pole of the second DC blocking capacitor C15 is electrically connected to the n output terminal out_n of the differential output terminal of the output stage matching circuit 500 .

In the present disclosure, there is no special limitation on the application scenarios of the single-end-to-differential signal amplifier. For example, the single-ended-to-differential signal amplifier can be used in any one of 5G mobile phone radio frequency front-end chips, phased array radar receiving front-end chips, K-Ka band base station receiving front-end chips, and other millimeter-wave front-end chips.

Example embodiments have been disclosed herein, and while specific terms have been employed, they are used and should be construed in a general descriptive sense only and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics and/or elements described in connection with a particular embodiment may be used alone, or may be described in combination with other embodiments, unless expressly stated otherwise. Combinations of features and/or elements. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

A balancing circuit, the balancing circuit includes a balun sub-circuit, wherein the balancing circuit further includes a first auxiliary balancing circuit and a second auxiliary balancing circuit;

The first auxiliary balancing circuit includes a first auxiliary inductance and a first auxiliary capacitor, the first end of the first auxiliary inductance is electrically connected to the intermediate node of the differential output end of the balun sub-circuit, and the first auxiliary inductance The second terminal of the first auxiliary capacitor is electrically connected to the first pole of the first auxiliary capacitor, the second pole of the first auxiliary capacitor is configured to be grounded, and the first pole of the first auxiliary capacitor is also configured to input a first bias voltage Signal;

The second auxiliary balancing circuit includes a second auxiliary inductance and a second auxiliary capacitor, the first end of the second auxiliary inductance is electrically connected to the intermediate node of the differential output end of the balun sub-circuit, and the second auxiliary inductance The second end of the second terminal is electrically connected to the first pole of the second auxiliary capacitor, and the second pole of the second auxiliary capacitor is configured to be grounded.
The balancing circuit according to claim 1, wherein the balancing circuit includes a bypass capacitor bank, the bypass capacitor bank includes at least one bypass capacitor,

The first pole of the bypass capacitor is grounded, and the second pole of the bypass capacitor is electrically connected to the high-level signal input terminal of the balun sub-circuit.
The balance circuit according to claim 1 or 2, wherein the balun sub-circuit comprises a single-ended-to-differential balun, a first common-mode filter capacitor, and a second common-mode filter capacitor, and the first common-mode filter capacitor connected in parallel to the single-ended input side of the single-ended-to-differential balun, and the second common-mode filter capacitor is connected in parallel to the differential output side of the single-ended-to-differential balun.
The balancing circuit according to claim 1 or 2, wherein the first auxiliary balancing circuit and the second auxiliary balancing circuit are symmetrical about the middle node of the differential output terminals of the balun sub-circuits.
A single-end to differential amplifier, the single-end to differential amplifier includes an input stage matching circuit, a single-end amplification circuit, a balance circuit, a differential amplification circuit and an output stage matching circuit, wherein the balance circuit is claimed in claims 1 to 4 The balanced circuit described in any one of the above, the output end of the single-ended amplifier circuit is electrically connected to the single-ended input end of the balun sub-circuit, and the differential output end of the balun sub-circuit is connected to the differential amplifier circuit The differential input terminals are electrically connected.
The single-end-to-differential amplifier according to claim 5, wherein the input stage matching circuit includes a series capacitor, a parallel inductor, a series inductor and a ground capacitor, and the first pole of the series capacitor is connected to the single-end-to-differential amplifier. The input end of the series capacitor is electrically connected to the first end of the parallel inductance, the second end of the parallel inductance is electrically connected to the second bias signal input end, and the series inductance The first terminal is electrically connected to the second pole of the series capacitor, the second terminal of the series inductor is electrically connected to the input terminal of the single-ended amplifier circuit, and the first terminal of the ground capacitor is electrically connected to the parallel inductor. The second end is electrically connected, and the second pole of the grounding capacitor is grounded.
The single-ended-to-differential amplifier according to claim 5 or 6, wherein the output stage matching circuit includes an output differential transformer, a first differential matching capacitor, and a second differential matching capacitor, and the differential input terminal of the output differential transformer is connected to The output end of the differential amplifier circuit is electrically connected, the first differential matching capacitor is connected in parallel with the output differential transformer at the differential input end of the output stage matching circuit, and the second differential matching capacitor is matched at the output stage The differential output terminal of the circuit is connected in parallel with the output differential transformer.
The single-ended-to-differential amplifier according to claim 7, wherein the output stage matching circuit further comprises a first decoupling capacitor and a second decoupling capacitor, one end of the first decoupling capacitor is grounded, and the first The other end of the decoupling capacitor is electrically connected to the input differential tap of the output differential transformer, one end of the second decoupling capacitor is grounded, and the other end of the second decoupling capacitor is connected to the input differential tap of the output differential transformer. electrical connection.
The single-end-to-differential amplifier according to claim 8, wherein the output stage matching circuit further comprises a parallel resistor connected in parallel with the first differential matching capacitor at the input end of the output stage matching circuit.
The single-ended-to-differential amplifier according to claim 8, wherein the output stage matching circuit further comprises a first DC blocking capacitor and a second DC blocking capacitor,

The first pole of the first DC blocking capacitor is electrically connected to the first pole of the second differential matching capacitor, and the second pole of the first DC blocking capacitor is connected to the p output of the differential output terminal of the output stage matching circuit. Terminal connection;

The first pole of the second DC blocking capacitor is electrically connected to the second pole of the second differential matching capacitor, and the second pole of the second DC blocking capacitor is connected to the n output of the differential output terminal of the output stage matching circuit. electrical connection.