WO2023273456A1 - Circuit d'équilibrage et amplificateur asymétrique à différentiel - Google Patents

Circuit d'équilibrage et amplificateur asymétrique à différentiel Download PDF

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Publication number
WO2023273456A1
WO2023273456A1 PCT/CN2022/084019 CN2022084019W WO2023273456A1 WO 2023273456 A1 WO2023273456 A1 WO 2023273456A1 CN 2022084019 W CN2022084019 W CN 2022084019W WO 2023273456 A1 WO2023273456 A1 WO 2023273456A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
circuit
differential
auxiliary
output
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Application number
PCT/CN2022/084019
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English (en)
Chinese (zh)
Inventor
曹松松
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深圳市中兴微电子技术有限公司
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Publication of WO2023273456A1 publication Critical patent/WO2023273456A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/42—Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
    • H03H7/425—Balance-balance networks
    • H03H7/427—Common-mode filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45484—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit
    • H03F3/45596—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by offset reduction
    • H03F3/45618—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by offset reduction by using balancing means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/42—Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns

Definitions

  • the present disclosure relates to, but is not limited to, the field of testing of communication devices.
  • the low-noise amplifier as a key component of the receiving front-end, needs to have excellent noise figure and broadband amplification characteristics.
  • the present disclosure provides a balanced circuit and a single-ended-to-differential amplifier.
  • a balancing circuit includes a balun sub-circuit, wherein the balancing circuit further includes a first auxiliary balancing circuit and a second auxiliary balancing circuit; the first auxiliary The balance circuit includes a first auxiliary inductance and a first auxiliary capacitor, the first end of the first auxiliary inductance is electrically connected to the intermediate node of the differential output end of the balun sub-circuit, and the second end of the first auxiliary inductance is connected to the The first pole of the first auxiliary capacitor is electrically connected, the second pole of the first auxiliary capacitor is configured to be grounded, and the first pole of the first auxiliary capacitor is also configured to input a first bias signal;
  • the two auxiliary balancing circuits include a second auxiliary inductance and a second auxiliary capacitor, the first end of the second auxiliary inductance is electrically connected to the intermediate node of the differential output end of the balun sub-circuit, and the second auxiliary inductance
  • a single-ended-to-differential amplifier includes an input-stage matching circuit, a single-ended amplifying circuit, a balancing circuit, a differential amplifying circuit, and an output-stage matching circuit, wherein,
  • the balanced circuit is any one of the balanced circuits described herein, the output end of the single-ended amplifier circuit is electrically connected to the single-ended input end of the balun sub-circuit, and the differential of the balun sub-circuit The output terminal is electrically connected to the differential input terminal of the differential amplifier circuit.
  • FIG. 1 is an exemplary circuit diagram of a balancing circuit provided by the present disclosure
  • FIG. 2 is a block diagram of a single-ended-to-differential amplifier provided by the present disclosure
  • FIG. 3 is a circuit diagram of a single-ended-to-differential amplifier provided by the present disclosure
  • Fig. 4 is an exemplary circuit diagram of a single-ended amplifier circuit
  • 5 is an exemplary circuit diagram of a differential amplifier circuit
  • FIG. 6 is an exemplary circuit diagram of an input stage matching circuit
  • FIG. 7 is an exemplary circuit diagram of an output stage matching circuit.
  • a balancing circuit 100 is provided, the balancing circuit 100 includes a balun (balun) sub-circuit 130, wherein the balancing circuit 100 also includes a first auxiliary balancing circuit 110 and the second auxiliary balancing circuit 120 .
  • the first auxiliary balancing circuit 110 includes a first auxiliary inductance L5 and a first auxiliary capacitor C9, the first end of the first auxiliary inductance L5 is electrically connected to the intermediate node of the differential output end of the balun sub-circuit 130, and the first end of the first auxiliary inductance L5
  • the two terminals are electrically connected to the first pole of the first auxiliary capacitor C9, the second pole of the first auxiliary capacitor C9 is configured to be grounded, and the first pole of the first auxiliary capacitor C9 is also configured to input the first bias signal ibias1.
  • the second auxiliary balancing circuit 120 includes a second auxiliary inductance L4 and a second auxiliary capacitor C8, the first end of the second auxiliary inductance L4 is electrically connected to the intermediate node of the differential output end of the balun sub-circuit 130, and the first end of the second auxiliary inductance L4 The two terminals are electrically connected to the first pole of the second auxiliary capacitor C8, and the second pole of the second auxiliary capacitor C8 is configured to be grounded.
  • auxiliary balancing circuits in addition to the balun sub-circuit 130 for balancing, there are also two auxiliary balancing circuits (respectively the first auxiliary balancing circuit 110 and the second auxiliary balancing circuit 120), which The two auxiliary balancing circuits are tuning circuits including capacitors and inductors connected in series, which can improve the balancing performance of the entire balancing circuit, and further improve the balancing performance of the single-end-to-differential amplifier circuit including the balancing circuit.
  • the first auxiliary inductance L5 and the second auxiliary inductance L4 can be made with a microstrip line structure, thereby improving the grounding performance of the first auxiliary balanced circuit and the second auxiliary balanced circuit, and improving the performance of the balanced circuit. Balance performance.
  • the balance circuit when used in a single-ended-to-differential amplifier, it is arranged between the single-ended amplifier circuit 300 and the differential amplifier circuit 400 .
  • the single-ended amplifier circuit 300 is a cascode amplifier circuit, including a cas tube and a gm tube.
  • the first pole of the cas tube is electrically connected to the grid of the cas tube, and is formed as the output terminal out of the single-ended amplifier circuit 300, and the grid of the gm tube is electrically connected to the signal input terminal in of the single-ended to differential amplifier.
  • the second pole of the gm tube is grounded through the inductor L3.
  • the differential amplifier circuit 400 is a cascode differential amplifier circuit, including p (positive) cascode amplifier circuits and n (negative) cascode amplifier circuits.
  • P-way cascode amplifying circuit includes p-way cas tube cas_p and p-way gm tube gm_p, the first pole of p-way cas tube is formed as p-way differential output terminal of differential amplifier circuit, and the gate of p-way cas tube is used to access the gate Pole bias voltage Vb.
  • the gate of the p-channel gm transistor is electrically connected to one end of the differential signal output end of the balance circuit 100 , and the second pole of the p-channel gm transistor is grounded through the inductor L6 .
  • the n-way cascode amplifying circuit includes n-way cas transistors cas_n and n-way gm transistors gm_n, and the first poles of the n-way cas transistors are formed as n-way differential output terminals of the differential amplifier circuit.
  • the gates of the n-way gm transistors are electrically connected to the other end of the differential signal output end of the balance circuit, and the second poles of the n-way gm transistors are grounded through the inductor L7.
  • the balance circuit 100 is an intermediate stage matching circuit between the single-ended amplifier circuit 300 and the differential amplifier circuit 400 , which not only converts the single-ended signal into a differential signal, but also improves the balance performance.
  • the output terminal of the balance circuit 100 is connected to the grid of the p-way gm transistor and the grid of the n-way gm transistor of the differential amplifier circuit 400, which provides a grid terminal bias for the grid terminal of the differential amplifier circuit 400, thereby improving The integration level of the single-ended-to-differential amplifier.
  • the specific structure of the balun sub-circuit 130 is not particularly limited. As shown in FIG. 1 , the balun sub-circuit 130 includes a single-ended-to-differential balun 131 . Both the first auxiliary balancing circuit 110 and the second auxiliary balancing circuit 120 are electrically connected to the single-ended-to-differential balun 131 .
  • the balancing circuit 100 may further include a bypass capacitor group 140, and the bypass capacitor group includes at least one bypass capacitor.
  • the first pole of the bypass capacitor is grounded, and the second pole of the bypass capacitor is electrically connected to the high-level signal input terminal avdd of the balun sub-circuit 130 .
  • the AC grounding of the bypass capacitor can implement DC bias (DC bias) on the output end of the single-ended amplifier circuit 300, so that the balanced circuit has two functions of a matching network and a DC bias, thereby simplifying the single-ended amplifier circuit 300.
  • DC bias DC bias
  • the bypass capacitor group includes three bypass capacitors, which are respectively a bypass capacitor C5 , a bypass capacitor C6 , and a bypass capacitor C7 .
  • the balun sub-circuit includes a single-ended-to-differential balun.
  • the balun sub-circuit 130 may also include a first common mode The filter capacitor C3 and the second common-mode filter capacitor C4, the first common-mode filter capacitor C3 is connected in parallel to the single-ended input side of the single-ended to differential balun, and the second common-mode filter capacitor C4 is connected in parallel to the single-ended to differential balun len's differential output side.
  • the first auxiliary balancing circuit 110 and the second auxiliary balancing circuit 120 are symmetrical about the middle node of the differential output terminal of the balun sub-circuit 130 .
  • a single-ended-to-differential amplifier is provided. As shown in FIG. 2 and FIG. , a differential amplifier circuit 400 and an output stage matching circuit 500.
  • the balance circuit 100 is the above-mentioned balance circuit provided in the first aspect of the present disclosure
  • the output end of the single-ended amplifier circuit 300 is electrically connected to the single-end input end of the balun sub-circuit 130
  • the differential output end of the balun sub-circuit 130 It is electrically connected with the differential input terminal of the differential amplifier circuit 400 .
  • the input end of the input stage matching circuit 200 is electrically connected to the general input end of the single-end-to-differential amplifier, and is configured to filter the single-end signal to be converted.
  • the input end of the single-ended amplifying circuit 300 is electrically connected to the output end of the input-stage matching circuit 200 , configured to amplify the signal output from the input-stage matching circuit 200 to the single-ended amplifying circuit 300 .
  • the balancing circuit 100 functions as a matching network and is configured to convert the single-ended amplified signal output by the single-ended amplifying circuit 300 into a differential signal.
  • the differential amplifier circuit 400 is configured to further amplify the differential signal output by the balancing circuit 100 .
  • the output stage matching circuit 500 is configured to perform further matching processing on the differential signal output by the differential amplifier circuit 400, so as to obtain a signal whose power matches the load.
  • the balance circuit 100 includes the first auxiliary balance circuit 110 and the second auxiliary balance circuit 120, which can improve the balance performance of the balance circuit, and further improve the balance performance of the single-ended-to-differential amplifier.
  • the specific structure of the input stage matching circuit 200 is not specifically limited.
  • the input stage matching circuit 200 includes a series capacitor C1, a parallel inductor L1, and a series inductor L2, and the first pole of the series capacitor C1 is connected to the input terminal of the single-ended-to-differential amplifier.
  • the second pole of the series capacitor C1 is electrically connected to the first terminal of the parallel inductor L1
  • the second terminal of the parallel inductor L1 is electrically connected to the second bias signal input terminal ibias2
  • the first terminal of the series inductor L2 is electrically connected to the series
  • the second pole of the capacitor C1 is electrically connected, and the second end of the series inductor L2 is electrically connected to the input end of the single-ended amplifier circuit 300 .
  • the series capacitor C1 can also isolate the DC signal.
  • the series capacitor C1, the parallel inductor L1, and the series inductor L2 form a T-shaped bandpass matching network (also a third-order bandpass structure), which can realize broadband noise matching and broadband input impedance matching.
  • the input stage matching circuit 200 may further include a grounding capacitor C2, the first pole of the grounding capacitor C2 is electrically connected to the second end of the parallel inductor L1, and the grounding capacitor C2 The second pole is grounded.
  • the structure of the output stage matching circuit 500 is not particularly limited.
  • the output stage matching circuit 500 includes an output differential transformer (transformer) 501, a first differential matching capacitor C12, The second differential matching capacitor C13, the differential input terminal of the output differential transformer 501 is electrically connected to the output terminal of the differential amplifier circuit 400, the first differential matching capacitor C12 is connected in parallel with the output differential transformer 501 at the differential input terminal of the output stage matching circuit 500, and the second Two differential matching capacitors C13 are connected in parallel with the output differential transformer 501 at the differential output terminal of the output stage matching circuit 500 .
  • the output stage matching circuit 500 may further include a first decoupling capacitor C10 and a second decoupling capacitor C11, one end of the first decoupling capacitor C10 is grounded, and the The other end of the first decoupling capacitor C10 is electrically connected to the input differential tap of the output differential transformer 501, one end of the second decoupling capacitor C11 is grounded, and the other end of the second decoupling capacitor C11 is connected to the input differential tap of the output differential transformer 501. electrical connection.
  • the output stage matching circuit 500 further includes a parallel resistor R1, and the parallel resistor R1 is connected in parallel with the first differential matching capacitor C12 at the input end of the output stage matching circuit 500 .
  • the parallel resistor R1 By setting the parallel resistor R1, the Q value of the matching circuit can be reduced, thereby expanding the bandwidth of the single-ended-to-differential amplifier and improving the gain flatness of the single-ended-to-differential amplifier.
  • the output stage matching circuit 400 further includes a first DC blocking capacitor C14 and a second DC blocking capacitor C15 .
  • the first pole of the first DC blocking capacitor C14 is electrically connected to the first pole of the second differential matching capacitor C13, and the second pole of the first DC blocking capacitor C14 is electrically connected to the p output terminal out_p of the differential output terminal of the output stage matching circuit 500 .
  • the first pole of the second DC blocking capacitor C15 is electrically connected to the second pole of the second differential matching capacitor C13, and the second pole of the second DC blocking capacitor C15 is electrically connected to the n output terminal out_n of the differential output terminal of the output stage matching circuit 500 .
  • the single-ended-to-differential signal amplifier can be used in any one of 5G mobile phone radio frequency front-end chips, phased array radar receiving front-end chips, K-Ka band base station receiving front-end chips, and other millimeter-wave front-end chips.
  • Example embodiments have been disclosed herein, and while specific terms have been employed, they are used and should be construed in a general descriptive sense only and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics and/or elements described in connection with a particular embodiment may be used alone, or may be described in combination with other embodiments, unless expressly stated otherwise. Combinations of features and/or elements. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the scope of the present disclosure as set forth in the appended claims.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

La présente divulgation concerne un circuit d'équilibrage, comprenant un sous-circuit symétriseur. Le circuit d'équilibrage comprend en outre un premier circuit d'équilibrage auxiliaire et un deuxième circuit d'équilibrage auxiliaire. Le premier circuit d'équilibrage auxiliaire comprend un premier inducteur auxiliaire et un premier condensateur auxiliaire, une première extrémité du premier inducteur auxiliaire étant électriquement connectée à un nœud intermédiaire d'une extrémité de sortie différentielle du sous-circuit symétriseur, et une deuxième extrémité du premier inducteur auxiliaire est connectée électriquement à une première électrode du premier condensateur auxiliaire ; et une deuxième électrode du premier condensateur auxiliaire est configurée pour être mise à la terre, et la première électrode du premier condensateur auxiliaire est également configurée pour entrer un premier signal de polarisation. Le deuxième circuit d'équilibrage auxiliaire comprend un deuxième inducteur auxiliaire et un deuxième condensateur auxiliaire, une première extrémité du deuxième inducteur auxiliaire étant électriquement connectée au nœud intermédiaire de l'extrémité de sortie différentielle du sous-circuit symétriseur, et une deuxième extrémité du deuxième inducteur auxiliaire est connectée électriquement à une première électrode du deuxième condensateur auxiliaire ; et une deuxième électrode du deuxième condensateur auxiliaire est configurée pour être mise à la terre. La présente invention concerne en outre un amplificateur asymétrique à différentiel.
PCT/CN2022/084019 2021-06-29 2022-03-30 Circuit d'équilibrage et amplificateur asymétrique à différentiel WO2023273456A1 (fr)

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CN202110726747.5A CN115549630A (zh) 2021-06-29 2021-06-29 平衡电路和单端转差分放大器
CN202110726747.5 2021-06-29

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WO2023273456A1 true WO2023273456A1 (fr) 2023-01-05

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090195324A1 (en) * 2008-02-04 2009-08-06 Freescale Semiconductor, Inc. Balun transformer with improved harmonic suppression
CN103503313A (zh) * 2011-07-27 2014-01-08 松下电器产业株式会社 功率分配电路
US20150137869A1 (en) * 2013-03-05 2015-05-21 Panasonic Intellectual Property Management Co., Ltd. Mixing circuit
US20180159516A1 (en) * 2016-12-05 2018-06-07 The Regents Of The University Of California High-efficiency frequency doubler with a compensated transformer-based input balun
US20190326872A1 (en) * 2018-04-23 2019-10-24 Qualcomm Incorporated Transformer with high common-mode rejection ratio (cmrr)
CN110932687A (zh) * 2019-12-24 2020-03-27 青海民族大学 一种交流堆叠功率放大器
CN210518232U (zh) * 2019-11-29 2020-05-12 成都多普勒科技有限公司 一种用于汽车雷达收发机的毫米波功率放大器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090195324A1 (en) * 2008-02-04 2009-08-06 Freescale Semiconductor, Inc. Balun transformer with improved harmonic suppression
CN103503313A (zh) * 2011-07-27 2014-01-08 松下电器产业株式会社 功率分配电路
US20150137869A1 (en) * 2013-03-05 2015-05-21 Panasonic Intellectual Property Management Co., Ltd. Mixing circuit
US20180159516A1 (en) * 2016-12-05 2018-06-07 The Regents Of The University Of California High-efficiency frequency doubler with a compensated transformer-based input balun
US20190326872A1 (en) * 2018-04-23 2019-10-24 Qualcomm Incorporated Transformer with high common-mode rejection ratio (cmrr)
CN210518232U (zh) * 2019-11-29 2020-05-12 成都多普勒科技有限公司 一种用于汽车雷达收发机的毫米波功率放大器
CN110932687A (zh) * 2019-12-24 2020-03-27 青海民族大学 一种交流堆叠功率放大器

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