CN116266973A - 交错双侧多芯片互连 - Google Patents

交错双侧多芯片互连 Download PDF

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CN116266973A
CN116266973A CN202211152745.0A CN202211152745A CN116266973A CN 116266973 A CN116266973 A CN 116266973A CN 202211152745 A CN202211152745 A CN 202211152745A CN 116266973 A CN116266973 A CN 116266973A
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chip package
printed circuit
circuit board
chip
pins
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张硕
朱祥
M·郑
翟鹏
张涛
马杰
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Nvidia Corp
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Abstract

公开了交错双侧多芯片互连，具体公开了用于印刷电路板上的芯片封装的布局技术，其解决了将芯片封装之间的高速I/O引脚的布线距离最小化的多元问题，同时为芯片封装提供了瞬态功率需求的快速供应。布局技术还可以实现改进对芯片封装的热管理。

Description

交错双侧多芯片互连
背景技术
印刷电路板(PCB)上的净布线路径长度所引入的插入损耗和串扰噪声随着工艺节点收缩(更高的电路密度)和时钟速度的增加而恶化。芯片间通信的路径长度尤其可能限制性能。
传统上，超大集成电路设备，如图形处理单元(GPU)、中央处理单元(CPU)和片上系统(SoC)，安装在电路板上，如图1或图2所示。例如，如图1所示，中央处理单元102和图形处理单元104可以安装在印刷电路板106的同一侧。在这种情况下，最小芯片间路径长度由芯片(或更一般地，芯片封装)两侧之间的间距确定。在某些情况下，芯片上某些性能关键的引脚之间的布线长度可能长达几厘米。
另一种方法是将第一芯片封装202安装在印刷电路板206的第一侧204上，与安装在印刷电路板206的第二侧210上的第二芯片封装208直接相对。在这种情况下，最小芯片间路径长度由印刷电路板206的厚度确定。然而，由第一芯片封装202、第二芯片封装208或两者都使用的其他组件的布局受到限制。这些其他组件被限制成沿一个或另一个芯片封装放置。
附图说明
为了便于识别对任何特定元素或行为的讨论，参考标号中的最重要数字指的是首次引入该元素的图号。
图1示出了安装在印刷电路板上的并排芯片封装的示例。
图2示出了安装在印刷电路板上的堆叠芯片封装的示例。
图3A示出了安装在印刷电路板上的堆叠和交错芯片封装的示例。
图3B示出了安装在印刷电路板上的堆叠和交错芯片封装的另一个示例。
图4A示出了根据一个实施例的芯片封装上的发送和接收引脚分配(pinout)的示例。
图4B示出了根据另一实施例的芯片封装上的发送和接收引脚分配的示例。
图4C示出了根据又一实施例的芯片封装上的发送和接收引脚分配的示例。
图5A示出了安装在印刷电路板上的堆叠和交错芯片封装的又一示例。
图5B示出了根据一个实施例的主题的一个方面。
具体实施方式
超大集成电路封装(例如GPU、CPU、SOC)通常在某些操作期间(例如初始化或执行某些耗电量大的计算或输入/输出(I/O)操作时)会消耗较大的(相对于其平均工作电流)瞬态电流。诸如去耦电容器和电源模块等之类的组件应尽可能靠近芯片封装的电源引脚，以便在需要时快速提供瞬态能量。这与在芯片封装之间传送数据和命令的高速I/O引脚的要求相竞争。
公开了PCB上的芯片封装的布局技术，该技术解决了将芯片封装之间的高速I/O引脚的布线距离最小化的多元问题，同时为芯片封装提供瞬态功率需求的快速供应和/或芯片封装的热管理。
图1示出了安装在印刷电路板106上的并排芯片封装的示例。印刷电路板106包括中央处理单元102封装，中央处理单元102封装安装在印刷电路板106的同一侧，与图形处理单元104封装相邻。这种并排安装的物理约束创建了最小芯片间路径长度，这又在中央处理单元102上的电路和图形处理单元104上的电路之间施加了最大信令速率。尽管该示例涉及中央处理单元102和图形处理单元104，但它通常适用于任何类型的计算机芯片。
图2示出了安装在印刷电路板上的堆叠芯片封装的示例。第一芯片封装202安装在印刷电路板206的第一侧204上，第二芯片封装208安装在印刷电路板206的第二侧210上。第一芯片封装202和第二芯片封装208的某些或所有IO引脚可以彼此对齐，从而将它们之间的信令长度最小化为大约印刷电路板206的厚度。然而，这种安装布局具有额外的缺点，因为印刷电路板206上与第一芯片封装202和第二芯片封装208通信或给第一芯片封装202和第二芯片封装208供能的其他组件不能在它们的对侧安装在印刷电路板206上，因为该空间现在被其中一个芯片封装所占用。
图3A示出了安装在印刷电路板上的堆叠和交错芯片封装的示例。如前所述，第一芯片封装202安装在印刷电路板206的第一侧204上，第二芯片封装208安装在印刷电路板206的第二侧210上，但现在交错安装。相互通信的第一芯片封装202和第二芯片封装208的IO引脚具体位于每个封装的互连区域302中，使得当封装安装在印刷电路板206的相对侧时，它们在印刷电路板206的厚度尺寸304上彼此对齐。互连区域302在此也可称为“芯片到芯片的关键互连区域”。互连区域302包括沿第一芯片封装202的一侧以及还沿第二芯片封装208的一个重叠侧的区域。
互连区域302可在第一芯片封装和第二芯片封装的发送和接收引脚之间提供直接路由连接(例如，使用过孔)。
这种安装布局缓解了现有技术的缺陷，使得印刷电路板206上与第一芯片封装202(例如，第一芯片封装去耦电容器306)和第二芯片封装208(例如，第二芯片封装去耦电容器308)通信或给第一芯片封装202和第二芯片封装208供能的其他组件现在可以在第一芯片封装202和第二芯片封装208的对侧安装在印刷电路板206上，因为其中一个芯片封装不再占用该空间。第一芯片封装去耦电容器306位于第一芯片封装202的“安装阴影”中，即在第一芯片封装202的外围内，但在印刷电路板206的与第一芯片封装202相对的一侧。
图3B示出了一种替代方案，其中第一芯片封装电源模块310和第一芯片封装去耦电容器306彼此相邻地安装在印刷电路板206的第二侧210上，在第一芯片封装202的对侧，并且第二芯片封装去耦电容器308和第二芯片封装功率模块312彼此相邻地安装在印刷电路板206的第一侧204上，在第二芯片封装208的对侧。
图4A示出了根据一个实施例的芯片封装上的发送(TX)和接收(RX)引脚分配的示例。一个或多个均匀的发送引脚402行与一个或多个均匀的接收引脚404行沿封装406的单侧组合，得到集成电路管芯408。在一些实施例中，集成电路管芯408的所有低延迟引脚，或与另一个特定集成电路通信的基本上全部(例如，≥75％)低延迟引脚集中在单侧。“低延迟引脚”是一个引脚，其工作速率(例如时钟频率)是芯片中最快的或最快的之一(例如，在前10-20％)，因此其到其他芯片的路线长度是芯片或系统整体性能的限制因素。换句话说，它是一个性能关键引脚。“统一行”是指仅包含特定功能的引脚的行，例如仅包含数据发送(输出)引脚或仅包含数据接收(输入)引脚。在一个实施例中，接收引脚404和发送引脚402一样，都是成对排列，从而导致两行相邻的发送引脚402与两行相邻的接收引脚404相邻。这在本文中被称为引脚的“均匀行对”配置。
图4B示出了根据另一实施例的芯片封装上的发送和接收引脚分配的示例。在本实施例中，发送引脚402与接收引脚404在每一行上以1:1的比例交错，并且每一相邻行交错排列，使得每一对行沿其长度形成发送引脚402和接收引脚404的相邻对。与图4A中的实施例一样，集成电路管芯408的所有或基本上所有低延迟引脚可沿封装406的单侧集中。这在本文中被称为引脚的“交织交错行对”配置。
图4C示出了根据另一实施例的芯片封装上的发送和接收引脚分配的示例。沿封装406的一侧，发送引脚402的均匀行与接收引脚404的均匀行交织。这在本文中被称为引脚的“交织均匀行”配置。
封装406在PCB另一侧与之接口的芯片封装一侧的引脚分配是这些引脚布局的镜像，发送和接收引脚与图4A-图4C中所示的引脚的位置交换。换句话说，发送引脚/接收引脚对在PCB的厚度尺寸上彼此直接对齐。
图3A、图3B和图5A所示类型的布局，其中芯片封装在PCB的相对侧堆叠和交错，低延迟/性能关键引脚主要或完全位于每个芯片封装的单侧，在此称为“堆叠和交错布局”。
图5A和图5B示出了安装在印刷电路板上的堆叠和交错芯片封装的其他示例，其中第一芯片封装散热器502安装在第一芯片封装202上，第二芯片封装散热器504安装在第二芯片封装208上。可证明这些布局对于管理芯片封装的温度是有效的，尤其是在功率需求较高的时段期间，同时适应如前所述的布线约束。
附图元素列表
102中央处理单元
104图形处理单元
106印刷电路板
202第一芯片封装
204第一侧
206印刷电路板
208第二芯片封装
210第二侧
302互连区域
304厚度尺寸
306第一芯片封装去耦电容器
308第二芯片封装去耦电容器
310第一芯片封装电源模块
312第二芯片封装电源模块
402发送引脚
404接收引脚
406封装
408集成电路管芯
502第一芯片封装散热器
504第二芯片封装散热器
本文描述的各种功能操作可以在使用反映所述操作或功能的名词或名词短语的逻辑中实现。例如，关联操作可以由“关联器”或“相关器”执行。同样，可以通过“开关”来进行切换，可以通过“选择器”来进行选择，等等。“逻辑”是指机器存储器电路和非暂时性机器可读介质，包括机器可执行指令(软件和固件)和/或电路(硬件)，其材料和/或材料能量配置包括控制和/或程序信号，和/或可能应用来影响设备运行的设置和值(如电阻、阻抗、电容、电感、电流/电压额定值等)。磁性介质、电子电路、电气和光学存储器(易失性和非易失性)以及固件都是逻辑的例子。逻辑明确排除了纯信号或软件本身(但不排除包含软件并由此形成物质配置的机器存储器)。
在本发明中，不同实体(可不同地称为“单元”、“电路”、“其他组件等”)可被描述或声称为“配置”以执行一个或多个任务或操作。这里使用该表述——[实体]被配置为[执行一个或多个任务]——来指代结构(即，物理的东西，例如电子电路)。更具体地说，该表述用于指示该结构被布置为在操作期间执行一个或多个任务。结构可以说是“配置为”执行某些任务，即使该结构当前未被操作。“配置为将信用分配给多个处理器核的信用分配电路”旨在覆盖例如具有在操作期间执行此功能的电路的集成电路，即使所述集成电路当前未被使用(例如，电源未连接到其)。因此，被描述或叙述为“配置为”执行某些任务的实体指的是物理的东西，例如存储有可执行以实施任务的程序指令的设备、电路、存储器等。本文中该短语不用于指无形的东西。
术语“配置为”并非指“可配置为”例如，未编程的FPGA不会被视为“配置为”执行某些特定功能，尽管它可能“可配置为”在编程后执行该功能。
在所附权利要求中叙述结构“配置为”执行一个或多个任务，明确目的是不援引《美国法典》第35章第112(f)条对该权利要求要素的规定。因此，本申请中不包括[执行功能]构造的“装置”的权利要求不应根据《美国法典》第35卷第112(f)条进行解释。
如本文所用，术语“基于”用于描述影响确定的一个或多个因素。该术语不能排除其他因素可能影响决定的可能性。也就是说，确定可以仅基于指定的因素，或者基于指定的因素以及其他未指定的因素。考虑短语“基于B确定A”。该短语规定B是用于确定A或影响A的确定的因素。该短语不能阻止A的确定也可以基于其他因素，例如C。该短语还旨在涵盖A仅基于B确定的实施例。如本文所用，短语“基于”与短语“至少部分地基于”同义。
如本文所用，短语“响应于”描述了触发效应的一个或多个因素。这句话并不能排除其他因素可能会影响或触发这种影响的可能性。也就是说，效应可能仅对这些因素作出反应，也可能对指定因素以及其他未指定因素作出反应。考虑短语“响应于B而执行A”。该短语指定B是触发A的执行的因素。该短语不能阻止执行A也可能是响应其他因素，例如C。该短语还旨在涵盖仅响应于B而执行A的实施例。
如本文所用，术语“第一”、“第二”等用作其前面的名词的标签，除非另有说明，否则并不意味着任何类型的排序(例如，空间、时间、逻辑等)。例如，在具有八个寄存器的寄存器文件中，术语“第一寄存器”和“第二寄存器”可用于指代八个寄存器中的任意两个，而不是仅指逻辑寄存器0和1。
当在权利要求中使用时，术语“或”被用作包含或，而不是排他或。例如，短语“x、y或z中的至少一个”表示x、y和z中的任何一个，以及它们的任何组合。
如本文所用，关于两个或更多个元素的“和/或”的叙述应解释为仅指一个元素或元素的组合。例如，“元素A、元素B和/或元素C”可仅包括元素A、元素B、元素C、元素A和元素B、元素A和元素C、元素B和元素C，或元素A、B和C。此外，“元素A或元素B中的至少一个”可包括元素A中的至少一个、元素B中的至少一个，或者元素A中的至少一个和元素B中的至少一个。此外，“元素A和元素B中的至少一个”可以包括元素A中的至少一个、元素B中的至少一个，或者元素A中的至少一个和元素B中的至少一个。
为了满足法定要求，本文对本公开的主题进行了详细描述。然而，描述本身并不旨在限制本发明的范围。相反，发明人已经设想，所要求保护的主题也可以以其他方式体现，包括与本文件中描述的步骤类似的不同步骤或步骤组合，以及其他现有或未来技术。此外，尽管本文中可以使用术语“步骤”和/或“块”来表示所采用的方法的不同元素，但除非明确描述了各个步骤的顺序，否则这些术语不应被解释为暗示本文公开的各个步骤之间的任何特定顺序。
在详细描述了示例性实施例之后，显而易见的是，在不脱离如权利要求所述的本发明的范围的情况下，可以进行修改和变化。本发明主题的范围不限于所描绘的实施例，而是在以下权利要求中阐述。

Claims (20)

1.一种印刷电路板，包括：
第一芯片封装，其安装于所述印刷电路板的第一侧；以及
第二芯片封装，其以堆叠和交错的布局安装于所述印刷电路板的第二侧。
2.根据权利要求1所述的印刷电路板，还包括：
用于所述第一芯片封装的去耦电容器，其安装在所述第一芯片封装的安装阴影中。
3.根据权利要求2所述的印刷电路板，还包括：
用于所述第一芯片封装的散热器，其安装在所述第一芯片封装的所述安装阴影中。
4.根据权利要求2所述的印刷电路板，还包括：
用于所述第一芯片封装的电源模块，其与所述第一芯片封装相邻安装于所述印刷电路板的所述第一侧。
5.根据权利要求2所述的印刷电路板，还包括：
用于所述第二芯片封装的去耦电容器，其安装在所述第二芯片封装的安装阴影中。
6.根据权利要求5所述的印刷电路板，还包括：
用于所述第二芯片封装的散热器，其安装在所述第二芯片封装的所述安装阴影中。
7.根据权利要求5所述的印刷电路板，还包括：
用于所述第二芯片封装的电源模块，其与所述第二芯片封装相邻安装于所述印刷电路板的所述第二侧。
8.一种印刷电路板，包括：
第一芯片封装，其安装于所述印刷电路板的第一侧；
第二芯片封装，其以堆叠和交错布局安装在所述印刷电路板的第二侧；以及
所述第一印刷电路板和所述第二印刷电路板之间的互连区域，其包括所述第一芯片封装和所述第二芯片封装的发送和接收引脚之间的直接布线连接。
9.根据权利要求8所述的印刷电路板，其中所述互连区域包括引脚的均匀行对配置。
10.根据权利要求8所述的印刷电路板，其中所述互连区域包括引脚的交织交错行对配置。
11.根据权利要求8所述的印刷电路板，其中所述互连区域包括引脚的交织均匀行配置。
12.根据权利要求8所述的印刷电路板，还包括：
用于所述第一芯片封装的去耦电容器，其安装在所述第一芯片封装的安装阴影中。
13.根据权利要求12所述的印刷电路板，还包括：
用于所述第一芯片封装的散热器，其安装在所述第一芯片封装的安装阴影中。
14.根据权利要求12所述的印刷电路板，还包括：
用于所述第二芯片封装的去耦电容器，其安装在所述第二芯片封装的安装阴影中。
15.根据权利要求14所述的印刷电路板，还包括：
用于所述第二芯片封装的散热器，其安装在所述第二芯片封装的所述安装阴影中。
16.一种印刷电路板，包括：
第一芯片封装，其安装于所述印刷电路板的第一侧；
第二芯片封装，其以堆叠和交错布局安装于所述印刷电路板的第二侧；
用于所述第一芯片封装的去耦电容器和散热器，安装在所述第一芯片封装的安装阴影中；
用于所述第二芯片封装的去耦电容器和散热器，安装在所述第二芯片封装的安装阴影中；
所述第一印刷电路板和所述第二印刷电路板之间的互连区域，包括引脚的均匀行对配置、引脚的交织交错行对配置和引脚的交织均匀行配置中的一个。
17.根据权利要求16所述的印刷电路板，还包括：
用于所述第一芯片封装的电源模块，其与所述第一芯片封装相邻安装于所述印刷电路板的所述第一侧。
18.根据权利要求16所述的印刷电路板，还包括：
用于所述第二芯片封装的电源模块，其与所述第二芯片封装相邻安装于所述印刷电路板的所述第二侧。
19.根据权利要求16所述的印刷电路板，其中所述第一芯片封装为图形处理单元，所述第二芯片封装为中央处理单元。
20.根据权利要求16所述的印刷电路板，其中所述第一芯片封装和所述第二芯片封装中的至少一个包括片上系统。
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