CN116209353A - Capacitor structure and forming method thereof, semiconductor structure and forming method thereof - Google Patents

Capacitor structure and forming method thereof, semiconductor structure and forming method thereof Download PDF

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Publication number
CN116209353A
CN116209353A CN202310502553.6A CN202310502553A CN116209353A CN 116209353 A CN116209353 A CN 116209353A CN 202310502553 A CN202310502553 A CN 202310502553A CN 116209353 A CN116209353 A CN 116209353A
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China
Prior art keywords
capacitance
layer
metal layer
capacitor
capacitive
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CN202310502553.6A
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Chinese (zh)
Inventor
邹道华
高谷信一郎
刘昱玮
朱晓洁
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Changzhou Chengxin Semiconductor Co Ltd
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Changzhou Chengxin Semiconductor Co Ltd
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Priority to CN202310502553.6A priority Critical patent/CN116209353A/en
Publication of CN116209353A publication Critical patent/CN116209353A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/067—Lateral bipolar transistor in combination with diodes, or capacitors, or resistors

Abstract

A capacitor structure and a forming method thereof, a semiconductor structure and a forming method thereof relate to the technical field of semiconductor manufacturing, wherein the capacitor structure comprises: a first capacitor metal layer; the first capacitor passivation layer covers the first capacitor metal layer; the second capacitance metal layer is positioned on the first capacitance passivation layer; the second capacitance passivation layer covers the second capacitance metal layer; the third capacitance metal layer is positioned on the second capacitance passivation layer; the first capacitor dielectric layer is positioned on the third capacitor metal layer and provided with a plurality of first through holes, part of the surfaces of the third capacitor metal layer are exposed by the first through holes, and the side walls of the first through holes are inclined; and the fourth capacitance metal layer is positioned on the first capacitance dielectric layer. The inclined side wall of the first through hole is utilized to rebound a part of pressure applied during wire bonding, so that the impact of the pressure on the capacitor metal layer is reduced, and the damage to the capacitor structure is reduced. In addition, the capacitor structure is manufactured on the routing area, so that the size of the chip can be effectively reduced.

Description

Capacitor structure and forming method thereof, semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a capacitor structure and a method for forming the capacitor structure, a semiconductor structure and a method for forming the semiconductor structure.
Background
In existing integrated circuit processes, polysilicon-insulator-polysilicon capacitance structures and metal-insulator-metal capacitance structures are common devices in integrated circuits. Among them, the capacitance structure of polysilicon-insulator-polysilicon is widely used in logic circuits or flash memory circuits to prevent noise and frequency demodulation of analog devices, and the capacitance structure of metal-insulator-metal is widely used in analog circuits, radio frequency circuits or mixed signal circuits.
However, many problems remain with the current metal-insulator-metal capacitor structures.
Disclosure of Invention
The invention solves the technical problem of providing a capacitor structure and a forming method thereof, a semiconductor structure and a forming method thereof, reducing the damage to the capacitor structure caused by pressure applied during wire bonding and reducing the size of a chip.
In order to solve the above problems, the present invention provides a capacitor structure, including: a first capacitor metal layer; a first capacitance passivation layer covering the first capacitance metal layer; a second capacitive metal layer on the first capacitive passivation layer over a first portion of the first capacitive metal layer; a second capacitor passivation layer covering the second capacitor metal layer; the third capacitance metal layer is positioned on the second capacitance passivation layer and is positioned above the second capacitance metal layer; the first capacitor dielectric layer is positioned on the third capacitor metal layer, the first capacitor dielectric layer is provided with a plurality of first through holes which penetrate through the first capacitor dielectric layer, part of the surface of the third capacitor metal layer is exposed out of the first through holes, the first through holes comprise opposite first openings and second openings, the first openings are positioned on the upper surface of the first capacitor dielectric layer, the second openings are positioned on the lower surface of the first capacitor dielectric layer, and the projection range of the second openings in the direction of the first capacitor metal layer is positioned in the projection range of the first openings in the direction of the first capacitor metal layer; and the fourth capacitance metal layer is positioned on the first capacitance medium layer and is filled with a plurality of first through holes to be electrically connected with the third capacitance metal layer.
Optionally, the material of the first capacitance dielectric layer includes: a polymer; the polymer comprises: one or more of benzocyclobutene, photo-sensitive epoxy photoresist, and polyimide.
Optionally, the plurality of first through holes are distributed in a grid shape.
Optionally, an included angle between the sidewall of the first through hole and the surface of the third capacitor metal layer is: 40 degrees to 60 degrees.
Optionally, the thickness of the third capacitance metal layer is smaller than the thickness of the second capacitance metal layer; the thickness of the third capacitance metal layer is smaller than that of the fourth capacitance metal layer.
Optionally, the thickness of the third capacitor metal layer is 0.1 to 0.2 microns.
Optionally, the second capacitive passivation layer is further located on the first capacitive passivation layer covering the second portion of the first capacitive metal layer.
Optionally, the first capacitive dielectric layer is further located on the second capacitive passivation layer above the second portion.
Optionally, the method further comprises: the second through hole penetrates through the first capacitance passivation layer, the second capacitance passivation layer and the first capacitance medium layer above the second part; the fourth capacitance metal layer is also filled with the second through hole and is electrically connected with the first capacitance metal layer.
Correspondingly, the invention also provides a method for forming the capacitor structure, which comprises the following steps: forming a first capacitance metal layer; forming a first capacitance passivation layer to cover the first capacitance metal layer; forming a second capacitance metal layer on the first capacitance passivation layer and above a first portion of the first capacitance metal layer; forming a second capacitance passivation layer to cover the second capacitance metal layer; forming a third capacitance metal layer which is positioned on the second capacitance passivation layer and above the second capacitance metal layer; forming a first capacitance medium layer on the third capacitance metal layer, wherein the first capacitance medium layer is provided with a plurality of first through holes penetrating through the first capacitance medium layer, part of the surface of the third capacitance metal layer is exposed by the first through holes, the first through holes comprise opposite first openings and second openings, the first openings are positioned on the upper surface of the first capacitance medium layer, the second openings are positioned on the lower surface of the first capacitance medium layer, and the projection range of the second openings towards the first capacitance metal layer is positioned in the projection range of the first openings towards the first capacitance metal layer; and forming a fourth capacitance metal layer on the first capacitance medium layer, wherein the fourth capacitance metal layer is filled with a plurality of first through holes and is electrically connected with the third capacitance metal layer.
Optionally, the method for forming the first capacitance dielectric layer includes: forming a first capacitance dielectric material layer, wherein the first capacitance dielectric material layer covers the surface of the third capacitance metal layer; forming a patterned layer on the first capacitance dielectric material layer, wherein the patterned layer exposes part of the top surface of the first capacitance dielectric material layer; and etching the first capacitance dielectric material layer by taking the patterned layer as a mask until the top surface of the third capacitance metal layer is exposed, so as to form the first capacitance dielectric layer, wherein the first capacitance dielectric layer is provided with a plurality of first through holes exposing part of the surface of the third capacitance metal layer.
Optionally, the second capacitive passivation layer is further located on the first capacitive passivation layer covering the second portion of the first capacitive metal layer.
Optionally, the first capacitive dielectric layer is further located on the second capacitive passivation layer above the second portion.
Optionally, the method further comprises: forming a second through hole penetrating through the first capacitance passivation layer, the second capacitance passivation layer and the first capacitance dielectric layer above the second part; the fourth capacitance metal layer is also filled with the second through hole and is electrically connected with the first capacitance metal layer.
Correspondingly, the technical scheme of the invention also provides a semiconductor structure, which comprises the following components: a substrate comprising a first device region and a second device region; a device structure located on the first device region; and a capacitor structure as described above located on the second device region.
Optionally, the device structure includes: heterojunction bipolar transistor structure.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first device region and a second device region; forming a device structure on the first device region; during the formation of the device structure, a capacitor structure as described above is formed on the second device region.
Optionally, the device structure includes: heterojunction bipolar transistor structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the capacitor structure of the technical scheme of the invention comprises: the first capacitor dielectric layer is located on the third capacitor metal layer, the first capacitor dielectric layer is provided with a plurality of first through holes, the first through holes penetrate through the first capacitor dielectric layer, the plurality of first through holes expose part of the surface of the third capacitor metal layer, the first through holes comprise a first opening and a second opening which are opposite, the first opening is located on the upper surface of the first capacitor dielectric layer, the second opening is located on the lower surface of the first capacitor dielectric layer, and the projection range of the second opening on the direction of the first capacitor metal layer is located in the projection range of the first opening on the direction of the first capacitor metal layer. The inclined side wall of the first through hole is utilized to rebound a part of pressure applied during wire bonding, so that the impact of the pressure on the capacitor metal layer is reduced, and the damage to the capacitor structure is reduced. In addition, the capacitor structure is manufactured on the routing area, so that the size of the chip can be effectively reduced.
The method for forming the capacitor structure in the technical scheme of the invention comprises the following steps: the method comprises the steps of forming a first capacitance medium layer on a third capacitance metal layer, wherein the first capacitance medium layer is provided with a plurality of first through holes, penetrating through the first capacitance medium layer, exposing part of the surface of the third capacitance metal layer through the first through holes, wherein the first through holes comprise opposite first openings and second openings, the first openings are positioned on the upper surface of the first capacitance medium layer, the second openings are positioned on the lower surface of the first capacitance medium layer, and the projection range of the second openings on the direction of the first capacitance metal layer is positioned in the projection range of the first openings on the direction of the first capacitance metal layer. The inclined side wall of the first through hole is utilized to rebound a part of pressure applied during wire bonding, so that the impact of the pressure on the capacitor metal layer is reduced, and the damage to the capacitor structure is reduced. In addition, the capacitor structure is manufactured on the routing area, so that the size of the chip can be effectively reduced.
According to the method for forming the semiconductor structure, disclosed by the invention, the capacitor structure is synchronously formed in the process of forming the device structure, so that the process steps can be effectively simplified, the process efficiency can be improved, and the manufacturing cost can be reduced.
Drawings
FIG. 1 is a schematic diagram of a capacitor structure;
fig. 2 to fig. 6 are schematic structural views illustrating steps of a method for forming a capacitor structure according to an embodiment of the invention;
fig. 7 to 8 are schematic views illustrating steps of a method for forming a capacitor structure according to another embodiment of the present invention;
FIGS. 9-17 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 18 to 20 are schematic views illustrating steps of a method for forming a semiconductor structure according to another embodiment of the present invention.
Detailed Description
As described in the background, there are still many problems with the current metal-insulator-metal capacitor structures. The following will make a detailed description with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a capacitor structure.
Referring to fig. 1, a capacitor structure includes: a first capacitive metal layer 101; a first capacitance passivation layer 103 covering the first capacitance metal layer 101; a second capacitance metal layer 102 on the first capacitance passivation layer 103 and above the first portion of the first capacitance metal layer 101; a second capacitance passivation layer 104 covering the second capacitance metal layer 102; a third capacitive metal layer 105 is located on the second capacitive passivation layer 104 and is located above the second capacitive metal layer 102.
In this embodiment, the first capacitor metal layer 101, the first capacitor passivation layer 103 and the second capacitor metal layer 102 are used to form a basic capacitor structure, and the dielectric between the capacitor metal layers is continuously added to the basic capacitor structure in the subsequent process, so as to form a series connection or a parallel connection of the multi-capacitor structure. However, the current capacitor structure has poor self-buffering property, and the capacitor structure is easily damaged by the force applied to the wire bonding area when the wire bonding process is performed on the wire bonding area.
At present, the capacitor structure can be manufactured by moving to the side edge of the wire bonding area, but the capacitor structure occupies a larger space area, which is not beneficial to reducing the size of the chip.
On the basis, the invention provides a capacitor structure, a forming method thereof, a semiconductor structure and a forming method thereof, wherein a first through hole of a first capacitor dielectric layer comprises a first opening and a second opening which are opposite, the first opening is positioned on the upper surface of the first capacitor dielectric layer, the second opening is positioned on the lower surface of the first capacitor dielectric layer, and the projection range of the second opening in the direction of the first capacitor metal layer is positioned in the projection range of the first opening in the direction of the first capacitor metal layer. The inclined side wall of the first through hole is utilized to rebound a part of pressure applied during wire bonding, so that the impact of the pressure on the capacitor metal layer is reduced, and the damage to the capacitor structure is reduced. In addition, the capacitor structure is manufactured on the routing area, so that the size of the chip can be effectively reduced.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 2 to fig. 6 are schematic structural diagrams illustrating steps of a method for forming a capacitor structure according to an embodiment of the invention.
Referring to fig. 2, a first capacitor metal layer 201 is formed; forming a first capacitance passivation layer 203 covering the first capacitance metal layer 201; a second capacitive metal layer 202 is formed on the first capacitive passivation layer 203 over a first portion (not shown) of the first capacitive metal layer 201.
In this embodiment, the first capacitor metal layer 201, the first capacitor passivation layer 203 and the second capacitor metal layer 202 are used to form a basic capacitor structure, and the dielectric between the capacitor metal layers is continuously added to the basic capacitor structure in the subsequent process, so as to form a series or parallel connection of multiple capacitor structures.
In this embodiment, the first portion of the first capacitor metal layer 201 is a portion of the capacitor itself, and a facing area is between the first portion of the first capacitor metal layer 201 and the second capacitor metal layer 202.
In this embodiment, the material of the first capacitance passivation layer 203 is silicon nitride.
Referring to fig. 3, a second capacitor passivation layer 204 is formed to cover the second capacitor metal layer 202.
In this embodiment, the material of the second capacitor passivation layer 204 is silicon nitride.
Referring to fig. 4, a third capacitor metal layer 205 is formed on the second capacitor passivation layer 204 and above the second capacitor metal layer 202.
In this embodiment, the thickness of the third capacitance metal layer 205 is smaller than the thickness of the second capacitance metal layer 202. The resistance of the third capacitor metal layer 205 is increased by forming the third capacitor metal layer 205 with a smaller thickness. When the current is applied to the center of the third capacitor metal layer 205, the current flowing to the edge of the third capacitor metal layer 205 is small, so that the electric field at the edge of the third capacitor metal layer 205 is reduced, and the electric field breakdown between the third capacitor metal layer 205 and the second capacitor metal layer 202 below can be prevented.
In this embodiment, the thickness of the third capacitance metal layer 205 is 0.1 to 0.2 micrometers.
In this embodiment, the projection range of the third capacitance metal layer 205 in the direction toward the first capacitance metal layer 201 is within the projection range of the second capacitance metal layer 202 in the direction toward the first capacitance metal layer 201. By reducing the area of the third capacitance metal layer 205, the edge of the third capacitance metal layer 205 is prevented from being opposite to the edge of the second capacitance metal layer 202, so that the electric field breakdown caused by the tip discharge between the third capacitance metal layer 205 and the second capacitance metal layer 202 below can be prevented.
In this embodiment, the second capacitive passivation layer 204 is further located on the first capacitive passivation layer 203 covering a second portion (not shown) of the first capacitive metal layer 201.
In this embodiment, the second portion of the first capacitor metal layer 201 is used to form a portion of the capacitor structure connected in series or parallel, and the second portion of the first capacitor metal layer 201 and the first portion of the first capacitor metal layer 201 are adjacent to each other to form the first capacitor metal layer 201 together.
Referring to fig. 5, a first capacitor dielectric layer 206 is formed on the third capacitor dielectric layer 205, the first capacitor dielectric layer 206 has a plurality of first through holes 207 penetrating the first capacitor dielectric layer 206, and the plurality of first through holes 207 expose a portion of the surface of the third capacitor dielectric layer 205, the first through holes 207 include opposite first openings and second openings, the first openings are located on the upper surface of the first capacitor dielectric layer 206, the second openings are located on the lower surface of the first capacitor dielectric layer 206, and a projection range of the second openings in a direction towards the first capacitor dielectric layer 201 is located in a projection range of the first openings in a direction towards the first capacitor dielectric layer 201.
In this embodiment, the inclined side wall of the first through hole 207 can rebound a part of pressure applied during wire bonding, so as to reduce impact of the pressure on the capacitor metal layer and reduce damage to the capacitor structure. In addition, the capacitor structure is manufactured on the routing area, so that the size of the chip can be effectively reduced.
In this embodiment, the method for forming the first capacitance medium layer 206 includes: forming a first capacitance dielectric material layer (not shown) covering the surface of the third capacitance metal layer 205; forming a patterned layer (not shown) on the first capacitive dielectric material layer, the patterned layer exposing a portion of a top surface of the first capacitive dielectric material layer; the patterned layer is used as a mask to etch the first capacitance dielectric material layer until the top surface of the third capacitance metal layer 205 is exposed, so as to form the first capacitance dielectric layer 206, and the first capacitance dielectric layer 206 has a plurality of first through holes 207 exposing a part of the surface of the third capacitance metal layer 205.
In this embodiment, the included angle between the sidewall of the first via 207 and the top surface of the third capacitance metal layer 205 is: 40 degrees to 60 degrees.
In this embodiment, the plurality of first through holes 207 are distributed in a grid shape.
In this embodiment, the materials of the first capacitive dielectric layer 206 include: a polymer; the polymer comprises: one or more of benzocyclobutene, photo-sensitive epoxy photoresist, and polyimide. The first capacitance dielectric layer 206 is made of a macromolecular material, and the compactness of the material is lower and the thickness is larger, so that the material has better buffering property. When the subsequent wire bonding process is performed in the wire bonding area, the first capacitor dielectric layer 206 is utilized to provide a better buffering effect for the capacitor structure in the wire bonding area, so that the damage to the capacitor structure caused by the pressure applied during wire bonding is further reduced.
In this embodiment, the first capacitive dielectric layer 206 is also located on the second capacitive passivation layer 204 over the second portion.
In this embodiment, further comprising: a second via 200 is formed through the first capacitive passivation layer 203, the second capacitive passivation layer 204 and the first capacitive dielectric layer 206 over the second portion.
Referring to fig. 6, a fourth capacitor metal layer 208 is formed on the first capacitor dielectric layer 206, and the fourth capacitor metal layer 208 is filled with a plurality of first vias 207 and electrically connected to the third capacitor metal layer 205.
In this embodiment, the projections of the fourth capacitance metal layer 208, the third capacitance metal layer 205 and the second capacitance metal layer 202 in the direction toward the first capacitance metal layer 201 have overlapping areas.
In this embodiment, the projection range of the second capacitance metal layer 202 toward the upper surface of the first capacitance metal layer 201 is within the range of the upper surface of the first capacitance metal layer 201; the fourth capacitance metal layer 208 also fills the second through hole 200 and is electrically connected to the first capacitance metal layer 201.
In this embodiment, a parallel structure of 2 capacitors is formed.
In this embodiment, the thickness of the third capacitance metal layer 205 is smaller than the thickness of the fourth capacitance metal layer 208.
Accordingly, in an embodiment of the present invention, a capacitor structure is further provided, please continue to refer to fig. 6, which includes: a first capacitive metal layer 201; a first capacitance passivation layer 203 covering the first capacitance metal layer 201; a second capacitance metal layer 202 on the first capacitance passivation layer 203, over a first portion of the first capacitance metal layer 201; a second capacitance passivation layer 204 covering the second capacitance metal layer 202; a third capacitance metal layer 205 on the second capacitance passivation layer 204, and above the second capacitance metal layer 202; the first capacitor dielectric layer 206 is located on the third capacitor dielectric layer 205, the first capacitor dielectric layer 206 has a plurality of first through holes 207 penetrating through the first capacitor dielectric layer 206, and a part of the surface of the third capacitor dielectric layer 205 is exposed by the plurality of first through holes 207, the first through holes 207 include opposite first openings and second openings, the first openings are located on the upper surface of the first capacitor dielectric layer 206, the second openings are located on the lower surface of the first capacitor dielectric layer 206, and the projection range of the second openings in the direction of the first capacitor dielectric layer 201 is located in the projection range of the first openings in the direction of the first capacitor dielectric layer 201; the fourth capacitor metal layer 208 is located on the first capacitor dielectric layer 206, and the fourth capacitor metal layer 208 is filled with a plurality of first vias 207 and electrically connected to the third capacitor metal layer 205.
In this embodiment, the inclined side wall of the first through hole 207 can rebound a part of pressure applied during wire bonding, so as to reduce impact of the pressure on the capacitor metal layer and reduce damage to the capacitor structure. In addition, the capacitor structure is manufactured on the routing area, so that the size of the chip can be effectively reduced.
In this embodiment, the material of the first capacitive dielectric layer includes: a polymer; the polymer comprises: one or more of benzocyclobutene, photo-sensitive epoxy photoresist, and polyimide. The first capacitance dielectric layer 206 is made of a macromolecular material, and the compactness of the material is lower and the thickness is larger, so that the material has better buffering property. When the subsequent wire bonding process is performed in the wire bonding area, the first capacitor dielectric layer 206 is utilized to provide a better buffering effect for the capacitor structure in the wire bonding area, so that the damage to the capacitor structure caused by the pressure applied during wire bonding is further reduced.
In this embodiment, the plurality of first through holes 207 are distributed in a grid shape.
In this embodiment, an included angle between the sidewall of the first via 207 and the top surface of the third capacitor metal layer is: 40 degrees to 60 degrees.
In this embodiment, the thickness of the third capacitance metal layer 205 is smaller than the thickness of the second capacitance metal layer 202; the thickness of the third capacitor metal layer 205 is smaller than the thickness of the fourth capacitor metal layer 208. The resistance of the third capacitor metal layer 205 is increased by forming the third capacitor metal layer 205 with a smaller thickness. When the current is applied to the center of the third capacitor metal layer 205, the current flowing to the edge of the third capacitor metal layer 205 is small, so that the electric field at the edge of the third capacitor metal layer 205 is reduced, and the electric field breakdown between the third capacitor metal layer 205 and the second capacitor metal layer 202 below can be prevented.
In this embodiment, the thickness of the third capacitance metal layer 205 is 0.1 to 0.2 micrometers.
In this embodiment, the projection range of the third capacitance metal layer 205 in the direction toward the first capacitance metal layer 201 is within the projection range of the second capacitance metal layer 202 in the direction toward the first capacitance metal layer 201. By reducing the area of the third capacitance metal layer 205, the edge of the third capacitance metal layer 205 is prevented from being opposite to the edge of the second capacitance metal layer 202, so that the electric field breakdown caused by the tip discharge between the third capacitance metal layer 205 and the second capacitance metal layer 202 below can be prevented.
In this embodiment, the second capacitive passivation layer 204 is also located on the first capacitive passivation layer 203 covering the second portion of the first capacitive metal layer 201.
In this embodiment, the first capacitive dielectric layer 206 is also located on the second capacitive passivation layer 204 over the second portion.
In this embodiment, further comprising: a second via 200 penetrating the first capacitive passivation layer 203, the second capacitive passivation layer 204, and the first capacitive dielectric layer 206 over the second portion; the fourth capacitance metal layer 208 also fills the second through hole 200 and is electrically connected to the first capacitance metal layer 201.
Fig. 7 to 8 are schematic structural diagrams illustrating steps of a method for forming a capacitor structure according to another embodiment of the invention.
The present embodiment is a description of a method for forming a capacitor structure based on the above embodiment (refer to fig. 6), and is different from the above embodiment in that: forming a structure with 3 capacitors connected in parallel. The specific forming process is shown in fig. 7 to 8.
Referring to fig. 7, a second capacitance dielectric layer 301 is formed on the fourth capacitance metal layer 208.
In this embodiment, the materials of the second capacitive dielectric layer 301 include: a polymer; the polymer comprises: one or more of benzocyclobutene, photo-sensitive epoxy photoresist, and polyimide.
Referring to fig. 8, a fifth capacitance metal layer 302 is formed on the second capacitance medium layer 301, and projections of the fifth capacitance metal layer 302, the fourth capacitance metal layer 208, the third capacitance metal layer 205 and the second capacitance metal layer 202 in a direction toward the first capacitance metal layer 201 have overlapping areas.
In this embodiment, a parallel structure of 3 capacitors is formed.
Correspondingly, in the embodiment of the present invention, further, please refer to fig. 8, and the description of the capacitor structure is continued based on the above embodiment (please refer to fig. 6), and compared with the above embodiment, the difference in this embodiment is that the capacitor structure further includes:
a second capacitive dielectric layer 301 on the fourth capacitive metal layer 208; a fifth capacitance metal layer 302 located on the second capacitance medium layer 301, where the projections of the fifth capacitance metal layer 302, the fourth capacitance metal layer 208, the third capacitance metal layer 205 and the second capacitance metal layer 202 in the direction towards the first capacitance metal layer 201 have overlapping areas.
Fig. 9 to 17 are schematic views illustrating the structure of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate 400, wherein the substrate 400 comprises a first device region I and a second device region II; forming a device structure on the first device region I; during the formation of the device structure, a capacitor structure as described above is formed on the second device region II.
In this embodiment, the capacitor structure is formed simultaneously in the process of forming the device structure, so that the process steps can be effectively simplified, the process efficiency can be improved, and the manufacturing cost can be reduced.
In this embodiment, the device structure is a heterojunction bipolar transistor structure.
The method of forming the semiconductor structure will be described in detail below taking the device structure as an example of a heterojunction bipolar transistor structure.
Referring to fig. 9, a substrate 400 is provided, the substrate 400 including a first device region I and a second device region II.
In this embodiment, the material of the substrate 400 is silicon.
In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group III-donor elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the III-group element multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
In this embodiment, the first device region I is used to form a heterojunction bipolar transistor, the second device region II is used to form the capacitor structure, and a wire bonding process is performed on the second device region II.
Referring to fig. 10, a collector layer 401 is formed on the substrate 400; forming a base layer 402, a collector electrode 403, and a first capacitance metal layer 404 on the collector layer 401; forming an emission layer 405 and a base electrode 406 on the base layer 402; an emitter electrode 407 is formed on the emitter layer 405, the collector electrode 403, the base layer 402, the base layer electrode 406, the emitter layer 405, and the emitter layer electrode 407 are located in the first device region I, and the first capacitor metal layer 404 is located in the second device region II.
In this embodiment, the emitter electrode 407 is in ohmic contact with the emitter layer 405.
The emission layer electrode 407 includes a multi-layered structure.
In this embodiment, the emitter electrode 407 is a multilayer metal layer of a titanium (Ti) film, a platinum (Pt) film, a Ti film, a Pt film, and a Ti film, which are stacked in this order.
In this embodiment, the base layer electrode 406 is in ohmic contact with the base layer 402.
The base electrode 406 includes a multi-layered structure.
In this embodiment, the base electrode 406 is a multi-layered metal layer in which a Pt film, a Ti film, a Pt film, and a gold (Au) film are sequentially stacked.
In this embodiment, the collector electrode 403 is in ohmic contact with the collector 401.
In this embodiment, the collector electrode 403 and the first capacitor metal layer 404 are formed based on the same metal material layer, and the collector electrode 403 and the first capacitor metal layer 404 are each in a multilayer structure.
In this embodiment, the collector electrode 403 and the first capacitor metal layer 404 are each a plurality of metal layers in which a Ti film and an Au film are sequentially stacked.
In the present embodiment, an emission layer structure in a heterojunction bipolar transistor structure is constituted by the emission layer 405 and the emission layer electrode 407; a base layer structure in a heterojunction bipolar transistor structure is formed by the base layer 402 and the base layer electrode 406; the collector layer 401 and the collector layer electrode 403 form a collector layer structure in a heterojunction bipolar transistor structure.
The collector layer 401 is doped with first ions; the base layer 402 is doped with a second ion, the first ion having a different electrical type than the second ion, the second ion having a doping concentration greater than the first ion.
The emitter layer 405 is doped with a third ion, the third ion has a different electrical type from the second ion, the third ion has a same electrical type as the first ion, the third ion has a doping concentration greater than the first ion, and the third ion has a doping concentration less than the second ion.
In this embodiment, the collector layer 401 has a doping concentration of 1E16atoms/cm 3 N-type gallium arsenide (GaAs); the base layer 402 has a doping concentration of 1E19atoms/cm 3 P-type gallium arsenide of (a); the emitter layer 405 has a doping concentration of 1E17atoms/cm 3 N-type gallium arsenide of (c).
Referring to fig. 11, a first passivation layer is formed, the first passivation layer includes a first device passivation layer 408 and a first capacitor passivation layer 409, the first device passivation layer 408 is located on the first device region I, and the first device passivation layer 408 exposes a portion of the top surface of the collector electrode 403, a portion of the top surface of the base electrode 406, and a portion of the top surface of the emitter electrode 407, the first capacitor passivation layer 409 is located on the second device region II, and the first capacitor passivation layer 409 exposes a portion of the top surface of the first capacitor metal layer 404.
In this embodiment, the first passivation layer is formed by a chemical vapor deposition process.
In this embodiment, the material of the first passivation layer is silicon nitride.
In this embodiment, a third via 421 exposing a portion of the top surface of the first capacitor metal layer 404 is formed in the first capacitor passivation layer 409.
Referring to fig. 12, a first metal layer is formed, the first metal layer includes a first device metal layer 410 and a second capacitor metal layer 411, the first device metal layer 410 is located on the first device region I, the first device metal layer 410 is located on the exposed top surface of the collector electrode 403, the exposed top surface of the base electrode 406, and the exposed top surface of the emitter electrode 407, the second capacitor metal layer 411 is located on the second device region II, the second capacitor metal layer 411 is located on the first capacitor passivation layer 409, and the second capacitor metal layer 411 is exposed to the third via 421.
In this embodiment, the first metal layer is formed by a photoresist exposure, metal evaporation, metal stripping, and photoresist stripping process.
Referring to fig. 13, a second passivation layer is formed on the surface of the first metal layer and the surface of the first passivation layer, the second passivation layer includes a second device passivation layer 412 and a second capacitor passivation layer 413, the second device passivation layer 412 is located on the first device region I, the second device passivation layer 412 covers the surface of the first device metal layer 410, the second capacitor passivation layer 413 is located on the second device region II, the second capacitor passivation layer 413 covers the surface of the second capacitor metal layer 411, and the second capacitor passivation layer 413 fills the third via 421.
In this embodiment, the second passivation layer is formed by a chemical vapor deposition process.
In this embodiment, the material of the second passivation layer is silicon nitride.
Referring to fig. 14, a third capacitor metal layer 414 is formed on the second capacitor passivation layer 413.
In this embodiment, the thickness of the third capacitance metal layer 414 is smaller than the thickness of the second capacitance metal layer 411. The resistance of the third capacitor metal layer 414 is increased by forming the third capacitor metal layer 414 to have a smaller thickness. When the current is applied to the center of the third capacitor metal layer 414, the current flowing to the edge of the third capacitor metal layer 414 is small, so that the electric field at the edge of the third capacitor metal layer 414 is reduced, and the electric field breakdown between the third capacitor metal layer 414 and the second capacitor metal layer 411 below can be prevented.
In this embodiment, the thickness of the third capacitor metal layer 414 is 0.1 to 0.2 microns.
In this embodiment, the projection range of the third capacitance metal layer 414 on the substrate 400 is within the projection range of the second capacitance metal layer 411 on the substrate 400. By reducing the area of the third capacitor metal layer 414, the edge of the third capacitor metal layer 414 is prevented from being opposite to the edge of the second capacitor metal layer 411, so that electric field breakdown caused by the tip discharge between the third capacitor metal layer 414 and the second capacitor metal layer 411 below can be prevented.
Referring to fig. 15, a first dielectric layer is formed on the surface of the third capacitor metal layer 414 and the surface of the second passivation layer, where the first dielectric layer includes a first device dielectric layer 415 and a first capacitor dielectric layer 416, the first device dielectric layer 415 is located on the first device region I, the first device dielectric layer 415 exposes a portion of the top surface of the second device passivation layer 412, the first capacitor dielectric layer 416 is located on the second device region II, and a plurality of first through holes 423 exposing a portion of the top surface of the third capacitor metal layer 414 are formed in the first capacitor dielectric layer 416, the first through holes 423 include opposite first openings and second openings, the first openings are located on the top surface of the first capacitor dielectric layer 416, the second openings are located on the bottom surface of the first capacitor dielectric layer 416, and a projection range of the second openings in a direction toward the first capacitor metal layer 404 is located in a projection range of the first openings in a direction toward the first capacitor metal layer 404.
In this embodiment, the inclined side wall of the first through hole 423 is used to rebound a part of pressure applied during wire bonding, so as to reduce impact of the pressure on the capacitor metal layer and reduce damage to the capacitor structure.
In this embodiment, the method for forming the first dielectric layer includes: forming a first dielectric material layer (not shown) that covers the third capacitor metal layer 414 surface and the second passivation layer surface; forming a patterned layer on the first dielectric material layer, wherein the patterned layer exposes part of the top surface of the first dielectric material layer; and etching the first dielectric material layer by taking the patterned layer as a mask until the top surface of the third capacitance metal layer 414 is exposed, wherein the first dielectric layer is formed, and the first capacitance dielectric layer 416 of the first dielectric layer is provided with a plurality of first through holes 423 exposing part of the surface of the third capacitance metal layer 414.
In this embodiment, the plurality of first through holes 423 are distributed in a grid shape.
In this embodiment, an included angle between the sidewall of the first via 423 and the top surface of the third capacitor metal layer 414 is: 40 degrees to 60 degrees.
In this embodiment, after etching the first capacitance dielectric material layer and exposing the third capacitance metal layer 414, the method further includes: continuing to etch the first capacitance dielectric material layer and the second capacitance passivation layer 413 by using the patterned layer as a mask to form a fourth through hole 422; after the fourth via 422 is formed, the second capacitor passivation layer 413 exposed by the fourth via 422 and located in the third via 421 is etched until the top surface of the first capacitor metal layer 404 is exposed, so that the third via 421 is not filled.
In the present embodiment, the second through hole is constituted by the third through hole 421 and the fourth through hole 422.
In the present embodiment, the projections of the fourth through hole 422 and the third through hole 421 on the substrate 400 have an overlapping area. By forming the third through hole 421 in the first capacitance passivation layer 409 in advance, the time for etching the second capacitance passivation layer 413 and the first capacitance passivation layer 409 by using the first dielectric layer as a mask later is reduced, and thus the synchronous etching damage to the third capacitance metal layer 414 is reduced.
In this embodiment, the method for forming the first dielectric layer includes: forming an initial first dielectric layer (not shown) on the surface of the third capacitance metal layer 414 and the surface of the second passivation layer; and carrying out graphical processing on the initial first dielectric layer to form the first dielectric layer.
In this embodiment, the material of the first dielectric layer includes: a polymer; the polymer comprises: one or more of benzocyclobutene, photo-sensitive epoxy photoresist, and polyimide. Because the first capacitance medium layer 416 is made of a macromolecular material, the compactness of the material is lower and the thickness is larger, so that the material has better buffering property. When the second device region II is subjected to the subsequent wire bonding process, the first capacitance medium layer 416 can provide a better buffering effect for the capacitance structure on the second device region II, so as to reduce the damage to the capacitance structure caused by the pressure applied during wire bonding.
With continued reference to fig. 15, in this embodiment, the second device passivation layer 412, the second capacitor passivation layer 413 and the first capacitor passivation layer 409 are etched using the first dielectric layer as a mask, so as to expose the top surface of the first device metal layer 410 and the top surface of the first capacitor metal layer 404.
In this embodiment, since the third capacitance metal layer 414 is different from the materials of the second device passivation layer 412, the second capacitance passivation layer 413 and the first capacitance passivation layer 409, by selecting the etching solution, it is ensured that less simultaneous etching damage is caused to the third capacitance metal layer 414 in the etching process of the second device passivation layer 412, the second capacitance passivation layer 413 and the first capacitance passivation layer 409.
Referring to fig. 16, a second metal layer is formed, the second metal layer includes a second device metal layer 417 and a fourth capacitor metal layer 418, the second device metal layer 417 is located on the first device region I, the second device metal layer 417 is located on the exposed top surface of the first device metal layer 410, the fourth capacitor metal layer 418 is located on the second device region II, the fourth capacitor metal layer 418 is located on the first capacitor dielectric layer 416 and is in contact with the third capacitor metal layer 414, and projections of the fourth capacitor metal layer 418, the third capacitor metal layer 414, the second capacitor metal layer 411 and the first capacitor metal layer 404 on the substrate 400 have overlapping areas.
In this embodiment, the second metal layer is formed by a photoresist exposure, metal evaporation, metal stripping, and photoresist stripping process.
In this embodiment, the thickness of the third capacitance metal layer 414 is smaller than the thickness of the fourth capacitance metal layer 418.
In this embodiment, the fourth capacitance metal layer 418 is further in contact with the first capacitance metal layer 404, and a parallel structure of 2 capacitances is formed by the first capacitance metal layer 404, the first capacitance passivation layer 409, the second capacitance metal layer 411, the second capacitance passivation layer 413, and the fourth capacitance metal layer 418.
In other embodiments, the fourth capacitance metal layer may not contact the first capacitance metal layer, and the corresponding first capacitance dielectric layer does not have the second via hole therein.
In this embodiment, the capacitor structure may be fabricated on the second device region II, so that the size of the chip may be effectively reduced.
Referring to fig. 17, a third passivation layer is formed on the second metal layer and the first dielectric layer, where the third passivation layer includes a third device passivation layer 419 and a third capacitor passivation layer 420, the third device passivation layer 419 is located in the first device region I, and the third device passivation layer 419 completely covers the surface of the second device metal layer 417, the third capacitor passivation layer 420 is located on the second device region II, and the third capacitor passivation layer 420 exposes the fourth capacitor metal layer 418 having a projection overlapping area with the third capacitor metal layer 414 on the substrate 400.
In this embodiment, the material of the third passivation layer is silicon nitride.
In this embodiment, a wire bonding process is performed on the surface of the fourth capacitor metal layer 418 exposed by the third capacitor passivation layer 420.
Accordingly, in an embodiment of the present invention, a semiconductor structure is further provided, please continue to refer to fig. 17, which includes: a substrate 400, the substrate 400 comprising a first device region I and a second device region II; a device structure located on the first device region I; and a capacitor structure as described above located on the second device region II.
In this embodiment, the device structure is a heterojunction bipolar transistor structure.
In this embodiment, the semiconductor structure specifically includes: a substrate 400, a collector layer 401 on the substrate 400, a base layer 402 on the collector layer 401, a collector layer electrode 403 and a first capacitive metal layer 404, an emitter layer 405 and a base layer electrode 406 on the base layer 402, and an emitter layer electrode 407 on the emitter layer 405, the collector layer electrode 403, the base layer electrode 406, the emitter layer electrode 407 being located in the first device region I, the first capacitive metal layer 404 being located in the second device region II; a first passivation layer on the surface of the semiconductor structure, the first passivation layer including a first device passivation layer 408 and a first capacitance passivation layer 409, the first device passivation layer 408 being on the first device region I, and the first device passivation layer 408 exposing a portion of the top surface of the collector electrode 403, a portion of the top surface of the base electrode 406, and a portion of the top surface of the emitter electrode 407, the first capacitance passivation layer 409 being on the second device region II, and the first capacitance passivation layer 409 covering a surface of the first capacitance metal layer 404; a first metal layer, the first metal layer including a first device metal layer 410 and a second capacitor metal layer 411, the first device metal layer 410 being located on the first device region I, and the first device metal layer 410 being located on the exposed top surface of the collector layer electrode 403, the top surface of the base layer electrode 406, and the top surface of the emitter layer electrode 407, the second capacitor metal layer 411 being located on the second device region II, and the second capacitor metal layer 411 being located on the first capacitor passivation layer 409; a second passivation layer on the first metal layer surface and the first passivation layer surface, the second passivation layer including a second device passivation layer 412 and a second capacitance passivation layer 413, the second device passivation layer 412 being on the first device region I and the second device passivation layer 412 exposing a surface of the first device metal layer 410, the second capacitance passivation layer 413 being on the second device region II and the second capacitance passivation layer 413 covering a surface of the second capacitance metal layer 411, the second capacitance passivation layer 413 exposing a portion of a top surface of the first capacitance metal layer 404; a third capacitive metal layer 414 on the second capacitive passivation layer 413; the first dielectric layer is located on the surface of the third capacitance metal layer 414 and the surface of the second passivation layer, the first dielectric layer comprises a first device dielectric layer 415 and a first capacitance dielectric layer 416, the first device dielectric layer 415 is located on the first device region I, the surface of the first device metal layer 410 exposed by the first device dielectric layer 415 is located on the second device region II, the first capacitance dielectric layer 416 is provided with a plurality of first through holes 423 exposing part of the top surface of the third capacitance metal layer 414, the first through holes 423 comprise a first opening and a second opening, the first opening is located on the top surface of the first capacitance dielectric layer 416, the second opening is located on the bottom surface of the first capacitance dielectric layer 416, and the projection range of the second opening in the direction towards the first capacitance metal layer 404 is located in the projection range of the first opening in the direction towards the first capacitance metal layer 404; a second metal layer, where the second metal layer includes a second device metal layer 417 and a fourth capacitor metal layer 418, where the second device metal layer 417 is located on the first device region I, and the second device metal layer 417 is located on the exposed top surface of the first device metal layer 410, the fourth capacitor metal layer 211 is located on the second device region II, and the fourth capacitor metal layer 418 is located on the first capacitor dielectric layer and is in contact with the third capacitor metal layer 414, where the projections of the fourth capacitor metal layer 418, the third capacitor metal layer 414, the second capacitor metal layer 411, and the first capacitor metal layer 404 on the substrate 400 have overlapping areas.
In this embodiment, the inclined side wall of the first through hole 423 is used to rebound a part of pressure applied during wire bonding, so as to reduce impact of the pressure on the capacitor metal layer and reduce damage to the capacitor structure. In addition, the capacitor structure is manufactured on the second device region II, so that the size of the chip can be effectively reduced.
In this embodiment, the material of the first dielectric layer includes: a polymer; the polymer comprises: one or more of benzocyclobutene, photo-sensitive epoxy photoresist, and polyimide. Because the first capacitance medium layer 416 is made of a macromolecular material, the compactness of the material is lower and the thickness is larger, so that the material has better buffering property. When the subsequent wire bonding process is performed in the wire bonding area, the first capacitor dielectric layer 416 is utilized to provide a better buffering effect for the capacitor structure in the second device area II, so as to reduce the damage to the capacitor structure caused by the pressure applied during wire bonding.
In this embodiment, the plurality of first through holes 423 are distributed in a grid shape.
In this embodiment, an included angle between the sidewall of the first via 423 and the top surface of the third capacitor metal layer 414 is: 40 degrees to 60 degrees.
In this embodiment, further comprising: the fourth via 422 located in the first capacitance medium layer and the second capacitance passivation layer 413, and the third via 421 located in the first capacitance passivation layer 409, the third via 421 exposing the top surface of the first capacitance metal layer 404, the fourth via 422 exposing the third via 421.
In the present embodiment, the second through hole is constituted by the third through hole 421 and the fourth through hole 422.
In this embodiment, the fourth capacitance metal layer 418 fills the second via and is in contact with the first capacitance metal layer 404.
In this embodiment, the thickness of the third capacitance metal layer 414 is smaller than the second capacitance metal layer 411; the thickness of the third capacitive metal layer 414 is less than the thickness of the fourth capacitive metal layer 418. The resistance of the third capacitor metal layer 414 is increased by forming the third capacitor metal layer 414 to have a smaller thickness. When the current is applied to the center of the third capacitor metal layer 414, the current flowing to the edge of the third capacitor metal layer 414 is small, so that the electric field at the edge of the third capacitor metal layer 414 is reduced, and the electric field breakdown between the third capacitor metal layer 414 and the second capacitor metal layer 411 below can be prevented.
In this embodiment, the thickness of the third capacitor metal layer 414 is 0.1 to 0.2 microns.
In this embodiment, the projection range of the third capacitance metal layer 414 on the substrate 400 is within the projection range of the second capacitance metal layer 411 on the substrate 400. By reducing the area of the third capacitor metal layer 414, the edge of the third capacitor metal layer 414 is prevented from being opposite to the edge of the second capacitor metal layer 411, so that electric field breakdown caused by the tip discharge between the third capacitor metal layer 414 and the second capacitor metal layer 411 below can be prevented.
In this embodiment, further comprising: and a third passivation layer on the second metal layer and the first dielectric layer, wherein the third passivation layer includes a third device passivation layer 419 and a third capacitor passivation layer 420, the third device passivation layer 419 is located in the first device region I, the third device passivation layer 419 exposes a portion of a surface (not shown) of the second device metal layer 417, the third capacitor passivation layer 420 is located on the routing region I, and the third capacitor passivation layer 420 exposes the fourth capacitor metal layer 418 having a projection overlap region with the third capacitor metal layer 414 on the substrate 400.
Fig. 18 to 20 are schematic views illustrating steps of a method for forming a semiconductor structure according to another embodiment of the present invention.
The present embodiment is a description of a method for forming a semiconductor structure based on the above embodiment (refer to fig. 17), and is different from the above embodiment in that: forming a structure with 3 capacitors connected in parallel. The specific forming process is shown in fig. 18 to 20.
Referring to fig. 18, a second dielectric layer is formed on the second metal layer and the first dielectric layer, where the second dielectric layer includes a second device dielectric layer 501 and a second capacitor dielectric layer 502, the second device dielectric layer 501 is located on the first device region I, the second device dielectric layer 501 exposes a surface of the second device metal layer 417, the second capacitor dielectric layer 502 is located on the second device region II, and the second capacitor dielectric layer 502 covers a surface of the fourth capacitor metal layer 418.
In this embodiment, the material of the second dielectric layer includes: a polymer; the polymer comprises: one or more of benzocyclobutene, photo-sensitive epoxy photoresist, and polyimide.
In this embodiment, the second capacitance medium layer 502 covered on the fourth capacitance metal layer 418 can further play a role of buffering, so as to reduce the damage of the pressure on the capacitance structure during wire bonding. In addition, the second capacitance medium layer 502 will maintain the surface morphology of the fourth capacitance metal layer 418, and the surface of the second capacitance medium layer 502 has a groove with an inclined sidewall, and a part of pressure can be rebounded by using the inclined sidewall of the groove, so as to reduce the impact of the pressure on the capacitance metal layer and further reduce the damage to the capacitance structure.
Referring to fig. 19, a third metal layer is formed, where the third metal layer includes a third device metal layer 503 and a fifth capacitor metal layer 504, the third device metal layer 503 is located on the first device region I, the third device metal layer 503 is located on the exposed top surface of the second device metal layer 417, the fifth capacitor metal layer 504 is located on the second device region II, the fifth capacitor metal layer 504 is located on the second capacitor dielectric layer 502, and projections of the fifth capacitor metal layer 504, the fourth capacitor metal layer 418, the third capacitor metal layer 414, the second capacitor metal layer 411 and the first capacitor metal layer 404 on the substrate 400 have overlapping areas.
In this embodiment, the first capacitance metal layer 404, the first capacitance passivation layer 409, the second capacitance metal layer 411, the second capacitance passivation layer 413, the fourth capacitance metal layer 418, the second capacitance dielectric layer 502 and the fifth capacitance metal layer 504 form a structure with 3 capacitances connected in parallel.
Referring to fig. 20, a third passivation layer is formed on the third metal layer and the second dielectric layer, where the third passivation layer includes a third device passivation layer 505 and a third capacitor passivation layer 506, the third device passivation layer 505 is located in the first device region I, and the third device passivation layer 505 exposes a portion of a surface (not shown) of the third device metal layer 503, the third capacitor passivation layer 506 is located on the second device region II, and the third capacitor passivation layer 506 exposes the fifth capacitor metal layer 504 having a projection overlapping area with the third capacitor metal layer 414 on the substrate 400.
In this embodiment, the material of the third passivation layer is silicon nitride.
In this embodiment, a wire bonding process is performed on the surface of the fifth capacitor metal layer 504 exposed by the third capacitor passivation layer 506.
Accordingly, in an embodiment of the present invention, with continued reference to fig. 20, the description of the semiconductor structure is continued based on the above embodiment (please refer to fig. 17), and compared with the above embodiment, the difference in this embodiment is that the semiconductor structure further includes:
the second dielectric layer is located on the second metal layer and the first dielectric layer, the second dielectric layer includes a second device dielectric layer 501 and a second capacitance dielectric layer 502, the second device dielectric layer 501 is located on the first device region I, the second device dielectric layer 501 exposes a surface of the second device metal layer 417, the second capacitance dielectric layer 502 is located on the second device region II, and the second capacitance dielectric layer 502 covers a surface of the fourth capacitance metal layer 418.
A third metal layer, where the third metal layer includes a third device metal layer 503 and a fifth capacitor metal layer 504, where the third device metal layer 503 is located on the first device region I, and the third device metal layer 503 is located on the exposed top surface of the second device metal layer 417, where the fifth capacitor metal layer 504 is located on the second device region II, where the fifth capacitor metal layer 504 is located on the second capacitor dielectric layer 502, where the projections of the fifth capacitor metal layer 504, the fourth capacitor metal layer 418, the third capacitor metal layer 414, the second capacitor metal layer 411, and the first capacitor metal layer 404 on the substrate 400 have overlapping areas.
And a third passivation layer on the third metal layer and the second dielectric layer, where the third passivation layer includes a third device passivation layer 505 and a third capacitor passivation layer 506, the third device passivation layer 505 is located in the first device region I, and the third device passivation layer 505 completely covers the surface of the third device metal layer 503, the third capacitor passivation layer 506 is located on the second device region II, and the third capacitor passivation layer 506 exposes the fifth capacitor metal layer 504 having a projection overlapping area with the third capacitor metal layer 414 on the substrate 400.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (18)

1. A capacitor structure, comprising:
a first capacitor metal layer;
a first capacitance passivation layer covering the first capacitance metal layer;
a second capacitive metal layer on the first capacitive passivation layer over a first portion of the first capacitive metal layer;
A second capacitor passivation layer covering the second capacitor metal layer;
the third capacitance metal layer is positioned on the second capacitance passivation layer and is positioned above the second capacitance metal layer;
the first capacitor dielectric layer is positioned on the third capacitor metal layer, the first capacitor dielectric layer is provided with a plurality of first through holes which penetrate through the first capacitor dielectric layer, part of the surface of the third capacitor metal layer is exposed out of the first through holes, the first through holes comprise opposite first openings and second openings, the first openings are positioned on the upper surface of the first capacitor dielectric layer, the second openings are positioned on the lower surface of the first capacitor dielectric layer, and the projection range of the second openings in the direction of the first capacitor metal layer is positioned in the projection range of the first openings in the direction of the first capacitor metal layer;
and the fourth capacitance metal layer is positioned on the first capacitance medium layer and is filled with a plurality of first through holes to be electrically connected with the third capacitance metal layer.
2. The capacitive structure of claim 1, wherein the material of the first capacitive dielectric layer comprises: a polymer; the polymer comprises: one or more of benzocyclobutene, photo-sensitive epoxy photoresist, and polyimide.
3. The capacitive structure of claim 1, wherein a plurality of the first vias are distributed in a grid pattern.
4. The capacitive structure of claim 1, wherein an angle between a sidewall of the first via and a surface of the third capacitive metal layer is: 40 degrees to 60 degrees.
5. The capacitive structure of claim 1, wherein a thickness of the third capacitive metal layer is less than a thickness of the second capacitive metal layer; the thickness of the third capacitance metal layer is smaller than that of the fourth capacitance metal layer.
6. The capacitive structure of claim 1, wherein the thickness of the third capacitive metal layer is 0.1 microns to 0.2 microns.
7. The capacitive structure of claim 1, wherein the second capacitive passivation layer is further located on the first capacitive passivation layer covering a second portion of the first capacitive metal layer.
8. The capacitive structure of claim 7, wherein the first capacitive dielectric layer is further located on the second capacitive passivation layer over the second portion.
9. The capacitive structure of claim 8, further comprising: the second through hole penetrates through the first capacitance passivation layer, the second capacitance passivation layer and the first capacitance medium layer above the second part; the fourth capacitance metal layer is also filled with the second through hole and is electrically connected with the first capacitance metal layer.
10. A method for forming a capacitor structure, comprising:
forming a first capacitance metal layer;
forming a first capacitance passivation layer to cover the first capacitance metal layer;
forming a second capacitance metal layer on the first capacitance passivation layer and above a first portion of the first capacitance metal layer;
forming a second capacitance passivation layer to cover the second capacitance metal layer;
forming a third capacitance metal layer which is positioned on the second capacitance passivation layer and above the second capacitance metal layer;
forming a first capacitance medium layer on the third capacitance metal layer, wherein the first capacitance medium layer is provided with a plurality of first through holes penetrating through the first capacitance medium layer, part of the surface of the third capacitance metal layer is exposed by the first through holes, the first through holes comprise opposite first openings and second openings, the first openings are positioned on the upper surface of the first capacitance medium layer, the second openings are positioned on the lower surface of the first capacitance medium layer, and the projection range of the second openings towards the first capacitance metal layer is positioned in the projection range of the first openings towards the first capacitance metal layer;
And forming a fourth capacitance metal layer on the first capacitance medium layer, wherein the fourth capacitance metal layer is filled with a plurality of first through holes and is electrically connected with the third capacitance metal layer.
11. The method of forming a capacitor structure of claim 10, wherein the method of forming the first capacitor dielectric layer comprises: forming a first capacitance dielectric material layer, wherein the first capacitance dielectric material layer covers the surface of the third capacitance metal layer; forming a patterned layer on the first capacitance dielectric material layer, wherein the patterned layer exposes part of the top surface of the first capacitance dielectric material layer; and etching the first capacitance dielectric material layer by taking the patterned layer as a mask until the top surface of the third capacitance metal layer is exposed, so as to form the first capacitance dielectric layer, wherein the first capacitance dielectric layer is provided with a plurality of first through holes exposing part of the surface of the third capacitance metal layer.
12. The method of forming a capacitive structure of claim 10, wherein the second capacitive passivation layer is further located on the first capacitive passivation layer covering a second portion of the first capacitive metal layer.
13. The method of forming a capacitor structure of claim 12, wherein the first capacitor dielectric layer is further on the second capacitor passivation layer over the second portion.
14. The method of forming a capacitor structure of claim 13, further comprising: forming a second through hole penetrating through the first capacitance passivation layer, the second capacitance passivation layer and the first capacitance dielectric layer above the second part; the fourth capacitance metal layer is also filled with the second through hole and is electrically connected with the first capacitance metal layer.
15. A semiconductor structure, comprising:
a substrate comprising a first device region and a second device region;
a device structure located on the first device region;
a capacitive structure as claimed in any one of claims 1 to 9 located on the second device region.
16. The semiconductor structure of claim 15, wherein the device structure comprises: heterojunction bipolar transistor structure.
17. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first device region and a second device region;
Forming a device structure on the first device region;
a capacitor structure as claimed in any one of claims 1 to 9 formed on the second device region during formation of the device structure.
18. The method of forming a semiconductor structure of claim 17, wherein the device structure comprises: heterojunction bipolar transistor structure.
CN202310502553.6A 2023-05-06 2023-05-06 Capacitor structure and forming method thereof, semiconductor structure and forming method thereof Pending CN116209353A (en)

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CN115050737A (en) * 2022-08-12 2022-09-13 常州承芯半导体有限公司 Semiconductor structure and forming method thereof
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