TW200425366A - Method of wire bonding over active area of a semiconductor circuit - Google Patents

Method of wire bonding over active area of a semiconductor circuit Download PDF

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Publication number
TW200425366A
TW200425366A TW093111710A TW93111710A TW200425366A TW 200425366 A TW200425366 A TW 200425366A TW 093111710 A TW093111710 A TW 093111710A TW 93111710 A TW93111710 A TW 93111710A TW 200425366 A TW200425366 A TW 200425366A
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patent application
scope
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structure capable
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TW093111710A
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TWI233653B (en
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Michael Chen
Jin-Yuan Lee
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Megic Corp
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Priority claimed from US10/434,142 external-priority patent/US8021976B2/en
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Publication of TWI233653B publication Critical patent/TWI233653B/en

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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Abstract

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Description

200425366 五、發明說明（1) 【發明所屬之技術領域】 本發明是有關於一種積體電路元件之製造方法，且特 別是有關於一種形成打線墊於位在下面之主動元件上、被 動元件上及脆弱的介電層上之方法。 【先前技術】 藉由縮減元件的尺寸可以提升半導體元件的效能，如 此可以增加元件的密度及元件封裝的密度。隨著元件密度 的增加，而半導體元件之内連線亦隨之增加，並且半導體 元件的封裝亦必須符合上述的要求。在半導體元件封裝於 封裝結構體内之後，半導體元件所具備之傳輸能力及封裝 結構體所具備之輸出入數目均是在封裝設計時所要考量的 主要因素。 在典型的半導體元件封裝中，半導體晶片係封裝於封 裝結構體中’並且错由打線導線或凸塊可以連接於基板之 連接線路。為了達到上述目的，半導體晶片具接墊，一般 係位在晶片的周圍區域上’而接塾係形成在並不具有主動 元件或被動元件之區域上。 打線墊並不形成於主動元件上或被動元件上的原因之 一是與打線製程所產生的熱應力或機械應力有關。在進行 打線製程時，打線導線可以從打線墊連接至可以作為支撐 用途的電路板或是連接至其他的連接裝置上。 在現今半導體產業的趨勢，係以低介電常數之材質作 為金屬間的介電層。然而，相較於傳統的介電材質，這些200425366 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing an integrated circuit element, and more particularly to a method for forming a wire bonding pad on an active element and a passive element located below. And fragile dielectric layers. [Previous technology] The performance of semiconductor devices can be improved by reducing the size of the components, which can increase the density of components and the density of component packages. As the density of components increases, the interconnects of semiconductor components also increase, and the packaging of semiconductor components must also meet the above requirements. After the semiconductor device is packaged in the package structure, the transmission capability of the semiconductor device and the number of inputs and outputs of the package structure are the main factors to be considered in the package design. In a typical semiconductor element package, a semiconductor wafer is packaged in a package structure 'and a wiring line or a bump can be connected to a connection line of a substrate by mistake. In order to achieve the above-mentioned purpose, semiconductor wafers are provided with pads, which are generally located on the peripheral area of the wafer ', and the contacts are formed on areas that do not have active or passive components. One of the reasons that the wire bonding pad is not formed on the active or passive components is related to the thermal or mechanical stress generated by the wire bonding process. During the wire bonding process, the wire can be connected from the wire bonding pad to a circuit board that can be used for support or to other connection devices. In the current semiconductor industry, materials with a low dielectric constant are used as dielectric layers between metals. However, compared to traditional dielectric materials, these

11944twf.ptd 第7頁 200425366 五、發明說明（2) 低介電常數之材質具有較低的機械強度，因此受到打線製 程的影響，這些材質可能會被損害。 美國專利第4, 636, 832號（Abe et al.)揭露形成接墊 於主動區域上的方法，其係利用矽層藉以降低應力。 美國專利第5，751，〇65號（(]1111:1:106(1(116七31.)揭露 形成具有主動元件之積體線路於接墊下的方法，其係利用 金屬藉以釋放應力。 美國專利第6,3 8 4,48 6號（Zuniga et al.)揭露形成積 體電路於接墊下的方法，其係利用金屬層作為應力吸收之 用。 美國專利第6,2 2 9,2 2 1號（Kloen et al.)揭露形成打 線導線在打線墊上的方法，其中打線墊係位於主動元件 上，而打線墊及保護層必須要具有一特定的厚度，藉以避 免位於打線區域下的元件受到損壞。 【發明内容】 因此，本發明之一目的就是提供一種能夠形成打線導 線於半導體晶片之元件區域上的晶片結構及其製造方法’ 並且可以避免損害位在下面的介電層、主動元件或被動元 件等。 本發明之另一目的就是利用打線導線可以使積體電路 連接於下一層級的封裝元件，並且可以減少半導體晶片的 尺寸及製造成本。 為了達到本發明之上述目的，本發明提出一種能夠形11944twf.ptd Page 7 200425366 V. Description of the invention (2) Materials with a low dielectric constant have low mechanical strength, and are therefore affected by the wire bonding process. These materials may be damaged. U.S. Patent No. 4,636,832 (Abe et al.) Discloses a method for forming a pad on an active area by using a silicon layer to reduce stress. U.S. Patent No. 5,751,065 (() 1111: 1: 106 (1 (116-731.)) Discloses a method of forming a integrated circuit with an active element under a pad, which uses metal to release stress. U.S. Patent No. 6,3 8 4,48 6 (Zuniga et al.) Discloses a method for forming an integrated circuit under a pad, which uses a metal layer for stress absorption. U.S. Patent 6,2 2 9, 2 2 No. 1 (Kloen et al.) Discloses a method for forming a wire bonding wire on a wire bonding pad, where the wire bonding pad is located on an active component, and the wire bonding pad and the protective layer must have a specific thickness, so as to avoid being located under the wire bonding area. The component is damaged. [Summary of the invention] Therefore, one object of the present invention is to provide a wafer structure capable of forming wire bonding on the element region of a semiconductor wafer and a method for manufacturing the same. Components or passive components, etc. Another object of the present invention is to use integrated wiring to connect the integrated circuit to the next level of packaging components, and to reduce the size and manufacturing cost of semiconductor wafers. In order to achieve the above object of the present invention, the present invention proposes a

11944twf.ptd 第8頁 200425366 五、發明說明（3) 成打線導線於半導體晶片之元件區域上的晶片結構及其製 造方法。主動元件或被動元件係形成在半導體晶片上，而 半導體晶片具有至少一連線金屬層，而連線金屬層具有至 少一位在上層之金屬接墊。保護層係位在連線金屬層上， 其中保護層具有至少一開口 ，暴露出位在上層之金屬接 墊。緩衝金屬接墊係形成於保護層上，經由開口可以連接 於位在上層之金屬接墊。 保護層之開口形式及結構係可以變化的，而緩衝介電 層可以形成於緩衝金屬接墊與保護層之間，並且打線導線 可以連接於緩衝金屬接墊上。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 【實施方式】 由於接墊係形成在介電層上，因此傳統的打線方法及 輸出入線路連接方法會導致位在下層的介電層損壞，而且 在接墊之下並不會形成主動元件，藉以避免打線時傷及主 動元件，因此會導致晶片尺寸大幅增加，而增加額外的製 造成本。 本發明提出一種方法，可以使打線導線連接至半導體 晶片上，且打線導線與半導體晶片連接的位置係位於主動 元件上或位於被動元件上，並且藉由這種方法可以避免傷 及主動元件或被動元件，而且亦不會損害介電層。11944twf.ptd Page 8 200425366 V. Description of the Invention (3) A wafer structure and a manufacturing method thereof by forming a wire on a component region of a semiconductor wafer. The active element or the passive element is formed on a semiconductor wafer, and the semiconductor wafer has at least one connection metal layer, and the connection metal layer has at least one metal pad on the upper layer. The protective layer is located on the connection metal layer, wherein the protective layer has at least one opening to expose the metal pad on the upper layer. The buffer metal pad is formed on the protective layer, and can be connected to the upper metal pad through the opening. The opening form and structure of the protective layer can be changed, and the buffer dielectric layer can be formed between the buffer metal pad and the protective layer, and the wire can be connected to the buffer metal pad. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in conjunction with the accompanying drawings, and are described in detail as follows: [Embodiment] Since the pad is formed in The dielectric layer, so the traditional wiring method and I / O line connection method will cause damage to the underlying dielectric layer, and no active components will be formed under the pads, so as to avoid damaging the active components during wiring, so This will result in a significant increase in wafer size and additional manufacturing costs. The invention proposes a method, which can make the wire to the semiconductor chip, and the position where the wire and the semiconductor chip are connected is located on the active element or on the passive element, and by this method, the active element or the passive can be avoided Components without damaging the dielectric layer.

11944twf.ptd 第9頁 200425366 五、發明說明（4) 、 傳統的打線方式係將打線導線連接於晶片的周圍區 域’如此將接墊配置在橫向地遠離於主動元件區域的位 置:目的就是要避免在打線時，機械應力進入於介電層中 之後’而導致的負面效果。 請參照第1 a圖及第丨b圖，第1 a圖中的第一區域7 〇係配 置有主動元件或被動元件。第一區域70係與第二區域7 5分 離二而接塾7 7係位在第二區域7 5上。第1 a圖係為上視圖， 而第1 b圖係為第丨a圖的剖面示意圖。主動元件或被動元件 =係，於基底71内或基底71上，第一連線金屬層73會藉由 j觸窗74連接至元件72，位在上方之一層或多層之連線金 屬層7 6係位在金屬間介電層7 6之内，而頂層之金屬層係定 義出接墊7 7。接墊7 7及打線導線8 0係位於第二區域7 5内， 並且橫向地遠離於第一區域7 0。如第la圖及第“圖所示， 接塾77的下方並沒有主動元件或被動元件。 如第la圖及第lb圖所示，接墊77係位於半導體晶片 上’並且橫向地遠離於主動元件或被動元件72，由於晶片 上表面可以作為打線連接之用的第一區域7 〇係不能配置有 主動元件或被動元件7 2，因此會導致晶片尺寸大幅地增 加0 在第2圖至第8 c圖將介紹本發明之詳細技術内容。 第2圖係為剖面示意圖，相關摞號及元件說明如下所 述： 標號1 0係為一基底，半導體主動元件或被動元件係位 於基底内或基底上，其中被動元件比如是金屬線路、電容11944twf.ptd Page 9 200425366 V. Description of the invention (4) The traditional wiring method is to connect the wiring wire to the surrounding area of the chip. Negative effects caused by mechanical stress entering the dielectric layer during wiring. Please refer to Fig. 1a and Fig. 丨 b. The first area 70 in Fig. 1a is configured with active or passive components. The first area 70 is separated from the second area 75, and the next area 7 is located on the second area 75. Figure 1a is a top view, and Figure 1b is a schematic cross-sectional view of Figure a. Active component or passive component = system, in the substrate 71 or on the substrate 71, the first connection metal layer 73 is connected to the component 72 through the j touch window 74, and the one or more layers of the connection metal layer 7 6 It is located within the intermetal dielectric layer 76, and the top metal layer defines the pads 7-7. The pads 77 and the wiring wires 80 are located in the second area 75, and are laterally far from the first area 70. As shown in Fig. 1a and "1", there is no active or passive component under the connector 77. As shown in Figs. 1a and 1b, the pad 77 is located on the semiconductor wafer 'and is laterally away from the active device. Element or passive element 72, because the upper surface of the chip can be used as the first area for wire connection. The 〇 series cannot be equipped with active or passive elements 72, so it will cause a significant increase in chip size. Figure c will introduce the detailed technical content of the present invention. Figure 2 is a schematic cross-sectional view, and the related symbols and component descriptions are as follows: Reference numeral 10 is a substrate, and a semiconductor active or passive component is located in or on the substrate. , Where passive components such as metal lines and capacitors

200425366 五、發明說明（5) 元件、電阻 標號1 2 而元件1 2具 標號1 4 標號1 5 標號1 6 標號1 7 元件、電感 比如為半導 有可以作為 係為第一層 係為一層或 係為金屬間 係為接墊， 元件等。 體元件，係位於基底内或基底上 電性接觸之導電接墊。 級間介電層。 多層之金屬連接線路。 介電層。 係由位於頂層之金屬連線層所形 成 標號1 8係為保護層，位於金屬間介電層1 6上及接墊1 7 上 標號1 9係為開口 ，貫穿保護層1 8，可以連通至接墊 17 標號20 本發明的重 標號22 在較佳 層2 0包括下 1 .濺鍍 濺鍍 藉由 電鍍 去除 蝕刻 蝕刻 係為緩衝金屬層，而緩衝金屬層2 0的配置係為 要特徵之一，位於保護層1 8上。 係為打線導線，可以連接於緩衝金屬層2 0上。 的情況下，形成可以作為打線接墊之緩衝金屬 列步驟： 阻障層 種子層 微影製程定義出開口 厚金屬層於開口中 光阻 種子層 阻障層200425366 V. Description of the invention (5) Element and resistance number 1 2 and element 12 with number 1 4 number 1 5 number 1 6 number 1 7 element and inductance such as semiconducting can be used as the first layer or the first layer or The system is metal, the system is pads, components, etc. Body components are conductive pads that are in electrical contact with the substrate. Interlevel dielectric layer. Multi-layer metal connection lines. Dielectric layer. The reference numeral 18 is formed by the metal wiring layer on the top layer. The reference numeral 18 is a protective layer. The reference numeral 19 on the intermetal dielectric layer 16 and the pad 17 is an opening. It penetrates the protective layer 18 and can be connected to The pad 17 is numbered 20, and the heavy number 22 of the present invention includes the following in the preferred layer 2 0. Sputtering Sputtering is performed by plating to remove the etching etching system as a buffer metal layer, and the configuration of the buffer metal layer 20 is a characteristic feature First, it is located on the protective layer 18. It is a wired wire and can be connected to the buffer metal layer 20. In the case of forming a buffer metal that can be used as a wire bonding pad, the steps are as follows: barrier layer, seed layer, lithography process to define the opening, thick metal layer in the opening, photoresist, seed layer, barrier layer

11944twf.ptd 第11頁 200425366 五、發明說明（6) 在較佳的情況下，阻障層的厚度係約略為3 0 0 0埃 (angstrom)，而其材質比如是鈦嫣合金。種子層的厚度係 約略為1 0 0 0埃，而其材質比如是金。在步驟3所用的光 阻，其厚度比如是介於1 0到1 2微米之間。 緩衝金屬層20之厚度至少要大於1微米，而在較佳的 情況下，係大於2微米，並且緩衝金屬層2 0之材質包括 金。值得注意的是，根據在打線製程時緩衝金屬層2 0所需 吸收的能量多募，可以調整緩衝金屬層2 0的厚度。當緩衝 金屬層20之厚度愈厚時，緩衝金屬層20便可以吸收愈多的 能量。 如第2圖及第3圖所示，保護層開口19之截面寬度至少 要大於0 . 1微米，而在較佳的情況下，係至少要大於0. 5微 米。每一保護層開口 1 9係僅位在接墊1 7之其中之一上，位 於緩衝金屬層20下之接墊17上，配置有保護層開口19，暴 露出接墊17，如第2圖所示。 請參照第3圖，打線導線2 2之打線區域可以相對於保 護層開口 1 9的位置做橫向移動，其中保護層開口 1 9係貫穿 保護層1 8。由於打線導線2 2相對於保護層開口 1 9的位置做 移動，因此在打線導線之連接位置上具有較大的彈性。 請參照第4 a圖，其繪示本發明之另一較佳實施例，藉 由較大的接墊1 7可以使打線導線連接於半導體元件。保護 層1 8可以形成較大的開口 1 9，貫穿保護層1 8，而經由此開 口 19可以使緩衝金屬層20大面積地接觸於最上層之金屬層11944twf.ptd Page 11 200425366 V. Description of the invention (6) In the best case, the thickness of the barrier layer is about 3 0 0 0 angstrom (angstrom), and the material is, for example, titanium alloy. The thickness of the seed layer is about 100 angstroms, and the material is, for example, gold. The thickness of the photoresist used in step 3 is, for example, between 10 and 12 microns. The thickness of the buffer metal layer 20 is at least greater than 1 micron, and in the preferred case, it is greater than 2 micrometers, and the material of the buffer metal layer 20 includes gold. It is worth noting that the thickness of the buffer metal layer 20 can be adjusted according to the amount of energy absorbed by the buffer metal layer 20 during the wire bonding process. When the thickness of the buffer metal layer 20 is thicker, the buffer metal layer 20 can absorb more energy. As shown in FIG. 2 and FIG. 3, the cross-sectional width of the protective layer opening 19 should be at least greater than 0.1 micrometer, and in a preferred case, it should be greater than 0.5 micrometer. Each protective layer opening 19 is only located on one of the pads 17 and is located on the pad 17 under the buffer metal layer 20. The protective layer opening 19 is configured to expose the pad 17, as shown in FIG. 2 As shown. Referring to FIG. 3, the wire-bonding area of the wire 22 can be moved laterally relative to the position of the protective layer opening 19, where the protective layer opening 19 runs through the protective layer 18. Since the position of the wire conductor 22 is moved relative to the opening 19 of the protective layer, the connection position of the wire conductor has greater flexibility. Please refer to FIG. 4a, which illustrates another preferred embodiment of the present invention. The larger pads 17 can connect the wire to the semiconductor device. The protective layer 18 can form a larger opening 19 through the protective layer 18, and through this opening 19, the buffer metal layer 20 can contact the uppermost metal layer in a large area.

11944twf.ptd 第12頁 200425366 五、發明說明（7) 17上，因此可以減少緩衝金屬層20與接墊17連接之串聯電 阻。 如第4a圖所示，暴露出接塾17之大的保護層開口 ，其 寬度大約是介於4 0微米到1 0 0微米之間。 在另外的較佳實施例中，如第4 b圖所示，其係配置有 大的接墊1 7，但是有許多開口貫穿保護層1 8，如此可以增 進緩衝金屬層20之上表面的表面平坦度。 為了增進打線力量的吸收程度，在如第5 a圖所示之另 一較佳實施例中，可以形成一緩衝介電層2 4於緩衝金屬層 2 6下，在較佳的情況下，緩衝介電層2 4係為一有機材料， 比如是聚醯亞胺（polyimide)或苯基環丁烯 (benzocyclobutene，BCB)等，藉以防止位在下層之介電 層1 6及主動元件或被動元件1 2受到損害。而其他可以作為 緩衝介電層2 4之聚合物材料包括彈性體，比如是砍酮 (si 1 icone)、多孔性低介電係數之有機材料或聚對二甲苯 基（parylene)等。而缓衝介電層24比如是利用旋塗的方式 製成。 開口 2 3係貫穿緩衝介電層2 4，並且與保護層開口 1 9連 通，藉以暴露出接墊1 7。開口 2 3可以具有大致上垂直的側 壁2 5，然而在較佳的情況下，開口 2 3之側壁2 5係具有如第 5a圖所示之傾斜度。比如是聚醯亞胺之緩衝介電層24在經 過旋塗、曝光、顯影等步驟之後，會具有垂直的側壁，然 而在接下來經過烘烤的步驟之後，開口 2 3之側壁2 5會具有 所需的斜率，而側壁2 5的斜率係大於4 5度，一般係介於5 011944twf.ptd Page 12 200425366 V. Description of the invention (7) 17 Therefore, the series resistance of the buffer metal layer 20 and the pad 17 can be reduced. As shown in Fig. 4a, the large protective layer opening of the junction 17 is exposed, and its width is between 40 microns and 100 microns. In another preferred embodiment, as shown in FIG. 4b, it is provided with large pads 17 but there are many openings penetrating the protective layer 18, so that the surface of the upper surface of the buffer metal layer 20 can be improved. flatness. In order to improve the absorption of the bonding force, in another preferred embodiment as shown in FIG. 5a, a buffer dielectric layer 24 can be formed under the buffer metal layer 26. In a better case, a buffer The dielectric layer 24 is an organic material, such as polyimide or benzocyclobutene (BCB), so as to prevent the underlying dielectric layer 16 and active or passive components. 1 2 was damaged. Other polymer materials that can be used as the buffer dielectric layer 24 include elastomers, such as si 1 icone, porous organic materials with low dielectric constant, or parylene. The buffer dielectric layer 24 is made by, for example, spin coating. The openings 2 3 pass through the buffer dielectric layer 2 4 and communicate with the protective layer openings 19 to expose the pads 17. The opening 23 may have substantially vertical side walls 25, but in a preferred case, the side walls 25 of the opening 23 have an inclination as shown in Fig. 5a. For example, the buffer dielectric layer 24 of polyimide will have vertical sidewalls after steps such as spin coating, exposure, and development, but after the subsequent baking step, the sidewalls 25 of the openings 2 3 will have The desired slope, and the slope of the side wall 25 is greater than 45 degrees, generally between 50

11944twf.ptd 第13頁 200425366 五、發明說明（8) 度到6 0度之間，而側壁2 5之傾斜角度亦可以是小至2 0度。 如前所述，在較佳的情況下，係利用電鍍的方式形成 緩衝金屬層2 6。而形成第5 a圖之較佳實施例的緩衝金屬層 2 6包括下列步驟： 1 .濺鍍阻障層 2 .濺鍵種子層 3 .進行微影製程 4.電鍍製程 5 .去除光阻 6. 蝕刻種子層 7. 蝕刻阻障層 緩衝金屬層2 6之厚度至少要大於1微米，而在較佳的 情況下，緩衝金屬層26之材質包括金。 在較佳的情況下，比如是利用旋塗的方式，形成緩衝 介電層24，緩衝介電層24的厚度比如至少要大於2微米。 而形成緩衝介電層2 4可以包括下列的步驟·· 1 .旋塗感光材料 2. 進行曝光顯影的步驟 3. 烘烤的步驟 另外，緩衝介電層2 4比如可以利用習知網板印刷的方 式，塗佈比如是聚酿亞胺或苯基環丁稀之高分子聚合物， 接著再進行烘烤的步驟而成。11944twf.ptd Page 13 200425366 V. Description of the invention (8) degrees to 60 degrees, and the inclination angle of the side wall 25 can be as small as 20 degrees. As mentioned above, in a preferred case, the buffer metal layer 26 is formed by electroplating. Forming the buffer metal layer 26 of the preferred embodiment of FIG. 5a includes the following steps: 1. Sputter barrier layer 2. Sputter key seed layer 3. Lithography process 4. Plating process 5. Removal of photoresist 6 Etching the seed layer 7. The thickness of the etch barrier layer buffer metal layer 26 should be at least greater than 1 micron, and in a preferred case, the material of the buffer metal layer 26 includes gold. In a preferred case, for example, spin-coating is used to form the buffer dielectric layer 24, and the thickness of the buffer dielectric layer 24 is, for example, at least greater than 2 micrometers. Forming the buffer dielectric layer 2 4 may include the following steps: 1. spin-coating the photosensitive material 2. performing exposure and development step 3. baking step In addition, the buffer dielectric layer 2 4 may be printed by a conventional screen printing, for example It is made by coating a high molecular polymer such as polyimide or phenylcyclobutane, and then performing a baking step.

11944twf.ptd 第14頁 200425366 五、發明說明（9) r r 门 具有夕 圖乡會示變化自第5a圖之另一結構，缓衝介電層24 S固開口 ’可以使緩衝金屬層2 6經由多個保護層開口 19連接至多個接墊17。 具有，5c圖乡會示變化自第5a圖之另一結構，緩衝介電層24 ^個開口 ，可以使緩衝金屬層2 6經由多個保護層開口 1 ^ 3¾ is. 5 留 在王早一且大的接墊17 〇 於緩衝^ 1卜的實施例中’如第6圖所示，打線導線2 8連接 地偏移、。’屬層2 6的位置可以相對於接墊1 7的位置存在橫向 金屬ί=較f實施例中，揭露多種緩衝介電層及緩衝 上層連接ί二:Ϊ ，至第6圖的實施例中係僅緣示兩層之 於此，而可以且熟知技藝者應知本發明的應用並不限 如兑二、具有更多層之連接線路。 位置，而藉由緩衝介二f 層之一個或多個開口的 與主動元件或被動元件與打線導線連接之接塾 於接ί夂=3Λ^·ν；Λ圖’打線導線22可以相對 暴露出位在金屬；介多個。每-開口Η均會 17。 9 上之頂層金屬連接線路之接墊 如第2圖及第3圖所干十办丨1 一 w 的尺寸，較小的接墊可以、缔J = Ζ思圖，相較於傳統接墊 、、生由貫穿保護層之較小的開口暴 ll944tWf.ptd 第15頁 200425366 五、發明說明（ίο) 露於外。而如第4圖所示之剖面示意圖，較大的接墊可以 經由貫穿保護層1 8之較大的開口暴露於外。 在第2圖所示的結構中，當緩衝金屬層26包括有4微米 厚的電鍍金，且金屬間介電層16的材質係為氟矽玻璃 (Fluorinated Silicate Glass ，FSG)時，在經過打線製 程之後，並沒有發現金屬間介電層1 6有損害的現象。 請參照第7圖及第8a-8c圖，將詳細地敘述形成本發明 打線墊（緩衝金屬層）的方法及其材質。 基本上，保護層1 8係為無機化合物的材料，保護層1 8 的材質比如包括約0 . 5微米厚的氧矽化合物層及0 . 7微米厚 的氮矽化合物層，氮矽化合物層係位在氧矽化合物層上。 熟悉該項技藝者應知，保護層1 8亦可以是其他的材質或厚 度。藉由保護層1 8可以保護位在下層之主動元件或被動元 件，藉以防止移動離子、過渡金屬、濕氣及其他的污染物 滲入。 如第7圖所示，在本發明之一較佳實施例中，黏著/阻 障層2 9係位在保護層1 8上，而黏著/阻障層2 9之材質比如 包括鈦、鉻、鈦嫣合金、鈕、鈕氮化合物或鈦氮化合物 等。在較佳的情況下，係利用賤鍵的方式形成黏著/阻障 層2 9 〇 接著，比如可以利用濺鍍的方式形成厚度約1 0 0 0埃的 金層，作為可以用來電鍍的種子層30，而種子層30係形成 在黏著/阻障層2 9上。 配合如前所述之微影製程，圖案化的接墊層3 2可以形11944twf.ptd Page 14 200425366 V. Description of the invention (9) The rr gate has another structure that is shown in Figure 5a. The buffer dielectric layer 24 S is fixed and can open the buffer metal layer 2 6 through The plurality of protective layer openings 19 are connected to the plurality of pads 17. There is another structure shown in Figure 5c that changes from Figure 5a. The buffer dielectric layer has 24 ^ openings, which can make the buffer metal layer 26 through multiple protective layer openings. 1 ^ 3¾ is. 5 Stay in Wang Zaoyi And the large pad 17 is in the buffered embodiment. As shown in FIG. 6, the connection wires 28 are offset and connected. 'The position of the metal layer 2 6 may have a lateral metal relative to the position of the pad 1 7. In the f embodiment, a variety of buffer dielectric layers and buffer upper layer connections are disclosed. 2: 至, to the embodiment of FIG. 6 The system only shows two layers here, and those skilled in the art should know that the application of the present invention is not limited to connecting lines with more layers. Position, and by buffering one or more openings of the two f layers, the connection between the active component or the passive component and the conductor is connected to the connection 夂 夂 3 = ^^ v; Λ diagram 'the conductor 22 can be exposed relatively Located in metal; more than one. Every-openings will be 17. The pads on the top metal connection line are as shown in Figures 2 and 3, and the size of a w is smaller. The smaller pads can be connected to J = ZE map, compared to traditional pads, It is caused by the small openings that penetrate the protective layer. Ll944tWf.ptd Page 15 200425366 V. Description of the invention (ίο) Exposed. As shown in the cross-sectional view in FIG. 4, the larger pad can be exposed to the outside through the larger opening through the protective layer 18. In the structure shown in FIG. 2, when the buffer metal layer 26 includes 4 μm-thick electroplated gold, and the material of the intermetal dielectric layer 16 is Fluorinated Silicate Glass (FSG), it is wired After the process, no damage was found to the intermetallic dielectric layer 16. Referring to FIG. 7 and FIGS. 8a-8c, the method of forming the wire pad (buffer metal layer) and the material of the present invention will be described in detail. Basically, the protective layer 18 is made of an inorganic compound. The material of the protective layer 18 includes, for example, an oxygen silicon compound layer with a thickness of about 0.5 micrometers and a nitrogen silicon compound layer with a thickness of 0.7 micrometers. Located on the oxygen silicon compound layer. Those skilled in the art should know that the protective layer 18 can also be made of other materials or thicknesses. The protective layer 18 can protect the active components or passive components in the lower layer to prevent the penetration of mobile ions, transition metals, moisture and other pollutants. As shown in FIG. 7, in a preferred embodiment of the present invention, the adhesion / barrier layer 29 is located on the protective layer 18, and the material of the adhesion / barrier layer 29 includes, for example, titanium, chromium, Titanium alloy, button, button nitrogen compound or titanium nitrogen compound. In a better case, an adhesion / barrier layer 2 9 is formed by means of a base bond. Then, for example, a gold layer having a thickness of about 100 angstroms can be formed by sputtering, as a seed for plating. Layer 30, and the seed layer 30 is formed on the adhesion / barrier layer 29. With the lithography process described above, the patterned pad layer 3 2 can be shaped

11944twf.ptd 第16頁 200425366 五、發明說明（11) 成在種子層30上，而接墊層32比如是利用電鍍的方式所形 成，且接塾層32比如為軟金（soft Au)材質。 如第7圖所示，金的接墊層3 2具有下列特徵： 1·硬度係小於150Hv (Vickers Hardness)，由於金係 為甚軟的材質，因此在進行打線時，金具有甚佳的吸收應 力之效果。 2 ·金的純度約略要大於9 7%，此乃因為金的純度愈 高，其硬度愈小。 一 、3·厚度約略要大於1微米，因為當厚度小於1微米時， 並不能提供適當的應力吸收效果。 成价L f火或回火過的金可以降低其硬度，故係為甚佳之 實施；參：St 3 f !8C圖，分別繪示本發明之三個較佳 衝金屬接墊。二佳實施例中，係利用複合金屬層作為緩 護層=述例中，黏著/阻障層29係形成於保 比如是約略5〇〇埃。早層29的材質包括鈦或鉻，其厚度 33比如是利用機铲/子層33係位於阻障層Μ上，種子層 如是約略5 0 0 0 J的方式形成金屬銅所製成，而其厚度比 38，iii;、：8:::複合金屬層包括三層金屬層34、36、 銅層、鎳層 '金；所播3士6、38分別是利用電鍍的方式形成 θ所構成。位在底部的銅層34，係為厚的11944twf.ptd Page 16 200425366 V. Description of the invention (11) is formed on the seed layer 30, and the pad layer 32 is formed by electroplating, for example, and the pad layer 32 is made of soft Au. As shown in Figure 7, the gold pad layer 3 2 has the following characteristics: 1. The hardness is less than 150Hv (Vickers Hardness). Because the gold system is a very soft material, gold has a good absorption when wire bonding is performed. The effect of stress. 2. The purity of gold is slightly greater than 9 7%, because the higher the purity of gold, the lower the hardness. 1. The thickness is slightly greater than 1 micron, because when the thickness is less than 1 micron, it cannot provide a proper stress absorption effect. The value of L f fired or tempered gold can reduce its hardness, so it is a good practice; see: St 3 f! 8C drawing, which shows the three preferred punched metal pads of the present invention. In the second preferred embodiment, a composite metal layer is used as a protective layer. In the example described above, the adhesion / barrier layer 29 is formed at about 500 angstroms, for example. The material of the early layer 29 includes titanium or chromium, and its thickness 33 is, for example, made of metal shovel / sublayer 33 on the barrier layer M, and the seed layer is made of metallic copper in a manner of approximately 5 0 0 J, and its Thickness ratio 38, iii; :: 8 ::: The composite metal layer includes three metal layers 34, 36, a copper layer, and a nickel layer 'gold; the broadcasted 3 ± 6, 38 are formed by the use of electroplating to form θ. Copper layer 34 at the bottom, thick

第17頁 200425366 五、發明說明（12) 導電層，其厚度約略係大於1微米，而位在中間部分的鎳 層3 6係為一擴散阻障層，其厚度略係介於1微米到5微米之 間。位在上面的金層3 8係為可與打線導線接合的金屬，而 其厚度至少要大於0 · 1微米。此外，位在上面之打線導線 接合層的材質亦可以是鋁。 在如第8 b圖所示之另一較佳實施例中，複合金屬層係 由兩層金屬層所構成，第一厚導電層34的材質包括銅，係 位於種子層3 3上，在較佳的情況下，其厚度係約略大於1 微米。第二金屬層3 8係作為與打線導線連接之用的，而第 二金屬層38係位於第一厚導電層34上，在較佳的情況下， 第二金屬層38包括比如是0.1微米厚的金層或是I呂層。 在如第8 c圖所示之較佳實施例中，可以利用電鍍的方 式形成銲料40，作為厚的導電金屬層，其材質比如包括含 錯合金、锡、含錫合金、或比如是錫銀合金或錫銀銅合金 之無鉛銲料。而種子層33比如包括銅或鎳。 在如第7圖及第8 a _ 8 c圖所示之實施例中，緩衝金屬接 墊的製造方法係如下所述。首先要提供半導體晶圓，半導 體晶圓具有位在上層的接墊，而保護層18可以暴露出這些 接墊。接著，可以利用濺鍍的方式，沈積黏著/阻障層2 9 及可以作為電鍍之用的種子層33。接著，可以塗佈一光阻 層3 1在晶圓上，而藉由習知的微影技術可以形成接墊開 口 ，貫穿光阻層31。接著可以利用電鍍的方式，依序形成 如這些圖所示的金屬層，其中利用電鍍的方式可以形成位 於頂層且能夠與打線導線連接之金屬層3 8，其材質比如是Page 17 200425366 V. Description of the invention (12) The thickness of the conductive layer is approximately greater than 1 micrometer, and the nickel layer 36 in the middle part is a diffusion barrier layer, and its thickness is slightly between 1 micrometer to 5 Between micrometers. The gold layer 38 above is a metal that can be bonded to the wire, and its thickness must be at least greater than 0 · 1 micron. In addition, the material of the bonding layer of the wire conductor on the top may be aluminum. In another preferred embodiment shown in FIG. 8b, the composite metal layer is composed of two metal layers. The material of the first thick conductive layer 34 includes copper, which is located on the seed layer 33. In the best case, the thickness is about 1 micron. The second metal layer 38 is used for connection with the wire, and the second metal layer 38 is located on the first thick conductive layer 34. In a preferred case, the second metal layer 38 includes, for example, 0.1 micron thick. Gold layer or I Lu layer. In the preferred embodiment shown in FIG. 8c, the solder 40 can be formed by electroplating as a thick conductive metal layer, and the material thereof includes, for example, an alloy containing tin, tin, a tin-containing alloy, or, for example, tin-silver Lead-free solders for alloys or tin-silver-copper alloys. The seed layer 33 includes, for example, copper or nickel. In the embodiments shown in Figs. 7 and 8a to 8c, the manufacturing method of the cushion metal pad is as follows. First, a semiconductor wafer is provided. The semiconductor wafer has pads on the upper layer, and the protective layer 18 can expose these pads. Then, the adhesion / barrier layer 29 and the seed layer 33 which can be used for electroplating can be deposited by sputtering. Next, a photoresist layer 31 can be coated on the wafer, and a pad opening can be formed through the photoresist layer 31 by a conventional lithography technique. Next, metal layers such as those shown in the figures can be sequentially formed by electroplating. Among them, the metal layer 38 can be formed on the top layer and can be connected to the wire. The material is, for example,

11944twf.ptd 第18頁 20042536611944twf.ptd Page 18 200425366

金。或者，亦可以利用無電電鍍 , 導線連接之金屬層38，其厚产可、方式，形成能夠與打線 以將光阻去除。接著，^以二二2二岔丨㈣埃。接著，可 f = 者/阻障層29。至此，便完成可以與 打線導線連接之緩衝金屬層。 、如第8a — 8c圖所示的結構，各金屬層的厚度係如下所 述· 1.在較佳的情況下，銅層34的厚度係約略大於1微 米0 2 ·在較佳的情況下，作為擴散阻障層之鎳層3 6的厚度 係約略大於〇· 5微米。 3 ·在較佳的情況下，可以與打線導線連接之金層3 8的 厚度係約略大於1 〇 〇埃。 4 ·在較佳的情況下，比如是含鉛合金、錫或含錫合金 之金屬層40的厚度係約略大於1微米。 值得注意的是，如第8 c圖所示之剖面結構，可以另外 形成比如是銅層34或鎳層36之金屬層在金屬層40與黏著/ 阻障層2 9之間。 為了要調整金層的硬度，可以使金層進行退火 (annealing)或回火（tempering)的製程，比如將金層加熱 到120 C與350 C之間，而製作完成之金層的硬度係介於' 150Hv到15Hv之間。一般而言，若是金層需要較高的硬 度’則需要在較低的溫度下進行退火或回火製程；而若是gold. Alternatively, it is also possible to use electroless plating and a wire-connected metal layer 38, which can be formed in a thick manner and can be wired to remove the photoresist. Then, ^ to 2 2 2 2 Cha 丨 ㈣ ㈣. Then, f = = / barrier layer 29. At this point, the buffer metal layer that can be connected to the wire is completed. As shown in Figures 8a-8c, the thickness of each metal layer is as follows: 1. In a better case, the thickness of the copper layer 34 is slightly greater than about 1 micron. 0 2 In a better case The thickness of the nickel layer 36 as the diffusion barrier layer is approximately greater than 0.5 micrometers. 3 · In a better case, the thickness of the gold layer 38 that can be connected to the wire is approximately greater than 100 angstroms. 4. In a preferred case, the thickness of the metal layer 40, such as a lead-containing alloy, tin, or a tin-containing alloy, is approximately greater than about 1 micron. It should be noted that, as shown in the cross-sectional structure in FIG. 8c, a metal layer such as a copper layer 34 or a nickel layer 36 may be additionally formed between the metal layer 40 and the adhesion / barrier layer 29. In order to adjust the hardness of the gold layer, the gold layer can be subjected to an annealing or tempering process, such as heating the gold layer to between 120 C and 350 C, and the hardness of the completed gold layer is introduced. Between '150Hv and 15Hv. Generally speaking, if the gold layer requires higher hardness ’, it needs to be annealed or tempered at a lower temperature; and if it is

200425366 五、發明說明（14) 金層需要較低的硬度，則需要在較高的溫度下進行退火或 回火製程。在較佳的情況下，係在2 7 0 °C的溫度下進行退 火或回火製程，這時金層的硬度係約略等於50 Hv。另外， 比如可以在氮氣的環境下進行退火或回火製程。 如本發明所述之位在保護層1 8上之緩衝金屬層2 0可以 作為低電阻值之電源平面、接地平面或是可以作為訊號傳 輸的線路，如美國專利第6，3 8 3，9 1 6號所示，美國專利第 6，3 8 3，9 1 6號之揭露内容均可作為本案之參考資料。 在本發明中，緩衝金屬層之”緩衝π二字的意思係如下 所述。本發明之緩衝金屬墊係可以保護位在下層之主動元 件、被動元件或低介電常數之介電層，藉以避免在進行打 線製程時受到損壞。藉由緩衝金屬墊之彈性，可以緩衝應 力，而藉由緩衝金屬墊之延展性，可以吸收衝擊波。為了 要吸收機械能量，缓衝金屬墊必須要是軟性及延展性佳的 材質，且緩衝金屬墊要足夠厚。軟性金屬（具有較大的彈 性）並不能夠吸收太多的機械能量，但是塑性變形的過程 卻可以決定一個物體能夠吸收多少機械能量，而愈厚的物 體所能夠吸收的機械能量就愈大。比如是金、銅、銲料及 銘之金屬均屬於軟性材質，由於金與銲料具有較佳的延展 性（ductility)，因此金與銲料所能夠吸收的機械能量係 優於銅及銘。在較佳的情況下，緩衝金屬接塾的總厚度要 大於1 . 5微米，才能足夠地吸收與打線導線接合時所產生 的機械能量。 在本發明中，可以避免打線製程受到損壞的低介電係200425366 V. Description of the invention (14) The gold layer needs lower hardness, so it needs to be annealed or tempered at a higher temperature. In the best case, the annealing or tempering process is performed at a temperature of 270 ° C. At this time, the hardness of the gold layer is approximately equal to 50 Hv. In addition, for example, an annealing or tempering process can be performed in a nitrogen environment. The buffer metal layer 20 on the protective layer 18 according to the present invention can be used as a low-resistance power plane, a ground plane, or a signal transmission line, such as U.S. Patent No. 6,3 8 3,9 As shown in No. 16, the disclosures in U.S. Patent Nos. 6,3,8,3,9,16 can be used as reference materials in this case. In the present invention, the meaning of the word "buffering π" of the buffer metal layer is as follows. The buffer metal pad of the present invention can protect active components, passive components or a low-k dielectric layer in the lower layer. Avoid damage during the wire bonding process. The elasticity of the cushion metal pad can cushion the stress, and the ductility of the cushion metal pad can absorb shock waves. In order to absorb mechanical energy, the cushion metal pad must be soft and stretch Good material, and the cushion metal pad must be thick enough. Soft metal (with greater elasticity) cannot absorb too much mechanical energy, but the process of plastic deformation can determine how much mechanical energy an object can absorb, and the more Thick objects can absorb more mechanical energy. For example, gold, copper, solder, and metal are soft materials. Because gold and solder have better ductility, gold and solder can absorb it. The mechanical energy is better than copper and Ming. In the best case, the total thickness of the buffer metal joint is greater than 1.5 microns, Can sufficiently absorb the mechanical energy produced by bonding wires joined In the present invention, the wire routing can be avoided from being damaged low dielectric lines

11944twf.ptd 第20頁 200425366 五、發明說明（15) 數之介電材料包括由化學氣相沈積所形成之化學材料’比 如是聚亞芳香基醚（polyarylene)或聚笨並°惡口坐 (polybenzoxazole)等，或者是由旋塗方式所形成之介電 材料’比如是SiWCXOYHZ化合物。這些介電材質之介電常 數均甚低，一般係小於3，並且至少會小於由化學氣相沈 積所形成之二氧化矽的介電常數，其介電常數係約略等於 4.2° 相杈於將打線 在遠離主動區域處之傳 配置在主動元件上，因 於本發明之打線接墊的 衝效果，因此位於下層 術，由於 縮減晶片 如是金， 金屬的繞 在進 吸收打線 主動元件 藉由材質 生的力量 應力的情 再者 衝介電層 相較 佳的力量 低介電係 是將本發 本發明可 的尺寸。 而金具有 線並不會 行打線製 的力量， 或被動元 比如是铭 之效果並 況下，則 ’本發明 ，藉以吸 於習知技 吸收能力 數的材料 明之緩衝 峡回。罝 以將接墊 再者，由 甚佳的緩 受到限制 程時，由 因此可以 件受到損 的接墊來 不佳，並 會增加沈 可以選擇 收在打線 術，本發 ’並且由 作為介電 金屬接墊 於本發明 避免位在 害。然而 吸收打線 且若是在 積接墊及 性地形成 導線接合 明之緩衝 於在深次 層之技術 應用在深 之緩衝 緩衝金 ’在傳 導線接 接塾甚 蝕刻接 比如是 時所產 金屬接 微米的 係愈來 次微米 金屬接 屬接墊 統的技 合於接 厚且足 墊的困 有機材 生的應 墊可以 技術中 愈廣泛 的技術 統技 此可以 材質比 之連接 墊可以 下方的 術中， 墊所產 夠吸收 難度。 料的緩 力。 提供甚 ’採用 ’而若 tb .11944twf.ptd Page 20 200425366 V. Description of the invention (15) The number of dielectric materials includes chemical materials formed by chemical vapor deposition, such as polyarylene or polybenzyl. polybenzoxazole), or a dielectric material formed by a spin coating method, such as a SiWCXOYHZ compound. The dielectric constants of these dielectric materials are very low, generally less than 3, and at least smaller than the dielectric constant of silicon dioxide formed by chemical vapor deposition. The dielectric constant is approximately equal to 4.2 °. The wire is placed on the active device away from the active area. Because of the punching effect of the wire bonding pad of the present invention, it is located in the lower layer. Because the chip is reduced, the metal is wound and absorbed. The wire active device is made of material. The strength of the stress and the better dielectric strength of the dielectric layer are the dimensions that the present invention can adopt. And gold has the power of the line and does not perform the threading system, or passive elements such as the effect of the inscription, then ‘the present invention, the material of the absorption capacity of the known technology to absorb the buffer. In addition, when the pad is restricted by a very good process, it is not good because the pad can be damaged, and it will increase the Shen. You can choose to receive it in wire bonding, the hair, and use it as a dielectric. Metal pads are avoided in the present invention. However, if the wire is absorbed and if the bonding pad and the wire bonding are formed naturally, the buffering is applied to the deep sublayer technology. In the deep buffering buffer gold, the conductive wire is connected to the etching and the metal produced is micron. The more and more sub-micron metal is connected to the pad system. The technology can be used to connect thick and thick pads. It can be used in a wider range of technologies. This material can be compared with the connection pad. The production is difficult to absorb. Material. Provide even ‘adopt’ if tb.

200425366 五、發明說明（16) 具有甚佳的效果。其中，這些低介電常數之介電材料比如 是利用化學氣相沈積的方式或旋塗的方式所製成。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之隔離 範圍當視後附之申請專利範圍所界定者為準。200425366 V. Description of the invention (16) Has excellent effect. Among them, these low dielectric constant dielectric materials are made by, for example, chemical vapor deposition or spin coating. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The isolation scope shall be determined by the scope of the attached patent application.

11944twf.ptd 第22頁 200425366 圖式簡單說明 第1 a圖及第1 b圖繪示形成打線導線於積體電路晶片上 之習知方法。 第2圖繪示依照本發明第一較佳實施例之作為打線導 線連接之用的緩衝金屬之剖面示意圖。 第3圖繪示依照本發明第二較佳實施例之作為打線導 線連接之用的緩衝金屬之剖面示意圖。 第4 a圖及第4 b圖繪示依照本發明第三較佳實施例之作 為打線導線連接之用的緩衝金屬之剖面示意圖。 第5 a圖至第5 c圖繪示依照本發明第四較佳實施例之剖 面示意圖，其中緩衝金屬接墊係位於緩衝材料上，而打線 導線可以與緩衝金屬接墊連接。 第6圖繪示依照本發明第五較佳實施例之剖面示意 圖，其中緩衝金屬接墊係位於緩衝材料上，而打線導線可 以與緩衝金屬接墊連接。 第7圖繪示緩衝金屬的剖面示意圖。 第8 a圖至第8 c圖繪示緩衝金屬之詳細結構。 圖式標示說明】 1 0 :基底 14 :介電層 1 6 :金屬間介電層 1 8 :保護層 2 0 :緩衝金屬層 23 :開口 12 :半導體元件 1 5 :金屬連接線路 1 7 :接墊 19 :開口 2 2 :打線導線 2 4 :緩衝介電層11944twf.ptd Page 22 200425366 Brief Description of Drawings Figures 1a and 1b show the conventional method of forming wire on the integrated circuit chip. Fig. 2 is a schematic cross-sectional view of a buffer metal used for wire connection according to a first preferred embodiment of the present invention. Fig. 3 is a schematic cross-sectional view of a buffer metal used for wire connection according to a second preferred embodiment of the present invention. Figures 4a and 4b are schematic cross-sectional views of a buffer metal used for wire bonding according to a third preferred embodiment of the present invention. Figures 5a to 5c show schematic sectional views according to a fourth preferred embodiment of the present invention. The buffer metal pads are located on the buffer material, and the wire can be connected to the buffer metal pads. Fig. 6 is a schematic cross-sectional view of a fifth preferred embodiment of the present invention, in which a buffer metal pad is located on a buffer material, and a wire can be connected to the buffer metal pad. FIG. 7 is a schematic cross-sectional view of a buffer metal. Figures 8a to 8c show the detailed structure of the buffer metal. Description of the diagrams] 10: substrate 14: dielectric layer 16: intermetal dielectric layer 18: protective layer 2 0: buffer metal layer 23: opening 12: semiconductor element 1 5: metal connection line 1 7: connection Pad 19: Opening 2 2: Wire bonding wire 2 4: Buffer dielectric layer

11944twf.ptd 第23頁 200425366 圖式簡單說明 25 側 壁 26 :緩 衝 金屬層 28 打 線 導 線 29 黏 著‘ /阻障層 30 種 子 層 31 光 阻 層 32 接 墊 層 33 種 子 層 34 金 屬 層 36 金 屬 層 38 金 屬 層 40 銲 料 70 第 一 區 域 71 基 底 72 主 動 元 件 或 被 動 元件 73 第 一 連 線 金 屬 層 74 接 觸 窗 75 ： :第 二 區域 76 連 線 金 屬 層 77 : 接 墊 80 ： ，打 線 導 線11944twf.ptd Page 23 200425366 Brief description of drawings 25 Side wall 26: Buffer metal layer 28 Wire bonding wire 29 Adhesive layer / Barrier layer 30 Seed layer 31 Photoresist layer 32 Pad layer 33 Seed layer 34 Metal layer 36 Metal layer 38 Metal Layer 40 solder 70 first area 71 substrate 72 active or passive component 73 first connection metal layer 74 contact window 75 :: second area 76 connection metal layer 77: pad 80: wire

11944twf.ptd 第24頁11944twf.ptd Page 24

Claims (1)

200425366 六、申請專利範圍 1 . 一種能夠連接打線導線於主動區域之晶片結構的製 作方法，至少包括： 提供一半導體基底，具有複數個主動元件或被動元件 形成於該半導體基底上； 提供一金屬連接線路，位在該些主動元件或被動元件 上，該金屬連接線路包括一上層金屬層； 提供一保護層，位在該金屬連接線路上，該保護層具 有複數個開口 ，貫穿該保護層並暴露出該上層金屬層；以 及 形成複數個緩衝金屬接墊於該保護層上，其中該些緩 衝金屬接墊係經過該些開口連接至該上層金屬層，並且該 些緩衝金屬接墊係位於該些主動元件或被動元件上。 2 .如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中該些緩衝金屬接墊 的厚度係大於1 . 5微米。 3. 如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中該些緩衝金屬接墊 係為複合層金屬結構，包括至少一厚金屬層及一金屬黏著 層。 4. 如申請專利範圍第3項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中該厚金屬層的厚度 係大於1微米。 5 .如申請專利範圍第3項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中係利用電鍍的方式200425366 VI. Scope of patent application 1. A method for fabricating a wafer structure capable of connecting wire bonding wires to an active area, at least comprising: providing a semiconductor substrate having a plurality of active or passive components formed on the semiconductor substrate; providing a metal connection The circuit is located on the active or passive components. The metal connection line includes an upper metal layer; a protection layer is provided on the metal connection line, the protection layer has a plurality of openings, penetrates the protection layer and is exposed. Forming the upper metal layer; and forming a plurality of buffer metal pads on the protective layer, wherein the buffer metal pads are connected to the upper metal layer through the openings, and the buffer metal pads are located in the Active or passive components. 2. The manufacturing method of a chip structure capable of connecting wire bonding wires to an active area as described in item 1 of the scope of patent application, wherein the thickness of the buffer metal pads is greater than 1.5 microns. 3. The manufacturing method of the chip structure capable of connecting the wire bonding wire to the active area as described in item 1 of the scope of the patent application, wherein the buffer metal pads are composite metal structures including at least a thick metal layer and a metal adhesion Floor. 4. The method for fabricating a wafer structure capable of connecting wire bonding wires to an active area as described in item 3 of the scope of patent application, wherein the thickness of the thick metal layer is greater than 1 micron. 5. The manufacturing method of a chip structure capable of connecting wire bonding wires to the active area as described in item 3 of the scope of patent application, wherein the method of plating is used 11944twf.ptd 第25頁 200425366 六、申請專利範圍 形成該厚金屬層。 6. 如申請專利範圍第3項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中該厚金屬層的材質 係選自於由金、銅、錫、含鉛合金、含錫合金、錫銀合金 及錫銀銅合金所組成之族群中之一種材質。 7. 如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中至少一該些緩衝金 屬接墊係位於對應之至少一該些開口上。 8. 如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中至少一該些緩衝金 屬接墊係相對於對應之至少一該些開口存在橫向地偏移。 9. 如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中每一該些開口之最 大寬度係至少大於0. 1微米。 1 0.如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，還包括形成一金屬間介 電層於該半導體基底上，並且位於該金屬連接線路之複數 層金屬層之間，其中該金屬間介電層係為一低介電常數之 材質。 1 1 .如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中該保護層包括一層 或多層之無機材料。 1 2.如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，還包括形成一黏著/阻11944twf.ptd Page 25 200425366 6. Scope of patent application The thick metal layer is formed. 6. The manufacturing method of the chip structure capable of connecting the wire to the active area as described in item 3 of the scope of patent application, wherein the material of the thick metal layer is selected from the group consisting of gold, copper, tin, lead-containing alloy, and tin Alloy, tin-silver alloy, and tin-silver-copper alloy. 7. The manufacturing method of the chip structure capable of connecting the wire to the active area as described in item 1 of the scope of the patent application, wherein at least one of the buffer metal pads is located on the corresponding at least one of the openings. 8. The manufacturing method of a chip structure capable of connecting wire bonding wires to the active area as described in item 1 of the scope of patent application, wherein at least one of the buffer metal pads is laterally offset relative to the corresponding at least one of the openings . 9. The manufacturing method of a wafer structure capable of connecting wire bonding wires to the active area as described in item 1 of the scope of the patent application, wherein the maximum width of each of these openings is at least greater than 0.1 micron. 10. The method for fabricating a wafer structure capable of connecting wire bonding wires to an active area as described in item 1 of the scope of the patent application, further comprising forming an intermetal dielectric layer on the semiconductor substrate and located on a plurality of the metal connection lines. Between two metal layers, wherein the intermetal dielectric layer is a material with a low dielectric constant. 1 1. The method for fabricating a wafer structure capable of connecting a wire bonding wire to an active area as described in item 1 of the scope of the patent application, wherein the protective layer includes one or more inorganic materials. 1 2. The manufacturing method of a chip structure capable of connecting wire bonding wires to the active area as described in item 1 of the scope of patent application, further comprising forming an adhesive / resistance 11944twf.ptd 第26頁 200425366 六、申請專利範圍 障層於該些緩衝金屬接墊下及該保護層上。 1 3 .如申請專利範圍第1 2項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該黏著/阻障層 之材質係選自於由鈦、鉻、鈦鎢合金、钽、鈕氮化合物及 鈦氮化合物所組成之族群中之一種材質。 1 4.如申請專利範圍第1 2項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該黏著/阻障層 的厚度係約小於等於3 0 0 0埃。 1 5 .如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中該些緩衝金屬接墊 包括一材質為金的厚金屬層，該厚金屬層的硬度係小於 150Hv，而金的純度係大於97%，並且該厚金屬層之厚度係 大於1微米。 1 6.如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中該些緩衝金屬接墊 包括一材質為金的厚金屬層，並且該些緩衝金屬接墊係在 1 2 0 °C到3 5 0 °C之間進行退火或回火製程。 1 7.如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中該些緩衝金屬接墊 包括一材質為金的厚金屬層，該厚金屬層係在氣氣的環境 下進行退火或回火製程。 1 8.如申請專利範圍第1 5項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，還包括形成一種子層 於該黏著/阻障層上，其中該種子層的材質係為金，且該11944twf.ptd Page 26 200425366 6. Scope of patent application The barrier layer is under the buffer metal pads and on the protective layer. 1 3. The method for fabricating a chip structure capable of connecting wire bonding wires to an active area as described in item 12 of the scope of patent application, wherein the material of the adhesion / barrier layer is selected from the group consisting of titanium, chromium, titanium tungsten alloy, A material of the group consisting of tantalum, button nitrogen compounds and titanium nitrogen compounds. 1 4. The method for fabricating a chip structure capable of connecting wire bonding wires to an active area as described in item 12 of the scope of the patent application, wherein the thickness of the adhesive / barrier layer is about 30.0 angstroms or less. 15. The manufacturing method of a chip structure capable of connecting a wire to a lead in an active area as described in item 1 of the scope of patent application, wherein the buffer metal pads include a thick metal layer made of gold, and the hardness of the thick metal layer The thickness is less than 150 Hv, the purity of gold is greater than 97%, and the thickness of the thick metal layer is greater than 1 micron. 16. The manufacturing method of a chip structure capable of connecting wire bonding wires to the active area as described in item 1 of the scope of patent application, wherein the buffer metal pads include a thick metal layer made of gold, and the buffer metal contacts The mat is annealed or tempered between 120 ° C and 350 ° C. 1 7. The manufacturing method of a chip structure capable of connecting wire bonding wires to the active area as described in item 1 of the scope of the patent application, wherein the buffer metal pads include a thick metal layer made of gold, and the thick metal layer is The annealing or tempering process is performed in a gas environment. 1 8. The method for fabricating a chip structure capable of connecting wire bonding wires to an active area as described in item 15 of the scope of patent application, further comprising forming a sub-layer on the adhesion / barrier layer, wherein the material of the seed layer is Is gold, and the 11944twf.ptd 第27頁 200425366 六、申請專利範圍 種子層的厚度係約略等於1 0 0 0埃。 1 9.如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，還包括形成一有機材料 層於該些緩衝金屬接墊與該保護層之間。 2 0 .如申請專利範圍第1 9項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中形成該有機材料 層之步驟依序包括旋塗感光材料之步驟、微影曝光之步 驟、顯影之步驟及烘烤之步驟。 2 1 .如申請專利範圍第1 9項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中形成該有機材料 層之步驟包括網板印刷之步驟及烘烤之步驟。 2 2.如申請專利範圍第1 9項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該有機材料層之 材質係選自於由聚醢亞胺（polyimide)、苯基環丁稀 (Benzocyclobutene ，BCB)、彈性體（elastomer)、石夕 _ (s i 1 i cone )、多孔性低介電係數之有機材料及聚對二甲苯 基（parylene)所組成之族群中之一種材質。 2 3.如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，還包括形成一個或多個 電源/接地平面及複數條輸出入訊號線路於該保護層上， 而該些電源/接地平面及該些輸出入訊號線路之材質係相 同於該緩衝金屬接墊之材質。 2 4.如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中該些緩衝金屬接墊11944twf.ptd Page 27 200425366 VI. Scope of patent application The thickness of the seed layer is approximately equal to 100 Angstroms. 19. The method for fabricating a wafer structure capable of connecting wire bonding wires to an active area as described in item 1 of the scope of the patent application, further comprising forming an organic material layer between the buffer metal pads and the protective layer. 20. The method for fabricating a wafer structure capable of connecting wire bonding wires to an active area as described in item 19 of the scope of patent application, wherein the step of forming the organic material layer includes a step of spin-coating a photosensitive material, and a step of lithographic exposure. Steps, development steps and baking steps. 2 1. The method for fabricating a wafer structure capable of connecting wire bonding wires to the active area as described in item 19 of the scope of patent application, wherein the step of forming the organic material layer includes a step of screen printing and a step of baking. 2 2. The manufacturing method of the chip structure capable of connecting the wire to the active area according to item 19 in the scope of the patent application, wherein the material of the organic material layer is selected from the group consisting of polyimide and phenyl One of the groups consisting of Benzocyclobutene (BCB), elastomer (elastomer), si 1 i cone, porous organic material with low dielectric constant, and parylene Material. 2 3. The manufacturing method of the chip structure capable of connecting the wire to the active area as described in item 1 of the scope of patent application, further comprising forming one or more power / ground planes and a plurality of input / output signal lines on the protective layer The materials of the power / ground planes and the input / output signal lines are the same as those of the buffer metal pads. 2 4. The manufacturing method of the chip structure capable of connecting the wire to the active area as described in item 1 of the scope of patent application, wherein the buffer metal pads 11944twf.ptd 第28頁 200425366 六、申請專利範圍 包括一材質為金的厚金屬層、一材質為金的種子層及一黏 著/阻障層，均位於該保護層上，而該種子層係位於該黏 著/阻障層上，該厚金屬層係位於該種子層上。 2 5.如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中每一該些緩衝金屬 接墊係經由貫穿該保護層之其中一個或其中多個之該些開 口連接至該上層金屬層。 2 6 .如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中每一該些緩衝金屬 接墊係經由貫穿該保護層之其中超過一個之該些開口連接 至該上層金屬層。 2 7.如申請專利範圍第1項所述之能夠連接打線導線於 主動區域之晶片結構的製作方法，其中每一該些緩衝金屬 接墊係經由貫穿該保護層之其中單——個之該些開口連接 至該上層金屬層。 2 8. —種能夠連接打線導線於主動區域之晶片結構的 製作方法，至少包括： 提供一半導體基底，具有複數個主動元件或被動元件 形成於該半導體基底上； 提供一金屬連接線路，位在該些主動元件或被動元件 上，該金屬連接線路包括一上層金屬層； 提供一保護層，位在該金屬連接線路上，該保護層具 有複數個開口 ，貫穿該保護層並暴露出該上層金屬層； 沈積一黏著/阻障層於該保護層上及該些開口中；11944twf.ptd Page 28 200425366 6. The scope of patent application includes a thick metal layer made of gold, a seed layer made of gold, and an adhesion / barrier layer, all located on the protective layer, and the seed layer is located on On the adhesion / barrier layer, the thick metal layer is located on the seed layer. 2 5. The manufacturing method of a chip structure capable of connecting wire bonding wires to the active area as described in item 1 of the scope of the patent application, wherein each of the buffer metal pads passes through one or more of the protective layers. The openings are connected to the upper metal layer. 26. The manufacturing method of the chip structure capable of connecting the wire bonding wire to the active area as described in item 1 of the scope of patent application, wherein each of the buffer metal pads passes through more than one of the openings penetrating the protective layer. Connected to the upper metal layer. 2 7. The manufacturing method of the chip structure capable of connecting the wire to the active area as described in item 1 of the scope of the patent application, wherein each of the buffer metal pads passes through one or more of the protective layers. Openings are connected to the upper metal layer. 2 8. —A method for manufacturing a wafer structure capable of connecting wire bonding wires to an active area, at least including: providing a semiconductor substrate having a plurality of active or passive components formed on the semiconductor substrate; providing a metal connection line located at On the active or passive components, the metal connection line includes an upper metal layer; a protection layer is provided on the metal connection line, the protection layer has a plurality of openings, penetrates the protection layer and exposes the upper layer metal Depositing an adhesion / barrier layer on the protective layer and in the openings; 11944twf.ptd 第29頁 200425366 六、申請專利範圍 沈積一用於電鍍之種子層於該黏著/阻障層上； 沈積一光阻於該半導體基底上，並形成複數個接墊開 口於該光阻中； 利用電鍍的方式，形成複數個緩衝金屬接墊於該些接 墊開口中； 去除該光阻；以及 利用該些緩衝金屬接墊作為罩蔽並去除位在該些緩衝 金屬接墊外之該種子層及該黏著/阻障層，其中該些緩衝 金屬接墊係經過該些開口連接至該上層金屬層，並且該些 緩衝金屬接墊係位於該些主動元件或被動元件上。 2 9 .如申請專利範圍第2 8項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該黏著/阻障層 之材質係選自於由鈦、鉻、鈦鹤合金、钽、钽氮化合物及 鈦氮化合物所組成之族群中之一種材質。 3 0 .如申請專利範圍第2 8項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該些緩衝金屬接 墊及該種子層係由金所構成。 3 1 .如申請專利範圍第2 8項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中在形成該些緩衝 金屬接墊時，係先利用電鍍的方式形成一材質為銅之厚金 屬層於該種子層上，接著再利用電鑛的方式形成一鎳層於 該厚金屬層上，接著再利用電鍍的方式形成一可以與打線 導線連接之金層層於該鎳層上。 3 2.如申請專利範圍第3 1項所述之能夠連接打線導線11944twf.ptd Page 29 200425366 VI. Patent application scope Deposit a seed layer for electroplating on the adhesion / barrier layer; deposit a photoresist on the semiconductor substrate and form a plurality of pad openings in the photoresist Medium; forming a plurality of buffer metal pads in the pad openings by electroplating; removing the photoresist; and using the buffer metal pads as a mask and removing the ones located outside the buffer metal pads The seed layer and the adhesion / barrier layer, wherein the buffer metal pads are connected to the upper metal layer through the openings, and the buffer metal pads are located on the active components or passive components. 29. The manufacturing method of the chip structure capable of connecting the wire to the active area as described in item 28 of the scope of the patent application, wherein the material of the adhesion / barrier layer is selected from the group consisting of titanium, chromium, titanium crane alloy, A material of the group consisting of tantalum, tantalum nitrogen compounds and titanium nitrogen compounds. 30. The method for fabricating a chip structure capable of connecting wire bonding wires to an active area as described in item 28 of the scope of patent application, wherein the buffer metal pads and the seed layer are made of gold. 31. The manufacturing method of a chip structure capable of connecting wire bonding wires to the active area as described in item 28 of the scope of patent application, wherein when forming the buffer metal pads, a material of copper is first formed by electroplating. A thick metal layer on the seed layer, and then a nickel layer is formed on the thick metal layer by means of electric ore, and then a gold layer that can be connected to the wire is formed on the nickel layer by means of electroplating. . 3 2. Capable of connecting wire as described in item 31 of the scope of patent application 11944twf.ptd 第30頁 200425366 六、申請專利範圍 於主動區域之晶片結構的製作方法，其中該厚金屬層的厚 度係大於1微米。 3 3.如申請專利範圍第3 1項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該鎳層的厚度係 大於0 . 5微米。 3 4.如申請專利範圍第3 1項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該鎳層的厚度係 介於1微米到5微米之間。 3 5 .如申請專利範圍第3 1項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該金層的厚度係 大於1 0 0埃。 3 6.如申請專利範圍第3 3項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中在形成該些緩衝 金屬接墊時，係先利用電鍍的方式形成一材質為銅之厚金 屬層於該些接墊開口中及該種子層上，接著再利用電鍍的 方式形成一可以與打線導線連接之金層於該厚金屬層上。 3 7.如申請專利範圍第3 6項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該厚金屬層的厚 度係大於1微米。 3 8.如申請專利範圍第3 6項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該金層的厚度係 大於1 00埃。 . 3 9.如申請專利範圍第2 8項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中在形成該些緩衝11944twf.ptd Page 30 200425366 6. Scope of Patent Application The manufacturing method of the wafer structure in the active area, wherein the thickness of the thick metal layer is greater than 1 micron. 3 3. The method for fabricating a wafer structure capable of connecting wire bonding wires to an active area as described in item 31 of the scope of patent application, wherein the thickness of the nickel layer is greater than 0.5 micrometers. 3 4. The method for fabricating a wafer structure capable of connecting wire bonding wires to the active area as described in item 31 of the scope of patent application, wherein the thickness of the nickel layer is between 1 micrometer and 5 micrometers. 35. The method for fabricating a chip structure capable of connecting wire bonding wires to an active area as described in item 31 of the scope of patent application, wherein the thickness of the gold layer is greater than 100 angstroms. 3 6. The manufacturing method of the chip structure capable of connecting the wire bonding wire to the active area as described in item 33 of the scope of patent application, wherein when forming the buffer metal pads, a material of copper is first formed by electroplating. A thick metal layer is formed in the pad openings and the seed layer, and then a gold layer that can be connected to the wire is formed on the thick metal layer by electroplating. 37. The method for fabricating a wafer structure capable of connecting wire bonding wires to the active area as described in item 36 of the scope of patent application, wherein the thickness of the thick metal layer is greater than 1 micron. 38. The manufacturing method of a wafer structure capable of connecting wire bonding wires to the active area as described in item 36 of the scope of patent application, wherein the thickness of the gold layer is greater than 100 angstroms. 3 9. The manufacturing method of a chip structure capable of connecting wire bonding wires to the active area as described in item 28 of the scope of patent application, wherein these buffers are formed 11944twf.ptd 第31頁 200425366 六、申請專利範圍 金屬接墊時，係先利用電鍍的方式形成一銲料於該些接墊 開口中及該種子層上，接著再利用電鍍的方式形成一可以 與打線導線連接之金層於該銲料上。 4 0 .如申請專利範圍第3 9項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該銲料的材質係 選自於由含鉛合金、錫、含錫合金、錫銀合金及錫銀銅合 金所組成之族群中之一種材質。 4 1 .如申請專利範圍第4 0項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該種子層的材質 係選自於由銅及鎳所組成之族群中之一種材質。 4 2 .如申請專利範圍第4 0項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該銲料的厚度係 大於1微米。 4 3 .如申請專利範圍第4 0項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中該金層的厚度係 大於1 0 0埃。 4 4.如申請專利範圍第2 8項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中每一該些缓衝金 屬接墊係經由貫穿該保護層之其中一個或其中多個之該些 開口連接至該上層金屬層。 4 5.如申請專利範圍第2 8項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中每一該些緩衝金 屬接墊係經由貫穿該保護層之其中超過一個之該些開口連 接至該上層金屬層。11944twf.ptd Page 31 200425366 6. When applying for a patent for metal pads, a solder is first formed in the pad openings and the seed layer by means of electroplating, and then electroplating is used to form a solderable wire. A gold layer of wire connection is on the solder. 40. The method for fabricating a chip structure capable of connecting wire bonding wires to an active area as described in item 39 of the scope of the patent application, wherein the material of the solder is selected from the group consisting of lead-containing alloys, tin, tin-containing alloys, and tin-silver A material of the group consisting of alloys and tin-silver-copper alloys. 41. The method for fabricating a chip structure capable of connecting wire bonding wires to the active area as described in item 40 of the scope of patent application, wherein the material of the seed layer is one selected from the group consisting of copper and nickel . 42. The method for manufacturing a wafer structure capable of connecting wire bonding wires to the active area as described in item 40 of the scope of patent application, wherein the thickness of the solder is greater than 1 micron. 43. The method for fabricating a chip structure capable of connecting wire bonding wires to an active area as described in item 40 of the scope of patent application, wherein the thickness of the gold layer is greater than 100 angstroms. 4 4. The manufacturing method of the chip structure capable of connecting the wire bonding wire to the active area as described in item 28 of the scope of patent application, wherein each of the buffer metal pads passes through one or more of the protective layers. The openings are connected to the upper metal layer. 4 5. The manufacturing method of the chip structure capable of connecting the wire bonding wire to the active area as described in item 28 of the scope of the patent application, wherein each of the buffer metal pads passes through more than one of the protective layers. The opening is connected to the upper metal layer. 11944twf.ptd 第32頁 200425366 六、申請專利範圍 4 6 .如申請專利範圍第2 8項所述之能夠連接打線導線 於主動區域之晶片結構的製作方法，其中每一該些緩衝金 屬接墊係經由貫穿該保護層之其中單——個之該些開口連 接至該上層金屬層。 4 7. —種能夠連接打線導線之晶片結構，至少包括： 一半導體基底，具有複數個主動元件或被動元件形成 於該半導體基底上； 一金屬連接線路，位在該些主動元件或被動元件上， 該金屬連接線路包括一上層金屬層； 一保護層，位在該金屬連接線路上，該保護層具有複 數個開口 ，貫穿該保護層並暴露出該上層金屬層；以及 複數個緩衝金屬接墊，位於該保護層上，而該些緩衝 金屬接墊係為複合層金屬結構，其中該些緩衝金屬接墊係 經過該些開口連接至該上層金屬層，並且該些緩衝金屬接 墊係位於該些主動元件或被動元件上。 4 8.如申請專利範圍第4 7項所述之能夠連搂打線導線 之晶片結構，其中該些緩衝金屬接墊的厚度係大於1 . 5微 米。 4 9 .如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，其中該些緩衝金屬接墊包括至少一厚金屬層 及一金屬黏著層。 5 0 .如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，其中該些緩衝金屬接墊包括至少一黏著層、 一厚金屬層及一可以與打線導線連接之金屬層，該黏著層11944twf.ptd Page 32 200425366 VI. Application for patent scope 46. The manufacturing method of the chip structure capable of connecting the wire to the active area as described in item 28 of the patent application scope, wherein each of these buffer metal pads is Connected to the upper metal layer through one or more of the openings through the protective layer. 4 7. —A chip structure capable of connecting wire bonding wires, including at least: a semiconductor substrate having a plurality of active or passive components formed on the semiconductor substrate; a metal connection line on the active or passive components The metal connection line includes an upper metal layer; a protective layer located on the metal connection line, the protective layer having a plurality of openings penetrating the protective layer and exposing the upper metal layer; and a plurality of buffer metal pads Is located on the protective layer, and the buffer metal pads are composite metal structures, wherein the buffer metal pads are connected to the upper metal layer through the openings, and the buffer metal pads are located on the Some active or passive components. 4 8. The chip structure capable of connecting wire bonding wires as described in item 47 of the scope of patent application, wherein the thickness of the buffer metal pads is greater than 1.5 micrometers. 49. The chip structure capable of connecting wire bonding wires according to item 47 of the scope of patent application, wherein the buffer metal pads include at least a thick metal layer and a metal adhesive layer. 50. The chip structure capable of connecting wire bonding wires as described in item 47 of the scope of the patent application, wherein the buffer metal pads include at least an adhesive layer, a thick metal layer, and a metal layer that can be connected to the wire bonding wires, The adhesive layer 11944twf.ptd 第33頁 200425366 六、申請專利範圍 係位於底層，該厚金屬層係位於該黏著層上，而該可以與 打線導線連接之金屬層係位於頂層。 5 1 .如申請專利範圍第5 0項所述之能夠連接打線導線 之晶片結構，其中該厚金屬層的厚度係大於1微米。 5 2.如申請專利範圍第5 0項所述之能夠連接打線導線 之晶片結構，其中該厚金屬層的材質係選自於由銅、鎳、 錫、錫鉛合金、錫銀合金及錫銀銅合金所組成之族群中之 一種材質。 5 3.如申請專利範圍第5 0項所述之能夠連接打線導線 之晶片結構，其中該黏著層的材質係選自於由鈦、鈦鎢合 金、鈦氮化合物、钽、钽氮化合物及鉻所組成之族群中之 一種材質。 5 4.如申請專利範圍第5 0項所述之能夠連接打線導線 之晶片結構，其中該可以與打線導線連接之金屬層的材質 係選自於由金及鋁所組成之族群中之一種材質。 5 5 .如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，其中該些緩衝金屬接墊之至少一個係相對於 對應之一個或多個之該些開口存在橫向地偏移。 5 6 .如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，其中該些緩衝金屬接墊之至少一個係位於對 應之一個或多個之該些開口上。 5 7 .如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，其中該些緩衝金屬接墊係由銅層/鎳層/金層 所構成之複合層結構，而該銅層係位於該些緩衝金屬接墊11944twf.ptd Page 33 200425366 6. The scope of patent application is located on the bottom layer, the thick metal layer is located on the adhesive layer, and the metal layer that can be connected to the wire is located on the top layer. 51. The chip structure capable of connecting wire bonding wires as described in item 50 of the scope of patent application, wherein the thickness of the thick metal layer is greater than 1 micron. 5 2. The chip structure capable of connecting wire bonding wires according to item 50 of the scope of patent application, wherein the material of the thick metal layer is selected from the group consisting of copper, nickel, tin, tin-lead alloy, tin-silver alloy, and tin-silver A material in a group of copper alloys. 5 3. The chip structure capable of connecting wire bonding wires as described in item 50 of the scope of patent application, wherein the material of the adhesive layer is selected from the group consisting of titanium, titanium tungsten alloy, titanium nitrogen compound, tantalum, tantalum nitrogen compound, and chromium One of the materials in the group. 5 4. The chip structure capable of connecting wire bonding wires as described in item 50 of the scope of patent application, wherein the material of the metal layer that can be connected to wire bonding wires is one selected from the group consisting of gold and aluminum . 5 5. The chip structure capable of connecting wire bonding wires as described in item 47 of the scope of patent application, wherein at least one of the buffer metal pads is laterally offset relative to the corresponding one or more of the openings . 56. The chip structure capable of connecting wire bonding wires according to item 47 of the scope of the patent application, wherein at least one of the buffer metal pads is located on the corresponding one or more of the openings. 57. The chip structure capable of connecting wire bonding wires as described in item 47 of the scope of patent application, wherein the buffer metal pads are a composite layer structure composed of a copper layer / nickel layer / gold layer, and the copper layer Are located on these buffer metal pads 11944twf.ptd 第34頁 200425366 六、申請專利範圍 之底層。 5 8.如申請專利範圍第5 7項所述之能夠連接打線導線 之晶片結構，其中該些緩衝金屬接墊係位於一材質為銅之 種子層上，而該些缓衝金屬接墊之該銅係為一厚金屬層， 該些緩衝金屬接墊之該鎳係為一擴散阻障層。 5 9 .如申請專利範圍第5 8項所述之能夠連接打線導線 之晶片結構，其中該厚金屬層的厚度係大於1微米。 6 0 .如申請專利範圍第5 8項所述之能夠連接打線導線 之晶片結構，其中該擴散阻障層的厚度係大於0 . 5微米。 6 1 .如申請專利範圍第5 8項所述之能夠連接打線導線 之晶片結構，其中該擴散阻障層的厚度係介於1微米到5微 米之間。 6 2.如申請專利範圍第5 8項所述之能夠連接打線導線 之晶片結構，其中該些緩衝金屬接墊之該金層，係可以與 至少一打線導線連接，其厚度係大於1 〇 〇埃。 6 3 .如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，其中該些緩衝金屬接墊係由銅層/金層所構 成之複合層結構，而該銅層係位於該些緩衝金屬接墊之底 層，且該銅層係為一厚金屬層。 6 4.如申請專利範圍第6 3項所述之能夠連接打線導線 之晶片結構，其中該些緩衝金屬接墊係位於一材質為銅之 種子層上。 6 5 .如申請專利範圍第6 3項所述之能夠連接打線導線 之晶片結構，其中該厚金屬層的厚度係大於1微米。11944twf.ptd Page 34 200425366 6. The bottom of the scope of patent application. 5 8. The chip structure capable of connecting wire bonding wires as described in item 57 of the scope of patent application, wherein the buffer metal pads are located on a seed layer made of copper, and the buffer metal pads are The copper system is a thick metal layer, and the nickel system of the buffer metal pads is a diffusion barrier layer. 599. The wafer structure capable of connecting wire bonding wires as described in item 58 of the scope of patent application, wherein the thickness of the thick metal layer is greater than 1 micron. 60. The chip structure capable of connecting wire bonding wires as described in item 58 of the scope of patent application, wherein the thickness of the diffusion barrier layer is greater than 0.5 microns. 6 1. The chip structure capable of connecting wire bonding wires as described in item 58 of the scope of patent application, wherein the thickness of the diffusion barrier layer is between 1 micrometer and 5 micrometers. 6 2. The chip structure capable of connecting wire bonding wires as described in item 58 of the scope of patent application, wherein the gold layer of the buffer metal pads can be connected to at least one wire bonding wire, and the thickness is greater than 100. Aye. 63. The chip structure capable of connecting wire bonding wires as described in item 47 of the scope of patent application, wherein the buffer metal pads are a composite layer structure composed of a copper layer / gold layer, and the copper layer is located in the The bottom layer of the buffer metal pads, and the copper layer is a thick metal layer. 64. The chip structure capable of connecting wire bonding wires as described in item 63 of the scope of patent application, wherein the buffer metal pads are located on a seed layer made of copper. 65. The chip structure capable of connecting wire bonding wires according to item 63 of the scope of patent application, wherein the thickness of the thick metal layer is greater than 1 micron. 11944twf.ptd 第 35 頁 200425366 六、申請專利範圍 6 6.如申請專利範圍第6 3項所述之能夠連接打線導線 之晶片結構，其中該些緩衝金屬接墊之該金層，係可以與 導線導線連接，其厚度係大於1 0 0埃。 6 7.如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，其中該些緩衝金屬接墊係由銲料/金層所構 成之複合層結構，而該銲料係位於該些緩衝金屬接墊之底 層。 6 8.如申請專利範圍第6 7項所述之能夠連接打線導線 之晶片結構，其中該些緩衝金屬接墊係位於一種子層上， 而該種子層之材質係選自於由銅及鎳所組成之族群中之一 種材質。 6 9 .如申請專利範圍第6 8項所述之能夠連接打線導線 之晶片結構，其中該銲料層的材質係選自於由含鉛合金、 锡、含錫合金、錫銀合金及錫銀銅合金所組成之族群中之 一種材質。 7 0 .如申請專利範圍第6 7項所述之能夠連接打線導線 之晶片結構，其中該銲料的厚度係大於1微米。 7 1 .如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，其中每一該些開口之最大寬度係至少大於0. 1微米。 7 2.如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，還包括一金屬間介電層，位於該半導體基底 上，其中該金屬間介電層係為一低介電常數之材質。 7 3.如申請專利範圍第4 7項所述之能夠連接打線導線11944twf.ptd Page 35 200425366 6. Application for patent scope 6 6. The chip structure capable of connecting wire as described in item 63 of the scope of patent application, wherein the gold layer of the buffer metal pads can be connected with the wire The thickness of the wire connection is greater than 100 angstroms. 6 7. The chip structure capable of connecting wire bonding wires as described in item 47 of the scope of patent application, wherein the buffer metal pads are a composite layer structure composed of a solder / gold layer, and the solder is located on the buffers The bottom layer of metal pads. 6 8. The chip structure capable of connecting wire bonding wires as described in item 67 of the scope of patent application, wherein the buffer metal pads are located on a sub-layer, and the material of the seed layer is selected from copper and nickel One of the materials in the group. 69. The chip structure capable of connecting wire bonding wires according to item 68 of the scope of patent application, wherein the material of the solder layer is selected from the group consisting of lead-containing alloy, tin, tin-containing alloy, tin-silver alloy, and tin-silver-copper. A material in a group of alloys. 70. The chip structure capable of connecting wire bonding wires as described in item 67 of the scope of patent application, wherein the thickness of the solder is greater than 1 micron. 1 μ。 As described in the scope of patent applications No. 4 7 of the chip structure capable of connecting wire bonding wires, wherein the maximum width of each of these openings is at least greater than 0.1 microns. 7 2. The chip structure capable of connecting wire bonding wires according to item 47 of the scope of patent application, further comprising an intermetal dielectric layer on the semiconductor substrate, wherein the intermetal dielectric layer is a low dielectric Constant material. 7 3. Capable of connecting wire as described in item 4 7 of the scope of patent application 11944twf.ptd 第36頁 200425366 六、申請專利範圍 之晶片結構，其中該保護層包括一層或多層之無機材料。 7 4.如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，還包括一黏著/阻障層，位於該些緩衝金屬 接墊下。 7 5 .如申請專利範圍第7 4項所述之能夠連接打線導線 之晶片結構，其中該黏著/阻障層之材質係選自於由鈦、 鉻、鈦鎢合金、鈕、钽氮化合物及鈦氮化合物所組成之族 群中之一種材質。 7 6.如申請專利範圍第7 4項所述之能夠連接打線導線 之晶片結構，其中該黏著/阻障層係位於該保護層上及該 些開口中。 7 7.如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，還包括一有機材料層，位於該些緩衝金屬接 墊與該保護層之間。 7 8.如申請專利範圍第7 7項所述之能夠連接打線導線 之晶片結構，其中該有機材料層之材質係選自於由聚醯亞 胺（polyimide)、苯基環丁烯（Benzocyclobutene，BCB)、 彈性體、矽酮（s i 1 i c ο n e )、多孔性低介電係數之有機材料 及聚對二甲苯基（parylene)所組成之族群中之一種材質。 7 9.如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，還包括一個或多個電源/接地平面及複數條 輸出入訊號線路，位於該保護層上，而該些電源/接地平 面及該些輸出入訊號線路之材質係相同於該緩衝金屬接墊 之材質。11944twf.ptd Page 36 200425366 6. The wafer structure with patent application scope, where the protective layer includes one or more inorganic materials. 7 4. The chip structure capable of connecting wire bonding wires as described in item 47 of the scope of patent application, further comprising an adhesion / barrier layer under the buffer metal pads. 75. The chip structure capable of connecting wire bonding wires as described in item 74 of the scope of patent application, wherein the material of the adhesion / barrier layer is selected from the group consisting of titanium, chromium, titanium tungsten alloy, buttons, tantalum nitrogen compounds, and A material of a group consisting of titanium nitrogen compounds. 7 6. The chip structure capable of connecting wire bonding wires according to item 74 of the scope of patent application, wherein the adhesion / barrier layer is located on the protective layer and in the openings. 7 7. The chip structure capable of connecting wire bonding wires as described in item 47 of the scope of patent application, further comprising an organic material layer located between the buffer metal pads and the protective layer. 7 8. The chip structure capable of connecting the wire as described in item 7 of the scope of the patent application, wherein the material of the organic material layer is selected from the group consisting of polyimide, benzocyclobutene, BCB), elastomer, silicone (si 1 ic ο ne), porous low dielectric constant organic materials, and a group of parylene group of materials. 7 9. The chip structure capable of connecting wire wires as described in item 47 of the scope of patent application, further comprising one or more power / ground planes and a plurality of input / output signal lines, which are located on the protective layer, and the power sources The material of the ground plane and the I / O signal lines is the same as the material of the buffer metal pad. 11944twf.ptd 第37頁 200425366 六、申請專利範圍 8 0 .如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，其中每一該些緩衝金屬接墊係經由貫穿該保 護層之其中一個或其中多個之該些開口連接至該上層金屬 層。 8 1 .如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，其中每一該些緩衝金屬接墊係經由貫穿該保 護層之其中超過一個之該些開口連接至該上層金屬層。 8 2.如申請專利範圍第4 7項所述之能夠連接打線導線 之晶片結構，其中每一該些緩衝金屬接墊係經由貫穿該保 護層之其中單一一個之該些開口連接至該上層金屬層。 8 3 . —種能夠連接打線導線之晶片結構，至少包括： 一半導體基底，具有複數個主動元件或被動元件形成 於該半導體基底上； 一金屬連接線路，位在該些主動元件或被動元件上， 該金屬連接線路包括一上層金屬層； 一保‘層，位在該金屬連接線路上，該保護層具有複 數個第一開口 ，貫穿該保護層並暴露出該上層金屬層； 一有機材料層，位於該保護層上，該有機材料層具有 複數個第二開口，位於該些第一開口上，並暴露出該上層 金屬層；以及 複數個金接墊，位於該有機材料層上，而該些金接墊 係經過該些第一開口及該些第二開口連接至該上層金屬 層，並且該些金接塾係位於該些主動元件或被動元件上。 8 4. —種能夠連接打線導線之晶片結構，至少包括：11944twf.ptd Page 37 200425366 VI. Patent application scope 80. The chip structure capable of connecting wire bonding wires as described in item 47 of the patent application scope, wherein each of the buffer metal pads is passed through the protective layer. The one or more of the openings are connected to the upper metal layer. 81. The chip structure capable of connecting wire bonding wires as described in item 47 of the scope of patent application, wherein each of the buffer metal pads is connected to the upper metal layer through more than one of the openings penetrating the protective layer. Floor. 8 2. The chip structure capable of connecting wire bonding wires according to item 47 of the scope of patent application, wherein each of the buffer metal pads is connected to the upper metal layer through a single one of the openings penetrating the protective layer. Floor. 8 3. A wafer structure capable of connecting wire bonding wires, including at least: a semiconductor substrate having a plurality of active or passive components formed on the semiconductor substrate; a metal connection line on the active or passive components The metal connection line includes an upper metal layer; a protection layer is located on the metal connection line, the protection layer has a plurality of first openings, penetrates the protection layer and exposes the upper metal layer; an organic material layer Is located on the protective layer, the organic material layer has a plurality of second openings, is located on the first openings, and exposes the upper metal layer; and a plurality of gold pads are located on the organic material layer, and the The gold pads are connected to the upper metal layer through the first openings and the second openings, and the gold pads are located on the active components or passive components. 8 4. —A chip structure capable of connecting wire, including at least: 11944twf.ptd 第38頁 六、申請專利範圍 一半導體基底，具 " '--— 於該半=基底上；’、複數個主動元件或被 一金屬連接線路，位 i 千形成 該金屬連接線路包括一，j，主動元件或被動 -保護層，位在ϋ金屬層；〗被動凡件上， 數個開口 ’貫穿該保護G ”線路λ，該保護層… 複數個緩衝金屬接塾尤^路出該上層金屬層；以^歿 金屬接墊係為複合層金於该保護層上，而該此 墊係經過該些開0之复:二構’其中每一該歧缓二，衝 層，並且該#緩衝金屬分別連接至該上層金屬接 件上。 …位於該些主動元件或被I 85·如申請專利範園 之晶片結構，其中每一該此項所述之能夠連接打線導 之其中複數個分別連接至ς緩衝金屬接墊係經過該些開口 8 6·如申請專利範園第Λ上層金屬層之每一單一接墊。 之晶片結構，還包括複數項所述之能夠連接打線導 些缓衝金屬接墊，每一該=打線導線，分別連接於每一該 一該些緩衝金屬接塾所^二打線導線係位於與其連接之每 87.如申請專利範圍第1之複數個該些開口上。 之晶片結構，其中每一該此n述之能夠連接打線導線 之其中複數個分別連接至ς %衝金屬接墊係經過該些開口 88·^ t tt ^ ^ ^ ^ ^ ^ ^ 〇 之晶片結構1包括複數所^之此夠連接打線導線 些緩衝金屬接每，每一該此J f 分別連接於每一該 二打線導線係位於與其連接之每11944twf.ptd Page 38 VI. Patent application scope A semiconductor substrate with " --- on the half = substrate; ", a plurality of active components or a metal connection line, the metal connection line is formed by the thousands of bits. Including one, j, active element or passive-protective layer, which is located on the metal layer; on the passive component, several openings 'through the protective G' line λ, the protective layer ... a plurality of buffer metal connections, especially the road Out of the upper metal layer; ^ 接 metal pad system as a composite layer of gold on the protective layer, and the pad is passed through these open 0 complex: two structure 'Each of the two slow, two layers, And the #buffer metal is respectively connected to the upper metal connector.... It is located on the active components or the wafer structure of I 85 · as claimed in the patent application, each of which can be connected to the wire guide. The plurality of metal pads respectively connected to the buffer metal buffer pass through these openings 8 6 · As for each single pad of the upper metal layer of the patent application Fanyuan, the wafer structure also includes a plurality of items that can be connected to the wire guide. Buffer metal Each wire is connected to each of the buffer metal connectors. The two wires are located on each of the 87. Such as the number of openings in the scope of the patent application. Structure, each of which described above can be connected to a wire, a plurality of which are respectively connected to ς% punch metal pads through the openings 88 · ^ t tt ^ ^ ^ ^ ^ ^ ^ 〇 The chip structure 1 includes This is enough to connect the wiring wires with some buffer metal connections, and each one of these J f is connected to each of the two wiring wires. 11944twf.ptd 第39頁 200425366 六、申請專利範圍 ------- 一該些緩衝金屬接塾所經過之複數個該此 89·如申請專利範圍第84項所述之能^ 打 之晶片結構’ $包括-有機材料層，位於接線導線 墊與該保護層之間，該有機材料層具有複數^第衝^屬接 分別位於該保護層之該些開口上，該些緩二=口’ 別經由該些第二開口及該保護層之該些開口連f，塾係分 金屬層上。 σ亥上層 9 0·如申請專利範圍第89項所述之能夠連接打 之晶片結構，其中每一該些緩衝金屬接墊係經過該此1線 之其中複數個分別連接至該上層金屬層之备一抑X 一開口 91•如申請專利範圍第90項所述之能约連接 之晶片結構，還包括複數條打線導線，分別連接於t導;線 些緩衝金屬接墊，每一該些打線導線係位於與其連^， 一該些緩衝金屬接墊所經過之複數個該些開口上。 母 9 2 ·如申請專利範圍第8 9項所述之能夠連接打線導線 之晶片結構’其中母一該些緩衝金屬接塾係經過該'此開'口 之其中複數個分別連接至該上層金屬層之複數個接墊。 9 3 ·如申請專利对圍第9 2項所述之能夠連接打線導線 之晶片結構，還包括複數條打線導線，分別連接於每一該 些緩衝金屬接墊，每一該些打線導線係位於與其連接之每 一該些緩衝金屬接墊所經過之複數個該些開口上。 9 4. 一種能夠連接打線導線於低介電係數之介電層上 之晶片結構的製作方法，至少包括： 提供一半導體基底；11944twf.ptd Page 39 200425366 VI. Scope of patent application ------- A number of buffered metal contacts pass through these 89. The chip that can be hit as described in item 84 of the scope of patent application ^ Structure '$ include-organic material layer, located between the wiring lead pad and the protective layer, the organic material layer has a plurality of ^ first punches ^ metal connections are respectively located on the openings of the protective layer, the two slower = mouth' Do not connect f through the second openings and the openings of the protective layer, which are on the metal layer. σ 海上 层 9 0. The wafer structure capable of being connected as described in item 89 of the scope of the patent application, wherein each of the buffer metal pads is connected to the upper metal layer through a plurality of the one wires respectively. Prepare a X-open 91. The chip structure capable of being connected as described in item 90 of the scope of the patent application, and also includes a plurality of wire conductors, each connected to the T conductor; wire buffer metal pads, each of these wires The lead wires are located on the plurality of openings connected to the buffer metal pads. Female 9 2 · The chip structure capable of connecting wire bonding wires as described in item 8 and 9 of the scope of the patent application, wherein the female-to-buffer metal connectors are connected to the upper metal through the 'this opening' mouth respectively. Layers of pads. 9 3 · The chip structure capable of connecting wire bonding wires as described in Item 92 of the patent application, further comprising a plurality of wire bonding wires respectively connected to each of the buffer metal pads, each of the wire bonding wires is located at Each of the buffer metal pads connected to it passes through the plurality of openings. 9 4. A manufacturing method of a chip structure capable of connecting a wire to a dielectric layer with a low dielectric constant, at least comprising: providing a semiconductor substrate; 11944twf.ptd 第40頁 200425366 六、申請專利範圍 提供具有低介電係數之至少一介電層於該半導體基底 上； 提供一金屬連接線路，位於該介電層上，該金屬連接 線路包括一上層金屬層； 提供一保護層，位在該金屬連接線路上，該保護層具 有複數個開口 ，貫穿該保護層並暴露出該上層金屬層；以 及 形成複數個緩衝金屬接墊於該保護層上，其中該些緩 衝金屬接墊係經過該些開口連接至該上層金屬層，並且該 些緩衝金屬接墊係位於具有低介電係數之該介電層上。 9 5 .如申請專利範圍第9 4項所述之能夠連接打線導線 於低介電係數之介電層上之晶片結構的製作方法，其中該 些緩衝金屬接墊的厚度係大於1 . 5微米。 9 6.如申請專利範圍第9 4項所述之能夠連接打線導線 於低介電係數之介電層上之晶片結構的製作方法，其中該 些緩衝金屬接墊係為複合層金屬結構，包括至少一厚金屬 層及一金屬黏著層。 9 7.如申請專利範圍第9 6項所述之能夠連接打線導線 於低介電係數之介電層上之晶片結構的製作方法，其中該 厚金屬層的厚度係大於1微米。 9 8.如申請專利範圍第9 6項所述之能夠連接打線導線 於低介電係數之介電層上之晶片結構的製作方法，其中係 利用電鍍的方式形成該厚金屬層。 9 9.如申請專利範圍第9 6項所述之能夠連接打線導線11944twf.ptd Page 40 200425366 VI. Patent application scope Provide at least one dielectric layer with a low dielectric constant on the semiconductor substrate; Provide a metal connection line on the dielectric layer, the metal connection line includes an upper layer A metal layer; providing a protective layer on the metal connection line, the protective layer having a plurality of openings penetrating the protective layer and exposing the upper metal layer; and forming a plurality of buffer metal pads on the protective layer, The buffer metal pads are connected to the upper metal layer through the openings, and the buffer metal pads are located on the dielectric layer having a low dielectric constant. 95. The method for fabricating a chip structure capable of connecting a wire to a dielectric layer with a low dielectric constant as described in item 94 of the scope of patent application, wherein the thickness of the buffer metal pads is greater than 1.5 microns . 9 6. The manufacturing method of a chip structure capable of connecting wire bonding wires to a dielectric layer with a low dielectric constant as described in item 94 of the scope of the patent application, wherein the buffer metal pads are composite metal structures including At least one thick metal layer and one metal adhesion layer. 9 7. The method for fabricating a wafer structure capable of connecting wire bonding wires to a dielectric layer with a low dielectric constant as described in item 96 of the scope of the patent application, wherein the thickness of the thick metal layer is greater than 1 micron. 9 8. The manufacturing method of a wafer structure capable of connecting wire bonding wires to a dielectric layer with a low dielectric constant as described in item 96 of the scope of patent application, wherein the thick metal layer is formed by electroplating. 9 9. Capable of connecting wire as described in item 96 of the scope of patent application 11944twf.ptd 第41頁 200425366 六、申請專利範圍 於低介電係數之介電層上之晶片結構的製作方法，其中該 厚金屬層的材質係選自於由金、銅、錫、含錯合金、含錫 合金、錫銀合金及錫銀銅合金所組成之族群中之一種材 質。 1 0 0 .如申請專利範圍第9 4項所述之能夠連接打線導線 於低介電係數之介電層上之晶片結構的製作方法，其中該 些緩衝金屬接墊之至少一個係位於對應之一個或多個之該 些開口上。 1 0 1 .如申請專利範圍第9 4項所述之能夠連接打線導線 於低介電係數之介電層上之晶片結構的製作方法，其中該 些緩衝金屬接墊之至少一個係相對於對應之一個或多個之 該些開口存在橫向地偏移。 1 0 2.如申請專利範圍第9 4項所述之能夠連接打線導線 於低介電係數之介電層上之晶片結構的製作方法，其中每 一該些開口之最大寬度係至少大於0 . 1微米。 1 0 3.如申請專利範圍第9 4項所述之能夠連接打線導線 於低介電係數之介電層上之晶片結構的製作方法，還包括 形成一有機材料層於該些緩衝金屬接塾與該保護層之間。 1 0 4.如申請專利範圍第1 0 3項所述之能夠連接打線導 線於低介電係數之介電層上之晶片結構的製作方法，其中 該有機材料層之材質係選自於由聚醢亞胺（polyimide)、 苯基環丁烯（Benzocyclobutene，BCB)、彈性體、石夕酮 (si 1 i cone)、多孔性低介電係數之有機材料及聚對二甲苯 基（parylene)所組成之族群中之一種材質。11944twf.ptd Page 41 200425366 VI. Method for manufacturing a wafer structure on a dielectric layer with a low dielectric constant, in which the material of the thick metal layer is selected from the group consisting of gold, copper, tin, and mismatched alloys , Tin-containing alloy, tin-silver alloy, and tin-silver-copper alloy. 1 0. The manufacturing method of a chip structure capable of connecting a wire to a dielectric layer with a low dielectric constant as described in item 94 of the scope of the patent application, wherein at least one of the buffer metal pads is located in a corresponding one. One or more of these openings. 1 0 1. The method for manufacturing a chip structure capable of connecting a wire to a dielectric layer with a low dielectric constant as described in item 94 of the scope of patent application, wherein at least one of the buffer metal pads is relative to the corresponding one. One or more of the openings are laterally offset. 10 2. The method of manufacturing a chip structure capable of connecting a wire to a dielectric layer with a low dielectric constant as described in item 94 of the scope of the patent application, wherein the maximum width of each of these openings is at least greater than 0 1 micron. 1 0 3. The method for manufacturing a chip structure capable of connecting a wire to a dielectric layer with a low dielectric constant as described in item 94 of the scope of the patent application, further comprising forming an organic material layer on the buffer metal contacts. And the protective layer. 104. The method for manufacturing a chip structure capable of connecting a wire to a dielectric layer with a low dielectric constant as described in item 103 of the scope of patent application, wherein the material of the organic material layer is selected from Polyimide, Benzocyclobutene (BCB), elastomers, si 1 i cone, porous low dielectric constant organic materials, and parylene One of the materials of the group of people. 11944twf.ptd 第42頁 200425366 六、申請專利範圍 1 0 5. —種能夠連接打線導線之晶片結構，至少包括： 一半導體基底； 至少一介電層，位於該半導體基底上，其中該介電層 係具有低的介電常數； 一金屬連接線路，位於該介電層上，該金屬連接線路 包括一上層金屬層； 一保護層，位在該金屬連接線路上，該保護層具有複 數個開口 ，貫穿該保護層並暴露出該上層金屬層；以及 複數個緩衝金屬接墊，位於該保護層上，而該些緩衝 金屬接墊係為複合層金屬結構，其中該些緩衝金屬接墊係 經過該些開口連接至該上層金屬層，並且該些緩衝金屬接 墊係位於具有低介電常數之該介電層上。 1 0 6.如申請專利範圍第1 0 5項所述之能夠連接打線導 線之晶片結構，其中該些緩衝金屬接墊的厚度係大於1 . 5 微米。 . 1 0 7.如申請專利範圍第1 0 5項所述之能夠連接打線導 線之晶片結構，其中該些緩衝金屬接墊包括至少一厚金屬 層及一金屬黏著層。 1 0 8.如申請專利範圍第1 0 5項所述之能夠連接打線導 線之晶片結構，其中該些緩衝金屬接墊包括至少一黏著 層、一厚金屬層及一可以與打線導線連接之金屬層，該黏 著層係位於底層，該厚金屬層係位於該黏著層上，而該可 以與打線導線連接之金屬層係位於頂層。 1 0 9.如申請專利範圍第1 0 8項所述之能夠連接打線導11944twf.ptd Page 42 200425366 VI. Application patent scope 1 0 5. —A chip structure capable of connecting wire bonding wires, including at least: a semiconductor substrate; at least one dielectric layer on the semiconductor substrate, wherein the dielectric layer Has a low dielectric constant; a metal connection line is located on the dielectric layer, the metal connection line includes an upper metal layer; a protection layer is located on the metal connection line, the protection layer has a plurality of openings, The protective layer is penetrated and the upper metal layer is exposed; and a plurality of buffer metal pads are located on the protective layer, and the buffer metal pads are a composite metal structure, wherein the buffer metal pads pass through the The openings are connected to the upper metal layer, and the buffer metal pads are located on the dielectric layer having a low dielectric constant. 106. The chip structure capable of connecting wire bonding wires as described in item 105 of the scope of patent application, wherein the thickness of the buffer metal pads is greater than 1.5 micrometers. 10 7. The chip structure capable of connecting wire bonding wires as described in item 105 of the scope of patent application, wherein the buffer metal pads include at least a thick metal layer and a metal adhesive layer. 10 8. The chip structure capable of connecting wire bonding wires as described in item 105 of the scope of patent application, wherein the buffer metal pads include at least an adhesive layer, a thick metal layer, and a metal that can be connected to wire bonding wires. Layer, the adhesive layer is located on the bottom layer, the thick metal layer is located on the adhesive layer, and the metal layer that can be connected to the wire is located on the top layer. 1 0 9. The wire guide can be connected as described in item 108 of the scope of patent application. 11944twf.ptd 第43頁 200425366 六、申請專利範圍 線之晶片結構，其中該厚金屬層的厚度係大於1微米。 1 1 0 .如申請專利範圍第1 0 5項所述之能夠連接打線導 線之晶片結構，還包括一有機材料層，位於該些緩衝金屬 接墊與該保護層之間。 1 1 1 .如申請專利範圍第11 0項所述之能夠連接打線導 線之晶片結構，其中該有機材料層之材質係選自於由聚醯 亞胺（polyimide)、苯基環丁烯（Benzocyclobutene ， B C B )、彈性體、矽酮（s i 1 i c ο n e )、多孔性低介電係數之有 機材料及聚對二甲苯基（P a r y 1 e n e )所組成之族群中之一種 材質。11944twf.ptd Page 43 200425366 VI. Scope of Patent Application For the wafer structure of the wire, the thickness of the thick metal layer is greater than 1 micron. 110. The chip structure capable of connecting wire bonding wires as described in item 105 of the scope of patent application, further comprising an organic material layer located between the buffer metal pads and the protective layer. 1 1 1. The chip structure capable of connecting wire bonding wires as described in item 110 of the scope of patent application, wherein the material of the organic material layer is selected from the group consisting of polyimide and phenylcyclobutene , BCB), elastomer, silicone (si 1 ic ο ne), porous low dielectric constant organic materials and poly-xylyl (P ary 1 ene) group. 11944twf.ptd 第44頁11944twf.ptd Page 44
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI450347B (en) * 2008-09-05 2014-08-21 Advanced Semiconductor Eng Wire bonding structure
CN116209353A (en) * 2023-05-06 2023-06-02 常州承芯半导体有限公司 Capacitor structure and forming method thereof, semiconductor structure and forming method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI450347B (en) * 2008-09-05 2014-08-21 Advanced Semiconductor Eng Wire bonding structure
CN116209353A (en) * 2023-05-06 2023-06-02 常州承芯半导体有限公司 Capacitor structure and forming method thereof, semiconductor structure and forming method thereof

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