CN116705844A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN116705844A CN116705844A CN202310642426.6A CN202310642426A CN116705844A CN 116705844 A CN116705844 A CN 116705844A CN 202310642426 A CN202310642426 A CN 202310642426A CN 116705844 A CN116705844 A CN 116705844A
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 108
- 229910052751 metal Inorganic materials 0.000 claims description 191
- 239000002184 metal Substances 0.000 claims description 191
- 238000002161 passivation Methods 0.000 claims description 107
- 150000002500 ions Chemical class 0.000 claims description 90
- 238000002955 isolation Methods 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 9
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 8
- 230000017525 heat dissipation Effects 0.000 abstract description 7
- 238000003475 lamination Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 331
- 239000010936 titanium Substances 0.000 description 20
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 16
- 239000000463 material Substances 0.000 description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 10
- 239000010931 gold Substances 0.000 description 10
- 229910052719 titanium Inorganic materials 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 6
- 239000002356 single layer Substances 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000012943 hotmelt Substances 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- 229910052697 platinum Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000004831 Hot glue Substances 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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- 230000005611 electricity Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
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- -1 group III-v elements Chemical compound 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7302—Bipolar junction transistors structurally associated with other devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7302—Bipolar junction transistors structurally associated with other devices
- H01L29/7304—Bipolar junction transistors structurally associated with other devices the device being a resistive element, e.g. ballasting resistor
Abstract
A semiconductor structure and method of forming the same, wherein the structure comprises: a substrate having opposite first and second sides; a heterojunction bipolar transistor located on a first side of the substrate, the heterojunction bipolar transistor comprising: a first current collecting layer, a first base layer and a first current collecting electrode on the first current collecting layer, a first base electrode and an emission layer on the first base layer, and an emission electrode on the emission layer; a number of passive devices located on a second side of the substrate. The heterojunction bipolar transistor and the passive devices are respectively located on two opposite sides of the substrate, so that the occupied area of the whole structure can be effectively reduced, and the integration level of the device structure is effectively improved. In addition, the lamination formed on the heterojunction bipolar transistor can be effectively reduced, heat dissipation of the heterojunction bipolar transistor is facilitated, gain of the heterojunction bipolar transistor is improved, and further performance of a device structure is improved.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the development of society and the demand for high performance and low cost RF components in the high frequency band for modern communications, conventional silicon material devices have failed to meet these new performance requirements. Because Heterojunction Bipolar Transistors (HBTs) have a high frequency performance that is much better than that of silicon bipolar transistors, and the compatibility with silicon technology makes them low-priced for silicon, gallium arsenide technology has achieved a great deal of progress, and gallium arsenide HBT technology has become one of the mainstream technologies in the RF integrated circuit market and has had a profound impact on the development of modern communication technologies.
However, there are still a number of problems with existing semiconductor structures formed based on heterojunction bipolar transistors.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor structure and a forming method thereof, and improves the integration level of a device structure and the performance of the device structure.
In order to solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate having opposite first and second sides; a heterojunction bipolar transistor located on a first side of the substrate, the heterojunction bipolar transistor comprising: a first current collecting layer, a first base layer and a first current collecting electrode on the first current collecting layer, a first base electrode and an emission layer on the first base layer, and an emission electrode on the emission layer; a number of passive devices located on a second side of the substrate.
Optionally, the method further comprises: a first passivation layer on the first side of the substrate, the first passivation layer covering the heterojunction bipolar transistor, and the first passivation layer exposing a top surface of the first collector electrode, a top surface of the first base electrode, and a top surface of the emitter electrode.
Optionally, the method further comprises: a diode on a first side of the substrate, the diode comprising: a second current collecting layer, a second base layer and a second current collecting electrode on the second current collecting layer, and a second base electrode on the second base layer; the first passivation layer also covers a surface of the diode, and exposes a top surface of the second collector electrode and a top surface of the second base electrode.
Optionally, the method further comprises: and the first current collecting layer and the second current collecting layer are respectively positioned between the adjacent isolating layers.
Optionally, the passive devices include: one or more of resistance, inductance, and capacitance.
Optionally, the method further comprises: a second metal layer on a second side of the substrate, the second metal layer comprising: the inductor comprises a second metal part, a third metal part, the inductor and a second lead part, wherein the second lead part is electrically connected with the second metal part, the third metal part and the inductor respectively.
Optionally, the second metal portion is electrically connected to the resistor.
Optionally, the method further comprises: a third passivation layer on the second side of the substrate, the third passivation layer covering a surface of the second metal layer and exposing a portion of the top surface of the second metal portion, a portion of the top surface of the third metal portion, and a portion of the top surface of the inductor; and a third metal layer positioned on the second side of the substrate, wherein the third metal layer is positioned on the surface of the third passivation layer, the projection of the third metal layer and the third metal part in the direction towards the substrate has an overlapping area, and the third metal layer, the third metal part and the third passivation layer positioned between the third metal layer and the third metal part form the capacitor.
Optionally, the method further comprises: the first metal layer is positioned on the first side of the substrate, the first metal layer comprises a first metal part and a first lead part, the first lead part is positioned on the first passivation layer, the first lead part and the first metal part are electrically connected, and the first metal part is respectively positioned on the exposed top surface of the first collector electrode, the exposed top surface of the first base electrode or the exposed top surface of the emission electrode.
Optionally, further comprising; a plurality of through holes penetrating the substrate and the first passivation layer, the through holes exposing a surface of the first lead portion; the second lead portion fills the through hole.
Optionally, the first current collection layer is doped with first ions; the first base layer is internally doped with second ions, the electrical type of the first ions is different from that of the second ions, and the doping concentration of the second ions is larger than that of the first ions.
Optionally, a third ion is doped in the emission layer, the electrical type of the third ion is different from the electrical type of the second ion, the electrical type of the third ion is the same as the electrical type of the first ion, the doping concentration of the third ion is greater than the doping concentration of the first ion, and the doping concentration of the third ion is less than the doping concentration of the second ion.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate having opposite first and second sides; forming a heterojunction bipolar transistor on a first side of the substrate, the heterojunction bipolar transistor comprising: a first current collecting layer, a first base layer and a first current collecting electrode on the first current collecting layer, a first base electrode and an emission layer on the first base layer, and an emission electrode on the emission layer; passive devices are formed on a second side of the substrate.
Optionally, after forming the heterojunction bipolar transistor, the method further comprises: a first passivation layer is formed on the first side of the substrate, the first passivation layer covering the surface of the heterojunction bipolar transistor, and the first passivation layer exposing the top surface of the first collector electrode, the top surface of the first base electrode, and the top surface of the emitter electrode.
Optionally, in forming the heterojunction bipolar transistor, the method further comprises: forming a diode on a first side of the substrate, the diode comprising: a second current collecting layer, a second base layer and a second current collecting electrode on the second current collecting layer, and a second base electrode on the second base layer; the first passivation layer also covers a surface of the diode, and exposes a top surface of the second collector electrode and a top surface of the second base electrode.
Optionally, the method for forming the heterojunction bipolar transistor and the diode comprises the following steps: forming an initial collector layer on a first side of the substrate; forming an initial base layer on the initial current collecting layer; forming an initial emission layer on the initial base layer; forming the emission electrode on the initial emission layer; etching the initial emission layer by taking the emission electrode as a mask to form the emission layer; forming the first base electrode and the second base electrode on the initial base layer, respectively; performing first patterning processing on the initial base layer to form the first base layer and the second base layer; forming the first collector electrode and the second collector electrode on the initial collector layer, respectively; and carrying out isolation ion implantation treatment on the initial current collecting layer to form a plurality of isolation layers, a first current collecting layer and a second current collecting layer, wherein the first current collecting layer and the second current collecting layer are respectively positioned between the adjacent isolation layers.
Optionally, forming the plurality of passive devices includes: one or more of resistance, inductance, and capacitance are formed.
Optionally, the forming method of the passive devices includes: forming a second metal layer on a second side of the substrate, the second metal layer comprising: the inductor comprises a second metal part, a third metal part, the inductor and a second lead part, wherein the second lead part is electrically connected with the second metal part, the third metal part or the inductor.
Optionally, the second metal portion is electrically connected to the resistor.
Optionally, the forming method of the passive devices further includes: forming a third passivation layer on the second side of the substrate, wherein the third passivation layer covers the surface of the second metal layer and exposes a part of the top surface of the second metal part, a part of the top surface of the third metal part and a part of the top surface of the inductor; and forming a third metal layer on the second side of the substrate, wherein the third metal layer is positioned on the surface of the third passivation layer, the projection of the third metal layer and the third metal part in the direction towards the substrate has an overlapping area, and the third metal layer, the third metal part and the third passivation layer positioned between the third metal layer and the third metal part form the capacitor.
Optionally, the method further comprises: a first metal layer is formed on the first side of the substrate, the first metal layer including a first metal portion and a first lead portion, the first lead portion being located on the first passivation layer, the first lead portion and the first metal portion being electrically connected, the first metal portion being located on the exposed top surface of the first collector electrode, the top surface of the first base electrode, or the top surface of the emitter electrode.
Optionally, before forming the passive devices, the method further includes: forming a plurality of through holes penetrating through the substrate and the first passivation layer, wherein the through holes expose the surface of the first lead part; the second lead portion fills the through hole.
Optionally, the first current collection layer is doped with first ions; the first base layer is internally doped with second ions, the electrical type of the first ions is different from that of the second ions, and the doping concentration of the second ions is larger than that of the first ions.
Optionally, a third ion is doped in the emission layer, the electrical type of the third ion is different from the electrical type of the second ion, the electrical type of the third ion is the same as the electrical type of the first ion, the doping concentration of the third ion is greater than the doping concentration of the first ion, and the doping concentration of the third ion is less than the doping concentration of the second ion.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the semiconductor structure of the technical scheme of the invention comprises the following components: a heterojunction bipolar transistor located on a first side of the substrate, the heterojunction bipolar transistor comprising: a first current collecting layer, a first base layer and a first current collecting electrode on the first current collecting layer, a first base electrode and an emission layer on the first base layer, and an emission electrode on the emission layer; a number of passive devices located on a second side of the substrate. The heterojunction bipolar transistor and the passive devices are respectively located on two opposite sides of the substrate, so that the occupied area of the whole structure can be effectively reduced, and the integration level of the device structure is effectively improved. In addition, the lamination formed on the heterojunction bipolar transistor can be effectively reduced, heat dissipation of the heterojunction bipolar transistor is facilitated, gain of the heterojunction bipolar transistor is improved, and further performance of a device structure is improved.
In the method for forming a semiconductor structure according to the present invention, a heterojunction bipolar transistor is formed on a first side of the substrate, and the heterojunction bipolar transistor includes: a first current collecting layer, a first base layer and a first current collecting electrode on the first current collecting layer, a first base electrode and an emission layer on the first base layer, and an emission electrode on the emission layer; passive devices are formed on a second side of the substrate. The heterojunction bipolar transistor and the passive devices are respectively formed on two opposite sides of the substrate, so that the occupied area of the whole structure can be effectively reduced, and the integration level of the device structure is effectively improved. In addition, the lamination formed on the heterojunction bipolar transistor can be effectively reduced, heat dissipation of the heterojunction bipolar transistor is facilitated, gain of the heterojunction bipolar transistor is improved, and further performance of a device structure is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 14 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, there are still a number of problems associated with the formation of semiconductor structures based on heterojunction bipolar transistors. The following will make a detailed description with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a semiconductor structure.
Referring to fig. 1, a semiconductor structure includes: a substrate 100, the substrate 100 having opposite first and second sides 101, 102; a heterojunction bipolar transistor on the first side 101 of the substrate 100, the heterojunction bipolar transistor comprising a collector layer 103, a base layer 104 and a collector 105 on the collector layer 103, an emitter layer 106 and a base electrode 107 on the base layer 104, and an emitter electrode 108 on the emitter layer 106; a first passivation layer 109 located on the first side 101 of the substrate 100, the first passivation layer 109 covering the surface of the heterojunction bipolar transistor, and the first passivation layer 109 exposing the top surface of the collector 105, the top surface of the base electrode 107, and the top surface of the emitter electrode 108; a first metal layer on the first side 101 of the substrate 100, the first metal layer including a first metal portion 110, a second metal portion 111, and a third metal portion 112, the first metal portion 110 and the second metal portion 111 being respectively located on the first passivation layer 109, the third metal portion 112 being respectively located on the exposed top surface of the collector electrode 105, the top surface of the base electrode 107, and the top surface of the emitter electrode 108; a resistor 113 located on the first side 101 of the substrate 100, the resistor 113 being located on the first passivation layer 109, and the resistor 113 covering a portion of the surface of the first metal portion 110; a second passivation layer 114 located on the first side 101 of the substrate 100, the second passivation layer 114 being located on the first passivation layer 109, the second passivation layer 114 covering a surface of the first metal layer, and the second passivation layer 114 exposing a portion of the surface of the first metal portion 110 and a portion of the surface of the third metal portion 112; the second metal layer 115 on the first side 101 of the substrate 100, the projection of the second metal layer 115 and the second metal part 111 in the direction towards the substrate 100 has an overlap area to constitute a capacitance.
In this embodiment, the heterojunction bipolar transistor, the resistor 113 and the capacitor are all located on the first side 101 of the substrate 100, so that the overall structure occupies a larger space, which is not beneficial to the integration level of the device structure. In addition, the heterojunction bipolar transistor has more laminated layers, and the heating position in the circuit structure is mainly in the emitting layer of the heterojunction bipolar transistor, so that the heat dissipation of the heterojunction bipolar transistor is not facilitated, the junction temperature of the heterojunction bipolar transistor is further increased, the starting voltage is reduced, the gain of the heterojunction bipolar transistor is reduced, and the performance of the device structure is influenced.
On the basis, the invention provides the semiconductor structure and the forming method thereof, and the heterojunction bipolar transistor and the passive devices are respectively positioned on two opposite sides of the substrate, so that the occupied area of the whole structure can be effectively reduced, and the integration level of the device structure is further effectively improved. In addition, the lamination formed on the heterojunction bipolar transistor can be effectively reduced, heat dissipation of the heterojunction bipolar transistor is facilitated, gain of the heterojunction bipolar transistor is improved, and further performance of a device structure is improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 2 to 14 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2, a substrate 200 is provided, the substrate 200 having opposite first and second sides 201, 202.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the material of the substrate may also be a multi-component semiconductor material comprising silicon carbide, silicon germanium, group III-v elements, silicon On Insulator (SOI), or Germanium On Insulator (GOI). Wherein the III-v element comprising multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
In this embodiment, after the substrate 200 is provided, it further includes: a heterojunction bipolar transistor is formed on a first side 201 of the substrate 200, the heterojunction bipolar transistor comprising: a first current collecting layer, a first base layer and a first current collecting electrode on the first current collecting layer, a first base electrode and an emission layer on the first base layer, and an emission electrode on the emission layer. The specific forming process is shown in fig. 3 to 6.
Referring to fig. 3, an initial collector layer 203 is formed on a first side 201 of the substrate 200; forming an initial base layer 204 on the initial collector layer 203; an initial emission layer 205 is formed on the initial base layer 204.
In this embodiment, the initial collector layer 203, the initial base layer 204, and the initial emitter layer 205 are formed by using an epitaxial growth process, respectively.
Referring to fig. 4, the emitter electrode 206 is formed on the initial emitter layer 205; the initial emitter layer 205 is etched using the emitter electrode 206 as a mask to form the emitter layer 207.
In this embodiment, the emitter electrode 206 is in ohmic contact with the emitter layer 207.
In this embodiment, the emitter electrode 206 has a multi-layered metal structure, and the emitter electrode 206 is a multi-layered metal layer of a titanium (Ti) film, a platinum (Pt) film, and a titanium (Ti) film, which are stacked in this order.
In other embodiments, the emitter electrode may also be a single layer metal structure.
In this embodiment, the method for forming the emitter electrode 206 includes: a first patterned layer (not shown) can be formed on the initial emissive layer 205, exposing a portion of the top surface of the initial emissive layer 205; forming a emitter electrode material layer (not shown) on a portion of the top surface of the initial emitter layer 205 and the top surface of the first patterned layer by an evaporation process; the emitter electrode 206 is formed by removing the emitter electrode material layer and the first patterned layer on the top surface of the patterned layer using a lift-off process.
Referring to fig. 5, the first base electrode 208 is formed on the initial base layer 204; the initial base layer 204 is subjected to a first patterning process to form the first base layer 209.
In this embodiment, further comprising: forming a second base electrode 210 on the initial base layer 204; the first patterning process is performed on the initial base layer 204 to form a second base layer 211.
In this embodiment, the first base electrode 208 is in ohmic contact with the first base layer 209; the second base electrode 210 is in ohmic contact with the second base layer 211.
In this embodiment, the first base electrode 208 and the second base electrode 210 respectively have a multi-layer metal structure, and the first base electrode 208 and the second base electrode 210 are multi-layer metal layers formed by sequentially stacking a platinum (Pt) film, a titanium (Ti) film, a Pt film, and a gold (Au) film.
In other embodiments, the first and second base electrodes may also be of a single-layer metal structure.
In this embodiment, the emitter layer 207 and the emitter electrode 206 are located on the first base layer 209.
Referring to fig. 6, the first collector 212 is formed on the initial collector layer 203.
In this embodiment, further comprising: the second collector 213 is formed on the initial collector layer 203.
With continued reference to fig. 6, after the first collector 212 and the second collector 213 are formed, the initial collector layer 203 is subjected to an isolation ion implantation process to form a plurality of isolation layers 214, the first collector layer 215 and the second collector layer 216, and the first collector layer 215 and the second collector layer 216 are respectively located between adjacent isolation layers 214.
In this embodiment, the isolation ions implanted are of a different electrical type from the first ions doped in the initial collector layer 203 to neutralize the formation of the intrinsic semiconductor, thereby preventing current cross-talk between different devices.
In this embodiment, the first collector 212 is in ohmic contact with the first collector layer 215; the second collector 213 is in ohmic contact with the second collector layer 216.
In this embodiment, the first collector 212 and the second collector 213 respectively have a multi-layered metal structure, and the first collector 212 and the second collector 213 are multi-layered metal layers in which a titanium (Ti) film and a gold (Au) film are sequentially stacked.
In other embodiments, the first collector and the second collector may also be a single-layer metal structure.
In this embodiment, the first current collecting layer 215 and the second current collecting layer 216 are doped with first ions; the first base layer 209 and the second base layer 211 are doped with second ions, the electrical type of the first ions is different from the electrical type of the second ions, and the doping concentration of the second ions is greater than the doping concentration of the first ions; the emitter layer 207 is doped with a third ion, the third ion has a different electrical type from the second ion, the third ion has a same electrical type as the first ion, the third ion has a doping concentration greater than the first ion, and the third ion has a doping concentration less than the second ion.
Specifically, in the present embodiment, the first current collecting layer 215 and the second current collecting layer 216 have a doping concentration of 1E16atoms/cm 3 N-type gallium arsenide (GaAs); the second base layer 209 and the second base layer 211 have a doping concentration of 1E19atoms/cm 3 P-type gallium arsenide of (a); the emitter layer 207 has a doping concentration of 1E17atoms/cm 3 N-type gallium arsenide of (c).
In this embodiment, the first base layer 209, the first base electrode 208, the emitter layer 207, and the emitter electrode 206 are respectively located on the first collector layer 215 to form the heterojunction bipolar transistor.
In this embodiment, the second base layer 211 and the second base electrode 210 are respectively located on the second collector layer 216 to form a diode.
In other embodiments, only the heterojunction bipolar transistor may be formed without forming the diode.
Referring to fig. 7, after the heterojunction bipolar transistor is formed, a first passivation layer 217 is formed on the first side 201 of the substrate 200, the first passivation layer 217 covers the heterojunction bipolar transistor, and the first passivation layer 217 exposes the top surface of the first collector 212, the top surface of the first base electrode 208, and the top surface of the emitter electrode 206.
In this embodiment, the first passivation layer 217 also covers the surface of the diode, and exposes the top surface of the second collector 213, and the top surface of the second base electrode 210.
In this embodiment, the method for forming the first passivation layer 217 includes: forming a first passivation layer of material (not shown) on a first side 201 of the substrate 200, the first passivation layer of material covering the heterojunction bipolar transistor and the diode surface; and etching the first passivation material layer to form the first passivation layer 217.
In this embodiment, the first passivation layer is formed by a chemical vapor deposition process.
In this embodiment, the material of the first passivation layer 217 is silicon nitride.
In other embodiments, the first passivation layer covers only the surface of the heterojunction bipolar transistor when only the heterojunction bipolar transistor is present.
Referring to fig. 8, after the first passivation layer 217 is formed, a first metal layer is formed on the first side 201 of the substrate 200, the first metal layer includes a first metal portion 218 and a first lead portion 219, the first lead portion 219 is located on the first passivation layer 217, the first lead portion 219 and the first metal portion 218 are electrically connected, and the first metal portion 218 is located on the exposed top surface of the first collector electrode 212, the exposed top surface of the first base electrode 208, and the exposed top surface of the emitter electrode 206, respectively.
In this embodiment, the first metal portion 218 is further located on the top surface of the second collector electrode 213 and the top surface of the second base electrode 210.
In other embodiments, when only the heterojunction bipolar transistor is present, the first metal portion is located only at the exposed top surface of the first collector electrode, the top surface of the first base electrode, and the top surface of the emitter electrode, respectively.
In this embodiment, the method for forming the first metal layer includes: a second patterned layer (not shown) can be formed on the first passivation layer 217, exposing a portion of the top surface of the first passivation layer 217, the top surface of the first collector electrode 212, the top surface of the first base electrode 208, the top surface of the emitter electrode 206, the top surface of the second collector electrode 213, and the top surface of the second base electrode 210; forming a first metal material layer (not shown) on a portion of the top surface of the first passivation layer 217, the top surface of the first collector 212, the top surface of the first base electrode 208, the top surface of the emitter layer electricity 206, the top surface of the second collector 213, the top surface of the second base electrode 210, and the top surface of the second patterned layer using an evaporation process; and removing the first metal material layer and the second patterned layer which are positioned on the top surfaces of the two patterned layers by adopting a stripping process to form the first metal layer.
In this embodiment, the first metal layer adopts a multi-layer metal structure, and the first metal layer is a multi-layer metal layer formed by stacking a titanium (Ti) film, a platinum (Pt) film, a gold (Au) film, and a titanium (Ti) film in this order.
In other embodiments, the first metal layer may also be a single-layer metal structure.
Referring to fig. 9, a second passivation layer 220 is formed on the second side 202 of the substrate 200.
In this embodiment, the second passivation layer 220 is formed by a chemical vapor deposition process.
In this embodiment, the material of the second passivation layer 220 is silicon nitride.
Referring to fig. 10, a plurality of through holes 221 penetrating the second passivation layer 220, the substrate 200, and the first passivation layer 217 are formed, and the through holes 221 expose the surface of the first lead portion 219.
In this embodiment, the via also penetrates the isolation layer 214.
In this embodiment, a plurality of the through holes 221 are used for filling metal materials therein later to realize electrical connection of the device structure between the opposite sides of the substrate 200.
In this embodiment, after forming the plurality of through holes 221, it further includes: forming passive devices on the second side 202 of the substrate 200, the forming passive devices comprising: one or more of resistance, inductance, and capacitance are formed. The specific forming process is shown in fig. 11 to 13.
Referring to fig. 11, a second metal layer is formed on the second side 202 of the substrate 200, the second metal layer is located on the second passivation layer 220, and the second metal layer includes: a second metal part 222, a third metal part 223, the inductor 224 and a second lead part 225, the second lead part 225 is electrically connected with the second metal part 222, the third metal part 223 and the inductor 224, respectively, and the second lead part 225 fills the through hole 221.
In this embodiment, the method for forming the second metal layer includes: a third patterned layer (not shown) can be formed on the second passivation layer 220, exposing a portion of the top surface of the second passivation layer 220; forming a second metal material layer (not shown) on a portion of the top surface of the second passivation layer 220 and the top surface of the third patterned layer by an evaporation process; and removing the second metal material layer and the third patterned layer which are positioned on the top surfaces of the three patterned layers by adopting a stripping process to form the second metal layer.
In this embodiment, the second metal layer adopts a multi-layer metal structure, and the second metal layer is a multi-layer metal layer formed by stacking a titanium (Ti) film, a platinum (Pt) film, a gold (Au) film, and a titanium (Ti) film in this order.
In other embodiments, the second metal layer may also be a single-layer metal structure.
With continued reference to fig. 11, the resistor 226 is formed on the second side 202 of the substrate 200, the resistor 226 is located on the second passivation layer 220, and the resistor 226 is electrically connected to the second metal portion 222.
In this embodiment, the resistor 226 is made of tantalum nitride.
Referring to fig. 12, a third passivation layer 227 is formed on the second side 202 of the substrate 200, the third passivation layer 227 is located on the second passivation layer 220, the third passivation layer 227 covers the surface of the second metal layer, and a portion of the top surface of the second metal portion 222, a portion of the top surface of the third metal portion 223, and a portion of the top surface of the inductor 224 are exposed.
In this embodiment, the method for forming the third passivation layer 227 includes: forming a third passivation material layer (not shown) on the second side 202 of the substrate 200, the third passivation material layer covering a surface of the second metal layer; the third passivation layer 227 is formed by performing an etching process on the third passivation material layer.
In this embodiment, the formation process of the third passivation layer adopts a chemical vapor deposition process.
In this embodiment, the material of the third passivation layer 227 is silicon nitride.
In this embodiment, a portion of the top surface of the second metal portion 222, a portion of the top surface of the third metal portion 223, and a portion of the top surface of the inductor 224, which are exposed by the third passivation layer 227, are used for electrical connection between device structures.
Referring to fig. 13, a third metal layer 228 is formed on the second side 202 of the substrate 200, the third metal layer 228 is located on the third passivation layer 227, and the third metal layer 228 and the third metal portion 223 have an overlapping area in a projection in a direction toward the substrate 200, and the third metal layer 228, the third metal portion 223 and the third passivation layer 227 located between the third metal layer 228 and the third metal portion 223 form the capacitor.
In this embodiment, the heterojunction bipolar transistor and the passive devices are respectively formed on two opposite sides of the substrate 200, so that the area occupied by the overall structure can be effectively reduced, and the integration level of the device structure can be effectively improved. In addition, the lamination formed on the heterojunction bipolar transistor can be effectively reduced, heat dissipation of the heterojunction bipolar transistor is facilitated, gain of the heterojunction bipolar transistor is improved, and further performance of a device structure is improved.
In this embodiment, the third metal layer 228 has a multi-layered metal structure, and the third metal layer 228 is a multi-layered metal layer formed by stacking a titanium (Ti) film, a platinum (Pt) film, a gold (Au) film, and a titanium (Ti) film in this order.
In other embodiments, the third metal layer may also be a single-layer metal structure.
In this embodiment, the electrical connection between the device structures (such as the heterojunction bipolar transistor and the diode, the resistor 226, the inductor 224 and the capacitor) located on the same side of the substrate 200 is only required to be routed on one side of the substrate 200, and the connection between the device structures located on the same side of the substrate 200 is not required to be achieved through a via hole.
In this embodiment, the passive devices are formed to form a resistor 226, an inductor 224, and a capacitor; in other implementations, forming the passive device may also be forming one or both of a resistance, an inductance, and a capacitance.
Referring to fig. 14, after forming a number of the passive devices, a hot melt layer 229 is formed on the first side 201 of the substrate 200, the hot melt layer 229 covering the heterojunction bipolar transistor and the diode.
In this embodiment, in order to better dissipate heat (since the heat-generating region of the heterojunction bipolar transistor is mainly at the current output end, i.e. the emitter layer 207), the active device can be more effectively dissipated by forming the hot-melt adhesive layer 229 with a heat-conducting effect.
Accordingly, in an embodiment of the present invention, a semiconductor structure is further provided, please continue to refer to fig. 14, which includes: a substrate 200, the substrate 200 having opposite first and second sides 201, 202; a heterojunction bipolar transistor located on a first side 201 of the substrate 200, the heterojunction bipolar transistor comprising: a first current collecting layer 215, a first base layer 209 and a first current collecting electrode 212 on the first current collecting layer 215, a first base electrode 208 and an emission layer on the first base layer 209, and an emission electrode 206 on the emission layer 207; a number of passive devices located on the second side 202 of the substrate 200.
In this embodiment, the heterojunction bipolar transistor and the passive devices are respectively located at two opposite sides of the substrate 200, so that the area occupied by the overall structure can be effectively reduced, and the integration level of the device structure can be effectively improved. In addition, the lamination formed on the heterojunction bipolar transistor can be effectively reduced, heat dissipation of the heterojunction bipolar transistor is facilitated, gain of the heterojunction bipolar transistor is improved, and further performance of a device structure is improved.
In this embodiment, further comprising: a first passivation layer 217 on the first side 201 of the substrate 200, the first passivation layer 217 covering the heterojunction bipolar transistor surface, and the first passivation layer 217 exposing the top surface of the first collector 212, the top surface of the first base electrode 208, and the top surface of the emitter electrode 206.
In this embodiment, further comprising: a diode located on a first side 201 of the substrate 200, the diode comprising: a second current collecting layer 216, a second base layer 211 and a second current collecting electrode 213 on the second current collecting layer 216, and a second base electrode 210 on the second base layer 211; the first passivation layer 217 also covers the surface of the diode, and the first passivation layer 217 exposes the top surface of the second collector electrode 213, and the top surface of the second base electrode 211.
In this embodiment, further comprising: a plurality of isolation layers 214 located on the first side 201 of the substrate 200, and the first current collecting layer 215 and the second current collecting layer 216 are respectively located between adjacent isolation layers 214.
In this embodiment, further comprising: a hot melt layer 229 on the first side 201 of the substrate 200, the hot melt layer 229 covering the heterojunction bipolar transistor and the diode.
In other embodiments, the hot melt layer 229 only covers the heterojunction bipolar transistor when the active device only exposes the heterojunction bipolar transistor.
In this embodiment, the passive devices are a resistor 226, an inductor 224, and a capacitor. In other implementations, the number of passive devices may also be one or both of forming a resistance, an inductance, and a capacitance.
In this embodiment, further comprising: a second metal layer on a second side 202 of the substrate 200, the second metal layer comprising: a second metal part 222, a third metal part 223, the inductor 224 and a second lead part 225, wherein the second lead part 225 is electrically connected with the second metal part 222, the third metal part 223 and the inductor 224, respectively.
In this embodiment, the second metal portion 222 is electrically connected to the resistor 226.
In this embodiment, further comprising: a third passivation layer 227 on the second side 202 of the substrate 200, the third passivation layer 227 covering the surface of the second metal layer and exposing a portion of the top surface of the second metal portion 222, a portion of the top surface of the third metal portion 223, and a portion of the top surface of the inductor 224; a third metal layer 228 located on the second side 202 of the substrate 200, the third metal layer 228 being located on the surface of the third passivation layer 227, and the projection of the third metal layer 228 and the third metal portion 223 in the direction towards the substrate 200 having an overlap area, the third metal layer 228, the third metal portion 223 and the third passivation layer 227 located between the third metal layer 228 and the third metal portion 223 constituting the capacitance.
In this embodiment, further comprising: a first metal layer on the first side 201 of the substrate 200, the first metal layer including a first metal portion 218 and a first lead portion 219, the first lead portion 219 being on the first passivation layer 217, the first lead portion 219 and the first metal portion 218 being electrically connected, the first metal portion 218 being on the exposed top surface of the first collector electrode 212, the top surface of the first base electrode 208, and the top surface of the emitter electrode 206, respectively.
In this embodiment, further comprising: a second passivation layer 220 located on the second side 202 of the substrate 200; the second metal layer is located on the second passivation layer 220, and the third passivation layer 227 is located on the second passivation layer 220; a plurality of through holes 221 penetrating the second passivation layer 220, the substrate 200, and the first passivation layer 217, the through holes 221 exposing a surface of the first lead part 219; the second lead portion 225 fills the through hole 221.
In this embodiment, the first current collecting layer 215 is doped with first ions; the first base layer 209 is doped with a second ion, and the electrical type of the first ion is different from the electrical type of the second ion, and the doping concentration of the second ion is greater than the doping concentration of the first ion.
In this embodiment, the emitter layer 207 is doped with a third ion, the electrical type of the third ion is different from the electrical type of the second ion, the electrical type of the third ion is the same as the electrical type of the first ion, the doping concentration of the third ion is greater than the doping concentration of the first ion, and the doping concentration of the third ion is less than the doping concentration of the second ion.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (24)
1. A semiconductor structure, comprising:
a substrate having opposite first and second sides;
a heterojunction bipolar transistor located on a first side of the substrate, the heterojunction bipolar transistor comprising: a first current collecting layer, a first base layer and a first current collecting electrode on the first current collecting layer, a first base electrode and an emission layer on the first base layer, and an emission electrode on the emission layer;
A number of passive devices located on a second side of the substrate.
2. The semiconductor structure of claim 1, further comprising: a first passivation layer on the first side of the substrate, the first passivation layer covering the heterojunction bipolar transistor, and the first passivation layer exposing a top surface of the first collector electrode, a top surface of the first base electrode, and a top surface of the emitter electrode.
3. The semiconductor structure of claim 2, further comprising: a diode on a first side of the substrate, the diode comprising: a second current collecting layer, a second base layer and a second current collecting electrode on the second current collecting layer, and a second base electrode on the second base layer; the first passivation layer also covers a surface of the diode, and exposes a top surface of the second collector electrode and a top surface of the second base electrode.
4. The semiconductor structure of claim 3, further comprising: and the first current collecting layer and the second current collecting layer are respectively positioned between the adjacent isolating layers.
5. The semiconductor structure of claim 2, wherein the plurality of passive devices comprises: one or more of resistance, inductance, and capacitance.
6. The semiconductor structure of claim 5, further comprising: a second metal layer on a second side of the substrate, the second metal layer comprising: the inductor comprises a second metal part, a third metal part, the inductor and a second lead part, wherein the second lead part is electrically connected with the second metal part, the third metal part and the inductor respectively.
7. The semiconductor structure of claim 6, wherein the second metal portion is electrically connected to the resistor.
8. The semiconductor structure of claim 6, further comprising: a third passivation layer on the second side of the substrate, the third passivation layer covering a surface of the second metal layer and exposing a portion of the top surface of the second metal portion, a portion of the top surface of the third metal portion, and a portion of the top surface of the inductor; and a third metal layer positioned on the second side of the substrate, wherein the third metal layer is positioned on the surface of the third passivation layer, the projection of the third metal layer and the third metal part in the direction towards the substrate has an overlapping area, and the third metal layer, the third metal part and the third passivation layer positioned between the third metal layer and the third metal part form the capacitor.
9. The semiconductor structure of claim 8, further comprising: the first metal layer is positioned on the first side of the substrate, the first metal layer comprises a first metal part and a first lead part, the first lead part is positioned on the first passivation layer, the first lead part and the first metal part are electrically connected, and the first metal part is respectively positioned on the exposed top surface of the first collector electrode, the exposed top surface of the first base electrode or the exposed top surface of the emission electrode.
10. The semiconductor structure of claim 9, further comprising; a plurality of through holes penetrating the substrate and the first passivation layer, the through holes exposing a surface of the first lead portion; the second lead portion fills the through hole.
11. The semiconductor structure of claim 1, wherein the first current collector is doped with first ions; the first base layer is internally doped with second ions, the electrical type of the first ions is different from that of the second ions, and the doping concentration of the second ions is larger than that of the first ions.
12. The semiconductor structure of claim 11, wherein a third ion is doped within the emitter layer, the third ion having a different electrical type than the second ion, the third ion having a same electrical type as the first ion, the third ion having a doping concentration greater than the first ion and a doping concentration less than the second ion.
13. A method of forming a semiconductor structure, comprising:
providing a substrate having opposite first and second sides;
forming a heterojunction bipolar transistor on a first side of the substrate, the heterojunction bipolar transistor comprising: a first current collecting layer, a first base layer and a first current collecting electrode on the first current collecting layer, a first base electrode and an emission layer on the first base layer, and an emission electrode on the emission layer;
passive devices are formed on a second side of the substrate.
14. The method of forming a semiconductor structure of claim 13, further comprising, after forming the heterojunction bipolar transistor: a first passivation layer is formed on the first side of the substrate, the first passivation layer covering the surface of the heterojunction bipolar transistor, and the first passivation layer exposing the top surface of the first collector electrode, the top surface of the first base electrode, and the top surface of the emitter electrode.
15. The method of forming a semiconductor structure of claim 14, further comprising, during forming the heterojunction bipolar transistor: forming a diode on a first side of the substrate, the diode comprising: a second current collecting layer, a second base layer and a second current collecting electrode on the second current collecting layer, and a second base electrode on the second base layer; the first passivation layer also covers a surface of the diode, and exposes a top surface of the second collector electrode and a top surface of the second base electrode.
16. The method of forming a semiconductor structure of claim 15, wherein the method of forming a heterojunction bipolar transistor and a diode comprises: forming an initial collector layer on a first side of the substrate; forming an initial base layer on the initial current collecting layer; forming an initial emission layer on the initial base layer; forming the emission electrode on the initial emission layer; etching the initial emission layer by taking the emission electrode as a mask to form the emission layer; forming the first base electrode and the second base electrode on the initial base layer, respectively; performing first patterning processing on the initial base layer to form the first base layer and the second base layer; forming the first collector electrode and the second collector electrode on the initial collector layer, respectively; and carrying out isolation ion implantation treatment on the initial current collecting layer to form a plurality of isolation layers, a first current collecting layer and a second current collecting layer, wherein the first current collecting layer and the second current collecting layer are respectively positioned between the adjacent isolation layers.
17. The method of forming a semiconductor structure of claim 14, wherein forming a plurality of passive devices comprises: one or more of resistance, inductance, and capacitance are formed.
18. The method of forming a semiconductor structure of claim 17, wherein the method of forming a plurality of passive devices comprises: forming a second metal layer on a second side of the substrate, the second metal layer comprising: the inductor comprises a second metal part, a third metal part, the inductor and a second lead part, wherein the second lead part is electrically connected with the second metal part, the third metal part or the inductor.
19. The method of forming a semiconductor structure of claim 18, wherein the second metal portion is electrically connected to the resistor.
20. The method of forming a semiconductor structure of claim 18, wherein the method of forming a plurality of passive devices further comprises: forming a third passivation layer on the second side of the substrate, wherein the third passivation layer covers the surface of the second metal layer and exposes a part of the top surface of the second metal part, a part of the top surface of the third metal part and a part of the top surface of the inductor; and forming a third metal layer on the second side of the substrate, wherein the third metal layer is positioned on the surface of the third passivation layer, the projection of the third metal layer and the third metal part in the direction towards the substrate has an overlapping area, and the third metal layer, the third metal part and the third passivation layer positioned between the third metal layer and the third metal part form the capacitor.
21. The method of forming a semiconductor structure of claim 20, further comprising: a first metal layer is formed on the first side of the substrate, the first metal layer including a first metal portion and a first lead portion, the first lead portion being located on the first passivation layer, the first lead portion and the first metal portion being electrically connected, the first metal portion being located on the exposed top surface of the first collector electrode, the top surface of the first base electrode, or the top surface of the emitter electrode.
22. The method of forming a semiconductor structure of claim 21, further comprising, prior to forming a plurality of said passive devices: forming a plurality of through holes penetrating through the substrate and the first passivation layer, wherein the through holes expose the surface of the first lead part; the second lead portion fills the through hole.
23. The method of forming a semiconductor structure of claim 13, wherein the first collector layer is doped with first ions; the first base layer is internally doped with second ions, the electrical type of the first ions is different from that of the second ions, and the doping concentration of the second ions is larger than that of the first ions.
24. The method of claim 23, wherein a third ion is doped in the emitter layer, the third ion having a different electrical type than the second ion, the third ion having a same electrical type as the first ion, the third ion having a doping concentration greater than the first ion and a doping concentration less than the second ion.
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| CN117577667B (en) * | 2024-01-19 | 2024-04-16 | 常州承芯半导体有限公司 | Semiconductor device and method of forming the same |
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