CN117577667B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN117577667B
CN117577667B CN202410078023.8A CN202410078023A CN117577667B CN 117577667 B CN117577667 B CN 117577667B CN 202410078023 A CN202410078023 A CN 202410078023A CN 117577667 B CN117577667 B CN 117577667B
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layer
substrate
forming
conductive plug
semiconductor device
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CN117577667A (en
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邹道华
刘宇浩
刘昱玮
陈俊奇
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Changzhou Chengxin Semiconductor Co Ltd
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Changzhou Chengxin Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

A semiconductor device and method of forming the same, wherein the structure includes: a first substrate comprising an active region; a transistor device bonded to a surface of the active region, the transistor device comprising: an emissive layer comprising opposing first and second sides, a base layer positioned on the first side, a current collector layer positioned on the first side, and a base layer positioned between the current collector layer and the emissive layer; the first substrate is positioned on the first side, the first substrate and the emission layer are positioned on two sides of the base layer and the current collecting layer, and the projection areas of the emission layer, the base layer and the current collecting layer on the first substrate are gradually decreased along the direction from the second side to the first side. The area of the collector layer is reduced to reduce the base-collector capacitance C bc, so that the cut-off frequency f T and the maximum oscillation frequency f m of the transistor are improved; the transistor device faces the first substrate, and the heat dissipation effect and the working performance of the transistor device are improved.

Description

Semiconductor device and method of forming the same
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
The radio frequency front end module typically includes a Power Amplifier (PA), a low noise amplifier (Low Noise Amplifier LNA), a switch (switch), and a filter (filter). The power amplifier generally includes a Heterojunction Bipolar Transistor (HBT) which is a transistor composed of an emitter region (Emitter), a base region (base) and a collector region (collector), wherein the emitter region adopts a lightly doped wide band gap, the base region adopts a heavily doped narrow band gap, the emission efficiency is determined by a forbidden band energy difference, the main function is a current gain, such as a gain collector region current or a gain base region current, and the heterojunction bipolar transistor has the characteristics of stable performance, high speed, high frequency and the like. Heterojunction bipolar transistor technology has become one of the mainstream technologies in the market of radio frequency integrated circuits and has a profound effect on the development of modern communication technologies.
The current heterojunction bipolar transistor is mainly a gallium arsenide device, however, in the working process of the heterojunction bipolar transistor, the heat dissipation effect of gallium arsenide is poor, and the performance of the heterojunction bipolar transistor is further affected.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of a transistor device and improving the integration level.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor device, including: a first substrate comprising an active region; a transistor device bonded to a surface of the active region, the transistor device comprising: the emission layer comprises a first side and a second side which are opposite to each other, the base layer is located on the first side, the current collecting layer is located on the first side, the base layer is located between the current collecting layer and the emission layer, the first substrate is located on the first side, the first substrate and the emission layer are located on the base layer and two sides of the current collecting layer, and the projection area of the emission layer, the base layer and the current collecting layer on the first substrate is decreased in a direction from the second side to the first side.
Optionally, the thermal conductivity of the first substrate is greater than the thermal conductivity of the current collecting layer, the base layer, and the emission layer.
Optionally, the material of the first substrate includes silicon, silicon carbide, and gallium nitride.
Optionally, the material of the emission layer includes indium gallium arsenide; the material of the base layer comprises gallium arsenide or indium gallium arsenide; the material of the current collecting layer comprises gallium arsenide or aluminum gallium arsenic.
Optionally, the transistor device further includes: a first barrier layer on a second side of the emissive layer.
Optionally, the material of the first barrier layer includes indium gallium phosphide in an eigenstate.
Optionally, the method further comprises: a first dielectric layer between the transistor device and the first substrate, the first dielectric layer overlying the transistor device, and the transistor device being bonded to the first substrate through the first dielectric layer.
Optionally, the method further comprises: the first contact layer is positioned on the surface of the current collecting layer; the second contact layer is positioned on the surface of the base layer, and the second contact layer and the current collecting layer are mutually separated; and a third contact layer positioned on the surface of the emitting layer.
Optionally, the surface of the emission layer has a groove, the groove is located on the first side, and the third contact layer is located in the groove.
Optionally, an isolation region is formed in the emission layer, and doped ions are formed in the isolation region, or the isolation region is an isolation opening formed by etching the emission layer.
Optionally, the method further comprises: and the conductive plug structures penetrate through the first substrate and are respectively and electrically connected with the current collecting layer, the base layer and the emission layer.
Optionally, the method further comprises: a first conductive plug penetrating the first substrate, the first conductive plug being electrically connected to the collector layer; the second conductive plug is electrically connected with the base layer, and the second conductive plug and the first conductive plug are positioned on two sides of the current collecting layer; and the third conductive plug is electrically connected with the emission layer, and the third conductive plug and the first conductive plug are positioned on two sides of the current collection layer.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor device, which comprises the following steps: providing a first substrate, wherein the first substrate comprises an active region; providing a second substrate; forming a plurality of transistor devices on the surface of the second substrate, wherein the transistor devices comprise an emission layer, a base layer and a current collecting layer, the emission layer is positioned on the second substrate, the emission layer comprises a first side and a second side which are opposite, the second substrate is positioned on the second side, the base layer and the current collecting layer are positioned on the first side, and the base layer is positioned between the current collecting layer and the emission layer; bonding the first substrate and the transistor device with the first side of the emission layer facing the surface of the first substrate, wherein the first substrate is positioned on the first side, the first substrate and the emission layer are positioned on two sides of the base layer and the current collecting layer, and the projection areas of the emission layer, the base layer and the current collecting layer on the first substrate are gradually reduced along the direction from the second side to the first side; after bonding the first substrate and the transistor device, the second substrate is removed.
Optionally, the thermal conductivity of the first substrate is greater than the thermal conductivity of the second substrate; the material of the first substrate comprises silicon, silicon carbide or gallium nitride; the material of the second substrate comprises gallium arsenide.
Optionally, the method for forming the transistor device includes: forming an emission layer on the second substrate; forming an initial base layer on a first side of the emissive layer; forming an initial current collecting layer on the initial base layer; etching the initial current collecting layer to expose part of the surface of the initial base layer and form a current collecting layer; and etching the initial base layer to expose part of the surface of the emission layer to form the base layer.
Optionally, the method further comprises: and forming a first dielectric layer, wherein the first dielectric layer covers the transistor device and is used for being bonded with the first substrate.
Optionally, the method further comprises: and doping treatment or etching treatment is carried out on the emitting layer, and an isolation region is formed in the emitting layer.
Optionally, the method for forming a transistor device further includes: a first barrier layer is formed between the second substrate and the emissive layer.
Optionally, the ratio of the etching rate of the second substrate to the etching rate of the first barrier layer is in a range of: 10:1 to 20:1.
Optionally, the method for forming a transistor device further includes: and forming a second barrier layer between the current collection layer and the base layer, wherein the second barrier layer exposes a part of the surface of the base layer.
Optionally, the method further comprises: forming a first contact layer on the surface of the current collecting layer; forming a second contact layer on the surface of the base layer; and forming a third contact layer on the surface of the emission layer.
Optionally, the method for forming the third contact layer includes: etching part of the surface exposed by the emission layer to form a groove; and forming the third contact layer in the groove.
Optionally, the method further comprises: and forming a plurality of conductive plug structures penetrating through the first substrate, wherein the conductive plug structures are respectively and electrically connected with the current collecting layer, the base layer and the emission layer.
Optionally, the method further comprises: forming a first conductive plug penetrating through the first substrate, wherein the first conductive plug is electrically connected with the current collecting layer; forming a second conductive plug, wherein the second conductive plug is electrically connected with the base layer, and the second conductive plug and the first conductive plug are positioned on two sides of the current collecting layer; and forming a third conductive plug, wherein the third conductive plug is electrically connected with the emission layer, and the third conductive plug and the first conductive plug are positioned on two sides of the current collection layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
In the semiconductor device provided by the technical scheme of the invention, the transistor device is connected to the first substrate, the emitting layer is positioned on the top layer, the areas of the emitting layer, the base layer and the collector layer are decreased, and the base-collector capacitance C bc is reduced by reducing the area of the collector layer, so that the cut-off frequency f T and the maximum oscillation frequency f m of the transistor are improved, and the high-frequency performance of the transistor is improved. In addition, the transistor device is jointed towards the first substrate, and the collector layer is close to the first substrate, so that the heat dissipation effect and the working performance of the transistor device are further improved.
Further, in the technical scheme of the invention, the first substrate is made of a material with high heat conductivity coefficient, so that the heat dissipation effect of the transistor device in the working process is improved, the performance of the transistor device is further improved, and the transistor device, the low-noise amplifier, the switch and the filter can be manufactured on the first substrate together, so that the integration level of the radio frequency integrated circuit is further improved.
Further, in the technical scheme of the invention, the first blocking layer is positioned on the surface of the emitting layer so as to protect the transistor device from being damaged in the process of forming, thereby ensuring the device integrity of the transistor device structure; and the crystal lattice of the material of the first barrier layer is matched with the crystal lattice of the material of the transistor device, so that an epitaxial layer forming the transistor device can be grown on the first barrier layer, and the quality of forming the transistor device is improved.
Further, in the technical scheme of the invention, the conductive plug structure comprises aluminum and copper, so that the process material cost is reduced, aluminum and copper are not easy to diffuse to the first substrate, the heat dissipation performance of the first substrate is ensured, and the heat dissipation performance and the working performance of the transistor device structure are further ensured.
Further, according to the technical scheme, the third contact layer is arranged in the groove of the emission layer, so that the third contact layer can contact the area with higher doping concentration of the emission layer, contact with a space charge area is avoided, and the working performance of the transistor device is ensured.
In the technical scheme of the invention, the emitting layer is positioned on the top layer of the device, the thickness of the emitting layer is smaller than that of the collector layer, and compared with the collector layer on the top layer of the device, the depth of the groove formed in the emitting layer in the scheme is small, namely the size required to be reserved is smaller, so that the size of the transistor device in the direction parallel to the surface of the first substrate is reduced, and the integration level of the transistor device is improved.
In the method for forming the transistor device, when the transistor device is formed on the second substrate, the emitting layer is positioned at the bottom layer, after the transistor device is bonded to the first substrate, the emitting layer is positioned at the top layer, the areas of the emitting layer, the base layer and the collector layer are decreased progressively, and the base-collector capacitance C bc is reduced by reducing the area of the collector layer, so that the cut-off frequency f T and the maximum oscillation frequency f m of the transistor are improved, and the high-frequency performance of the transistor is improved. In addition, the transistor device is jointed towards the first substrate, the collector layer is close to the first substrate, and the heat dissipation effect and the working performance of the transistor device are further improved; the transistor device is transferred to the first substrate after the transistor device is formed on the second substrate, so that the operability of the preparation process of the transistor device is improved, the problem that the edge of an epitaxial layer used for forming the transistor device exceeds the first substrate after the bonding transfer is caused by mismatching of the size of the first substrate and the size of the second substrate, and the transistor device cannot be formed by etching operation on the epitaxial layer positioned on the first substrate is solved, the process selection is increased, the transistor device transfer method is suitable for transistor device transfer among substrates with different sizes, and the application range is wide.
Further, according to the technical scheme, the material of the second substrate comprises gallium arsenide, so that the material of the second substrate is lattice matched with the material of the transistor device, namely, the transistor device is formed on the second substrate by means of easy growth, and the formed transistor device is good in performance and not easy to fall off.
Furthermore, the first substrate in the technical scheme of the invention is made of the material with high heat conductivity coefficient, so that the heat dissipation effect of the transistor device in the working process is improved, the performance of the transistor device structure is further improved, and the material of the first substrate comprises silicon, namely the transistor device is positioned on the silicon substrate, so that the transistor device, the low-noise amplifier, the switch and the filter can be manufactured on the first substrate together, and the integration level of the radio frequency integrated circuit is further improved.
Further, in the technical scheme of the invention, the first barrier layer is formed on the surface of the second substrate, and the etching rate of the first barrier layer is smaller than that of the second substrate, so that etching is stopped at the first barrier layer when the second substrate is removed by etching, and the adjacent emitting layer is protected, so that the transistor device is protected from being damaged, and the performance of the transistor device is further ensured; and the crystal lattice of the material of the first barrier layer is matched with the crystal lattice of the material of the transistor device, so that an epitaxial layer of the transistor device can be formed on the first barrier layer in a growing way, the falling-off between the epitaxial layer and the second substrate is avoided, and the quality of the transistor device is improved.
Further, according to the technical scheme, the grooves are formed in the emission layer, so that the subsequently formed third contact layer can contact the area with higher doping concentration of the emission layer, contact with a space charge area is avoided, and the working performance of the transistor device is guaranteed.
In the technical scheme of the invention, before the first substrate and the transistor device are jointed, the emitting layer is positioned at the bottoms of the base layer and the current collecting layer, and the thickness of the emitting layer is smaller than that of the current collecting layer.
Further, in the technical scheme of the invention, the conductive plug structure comprises aluminum and copper, so that the process material cost is reduced, aluminum and copper are not easy to diffuse to the first substrate, the heat dissipation performance of the first substrate is ensured, and the heat dissipation performance and the working performance of the transistor device are further ensured.
Drawings
Fig. 1 is a schematic structural view of a semiconductor device.
Fig. 2 to 19 are schematic structural views of a forming process of a semiconductor device according to an embodiment of the present invention;
Fig. 20 to 21 are schematic structural views illustrating a process of forming a conductive plug structure in a semiconductor device according to an embodiment of the present invention;
Fig. 22 to 23 are schematic structural views of a forming process of a semiconductor device in another embodiment of the present invention.
Detailed Description
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
As described in the background, there is a need to improve the performance of heterojunction bipolar transistor devices. The analysis will now be described with reference to specific examples.
Fig. 1 is a schematic structural view of a semiconductor device.
Referring to fig. 1, the semiconductor device includes: a gallium arsenide substrate 100; a transistor device on a surface of the gallium arsenide substrate, the transistor device comprising: a collector layer 101 on a gallium arsenide substrate 100, a collector 102 on the surface of the collector layer 101, a base layer 103 on the collector layer 101, a base 104 on the surface of the base layer 103, an emitter layer 105 on the base layer 103, and an emitter 106 on the surface of the emitter layer 105.
In the scheme, gallium arsenide is adopted as a transistor device, but the radiating effect of gallium arsenide is not ideal, so that the performance of the transistor device is reduced.
Second, since the heterojunction bipolar transistor is formed on the gallium arsenide substrate, it cannot be integrated with the silicon-based device, reducing the integration level of the semiconductor device.
In addition, a metal interconnection structure (not shown in the figure) is formed on the gallium arsenide transistor device, and the material of the metal interconnection structure is gold, because gold does not diffuse in gallium arsenide, i.e. the heat dissipation effect of the substrate is not affected, but the use of gold further increases the cost of the process material.
On the basis, in the semiconductor device provided by the technical scheme of the invention, the transistor device is connected to the first substrate, the emitting layer is positioned on the top layer, the areas of the emitting layer, the base layer and the collector layer are decreased progressively, and the base-collector capacitance C bc is reduced by reducing the area of the collector layer, so that the cut-off frequency f T and the maximum oscillation frequency f m of the transistor are improved, and the high-frequency performance of the transistor is improved. In addition, the transistor device is jointed towards the first substrate, and the collector layer is close to the first substrate, so that the heat dissipation effect and the working performance of the transistor device are further improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 19 are schematic structural views of a forming process of a semiconductor device according to an embodiment of the present invention.
Referring to fig. 2, a second substrate 200 is provided.
The second substrate 200 is used to provide a structural basis for the formation of transistor devices.
In this embodiment, the material of the second substrate 200 includes gallium arsenide, and the thermal conductivity of the second substrate 200 is 46W/mk.
In the above scheme, the material of the second substrate comprises gallium arsenide, so that the material of the second substrate is lattice matched with the material of the transistor device, i.e. the transistor device is easily formed on the second substrate by growth and is not easy to fall off.
Referring to fig. 3, a plurality of transistor devices are formed on the surface of the second substrate 200.
The method for forming the transistor device comprises the following steps: forming an emission layer 202 on the second substrate 200; the emissive layer 202 includes opposing first and second sides a, b, the first side a being remote from the second substrate 200.
Forming an initial base layer 203 on a first side a of the emission layer 202; an initial current collecting layer 205 is formed on the initial base layer 203, and the initial current collecting layer 205 is located on a side of the initial base layer 203 remote from the emission layer 202. The initial base layer 203 and the initial collector layer 205 are used to provide a structural basis for the formation of transistor devices.
The method for forming the transistor device further comprises the following steps: a first barrier layer 201 is formed between the second substrate 200 and the emissive layer 202.
The first barrier layer 201 is used to protect the transistor device under the first barrier layer 201 from damage during the subsequent removal of the second substrate 200.
In this embodiment, the etching rate of the first barrier layer 201 is smaller than the etching rate of the second substrate 200.
The material of the first barrier layer 201 comprises indium gallium phosphide (InGaP) in its eigenstate.
In this embodiment, the material of the first barrier layer 201 includes intrinsic indium gallium phosphide (In 0.49Ga0.51 P); the thickness of the first barrier layer 201 ranges from 40 nm to 10000 nm.
The method for forming the transistor device further comprises the following steps: an initial second barrier layer 204 is formed on the surface of the initial base layer 203 before the initial collector layer 205 is formed.
Referring to fig. 4, a first contact layer 206 is formed on a portion of the surface of the initial collector layer 205.
Ohmic contact is provided between the first contact layer 206 and the initial collector layer 205.
In this embodiment, the first contact layer 206 has a multi-layer metal structure, and the first contact layer 206 is a multi-layer metal layer of titanium (Ti), platinum (Pt) film, titanium (Ti) film, platinum (Pt) film, and titanium (Ti) film, which are sequentially stacked.
In other embodiments, the first contact layer 206 may also be a single-layer metal structure.
Referring to fig. 5, the initial collector layer 205 is etched until a portion of the surface of the initial base layer is exposed, so as to form a collector layer 207.
In this embodiment, the initial collector layer 205 is etched using a dry etching process.
The dry etching process comprises the following technological parameters: the etching gas includes: chlorine gas; the flow rate of the etching gas is 10 sccm-500 sccm: when the flow rate of the etching gas is greater than 500sccm, the etching rate is too fast, and the etching is easy to reach the initial base layer below the initial collector layer 205, so that the device is invalid; when the etching gas is less than 10sccm, the material at the bottom of the initial collector layer 205 is easy to be etched, so that electrons are accumulated, and the reliability of the device is disabled due to heat generation.
After forming the collector layer 207, further including: the initial second barrier layer 204 is etched until the surface of the initial base layer 203 is exposed, forming a second barrier layer 208.
The second barrier layer 208 is configured to: when the initial collector layer 205 is etched, the initial base layer 203 is protected from etching damage to the initial base layer 203.
The material of the second barrier layer 208 includes indium gallium phosphide (InGaP).
In this embodiment, the material of the second barrier layer 208 includes indium gallium phosphide (In 0.49Ga0.51 P), the doping ion type In the second barrier layer 208 is N-type, and the doping ion concentration In the second barrier layer 208 is 1.0x10 15atom/cm3.
In this embodiment, the area of the upper surface of the second blocking layer 208 corresponds to the area of the lower surface of the current collecting layer 207.
In other embodiments not shown, the method further includes: a third barrier layer is formed between the initial base layer and the initial emissive layer.
The third barrier layer is used for: and when the initial base layer is etched, protecting the emitting layer from being damaged by etching.
Referring to fig. 6, a second contact layer 209 is formed on a portion of the surface of the initial base layer 203.
Ohmic contact is provided between the second contact layer 209 and the initial base layer 203.
In this embodiment, the second contact layer 209 has a multi-layered metal structure, and the second contact layer 209 is a multi-layered metal layer of a titanium (Ti) film, a platinum (Pt) film, and a titanium (Ti) film, which are sequentially stacked.
In other embodiments, the second contact layer 209 may also be a single-layer metal structure.
Referring to fig. 7, the initial base layer 203 is etched until the surface of the emission layer 202 is exposed, so as to form a base layer 210, and the second contact layer 209 is located on the surface of the base layer 210 away from the emission layer 202.
In other embodiments, the second contact layer 209 may be formed after the transistor device is transferred to the first substrate, and the second contact layer 209 is formed on the surface of the base layer 210 facing the emission layer 202.
The projected areas of the emission layer 202, the base layer 210 and the collector layer 207 on the second substrate 200 decrease from the second side b to the first side a.
In the above scheme, the area of the collector layer 207 is reduced to reduce the base-collector capacitance C bc, so that the cut-off frequency f T and the maximum oscillation frequency f m of the transistor are improved, and the high-frequency performance of the transistor is improved.
In this embodiment, the initial base layer 203 is etched by a dry etching process.
The dry etching process comprises the following technological parameters: the etching gas includes: chlorine gas; the flow rate of the etching gas is 10 sccm-500 sccm: when the flow rate of the etching gas is greater than 500sccm, the etching rate is too fast, and the etching gas is easy to etch the emission layer 202 below the initial base layer 203, so that the device is invalid; when the etching gas is less than 10sccm, the material at the bottom of the initial substrate 203 is easy to be etched, so that electrons are accumulated, and the reliability of the device is disabled due to heat generation.
The doping type of the emission layer 202 is consistent with the doping type of the current collection layer 207, and the doping type of the emission layer 202 is opposite to the doping type of the base layer 210; the material of the emission layer 202 includes gallium arsenide (GaAs) or indium gallium arsenide (InGaAs), the material of the base layer 210 includes gallium arsenide (GaAs) or indium gallium arsenide (InGaAs), and the material of the collector layer 207 includes gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs).
In this embodiment, the material of the emission layer 202 includes In 0.6Ga0.4 As, the material of the base layer 210 includes GaAs, and the material of the current collecting layer 207 includes GaAs.
In this embodiment, the doping ion type in the emission layer 202 is N-type doping, and the doping ion concentration in the emission layer 202 is 1.0×10 17atom/cm3 to 2.0×10 19atom/cm3; the doping ion type in the base layer 210 is P-type doping, and the doping ion concentration in the base layer 210 is 1.0x10 19atom/cm3; the concentration of the doping ions in the collector layer 207 is 1.0x10 15atom/cm3 to 1.0x10 18atom/cm3, the doping ions of the emitter layer 202 are identical to the doping type of the collector layer 207, and the doping type of the emitter layer 202 is opposite to the doping type of the base layer 210.
Referring to fig. 8, after the base layer 210 is formed, the exposed surface of the emission layer 202 is etched to form a recess 211, the base layer 210 is located on a portion of the surface of the emission layer 202, and the current collecting layer 207 is located on a portion of the surface of the base layer 210.
In this embodiment, the depth of the recess 211 is smaller than the thickness of the emission layer 202.
The depth of the grooves 211 ranges from 200 nm to 300 nm.
In this embodiment, the thickness of the emission layer 202 is 400 nm.
Referring to fig. 9, the third contact layer 213 is formed in the recess 211, the third contact layer 213 is located on the first side a of the emission layer 202, and ohmic contact is formed between the third contact layer 213 and the emission layer 202.
In other embodiments, the third contact layer 213 may be formed after the transistor device is transferred to the first substrate, the third contact layer 213 being formed on the second side b of the emitter layer 202.
Fig. 10 is a schematic plan view of fig. 9, in which the emission layer 202, the base layer 210, the second blocking layer 208, and the collector layer 207 are omitted, and fig. 9 is a schematic sectional view along line AA1 in fig. 10, that is, only the structures of the first contact layer 206, the second contact layer 209, and the third contact layer 213 are shown in fig. 10.
In the above solution, the doping concentration of the emitter layer 202 decreases along the direction from the second side to the first side, so that the doping concentration of the first side a of the emitter layer 202 is low, and a space charge region, that is, a non-conductive region, is easy to occur, so that ohmic contact cannot be formed between the third contact layer 213 and the emitter layer 202.
In this embodiment, the third contact layer 213 has a multi-layered metal structure, and the third contact layer 213 is a multi-layered metal layer of a titanium (Ti) film, a platinum (Pt) film, and a titanium (Ti) film, which are sequentially stacked.
In other embodiments, the third contact layer 213 may also be a single-layer metal structure.
In addition, in the technical solution of the present invention, before the first substrate 216 and the transistor device are bonded, the emitter layer 202 is located at the bottom of the base layer 210 and the collector layer 207, and the thickness of the emitter layer 202 is smaller than that of the collector layer 207.
The emissive layer 202 includes a device region and an isolation region 212, and the base layer 210 is located on a surface of the device region.
In this embodiment, after the initial base layer 203 is etched, the emitter layer 202 is doped, and an isolation region 212 is formed in the emitter layer 202.
The isolation regions 212 are used to avoid electrical cross-talk between adjacent active devices.
In other embodiments, after the first substrate 216 and the transistor device are bonded, the emitter layer 202 is doped to form isolation regions 212 within the emitter layer 202.
In this embodiment, the doping ions of the doping treatment include hydrogen ions, and the doping concentration of the ion doping treatment is 6×10 13atom/cm3.
In another embodiment, the method of forming the isolation region 212 further includes: after the initial base layer 203 is etched, the emitter layer 202 is etched until the second substrate 200 is exposed, forming isolation openings (not shown in the figure), and forming isolation regions 212 in the isolation openings.
In other embodiments, the method of forming the isolation region 212 further includes: after bonding the first substrate 216 and the transistor device, the emitter layer 202 is etched until the first passivation layer 214 is exposed, forming isolation openings (not shown) in which isolation regions 212 are formed.
The second substrate 200 includes a plurality of the transistor devices thereon.
In this embodiment, two transistor devices are provided, and isolation regions are respectively disposed on two opposite sides of the two transistor devices, and the two transistor devices are still electrically connected therebetween, so that the two transistor devices are connected in parallel to form a semiconductor device, so as to increase the current of the semiconductor device.
In other embodiments, isolation regions 212 are disposed on both sides of the one transistor device, respectively, and the one transistor device is used as a semiconductor device.
Referring to fig. 11, a first passivation layer 214 is formed to cover the transistor device, and the first passivation layer 214 covers the surface of the emission layer 202, the surface of the base layer 210, the surface of the collector layer 207, the surfaces of the first contact layer 206, the second contact layer 209, the third contact layer 213, and the surface of the second barrier layer 208.
The material of the first passivation layer 214 includes at least one of silicon oxide, silicon oxynitride, and silicon nitride.
In this embodiment, the first passivation layer 214 is formed by a plasma enhanced chemical vapor deposition process.
Referring to fig. 12, a first dielectric layer 215 is formed on the surface of the first passivation layer 214, and the first dielectric layer 215 covers the transistor device.
In this embodiment, the bonding manner is bonding, and the first dielectric layer 215 is used for bonding with the first substrate 216 formed later. The material of the first dielectric layer 215 includes silicon dioxide, silicon nitride, or silicon oxynitride.
Referring to fig. 13, the first side a of the emitter layer 202 faces the surface of the first substrate 216, the first substrate 216 and the plurality of transistor devices are bonded, and the surface of the first dielectric layer 215 is bonded to the surface of the first substrate 216.
The first substrate 216 is used to provide a structural basis for the transistor device.
The first substrate 216 includes an active region I.
In this embodiment, the material of the first substrate 216 includes silicon, and the thermal conductivity of the first substrate 216 is 124W/mk to 148W/mk, and the thermal conductivity of the first substrate 216 is greater than the thermal conductivity of the second substrate 200. The material of the first dielectric layer 215 includes silicon dioxide, and covalent bonding is easy to form when the first dielectric layer 215 and the first substrate 216 are bonded together, so that bonding performance of the subsequent transistor device and the material of the first substrate 216 is improved.
In this embodiment, the distance between the surface of the first contact layer 206 and the surface of the first substrate 216 is greater than 0nm.
In the above solution, since the thermal conductivity of the first substrate 216 is greater than that of the second substrate 200, transferring the transistor device from the second substrate 200 to the first substrate 216 may greatly improve the heat dissipation performance of the semiconductor device.
In addition, when the material of the first substrate is silicon, that is, the transistor device is located on the silicon substrate, it can be formed on the first substrate together with the low noise amplifier, the switch and the filter, thereby improving the integration level of the radio frequency integrated circuit.
Referring to fig. 14, after the first substrate 216 and the plurality of transistor devices are bonded, the semiconductor devices are vertically flipped, and the second substrate 200 is removed.
The method of removing the second substrate 200 includes: the second substrate 200 is subjected to planarization treatment so that the remaining thickness of the second substrate 200 is 5 μm.
In this embodiment, the planarization method includes: mechanical polishing, chemical polishing, fluid polishing, chemical mechanical polishing, and the like. Specifically, in the present embodiment, the planarization process is a chemical mechanical polishing process. Unlike traditional mechanical polishing method, chemical mechanical polishing method has the combined chemical and mechanical effect to avoid the damage of the surface caused by mechanical polishing and the low polishing speed, poor surface flatness and polishing consistency caused by chemical polishing. Chemical mechanical polishing is widely used for high planarization polishing of various materials on the nanometer scale.
Referring to fig. 15, the second substrate 200 is etched until the surface of the first barrier layer 201 is exposed.
In this embodiment, the second substrate 200 is etched by a wet etching process.
The etching process is aimed at removing the second substrate 200.
The ratio of the etching rate of the second substrate 200 to the etching rate of the first barrier layer 201 is in the range of: 10:1 to 20:1.
In the above solution, the first barrier layer 201 is formed on the surface of the second substrate 200, and the etching rate of the first barrier layer 201 is smaller than that of the second substrate 200, so that etching stops at the first barrier layer 201 when the second substrate 200 is removed by etching, and the adjacent emitter layer 202 is protected, so as to protect the transistor device from being damaged, and further ensure the performance of the transistor device.
In addition, the crystal lattice of the material of the first barrier layer 201 is matched with the crystal lattice of the material of the transistor device, so that an epitaxial layer of the transistor device can be grown on the first barrier layer 201, the falling-off between the epitaxial layer and the second substrate 200 is avoided, and the quality of forming the transistor device is improved.
After the transistor is formed on the second substrate 200, the transistor device is transferred to the first substrate 216, so that the operability of the preparation process of the transistor device is improved, the problem that the size of the first substrate 216 is not matched with that of the second substrate 200 (for example, the area of the first substrate 216 is smaller than that of the second substrate 200), the edge of an epitaxial layer used for forming the transistor device after bonding transfer exceeds the first substrate 216, and the epitaxial layer on the first substrate 216 cannot be etched to form the transistor device is solved, the process selection is increased, and the transistor device transfer method is suitable for transistor device transfer among substrates with different sizes and wide in application range.
Referring to fig. 16, after the second substrate 200 is removed, a second dielectric layer 217 is formed on the surface of the first barrier layer 201.
In this embodiment, the material of the second dielectric layer 217 includes silicon nitride.
Referring to fig. 17, the first substrate 216 further includes a passive region II; the method for forming the semiconductor device further comprises the following steps: and forming a passive device structure on the surface of the passive region II.
The method for forming the passive device structure comprises the following steps: forming a first metal layer 219 on the surface of the first substrate 216; forming a third dielectric layer 220 on the surface of the first metal layer 219 and the surface of the first substrate 216; a second metal layer 221 is formed on the surface of the third dielectric layer 220.
In this embodiment, the third dielectric layer 220 includes silicon nitride.
The passive device includes: one or more of capacitance, inductance, and resistance.
In this embodiment, the passive device is a capacitor.
After forming the transistor device and the passive device structure, forming a second passivation layer 218 on the first substrate 216 surface, the transistor device surface, and the passive device surface; the material of the second passivation layer 218 includes silicon nitride and/or a macromolecular polymer.
Referring to fig. 18 and 19, fig. 19 is a schematic top view of fig. 18, in which the first barrier layer 201, the emission layer 202, the base layer 210, the second barrier layer 208, the collector layer 207, and the first passivation layer 214 are omitted, and fig. 18 is a schematic cross-sectional view along line BB1 in fig. 19, that is, fig. 19 shows only the structures of the first contact layer 206, the second contact layer 209, and the third contact layer 213.
Fig. 20 to 21 are schematic structural views illustrating a process of forming a conductive plug structure in a semiconductor device according to an embodiment of the present invention.
Referring to fig. 20 on the basis of fig. 18, the first substrate 216, the first dielectric layer 215 and the first passivation layer 214 are etched until the surfaces of the first contact layer 206, the second contact layer 209 and the third contact layer 213 are exposed, so as to form an opening 222 penetrating through the first substrate 216.
In other embodiments, not shown, after forming the opening 222, further includes: a first contact layer 206, a second contact layer 209, and a third contact layer 213 are formed on the bottom surface of the opening 222, where the first contact layer 206 is electrically connected to the collector layer 207, the second contact layer 209 is electrically connected to the base layer 210, and the third contact layer 213 is electrically connected to the emitter layer 202.
Referring to fig. 21, a plurality of conductive plug structures 223 penetrating the first substrate 216 are formed in the opening 222, and the conductive plug structures 223 are electrically connected to the first contact layer 206, the second contact layer 209 and the third contact layer 213, respectively.
The material of the conductive plug structure 223 includes aluminum and/or copper.
A diffusion barrier layer (not shown) is further included between the first contact layer 206, the second contact layer 209, and the third contact layer 213, and the conductive plug structure 223, respectively. The diffusion barrier layer is used to separate the first contact layer 206, the second contact layer 209, and the third contact layer 213 from the conductive plug structure 223, respectively, so as to prevent copper and aluminum from diffusing to the collector layer 207, the base layer 210, and the emitter layer 202 through the first contact layer 206, the second contact layer 209, and the third contact layer 213.
In the above solution, since the material of the first substrate 216 is silicon, aluminum and copper are not easy to diffuse into the first substrate 216, the use of aluminum and copper as the material of the conductive plug structure 223 reduces the cost of process materials, and ensures the heat dissipation performance of the first substrate 216, thereby ensuring the heat dissipation performance and the working performance of the transistor device; in addition, by providing a diffusion barrier layer, aluminum and copper are prevented from diffusing to the collector layer 207, the base layer 210 and the emitter layer 202 through the first contact layer 206, the second contact layer 209 and the third contact layer 213, thereby improving the performance of the transistor device.
Fig. 22 to 23 are schematic structural views illustrating a process of forming a conductive plug structure in a semiconductor device according to another embodiment of the present invention.
Referring to fig. 22 on the basis of fig. 18, the first substrate 216, the first dielectric layer 215 and the first passivation layer 214 are etched until the surface of the first contact layer 206 is exposed, so as to form a first opening 322; etching the base layer 210, the emission layer 202 and the first barrier layer 201 until the surface of the second contact layer 209 is exposed, so as to form a second opening 323; the emitter layer 202 and the first barrier layer 201 are etched until the surface of the third contact layer 213 is exposed, thereby forming a third opening 324.
In other embodiments, the first barrier layer 201 and the emission layer 202 are etched until the surface of the base layer 210 is exposed, a second opening is formed, a second contact layer 209 is formed on the surface of the base layer 210 exposed by the second opening, the second contact layer 209 is located on the surface of the base layer 210 facing the emission layer 202, and the second contact layer 209 is electrically connected to the base layer 210.
In other embodiments, the first barrier layer 201 is etched until the surface of the emission layer 202 is exposed, a third opening is formed, a third contact layer 213 is formed on the surface of the emission layer 202 exposed by the third opening, the third contact layer 213 is located on the second side b of the emission layer 202, and the third contact layer 213 is electrically connected to the emission layer 202.
An isolation layer 317 is formed on the surfaces of the second opening 323 and the third opening 324.
In this embodiment, the isolation layer 317 includes silicon nitride.
The isolation layer 317 is used to prevent a short circuit between the emitter layer 202 and the base layer 210 when the conductive plug structure is formed later, so as to avoid electrical interference between the conductive plug structure and the transistor device.
Referring to fig. 23, a plurality of conductive plug structures are formed in the first opening 322, the second opening 323, the third opening 324 and the surface of the first substrate 216, and the conductive plug structures are electrically connected to the first contact layer 206, the second contact layer 209 and the third contact layer 213, respectively.
The conductive plug structure includes: a first conductive plug 325 in the first opening 322, a second conductive plug 326 in the second opening 323, and a third conductive plug 327 in the third opening 324, wherein the second conductive plug 326 and the first conductive plug 325 are located at two sides of the collector layer 207, and the third conductive plug 327 and the first conductive plug 325 are located at two sides of the collector layer 207.
In this embodiment, before forming the second conductive plugs 326 and the third conductive plugs 327, the method further includes: the isolation layer 317 on the surfaces of the second contact layer 209 and the third contact layer 213 is etched to expose the surfaces of the second contact layer 209 and the third contact layer 213, so that the second conductive plug structure 326 and the third conductive plug structure 327, which are formed later, are electrically connected to the second contact layer 209 and the third contact layer 213, respectively.
The second conductive plugs 326 and the third conductive plugs 327 are in a multi-layered metal structure.
In this embodiment, the second conductive plug 326 and the third conductive plug 327 are two-layer metal structures, and the two-layer metal structures are respectively formed corresponding to and simultaneously with the first metal layer 219 and the second metal layer 221 in the passive device.
In one embodiment, the two metal structures in the second conductive plug 326 are formed corresponding to and simultaneously with the first metal layer 219 and the second metal layer 221 in the passive device, respectively.
In other embodiments, the two metal structures in the third conductive plug 327 are formed corresponding to and simultaneously with the first metal layer 219 and the second metal layer 221 in the passive device, respectively.
Specifically, a first metal structure of the second conductive plug 326 and a first metal structure of the third conductive plug 327 are formed in the second opening 323 and the third opening 324, respectively, and a first metal layer 219 is formed on the surface of the first substrate 216; forming a third dielectric layer 220 on the first substrate 216, the isolation layer 317, the first metal structure of the second conductive plug 326, the first metal structure of the third conductive plug 327, and the surface of the first metal layer 219, wherein the third dielectric layer 220 exposes the first metal structure of the second conductive plug 326 and a portion of the surface of the first metal structure of the third conductive plug 327; forming a second metal structure on the first metal structure of the second conductive plug 326, forming a second metal structure on the first metal structure of the third conductive plug 327, and forming a second metal layer 221 on the surface of the third dielectric layer 220; a second passivation layer 218 is formed to cover the third dielectric layer 220, the second conductive plugs 326, the third conductive plugs 327, and the surface of the second metal layer 221.
The material of the conductive plug comprises aluminum and/or copper. Diffusion barriers are further included between the first contact layer 206 and the first conductive plug 325, between the second contact layer 209 and the second conductive plug 326, and between the third contact layer 213 and the third conductive plug 327, for separating the first contact layer 206, the second contact layer 209, and the third contact layer 213 from the first conductive plug 325, the second conductive plug 326, and the third conductive plug 327, respectively, so as to prevent copper and aluminum from diffusing to the collector layer 207, the base layer 210, and the emitter layer 202 through the first contact layer 206, the second contact layer 209, and the third contact layer 213.
In the above solution, since the material of the first substrate 216 is silicon, aluminum and copper are not easy to diffuse into the first substrate 216, the use of aluminum and copper as the material of the conductive plug reduces the cost of the process material, and ensures the heat dissipation performance of the first substrate 216, thereby ensuring the heat dissipation performance and the working performance of the transistor device.
Accordingly, please continue to refer to fig. 17 and 21, the technical scheme of the present invention further provides a semiconductor device, which includes: a first substrate 216, the first substrate 216 comprising an active region I; a transistor device bonded to a surface of the active region I, the transistor device comprising: the light emitting device comprises an emitting layer 202, a base layer 210 and a current collecting layer 207, wherein the emitting layer 202 comprises a first side a and a second side b which are opposite, the base layer 210 is positioned on the first side a, the current collecting layer 207 is positioned on the first side a, the base layer 210 is positioned between the current collecting layer 207 and the emitting layer 202, a first substrate 216 is positioned on the first side a, the first substrate 216 and the emitting layer 202 are positioned on two sides of the base layer 210 and the current collecting layer 207, and the projection area of the emitting layer 202, the base layer 210 and the current collecting layer 207 on the first substrate 216 is gradually reduced along the direction from the second side b to the first side a.
The material of the emission layer 202 includes indium gallium arsenide (InGaAs); the material of the base layer 210 includes gallium arsenide (GaAs) or indium gallium arsenide (InGaAs); the material of the collector layer 207 includes gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs).
In this embodiment, the material of the emission layer 202 includes In 0.6Ga0.4 As, the material of the base layer 210 includes GaAs, and the material of the current collecting layer 207 includes GaAs.
In this embodiment, the thermal conductivity of the first substrate 216 is greater than the thermal conductivity of the current collecting layer 207, the base layer 210 and the emission layer 202.
In this embodiment, the material of the first substrate 216 includes silicon, silicon carbide, or gallium nitride.
In this embodiment, the thermal conductivity of the first substrate 216 is 124W/mk to 148W/mk; the thermal conductivity of the emissive layer 202 is 30W/mk to 50W/mk; the thermal conductivity of the base layer 210 is 46W/mk; the heat conductivity of the collector layer is 46W/mk.
The material of the first substrate 216 is not limited by the present invention, and other materials (with a thermal conductivity greater than that of the second substrate 200) of the first substrate 216 are all within the scope of the present invention.
In this embodiment, the transistor device further includes: a first barrier layer 201 on the second side b of the emissive layer 202, and a second barrier layer 208 between the base layer 210 and the current collector layer 207.
In this embodiment, the material of the first barrier layer 201 includes intrinsic indium gallium phosphide (InGaP); the thickness of the first barrier layer 201 ranges from 40 nm to 10000 nm; the material of the first barrier layer 201 is different from the material of the emissive layer 202.
In this embodiment, the doping type of the emission layer 202 is identical to the doping type of the current collecting layer 207, and the doping type of the emission layer 202 is opposite to the doping type of the base layer 210; the material of the emission layer 202 includes gallium arsenide and indium gallium arsenide, the material of the base layer 210 includes gallium arsenide and indium gallium arsenide, and the material of the collector layer 207 includes gallium arsenide and aluminum gallium arsenide.
In this embodiment, the doping ion type in the emission layer 202 is N-type doping, and the doping ion concentration in the emission layer 202 is 1.0×10 17atom/cm3 to 2.0×10 19atom/cm3; the doping ion type in the base layer 210 is P-type doping, and the doping ion concentration in the base layer 210 is 1.0x10 19atom/cm3; the concentration of the doping ions in the collector layer 207 is 1.0x10 15atom/cm3 to 1.0x10 18atom/cm3, the doping ions of the emitter layer 202 are identical to the doping type of the collector layer 207, and the doping type of the emitter layer 202 is opposite to the doping type of the base layer 210. The thickness of the emission layer 202 is smaller than the thickness of the current collection layer 207.
In this embodiment, the transistor device further includes: a first dielectric layer 215 on the first side a, wherein the first dielectric layer 215 covers the transistor device, and the transistor device is bonded to the surface of the first substrate 216 through the surface of the first dielectric layer 215. The material of the first dielectric layer 215 includes silicon dioxide, silicon nitride, or silicon oxynitride.
In this embodiment, the transistor device further includes: a first passivation layer 214 on the surface of the emission layer 202, the surface of the base layer 210, and the surface of the collector layer 207; the first dielectric layer 215 is located on the surface of the passivation layer; the material of the first passivation layer 214 includes silicon nitride.
In this embodiment, the transistor device further includes: a second dielectric layer 217 on the surface of the first barrier layer 201; the material of the second dielectric layer 217 includes silicon nitride.
In this embodiment, the transistor device further includes: a first contact layer 206 located on the surface of the collector layer 207; a second contact layer 209 located on a surface of the base layer 210 remote from the emission layer 202, the second contact layer 209 being separated from the current collection layer 207; and a third contact layer 213 located on the surface of the emission layer 202.
In other embodiments, the second contact layer 209 is located on the surface of the base layer 210 facing the emission layer 202.
In this embodiment, the surface of the emission layer 202 has a groove 211, the groove 211 is located on the first side a, and the third contact layer 213 is located in the groove 211.
In other embodiments, the third contact layer 213 is located on the second side b of the emissive layer 202.
In this embodiment, the material of the first contact layer 206 includes one or more of titanium and platinum; the material of the second contact layer 209 comprises one or more combinations of titanium and platinum; the material of the third contact layer 213 includes one or more combinations of titanium and platinum.
In one embodiment, the first contact layer 206 adopts a multi-layered metal structure, and the first contact layer 206 is a multi-layered metal layer of a titanium (Ti) film, a platinum (Pt) film, and a titanium (Ti) film, which are sequentially stacked.
In other embodiments, the first contact layer 206 may also be a single-layer metal structure.
In this embodiment, the emission layer 202 includes an isolation region 212, and doped ions are further included in the isolation region; the dopant ions include hydrogen ions, and the isolation region 212 has a doping concentration of 6×10 13atom/cm3.
In other embodiments, the isolation regions include isolation openings formed by an etching process to the emitter layer 202.
In this embodiment, the semiconductor device further includes: a second passivation layer 218 located on the surface of the first substrate 216 and the surface of the transistor device; the material of the second passivation layer 218 includes silicon nitride and/or a macromolecular polymer.
In this embodiment, the first substrate 216 further includes a passive region II; the semiconductor device further includes: the passive device structure is positioned on the surface of the passive region II; the passive device structure comprises one or more of a resistor, a capacitor and an inductor; the second passivation layer 218 is also located on the passive device structure surface.
In this embodiment, the passive device is a capacitor.
In this embodiment, the semiconductor device further includes: a plurality of conductive plug structures 223 extending through the first substrate 216, the conductive plug structures 223 being electrically connected to the collector layer 207, the base layer 210 and the emitter layer 202, respectively.
Accordingly, please continue to refer to fig. 17 and 23, the technical scheme of the present invention further provides a semiconductor device, wherein the semiconductor device in fig. 17 is the same as the semiconductor device described above, and the differences are that: the conductive plug structure is arranged on two sides of the current collecting layer.
In this embodiment, the conductive plug structure further includes: a first conductive plug 325 penetrating the first substrate 216, the first conductive plug 325 being electrically connected to the collector layer 207; a second conductive plug 326 extending through the emissive layer 202 and the base layer 210, the second conductive plug 326 being electrically connected to the base layer 210; a third conductive plug 327 extending through the emissive layer 202, the third conductive plug 327 electrically connected to the emissive layer 202.
In other embodiments, the second contact layer 209 is located on a surface of the base layer 210 facing the emission layer 202, and the second conductive plug 326 is electrically connected to the base layer 210 through the emission layer 202.
In other embodiments, the third contact layer 213 is located on the second side surface of the emission layer 202, and the third conductive plug 327 is located above the emission layer 202 and electrically connected to the emission layer 202.
The second conductive plugs 326 and the third conductive plugs 327 are in a multi-layered metal structure.
In this embodiment, the second conductive plug 326 and the third conductive plug 327 are two-layer metal structures, and one of the two-layer metal structures corresponds to the first metal layer 219 and the second metal layer 221 in the passive device, respectively.
In one embodiment, one of the two metal structures in the second conductive plug 326 corresponds to the first metal layer 219 and the second metal layer 221, respectively, in a passive device.
In other embodiments, one of the two metal structures in the third conductive plug 327 corresponds to the first metal layer 219 and the second metal layer 221 in the passive device, respectively.
In this embodiment, the conductive plugs include aluminum and/or copper.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (24)

1. A semiconductor device, comprising:
a first substrate comprising an active region;
A transistor device bonded to a surface of the active region, the transistor device comprising: the emission layer comprises a first side and a second side which are opposite, the base layer is positioned on the first side, the current collecting layer is positioned on the first side, the base layer is positioned between the current collecting layer and the emission layer, the first substrate is positioned on the first side, the first substrate and the emission layer are positioned on two sides of the base layer and the current collecting layer, and the projection areas of the emission layer, the base layer and the current collecting layer on the first substrate are gradually reduced along the direction from the second side to the first side;
And a first dielectric layer between the transistor device and the first substrate, the transistor device being bonded to the first substrate through the first dielectric layer.
2. The semiconductor device according to claim 1, wherein a thermal conductivity of the first substrate is greater than thermal conductivity of the collector layer, the base layer, and the emitter layer.
3. The semiconductor device of claim 2, wherein the material of the first substrate comprises silicon, silicon carbide, or gallium nitride.
4. The semiconductor device of claim 2, wherein a material of the emissive layer comprises indium gallium arsenide; the material of the base layer comprises gallium arsenide or indium gallium arsenide; the material of the current collecting layer comprises gallium arsenide or aluminum gallium arsenic.
5. The semiconductor device according to claim 1, wherein the transistor device further comprises: a first barrier layer on a second side of the emissive layer.
6. The semiconductor device of claim 5, wherein the material of the first barrier layer comprises intrinsic state indium gallium phosphide.
7. The semiconductor device of claim 1, wherein the first dielectric layer covers the transistor device.
8. The semiconductor device according to claim 1, further comprising: the first contact layer is positioned on the surface of the current collecting layer; the second contact layer is positioned on the surface of the base layer, and the second contact layer and the current collecting layer are mutually separated; and a third contact layer positioned on the surface of the emitting layer.
9. The semiconductor device of claim 8, wherein a surface of the emissive layer has a recess, the recess being located on the first side, and a third contact layer being located within the recess.
10. The semiconductor device of claim 1, wherein the emitter layer has an isolation region therein, the isolation region having dopant ions therein, or the isolation region is an isolation opening formed by etching the emitter layer.
11. The semiconductor device according to claim 1, further comprising: and the conductive plug structures penetrate through the first substrate and are respectively and electrically connected with the current collecting layer, the base layer and the emission layer.
12. The semiconductor device according to claim 1, further comprising: a first conductive plug penetrating the first substrate, the first conductive plug being electrically connected to the collector layer; the second conductive plug is electrically connected with the base layer, and the second conductive plug and the first conductive plug are positioned on two sides of the current collecting layer; and the third conductive plug is electrically connected with the emission layer, and the third conductive plug and the first conductive plug are positioned on two sides of the current collection layer.
13. A method of forming a semiconductor device, comprising:
Providing a first substrate, wherein the first substrate comprises an active region;
Providing a second substrate;
forming a plurality of transistor devices on the surface of the second substrate, wherein the transistor devices comprise an emission layer, a base layer and a current collecting layer, the emission layer is positioned on the second substrate, the emission layer comprises a first side and a second side which are opposite, the second substrate is positioned on the second side, the base layer and the current collecting layer are positioned on the first side, and the base layer is positioned between the current collecting layer and the emission layer;
Bonding the first substrate and the transistor device with the first side of the emission layer facing the surface of the first substrate, wherein the first substrate is positioned on the first side, the first substrate and the emission layer are positioned on two sides of the base layer and the current collecting layer, and the projection areas of the emission layer, the base layer and the current collecting layer on the first substrate are gradually reduced along the direction from the second side to the first side;
after bonding the first substrate and the transistor device, the second substrate is removed.
14. The method of forming a semiconductor device according to claim 13, wherein a thermal conductivity of the first substrate is greater than a thermal conductivity of the second substrate; the material of the first substrate comprises silicon, silicon carbide or gallium nitride; the material of the second substrate comprises gallium arsenide.
15. The method of forming a semiconductor device according to claim 13, wherein the method of forming a transistor device comprises: forming an emission layer on the second substrate; forming an initial base layer on a first side of the emissive layer; forming an initial current collecting layer on the initial base layer; etching the initial current collecting layer to expose part of the surface of the initial base layer and form a current collecting layer; and etching the initial base layer to expose part of the surface of the emission layer to form the base layer.
16. The method of forming a semiconductor device according to claim 13, further comprising: and forming a first dielectric layer, wherein the first dielectric layer covers the transistor device and is used for being bonded with the first substrate.
17. The method of forming a semiconductor device according to claim 13, further comprising: and doping treatment or etching treatment is carried out on the emitting layer, and an isolation region is formed in the emitting layer.
18. The method of forming a semiconductor device according to claim 13, wherein the method of forming a transistor device further comprises: a first barrier layer is formed between the second substrate and the emissive layer.
19. The method of forming a semiconductor device of claim 18, wherein a ratio of an etch rate of the second substrate to an etch rate of the first barrier layer ranges from: 10:1 to 20:1.
20. The method of forming a semiconductor device according to claim 13, wherein the method of forming a transistor device further comprises: and forming a second barrier layer between the current collection layer and the base layer, wherein the second barrier layer exposes a part of the surface of the base layer.
21. The method of forming a semiconductor device according to claim 15, further comprising: forming a first contact layer on the surface of the current collecting layer; forming a second contact layer on the surface of the base layer; and forming a third contact layer on the surface of the emission layer.
22. The method of forming a semiconductor device according to claim 21, wherein the method of forming the third contact layer comprises: etching part of the surface exposed by the emission layer to form a groove; and forming the third contact layer in the groove.
23. The method of forming a semiconductor device according to claim 13, further comprising: and forming a plurality of conductive plug structures penetrating through the first substrate, wherein the conductive plug structures are respectively and electrically connected with the current collecting layer, the base layer and the emission layer.
24. The method of forming a semiconductor device according to claim 13, further comprising: forming a first conductive plug penetrating through the first substrate, wherein the first conductive plug is electrically connected with the current collecting layer; forming a second conductive plug, wherein the second conductive plug is electrically connected with the base layer, and the second conductive plug and the first conductive plug are positioned on two sides of the current collecting layer; and forming a third conductive plug, wherein the third conductive plug is electrically connected with the emission layer, and the third conductive plug and the first conductive plug are positioned on two sides of the current collection layer.
CN202410078023.8A 2024-01-19 2024-01-19 Semiconductor device and method of forming the same Active CN117577667B (en)

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