CN220510039U

CN220510039U - Heterojunction bipolar transistor structure

Info

Publication number: CN220510039U
Application number: CN202322004875.6U
Authority: CN
Inventors: 邹道华; 高谷信一郎; 刘昱玮; 陈俊奇
Original assignee: Changzhou Chengxin Semiconductor Co Ltd
Current assignee: Changzhou Chengxin Semiconductor Co Ltd
Priority date: 2023-07-27
Filing date: 2023-07-27
Publication date: 2024-02-20
Anticipated expiration: 2033-07-27

Abstract

A heterojunction bipolar transistor structure comprising: a substrate; the collector layer comprises an edge part, a side wall part and a main body part; an emitter electrode on the emitter layer; an isolation region located within the edge portion and the sidewall portion; the base electrode comprises the end part, a plurality of finger parts and a plurality of connecting parts, wherein the connecting parts are positioned on the isolation areas in the side wall parts, and the end part is positioned on the isolation areas in the edge parts. The end part of the base electrode is positioned on the isolation region in the edge part, so that the area of the base layer can be reduced, the area of a PN junction between the base layer and the current collecting layer is further reduced, the parasitic capacitance is reduced, and the performance of the device structure is improved. The part which is used for providing placement for the end part of the base electrode and cannot contribute current is removed from the base layer, so that the utilization efficiency of the device structure can be effectively improved. In addition, the isolation region is used for carrying out electrical isolation in the device structure, so that the device structure is simpler, and the manufacturing cost is effectively reduced.

Description

Heterojunction bipolar transistor structure

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a heterojunction bipolar transistor structure.

Background

With the development of society and the demand for high performance and low cost RF components in the high frequency band for modern communications, conventional silicon material devices have failed to meet these new performance requirements. Because Heterojunction Bipolar Transistors (HBTs) have a high frequency performance that is much better than that of silicon bipolar transistors, and the compatibility with silicon technology makes them low-priced for silicon, gallium arsenide technology has achieved a great deal of progress, and gallium arsenide HBT technology has become one of the mainstream technologies in the RF integrated circuit market and has had a profound impact on the development of modern communication technologies.

However, heterojunction bipolar transistor structures still have a number of problems.

Disclosure of Invention

The technical problem solved by the utility model is to provide a heterojunction bipolar transistor structure, which improves the utilization efficiency of devices, reduces parasitic capacitance and reduces manufacturing cost.

In order to solve the above problems, the present utility model provides a heterojunction bipolar transistor structure, comprising: a substrate; a current collecting layer on the substrate, the current collecting layer including an edge portion, a side wall portion, and a main body portion arranged and abutted along a first direction, the side wall portion being located between the edge portion and the main body portion, the first direction being parallel to the substrate surface; a base layer on the body portion; the emission layers are arranged in parallel along a second direction, the second direction is parallel to the surface of the substrate, and the first direction is perpendicular to the second direction; an emitter electrode on the emitter layer; a first passivation layer on the base layer partial surface, the emission layer surface and the emission electrode partial surface, the first passivation layer exposing a partial top surface of the emission electrode and a partial top surface of the base layer between adjacent emission layers; an isolation region within the edge portion and the sidewall portion, the isolation region having isolation particles therein; the base electrode comprises an end part, a plurality of finger parts and a plurality of connecting parts, wherein the finger parts are connected with the end part through the connecting parts and are respectively and electrically connected with the exposed base layer, the connecting parts are positioned on the isolation areas in the side wall parts, the main body parts and the connecting parts are respectively positioned on two sides of the isolation areas in the side wall parts, and the end part is positioned on the isolation areas in the edge parts; and a collector electrode positioned on the collector layer along the second direction, wherein the collector electrode is electrically connected with the collector layer.

Optionally, the isolation region is also located within a portion of the body portion.

Alternatively, the emission electrode adopts a single-layer metal structure or a multi-layer metal structure.

Optionally, the method further comprises: and a second passivation layer positioned on a surface of the first passivation layer, a surface of the collector layer, a partial surface of the base electrode, and a partial surface of the collector electrode, and exposing a partial top surface of the end portion of the base electrode, and a partial top surface of the collector electrode.

Optionally, the method further comprises: and an interconnection metal layer electrically connected to the exposed surface of the emitter electrode, the exposed surface of the end portion of the base electrode, and the exposed surface of the collector electrode, respectively.

Optionally, the interconnect metal layer includes a first interconnect, a second interconnect, and a third interconnect that are separated from each other, the first interconnect being electrically connected to the exposed surface of the emitter electrode, the second interconnect being electrically connected to the exposed surface of the end portion of the base electrode, and the third interconnect being electrically connected to the exposed surface of the collector electrode.

Optionally, the collector layer is doped with first ions; the base layer is doped with second ions, the electrical type of the first ions is different from that of the second ions, and the doping concentration of the second ions is larger than that of the first ions.

Optionally, a third ion is doped in the emission layer, the electrical type of the third ion is different from the electrical type of the second ion, the electrical type of the third ion is the same as the electrical type of the first ion, the doping concentration of the third ion is greater than the doping concentration of the first ion, and the doping concentration of the third ion is less than the doping concentration of the second ion.

Compared with the prior art, the technical scheme of the utility model has the following advantages:

in the heterojunction bipolar transistor structure of the technical scheme of the utility model, the end part of the base electrode is positioned on the isolation region in the edge part, the base layer does not need to provide a placement position for the end part of the base electrode, the area of the base layer can be effectively reduced, and then the area of a PN junction formed between the base layer and the current collecting layer is reduced, so that when the device structure works, the parasitic capacitance formed between the base layer and the current collecting layer is reduced, thereby improving the radio frequency gain and the cut-off frequency of the device structure and improving the performance of the device structure. The base layer is provided with the base electrode, and the base electrode is provided with the end part which is placed and cannot contribute current, so that the utilization efficiency of the device structure can be effectively improved.

In addition, the isolation region not only can effectively prevent the device structure from being electrically connected with the device structures in other areas in series, but also can be used for electrically isolating the connection part and the end part of the base electrode in the device structure from being respectively connected with the current collecting layer, so that an insulating layer for electrical isolation is prevented from being additionally formed, the device structure is simpler, and the manufacturing cost is effectively reduced.

Drawings

Fig. 1 to 3 are schematic structural views of a heterojunction bipolar transistor structure;

fig. 4 to 20 are schematic structural diagrams of heterojunction bipolar transistor structures according to embodiments of the present utility model.

Detailed Description

As described in the background, there are still a number of problems with heterojunction bipolar transistor structures. The following will make a detailed description with reference to the accompanying drawings.

Fig. 1 to 3 are schematic structural diagrams of a heterojunction bipolar transistor structure.

Referring to fig. 1 to 3, fig. 2 is a schematic cross-sectional view taken along line A-A in fig. 1, and fig. 3 is a schematic cross-sectional view taken along line B-B in fig. 1, a heterojunction bipolar transistor structure comprising: a substrate 100; a current collecting layer 101 located on the substrate 100, a base layer 102 located on the current collecting layer 101, and a plurality of emission layers 103 located on the base layer 102, wherein the emission layers 103 are arranged in parallel along a first direction X; an emitter electrode 104 on the emitter layer 103; a first passivation layer 105 located on a part of the surface of the base layer 102, the surface of the emission layer 103 and a part of the surface of the emission electrode 104, the first passivation layer 105 exposing a part of the top surface of the emission electrode 104 and a part of the top surface of the base layer 102 between and at one side of adjacent emission layers 103; a base electrode 106, wherein the base electrode 106 includes an end portion 106b, a plurality of finger portions 106a, and a plurality of connection portions 106c, the plurality of finger portions 106a are connected to the end portion 106b through the plurality of connection portions 106c, and the plurality of finger portions 106a are respectively electrically connected to the exposed base layer 102, and the end portion 106b and the connection portions 103c are located on the base layer 102 and are electrically connected to the base layer 102; a plurality of collector electrodes 107 located on the collector layer 101, the collector electrodes 107 being electrically connected to the collector layer 101.

In this embodiment, since the end portion of the base electrode 106 is located on the base layer 102, the base layer 102 requires a larger area for the end portion of the base electrode 106 to be placed. However, when the area of the base layer 102 is large, the contact area between the base layer 102 and the collector layer 101 is increased. Since the electrical types of the ions doped in the base layer 102 and the ions doped in the collector layer 101 are opposite, when the contact area between the base layer 102 and the collector layer 101 is large, a PN junction with a large area is formed on the contact surface of the base layer 102 and the collector layer 101. When the device structure works, a space charge region is formed in the middle of the PN junction, the P electrode and the N electrode are equivalent to the two electrodes, and when the PN junction is larger in area, the parasitic capacitance correspondingly formed is larger, so that the performance of the device structure is affected. In addition, the base layer 102 additionally provides a region where the end portion 106b of the base electrode 106 is placed does not contribute to current, so that the utilization efficiency of the device is low.

On the basis, the utility model provides a heterojunction bipolar transistor structure, the end part of the base electrode is positioned on the isolation region in the edge part, the base layer does not need to provide a placement position for the end part of the base electrode, the area of the base layer can be effectively reduced, and then the PN junction area formed between the base layer and the current collecting layer is reduced, so that parasitic capacitance formed between the base layer and the current collecting layer is reduced when the device structure works, the radio frequency gain and the cut-off frequency of the device structure are improved, and the performance of the device structure is improved. The base layer is provided with the base electrode, and the base electrode is provided with the end part which is placed and cannot contribute current, so that the utilization efficiency of the device structure can be effectively improved. In addition, the isolation region not only can effectively prevent the device structure from being electrically connected with the device structures in other areas in series, but also can be used for electrically isolating the connection part and the end part of the base electrode in the device structure from being respectively connected with the current collecting layer, so that an insulating layer for electrical isolation is prevented from being additionally formed, the device structure is simpler, and the manufacturing cost is effectively reduced.

In order that the above-recited objects, features and advantages of the present utility model will become more readily apparent, a more particular description of the utility model briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

Fig. 4 to 20 are schematic structural diagrams illustrating steps of a method for forming a heterojunction bipolar transistor structure according to an embodiment of the utility model.

Referring to fig. 4, a substrate is provided, and includes a base 200, an initial collector layer 209 on the base 200, an initial base layer 202 on the initial collector layer 209, and an initial emission layer 203 on the initial base layer 202.

In this embodiment, the material of the substrate 200 is silicon.

In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material of group III-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the III-group element multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.

Referring to fig. 5 and 6, fig. 6 is a schematic cross-sectional view taken along line A-A in fig. 5, a plurality of emitter electrodes 204 are formed on the initial emitter layer 203, the plurality of emitter electrodes 204 cover a portion of the top surface of the initial emitter layer 203, and the plurality of emitter electrodes 204 are arranged in parallel along a second direction Y, and the second direction Y is parallel to the surface of the substrate 200.

In this embodiment, the method for forming the plurality of emitter electrodes 204 on the initial emitter layer 203 includes: forming a first photoresist layer (not shown) on the initial emission layer 203, the first photoresist layer exposing a portion of a top surface of the initial emission layer 203; forming a transmitting electrode material layer (not shown) on the exposed top surface of the initial transmitting layer 203 and the surface of the first photoresist layer by using an evaporation process; and removing the emitter electrode material layer on the first photoresist layer and the first photoresist layer by adopting a stripping process to form a plurality of emitter electrodes 204.

In this embodiment, the emitter electrode 204 is in ohmic contact with the initial emitter layer 203.

In this embodiment, the emitter electrode 204 has a multi-layered metal structure, and the emitter electrode 205 is a multi-layered metal layer formed by stacking a titanium (Ti) film, a platinum (Pt) film, and a titanium (Ti) film in this order.

In other embodiments, the emitter electrode may also be a single layer metal structure.

Referring to fig. 7, the view directions of fig. 7 and fig. 6 are consistent, the initial emission layer 203 is etched with the emission electrodes 204 as masks until the top surface of the initial base layer 202 is exposed, so that the initial emission layer 203 forms emission layers 205.

In this embodiment, the initial emission layer 203 is etched using a dry etching process.

In this embodiment, the process parameters of the dry etching process include: the etching gas includes: chlorine gas; the flow rate of the etching gas is 10 sccm-500 sccm: when the flow rate of the etching gas is greater than 500sccm, the etching rate is too fast, and the etching gas is easy to etch to the initial base layer 202 below the initial emission layer 203, so that the device is invalid; when the etching gas is less than 10sccm, the material at the bottom of the initial emission layer 203 is easy to be etched, so that electrons are accumulated, and the reliability of the device is disabled due to heat generation.

By etching the initial emitter layer 203 with the emitter electrode 204 as a mask, the size of the emitter layer 205 formed is the same as the size of the emitter electrode 204, so that the electrical conductivity and thermal conductivity between the emitter layer 205 and the emitter electrode 204 can be effectively improved, and the performance of the device structure can be further improved.

Referring to fig. 8, a first passivation material layer 206 is formed on the surfaces of the initial base layer 202, the emission layers 205, and the emission electrodes 204.

In this embodiment, the material of the first passivation material layer 206 is silicon nitride.

In this embodiment, the first passivation layer 206 is formed by a plasma enhanced chemical vapor deposition process.

Referring to fig. 9 and 10, fig. 10 is a schematic cross-sectional view taken along line B-B in fig. 9, a reserved area is selected on the initial base layer 202, a plurality of the emitter layers 205 and a plurality of the emitter electrodes 204 are located in the reserved area, and a first mask layer 207 is formed on the first passivation material layer 206 located in the reserved area, and the first mask layer 207 covers the first passivation material layer 206 located in the reserved area.

In this embodiment, the end of the base electrode does not need to be placed on the base layer, so the remaining area may be selected to be consistent with or slightly larger than the overall contour surrounded by the emission layers 205.

Referring to fig. 11, the view directions of fig. 11 and fig. 10 are identical, and the first mask layer 207 is used as a mask to perform etching treatment on the initial base layer 202, the initial collector layer 209 and the first passivation material layer 206, so as to form a base layer 208, a collector layer 209 and a first passivation layer 218 respectively.

In this embodiment, the collector layer 209 is doped with first ions; the base layer 208 is doped with a second ion, and the electrical type of the first ion is different from the electrical type of the second ion, and the doping concentration of the second ion is greater than the doping concentration of the first ion.

The emitter layer 205 is doped with a third ion, the third ion has a different electrical type from the second ion, the third ion has a same electrical type as the first ion, the third ion has a doping concentration greater than the first ion, and the third ion has a doping concentration less than the second ion.

In this embodiment, the collector layer 209 has a doping concentration of 1E16atoms/cm ³ N-type gallium arsenide (GaAs); the base layer 208 has a doping concentration of 1E19atoms/cm ³ P-type gallium arsenide of (a); the emitter layer 205 has a doping concentration of 1E17atoms/cm ³ N-type gallium arsenide of (c).

In the present embodiment, the current collecting layer 209 includes an edge portion 209a, a side wall portion 209b, and a main body portion 209c that are arranged and adjoined in the first direction X, the side wall portion 209b being located between the edge portion 209a and the main body portion 209 c.

With continued reference to fig. 11, in this embodiment, after the base layer 208 and the collector layer 209 are formed, the first mask layer 207 is removed.

Referring to fig. 12, an isolation region 210 is formed in the collector layer 209.

In this embodiment, the isolation region 210 is formed in the edge portion 209a, the sidewall portion 209b, and a part of the main body portion 209c, and the isolation region 210 has isolation particles therein.

In this embodiment, the method for forming the isolation region 210 in the collector layer 209 includes: selecting a functional region on the collector layer 209, within which the base layer 208, the plurality of emission layers 205, and the plurality of emission electrodes 204 are located; forming a second mask layer (not shown) on the functional region, the second mask layer covering a portion of the collector layer 209, the plurality of emission layers 205, and the plurality of emission electrodes 204; and performing particle implantation treatment on the exposed collector layer 209 by using the second mask layer as a mask, and forming the isolation region 210 in the collector layer 209.

In this embodiment, the particles include: hydrogen ions, helium ions or argon ions.

In this embodiment, the isolation region 210 formed in the edge portion 209a and part of the main body portion 209c can effectively prevent the formed device structure from being electrically connected in series with the device structure in other regions, and the isolation region 210 formed in the sidewall portion 209b is used to prevent the base electrode formed subsequently from being shorted with the main body portion 209 c.

Referring to fig. 13-14, fig. 14 is a schematic cross-sectional view taken along line C-C in fig. 13, wherein the first passivation layer 218 is etched to expose a portion of the top surface of the base layer 208 between adjacent ones of the emitter layers 205.

In this embodiment, the method for etching the first passivation layer 218 includes: forming a third mask layer (not shown) on the first passivation layer 218, the third mask layer exposing a portion of a top surface of the first passivation layer 218; the first passivation layer 218 is etched using the third mask layer as a mask until the top surface of the base layer 208 between adjacent ones of the emitter layers 205 is exposed.

Referring to fig. 15 to 16, fig. 16 is a schematic cross-sectional view taken along line D-D in fig. 15, a base electrode 211 is formed, the base electrode 211 includes an end portion 211a, a plurality of finger portions 211b and a plurality of connection portions 211c, the plurality of finger portions 211b are connected to the end portion 211a through the plurality of connection portions 211c, the plurality of finger portions 211b are respectively electrically connected to the exposed base layer 208, the connection portions 211c are formed on the isolation regions 210 in the sidewall portions 209b, the main portion 209c and the connection portions 211c are respectively formed on both sides of the isolation regions 210 in the sidewall portions 209b, and the end portion 211a is formed on the isolation regions 210 in the edge portions 209 a.

In this embodiment, the end portion 211a of the base electrode 211 is formed on the isolation region 210 in the edge portion 209a, the base layer 208 does not need to provide a placement position for the end portion 211a of the base electrode 211, so that the area of the base layer 208 can be effectively reduced, and further the area of the PN junction formed between the base layer 208 and the collector layer 209 is reduced, so that when the device structure works, the parasitic capacitance formed between the base layer 208 and the collector layer 209 is reduced, and thus the radio frequency gain (i.e. the current amplification factor) and the cut-off frequency (the special frequency for explaining the frequency characteristic index of the circuit, i.e. the corresponding frequency when the amplitude of the input signal of the circuit is kept unchanged and the frequency is changed to reduce the output signal to 0.707 times the maximum value or a certain special rated value, which is called the cut-off frequency) of the device structure are improved. Since the portion of the base layer 208 that provides a place for the end portion 211a of the base electrode 211 and is not capable of contributing current is removed, the utilization efficiency of the device structure can be effectively improved. In addition, the isolation region 210 not only can effectively prevent the device structure from being electrically connected with the device structures in other regions in series, but also can be used for electrically isolating the connection portion 211c and the end portion 211a of the base electrode 211 from the collector layer 209 in the device structure itself, so as to avoid forming an insulating layer for electrical isolation additionally, and make the device structure more concise and reduce the manufacturing cost effectively.

In this embodiment, the base electrode 211 is in ohmic contact with the base layer 208.

In this embodiment, the base electrode 211 has a multi-layered metal structure, and the base electrode 211 is a multi-layered metal layer in which a platinum (Pt) film, a titanium (Ti) film, a Pt film, and a gold (Au) film are sequentially stacked.

In other embodiments, the base electrode may also be a single layer metal structure.

Referring to fig. 17, the view directions of fig. 17 and 15 are identical, a plurality of collector electrodes 212 are formed on the exposed collector layer 209, and the collector electrodes 212 are electrically connected to the collector layer 209.

In this embodiment, the collector 212 and the collector layer 209 are in ohmic contact.

In this embodiment, the collector 212 has a multi-layered metal structure, and the collector 212 is a multi-layered metal layer in which a titanium (Ti) film and a gold (Au) film are sequentially stacked.

In other embodiments, the collector electrode may also be a single-layer metal structure.

In the present embodiment, an emission layer structure in the HBT is constituted by the emission layer 205 and the emission electrode 206; a base layer structure in the HBT is formed by the base layer 208 and the base electrode 211; the collector layer 209 and the collector 212 form a collector layer structure in the HBT.

Referring to fig. 18 to 20, fig. 19 is a schematic cross-sectional view taken along line E-E in fig. 18, and fig. 20 is a schematic cross-sectional view taken along line F-F in fig. 18, a second passivation material layer (not shown) is formed on the surface of the first passivation layer 218, the surface of the collector layer 209, the surface of the base electrode 211, and the surface of the collector electrode 212; etching the second passivation material layer until a portion of the top surface of the end portion 211a of the base electrode 211, a portion of the top surface of the collector electrode 212, and a portion of the surface of the first passivation layer 218 are exposed, forming a second passivation layer 213; etching the first passivation layer 218 exposed by the second passivation layer 213 until a portion of the top surface of the emitter electrode is exposed; an interconnection metal layer 214 is formed, and the interconnection metal layer 214 is electrically connected to the exposed surface of the emitter electrode 204, the exposed surface of the end portion 211a of the base electrode 211, and the exposed surface of the collector electrode 212, respectively.

In this embodiment, the material of the second passivation layer 213 is silicon nitride.

In this embodiment, forming the interconnect metal layer 214 includes: a first interconnect 215, a second interconnect 216, and a third interconnect 217 are formed separately from each other, the first interconnect 215 being electrically connected to the exposed surface of the emitter electrode 204, the second interconnect 216 being electrically connected to the exposed surface of the end portion 211a of the base electrode 211, and the third interconnect 217 being electrically connected to the exposed surface of the collector electrode 212.

Accordingly, in an embodiment of the present utility model, a heterojunction bipolar transistor structure is further provided, please continue to refer to fig. 18 to 20, which includes: a substrate 200; a current collecting layer 209 on the substrate 200, the current collecting layer 209 including an edge portion 209a, a side wall portion 209b, and a main body portion 209c arranged and abutted along a first direction X, the side wall portion 209b being located between the edge portion 209a and the main body portion 209c, the first direction X being parallel to the surface of the substrate 200; a base layer 208 on the main body portion 209 c; the emission layers 205 are disposed on the base layer 208, the emission layers 205 are arranged in parallel along a second direction Y, the second direction Y is parallel to the surface of the substrate 200, and the first direction X is perpendicular to the second direction Y; an emitter electrode 204 located on the emitter layer 205; a first passivation layer 218 located on a portion of the surface of the base layer 208, the surface of the emitter layer 205, and a portion of the surface of the emitter electrode 204, the first passivation layer 218 exposing a portion of the top surface of the emitter electrode 204, and a portion of the top surface of the base layer 208 between adjacent ones of the emitter layers 205; an isolation region 210 located within the edge portion 209a and the sidewall portion 209b, the isolation region 210 having isolation particles therein; a base electrode 211, wherein the base electrode 211 comprises an end 211a, a plurality of finger parts 211b and a plurality of connecting parts 211c, the plurality of finger parts 211b are connected with the end 211a through the plurality of connecting parts 211c, the plurality of finger parts 211b are respectively electrically connected with the exposed base layer 208, the connecting parts 211c are positioned on the isolation region 210 in the side wall part 209b, the main body part 209c and the connecting parts 211c are respectively positioned on two sides of the isolation region 210 in the side wall part 209b, and the end 211a is positioned on the isolation region 210 in the edge part 209 a; a collector 212 located on the collector layer 209 along the second direction Y, the collector 212 being electrically connected to the collector layer 209.

In this embodiment, the end portion 211a of the base electrode 211 is located on the isolation region 210 in the edge portion 209a, the base layer 208 does not need to provide a placement position for the end portion 211a of the base electrode 211, so that the area of the base layer 208 can be effectively reduced, and the area of the PN junction formed between the base layer 208 and the collector layer 209 is further reduced, so that when the device structure works, the parasitic capacitance formed between the base layer 208 and the collector layer 209 is reduced, thereby improving the radio frequency gain (i.e. current amplification factor) and the cut-off frequency (for describing the special frequency of the circuit frequency characteristic index, i.e. the frequency corresponding to when the amplitude of the input signal of the circuit is kept unchanged and the frequency is changed to reduce the output signal to 0.707 times the maximum value or a certain special rated value is referred to as the cut-off frequency), and improving the performance of the device structure. Since the portion of the base layer 208 that provides a place for the end portion 211a of the base electrode 211 and is not capable of contributing current is removed, the utilization efficiency of the device structure can be effectively improved. In addition, the isolation region 210 not only can effectively prevent the device structure from being electrically connected with the device structures in other regions in series, but also can be used for electrically isolating the connection portion 211c and the end portion 211a of the base electrode 211 from the collector electrode 209 in the device structure itself, so as to avoid forming an insulating layer for electrical isolation, and make the device structure more concise and reduce the manufacturing cost effectively.

In this embodiment, the material of the substrate 200 is silicon.

In this embodiment, the emitter electrode 204 is in ohmic contact with the emitter layer 205.

In this embodiment, the emitter electrode 204 has a multi-layered metal structure, and the emitter electrode is a multi-layered metal layer of a titanium (Ti) film, a platinum (Pt) film, and a titanium (Ti) film, which are stacked in this order.

In other embodiments, the collector may also be a single layer metal structure.

In the present embodiment, an emission layer structure in the HBT is constituted by the emission layer 205 and the emission electrode 204; a base layer structure in the HBT is formed by the base layer 208 and the base electrode 211; the collector layer 209 and the collector 212 form a collector layer structure in the HBT.

In this embodiment, the material of the first passivation layer 218 is silicon nitride.

In this embodiment, the collector layer 209 is doped with first ions; the base layer 208 is doped with a second ion, and the electrical type of the first ion is different from the electrical type of the second ion, and the doping concentration of the second ion is greater than the doping concentration of the first ion; the emitter layer 205 is doped with a third ion, the third ion has a different electrical type from the second ion, the third ion has a same electrical type as the first ion, the third ion has a doping concentration greater than the first ion, and the third ion has a doping concentration less than the second ion.

Specifically, the collector layer 209 has a doping concentration of 1E16atoms/cm ³ N-type gallium arsenide (GaAs); the base layer 208 has a doping concentration of 1E19atoms/cm ³ P-type gallium arsenide of (a); the emitter layer 205 has a doping concentration of 1E17atoms/cm ³ N-type gallium arsenide of (c).

In this embodiment, the isolation particles in the isolation region 210 include: hydrogen ions, helium ions or argon ions.

In this embodiment, the isolation region 210 is also located within a portion of the body portion 209 c.

With continued reference to fig. 4 to 6, in this embodiment, the method further includes: and a second passivation layer 213 positioned on the surface of the first passivation layer 218, the surface of the collector layer 209, a partial surface of the base electrode 211, and a partial surface of the collector electrode 212, and the second passivation layer 213 exposes a partial top surface of the end portion 211a of the base electrode 211, and a partial top surface of the collector electrode 212.

With continued reference to fig. 4 to 6, in this embodiment, the method further includes: an interconnection metal layer 214, the interconnection metal layer 214 being electrically connected to the exposed surface of the emitter electrode 204, the exposed surface of the end portion 211a of the base electrode 211, and the exposed surface of the collector electrode 212, respectively.

In this embodiment, the interconnect metal layer 214 includes a first interconnect 215, a second interconnect 216, and a third interconnect 217 that are separated from each other, the first interconnect 215 being electrically connected to the exposed surface of the emitter electrode 204, the second interconnect 216 being electrically connected to the exposed surface of the end portion 211a of the base electrode 211, and the third interconnect 217 being electrically connected to the exposed surface of the collector electrode 212.

Although the present utility model is disclosed above, the present utility model is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the utility model, and the scope of the utility model should be assessed accordingly to that of the appended claims.

Claims

1. A heterojunction bipolar transistor structure comprising:

a substrate;

a current collecting layer on the substrate, the current collecting layer including an edge portion, a side wall portion, and a main body portion arranged and abutted along a first direction, the side wall portion being located between the edge portion and the main body portion, the first direction being parallel to the substrate surface;

a base layer on the body portion;

the emission layers are arranged in parallel along a second direction, the second direction is parallel to the surface of the substrate, and the first direction is perpendicular to the second direction;

an emitter electrode on the emitter layer;

a first passivation layer on the base layer partial surface, the emission layer surface and the emission electrode partial surface, the first passivation layer exposing a partial top surface of the emission electrode and a partial top surface of the base layer between adjacent emission layers;

an isolation region within the edge portion and the sidewall portion, the isolation region having isolation particles therein; the base electrode comprises an end part, a plurality of finger parts and a plurality of connecting parts, wherein the finger parts are connected with the end part through the connecting parts and are respectively and electrically connected with the exposed base layer, the connecting parts are positioned on the isolation areas in the side wall parts, the main body parts and the connecting parts are respectively positioned on two sides of the isolation areas in the side wall parts, and the end part is positioned on the isolation areas in the edge parts;

and a collector electrode positioned on the collector layer along the second direction, wherein the collector electrode is electrically connected with the collector layer.

2. The heterojunction bipolar transistor structure of claim 1 wherein said isolation region is further located within a portion of said body portion.

3. The heterojunction bipolar transistor structure of claim 1 wherein said emitter electrode is of a single-layer metal structure or a multi-layer metal structure.

4. The heterojunction bipolar transistor structure of claim 1 further comprising: and a second passivation layer positioned on a surface of the first passivation layer, a surface of the collector layer, a partial surface of the base electrode, and a partial surface of the collector electrode, and exposing a partial top surface of the end portion of the base electrode, and a partial top surface of the collector electrode.

5. The heterojunction bipolar transistor structure of claim 4 further comprising: and an interconnection metal layer electrically connected to the exposed surface of the emitter electrode, the exposed surface of the end portion of the base electrode, and the exposed surface of the collector electrode, respectively.

6. The heterojunction bipolar transistor structure of claim 5 wherein said interconnect metal layer comprises a first interconnect, a second interconnect and a third interconnect that are discrete from each other, said first interconnect being electrically connected to a surface of said exposed emitter electrode, said second interconnect being electrically connected to a surface of said exposed end portion of said base electrode, and said third interconnect being electrically connected to a surface of said exposed collector electrode.

7. The heterojunction bipolar transistor structure of claim 1 wherein said collector layer is doped with first ions; the base layer is doped with second ions, the electrical type of the first ions is different from that of the second ions, and the doping concentration of the second ions is larger than that of the first ions.

8. The heterojunction bipolar transistor structure of claim 7 wherein a third ion is doped within said emitter layer, said third ion having a different electrical type than said second ion, said third ion having a same electrical type as said first ion, said third ion having a doping concentration greater than a doping concentration of said first ion, and said third ion having a doping concentration less than a doping concentration of said second ion.