CN117594644B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN117594644B CN117594644B CN202410076508.3A CN202410076508A CN117594644B CN 117594644 B CN117594644 B CN 117594644B CN 202410076508 A CN202410076508 A CN 202410076508A CN 117594644 B CN117594644 B CN 117594644B
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3738—Semiconductor materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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Abstract
A semiconductor device and a method of forming the same, the structure comprising: a first substrate having opposite first and second sides; a transistor bonded to the first side, the transistor comprising: the current collecting layer is provided with a first side and a second side which are opposite, the base layer and the emission layer are positioned on the first side, the blocking layer is positioned on the second side, the first substrate is positioned on the first side, the base layer and the emission layer are positioned between the first substrate and the current collecting layer, the material of the blocking layer is different from the material of the current collecting layer, the blocking layer is used for protecting the current collecting layer, and the material of the current collecting layer, the material of the base layer and the material of the emission layer are different from the material of the first substrate. The blocking layer protects the collector layer from being damaged, and the transistor is transferred to the first substrate, so that the heat dissipation performance of the semiconductor device is improved; the transistor is inverted on the first substrate, so that the heat dissipation performance of the semiconductor device is further improved.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
The radio frequency front end is one of core devices in the smart phone and mainly comprises four modules: power amplifiers, switches, filters, and low noise amplifiers. The power amplifier is classified into a bipolar junction transistor (Bipolar Junction Transistor, BJT), a heterojunction bipolar transistor (heteroj ection BipolarTransistor, HBT), and a high electron mobility transistor (High Electron Mobility Transistor, HEMT) according to the transistor type. The heterojunction bipolar transistor is a bipolar junction transistor, and the emitter region and the base region have two different semiconductor materials with different energy bandgaps. Heterojunction bipolar transistors are widely used in industry due to their low base resistance, high cut-off frequency, high efficiency, large design flexibility, low cost, and the like.
However, the current heterojunction bipolar transistor structure still has a number of problems.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the heat dissipation performance and the integration level of a heterojunction bipolar transistor structure.
In order to solve the above technical problems, the present invention provides a semiconductor device, including: a first substrate having opposite first and second sides; a transistor bonded to the first side, the transistor comprising: the current collecting layer is provided with a first side and a second side which are opposite, the base layer and the emission layer are positioned on the first side, the blocking layer is positioned on the second side, the first substrate is positioned on the first side, the base layer and the emission layer are positioned between the first substrate and the current collecting layer, the material of the blocking layer is different from the material of the current collecting layer, the blocking layer is used for protecting the current collecting layer, and the material of the current collecting layer, the material of the base layer and the material of the emission layer are different from the material of the first substrate.
Optionally, the barrier layer material includes intrinsic state gallium indium phosphide or intrinsic state gallium aluminum arsenide.
Optionally, the thermal conductivity of the first base material is greater than the thermal conductivity of the current collector material, the base material, and the emissive layer material.
Optionally, the material of the first substrate includes silicon, gallium nitride or silicon carbide; the material of the current collecting layer comprises gallium arsenide; the material of the base layer comprises gallium arsenide; the material of the emission layer comprises gallium arsenide or gallium indium arsenide.
Optionally, the method further comprises: a collector electrode positioned on the surface of the collector layer; a base electrode located on the surface of the base layer; and an emitter electrode positioned on the surface of the emitter layer.
Optionally, the method further comprises: and the first interconnection layer is positioned on the first side of the current collecting layer, penetrates through the first substrate and is electrically connected with the emitting electrode.
Optionally, the method further comprises: and the second interconnection layer is electrically connected with the base electrode and is positioned on the same side of the emission layer as the first interconnection layer.
Optionally, the method further comprises: and the second interconnection layer is electrically connected with the base electrode, and the second interconnection layer and the first interconnection layer are positioned on two sides of the emission layer.
Optionally, the method further comprises: and a third interconnect layer electrically connected to the collector electrode, the third interconnect layer being on the same side of the emitter layer as the first interconnect layer.
Optionally, the method further comprises: and the third interconnection layer is electrically connected with the collector electrode, and the third interconnection layer and the first interconnection layer are positioned on two sides of the emission layer.
Optionally, the second interconnect layer penetrates through the collector layer, and the semiconductor device further includes: an isolation layer located between the collector layer and the second interconnect layer; the material of the isolation layer comprises silicon nitride.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor device, which comprises the following steps: providing a first substrate, wherein the first substrate is provided with a first surface and a second surface which are opposite; providing a second substrate; forming a transistor on the second substrate, the transistor comprising: a barrier layer, a current collector layer, a base layer, and an emissive layer, the current collector layer having opposite first and second sides, the base layer and the emissive layer being on the first side, the barrier layer and the second substrate being on the second side; first bonding the transistor and the first substrate with a first side of the current collecting layer facing the first surface of the first substrate, the first substrate being located on the first side, the base layer and the emission layer being located between the first substrate and the current collecting layer; after the first bonding process, the second substrate is removed.
Optionally, the transistor further includes: an emitter electrode on the surface of the emitter layer, a base electrode on the surface of the base layer, and a collector electrode on the surface of the collector layer.
Optionally, the thermal conductivity of the first substrate is greater than the thermal conductivity of the second substrate; the material of the first substrate comprises silicon, gallium nitride or silicon carbide; the material of the second substrate comprises gallium arsenide.
Optionally, the method for removing the second substrate includes: turning over the structure after the first bonding treatment, and thinning the second substrate; and etching the thinned second substrate until the surface of the barrier layer is exposed.
Optionally, the etching treatment method comprises wet etching; the ratio of the etching rate of the second substrate material to the etching rate of the barrier layer material in the wet etching is 10:1-20:1.
Optionally, the first bonding process includes a bonding process, and the method further includes: forming a first bonding layer on the transistor; forming a second bonding layer on the first surface of the first substrate; the first bonding process bonds the first bonding layer to the second bonding layer.
Optionally, the material of the first bonding layer includes silicon oxide, silicon oxynitride or silicon nitride; the material of the second bonding layer comprises silicon oxide, silicon oxynitride or silicon nitride.
Optionally, the method further comprises: and forming a first interconnection layer penetrating through the first substrate on the first side of the current collection layer, wherein the first interconnection layer is electrically connected with the emission electrode.
Optionally, the method further comprises: and forming a second interconnection layer, wherein the second interconnection layer is electrically connected with the base electrode, and the second interconnection layer and the first interconnection layer are positioned on the same side of the emission layer.
Optionally, the method further comprises: and forming a second interconnection layer, wherein the second interconnection layer is electrically connected with the base electrode, and the second interconnection layer and the first interconnection layer are positioned on two sides of the emission layer.
Optionally, the second interconnect layer penetrates through the current collecting layer, and the method further includes: an isolation layer is formed between the collector layer and the second interconnect layer.
Optionally, the method further comprises: a third interconnect layer is formed, the third interconnect layer being electrically connected to the collector electrode, the third interconnect layer being on the same side of the emitter layer as the first interconnect layer.
Optionally, the method further comprises: and forming a third interconnection layer, wherein the third interconnection layer is electrically connected with the collector electrode, and the third interconnection layer and the first interconnection layer are positioned on two sides of the emission layer.
Optionally, the barrier layer material includes intrinsic state gallium indium phosphide or intrinsic state gallium aluminum arsenide.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
In the semiconductor device according to the technical scheme of the invention, on one hand, the blocking layer is positioned on the second side of the current collecting layer, the base layer and the emission layer are positioned on the first side of the current collecting layer, and the blocking layer can protect the current collecting layer from being damaged; on the other hand, the material of the first substrate is different from the material of the current collecting layer, the material of the base layer and the material of the emission layer, and the transistor can be selectively bonded on the material of the first substrate with larger heat conduction coefficient, so that the heat dissipation performance of the semiconductor device is greatly improved, the transistor is inverted on the first substrate, the emission layer is close to the first substrate, the heat dissipation performance of the semiconductor device is further improved, and in addition, the transistor, the low-noise amplifier, the filter and the switch can be integrated on the first substrate, and the integration level of the semiconductor radio frequency device is improved.
Further, the transistor structure further includes: and the first interconnection layer penetrates through the first substrate, and is electrically connected with the emission electrode. The first interconnection layer is electrically connected with the emission layer from the second surface of the first substrate and the emission layer is grounded, so that the heat dissipation effect of the emission layer and the first interconnection layer can be improved.
Further, the material of the first substrate comprises silicon, gallium nitride or silicon carbide; in the fabrication of transistors and passive devices, the materials used for the conductive layer include aluminum or copper. Aluminum and copper are used as conducting layer materials and cannot diffuse in the material of the first substrate, the cost of the copper and the aluminum is low, the thickness of the conducting layer can be adjusted according to production requirements, and the performance of the passive device is improved.
In the method for forming the semiconductor device according to the technical scheme of the invention, on one hand, a blocking layer is formed between the second substrate and the second side of the current collecting layer, the material of the blocking layer is different from that of the second substrate, the etching rate of the blocking layer is smaller than that of the second substrate, and when the second substrate is removed later, the blocking layer is used as an etching blocking layer in the process of etching the second substrate, so that the current collecting layer is prevented from being damaged, and the performance of the transistor device is further ensured; on the other hand, the transistor is transferred from the second substrate to the first substrate, the first substrate is made of a material with a larger heat conduction coefficient, so that the heat dissipation performance of the semiconductor device is greatly improved, the transistor is inverted on the first substrate, the emission layer is close to the first substrate, the heat dissipation performance of the semiconductor device is further improved, and in addition, the transistor, the low-noise amplifier, the filter and the switch can be integrated on the first substrate, and the integration level of the semiconductor radio-frequency device is improved; in still another aspect, after the transistor is formed on the second substrate, the transistor is transferred to the first substrate, so that the operability of a preparation process of the transistor is improved, the problem that the edge of the epitaxial layer for forming the transistor exceeds the first substrate after bonding transfer and cannot be etched to form the transistor after bonding transfer due to mismatching of the size of the first substrate and the size of the second substrate for forming the epitaxial layer of the transistor is avoided, the process selection is increased, and the transistor transfer method is suitable for transistor transfer between substrates with different sizes and wide in application range.
Further, the first interconnection layer penetrates through the first substrate, and the first interconnection layer is electrically connected with the emission electrode. The first interconnection layer is electrically connected with the emission layer from the second surface of the first substrate and the emission layer is grounded, so that the heat dissipation effect of the emission layer and the first interconnection layer can be improved.
Further, the material of the second substrate comprises gallium arsenide; the material of the first substrate comprises silicon, gallium nitride or silicon carbide; the material of the conductive layer comprises aluminum or copper. Aluminum and copper cannot diffuse in the material of the first substrate, the cost of the copper and the aluminum is low, the thickness of the conductive layer can be adjusted according to production requirements, and the performance of passive devices in the passive area is improved.
Drawings
Fig. 1 to 24 are schematic structural views of steps of a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 25 to 28 are schematic structural views illustrating steps of a method for forming a semiconductor device according to another embodiment of the present invention.
Detailed Description
As described in the background, the heterojunction bipolar transistor of the prior art still has a number of problems.
In an embodiment of a semiconductor device, a substrate is provided, the substrate material being gallium arsenide. A transistor is formed on the substrate, the material of the transistor including gallium arsenide. However, firstly, gallium arsenide has poor heat dissipation performance as a base material; secondly, the transistor is formed on the gallium arsenide substrate and cannot be integrated with the silicon-based device, so that the integration level of different modules in the semiconductor device is poor; and when the conductive layer is formed on the surface of the transistor, gold is used as a material of the conductive layer, so that the cost of the semiconductor device is increased.
On the basis, the technical scheme of the invention provides a semiconductor device and a forming method thereof, firstly, a blocking layer is formed between the second substrate and the first side of the current collecting layer, the material of the blocking layer is different from that of the second substrate, the etching rate of the blocking layer is smaller than that of the second substrate, and when the second substrate is removed later, the blocking layer is used as an etching blocking layer in the process of etching the second substrate, so that the current collecting layer is prevented from being damaged, and the performance of the transistor device is further ensured; secondly, transferring the transistor from the second substrate to the first substrate, wherein the heat conductivity coefficient of the first substrate is larger than that of the second substrate, so that the heat dissipation performance of the semiconductor device is greatly improved; and forming a first interconnection layer in the first substrate, wherein the first interconnection layer is electrically connected with the emission layer from the second surface of the first substrate and the emission layer is grounded, so that the heat dissipation effect of the emission layer and the first interconnection layer can be improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 24 are schematic structural views of a forming process of a semiconductor device according to an embodiment of the present invention.
Referring to fig. 1, a second substrate 100 is provided.
The material of the second substrate 100 includes gallium arsenide (GaAs).
The thickness of the second substrate 100 ranges from: 600 μm to 800 μm.
The thermal conductivity of the second substrate 100 material is: 45W/mk to 52W/mk.
The second substrate 100 provides the structural basis for forming transistors.
The subsequent transfer of the transistor from the second substrate 100 to the first substrate 112 may greatly enhance the heat dissipation performance of the semiconductor device.
Forming a transistor on the second substrate 100, the transistor including: a barrier layer 101, a current collecting layer 109, a base layer 108 and an emissive layer 106, the current collecting layer 109 having opposite first and second sides, the base layer 108 and the emissive layer 106 being located on the first side, the barrier layer 101 and the second substrate 100 being located on the second side. The transistor further includes: an emitter electrode 105 located on the surface of the emitter layer 106, a base electrode 107 located on the surface of the base layer 108, and a collector electrode 110 located on the surface of the collector layer 109. Please refer to fig. 2 to fig. 10 in detail.
Referring to fig. 2, a barrier layer 101 is formed on the second substrate 100.
The material of the blocking layer 101 is different from the material of the current collecting layer 109, the base layer 108, and the emission layer 106, which are formed later.
The material of the barrier layer 101 includes: intrinsic gallium indium phosphide (lnGaP) or intrinsic gallium aluminum arsenide (AlGaAs). Specifically, in this embodiment, the material of the blocking layer 101 is intrinsic gallium indium phosphide (ln 0.49Ga0.51 P).
The thickness range of the barrier layer 101 is as follows: 20nm to 0.5 μm.
The barrier layer 101 serves to protect the transistor from being damaged by removing the etch barrier layer 101 of the second substrate 100 as a subsequent etch.
The method of forming the barrier layer 101 includes chemical vapor deposition (MOCVD) and atomic layer deposition (MBE).
Referring to fig. 3, an initial current collecting layer 102, an initial base layer 103 on the surface of the initial current collecting layer 102, and an initial emission layer 104 on the surface of the initial base layer 103 are formed on the barrier layer 101.
The doping type of the initial collector layer 102 is opposite to the doping type of the initial base layer 103; the doping type of the initial base layer 103 is opposite to the doping type of the initial emission layer 104.
The material of the initial collector layer 102 includes gallium arsenide (GaAs).
The initial collector 102 provides a structural basis for the subsequent formation of collector 109.
The thermal conductivity of the initial collector layer 102 material is: 45W/mk to 52W/mk.
The thickness range of the initial collector layer 102 is: 1 μm to 1.5 μm.
The doping ions of the initial current collecting layer 102 are N-type doping, and the doping ion concentration of the initial current collecting layer 102 is 1.0×10 15atom/cm3 to 1.0×10 18atom/cm3.
The initial current collecting layer 102 includes a single layer structure or a multi-layer stack structure. Specifically, in this embodiment, the initial current collecting layer 102 is a multi-layer stacked structure, and the doping ion concentration of each layer of the initial current collecting layer 102 increases sequentially along the direction from the first side to the second side.
In this embodiment, the initial collector layer 102 has 4 layers, and the directions along the first side and the second side are respectively: an initial first collector layer (not shown), an initial second collector layer (not shown), an initial third collector layer (not shown), and an initial fourth collector layer (not shown).
The initial first current collector layer has a dopant ion concentration of 1.0x10 15atom/cm3.
The initial second current collector layer has a dopant ion concentration of 1.0×10 15atom/cm3 to 1.0×10 16atom/cm3.
The initial third current collector layer has a dopant ion concentration of 1.0×10 16atom/cm3 to 1.0×10 17atom/cm3.
The initial fourth current collector has a dopant ion concentration of 1.0×10 17atom/cm3 to 1.0×10 18atom/cm3.
The doping ion concentration of each layer of the initial current collecting layer 102 is sequentially increased along the direction from the first side to the second side, so that the width of a space charge region in the initial current collecting layer 102 is increased, and the carrier collecting efficiency is improved; meanwhile, the initial collector layer 102 gradually increases in conductivity along the direction from the first side to the second side, thereby improving the mobility of electrons and further improving the performance of the transistor.
In other embodiments, the dopant ion concentration of each layer of the initial collector layer is other values.
The material of the initial base layer 103 includes gallium arsenide (GaAs).
The initial base layer 103 provides a structural basis for the subsequent formation of the base layer 106.
The thermal conductivity of the initial base layer 103 material is: 45W/mk to 52W/mk.
The thickness range of the initial base layer 103 is as follows: 40 nm to 80 nm.
The doping ions of the initial base layer 103 are P-type doping, and the doping ion concentration of the initial base layer 103 is 1.0x10 19atom/cm3 to 5.5x10 19atom/cm3.
The initial base layer 103 includes a single layer structure or a multi-layer stack structure. Specifically, in this embodiment, the initial base layer 103 has a single-layer structure.
The materials of the initial emission layer 104 include: gallium arsenide (GaAs) or gallium indium arsenide (lnGaAs).
The initial emissive layer 104 provides a structural basis for the subsequent formation of the emissive layer 106.
The initial emission layer 104 material has a thermal conductivity of: 45W/mk to 52W/mk.
The thickness of the initial emission layer 104 ranges from: 0.2 μm to 0.3 μm.
The doping ions of the initial emission layer 104 are N-type doping, and the doping ion concentration of the initial emission layer 104 is 1.0×10 17atom/cm3 to 2.0×10 19atom/cm3.
The initial emission layer 104 includes a single layer structure or a multi-layer stack structure. Specifically, in this embodiment, the initial emission layer 104 is a multi-layer stacked structure, and the doping ion concentration of each layer of the initial emission layer 104 decreases in the direction from the first side to the second side.
In this embodiment, the initial emission layer 104 has 3 layers, and the directions along the first side and the second side are respectively: an initial first emissive layer (not shown), an initial second emissive layer (not shown), and an initial third emissive layer (not shown).
The doping ion concentration of the initial third emission layer is 1.0×10 17atom/cm3, and the material of the initial third emission layer is gallium arsenide (GaAs).
The doping ion concentration of the initial second emission layer is 1.0×10 19atom/cm3, and the material of the initial second emission layer is gallium arsenide (GaAs).
The doping ion concentration of the initial first emission layer is 2.0×10 19atom/cm3, and the material of the initial first emission layer is gallium indium arsenide (ln 0.6Ga0.4 As).
The initial emission layer 104 decreases in sequence along the direction from the first side to the second side, so that the space charge region width of the initial emission layer 104 is controlled not to be too large while increasing the number of emitted carriers, and the loss of carriers is reduced.
In other embodiments, the dopant ion concentration of each layer of the initial emissive layer may be other values.
Referring to fig. 4, an emitter electrode 105 is formed on the initial emitter layer 104.
Ohmic contact is made between the emitter 105 and the initial emitter layer 104.
In this embodiment, the emitter electrode 105 is a multilayer stack structure of titanium, platinum, and gold.
The method for forming the emitter 105 includes: metal deposition or metal sputtering.
In other embodiments, the emitter may also be a single metal structure.
Referring to fig. 5, the initial emission layer 104 (as shown in fig. 4) is etched until a portion of the surface of the initial base layer 103 is exposed, so as to form an emission layer 106.
The method for forming the emission layer 106 includes: forming a mask layer on the surface of the initial emission layer 104, wherein the mask layer exposes part of the surface of the initial emission layer 104; and etching the initial emission layer 104 by taking the mask layer as a mask until part of the surface of the initial base layer 103 is exposed, so as to form the emission layer 106.
The etching method comprises the following steps: wet etching and dry etching.
The materials of the emission layer 106 include: gallium arsenide (GaAs) or gallium indium arsenide (lnGaAs).
The thermal conductivity of the material of the emission layer 106 is: 45W/mk to 52W/mk.
The thickness of the emission layer 106 ranges from: 0.2 μm to 0.3 μm.
The doping ions of the emission layer 106 are N-type doping, and the doping ion concentration of the emission layer 106 is 1.0×10 17atom/cm3 to 2.0×10 19atom/cm3.
The emission layer 106 includes a single layer structure or a multi-layer stack structure. Specifically, in this embodiment, the emission layer 106 is a multi-layer stacked structure; the dopant ion concentration of each layer of the emission layer 106 decreases in sequence in the direction from the first side to the second side.
In this embodiment, the emitting layer 106 has 3 layers, and the directions along the first side and the second side are respectively: a first emissive layer (not shown), a second emissive layer (not shown), and a third emissive layer (not shown).
The doping ion concentration of the third emission layer is 1.0x10 17atom/cm3, and the material of the third emission layer is gallium arsenide (GaAs).
The doping ion concentration of the second emission layer is 1.0x10 19atom/cm3, and the material of the second emission layer is gallium arsenide (GaAs).
The doping ion concentration of the first emission layer is 2.0x10 19atom/cm3, and the material of the first emission layer is gallium indium arsenide (ln 0.6Ga0.4 As).
The emission layer 106 decreases in sequence along the direction from the first side to the second side, so that the space charge region width of the emission layer 106 is controlled not to be too large while increasing the number of emitted carriers, and the loss of carriers is reduced.
In other embodiments, the dopant ion concentration of each layer of the emissive layer may be other values.
Referring to fig. 6, a base electrode 107 is formed on the initial base layer 103.
Ohmic contact is provided between the base electrode 107 and the initial base layer 103.
In this embodiment, the base electrode 107 is a multilayer stack structure of titanium, platinum, and gold.
The method for forming the base electrode 107 includes: metal deposition or metal sputtering.
In other embodiments, the base electrode may also be a single layer metal structure.
Referring to fig. 7, the initial base layer 103 (as shown in fig. 6) is etched until a portion of the surface of the initial collector layer 102 is exposed, forming a base layer 108.
The method for forming the base layer 108 includes: forming a mask layer on the surface of the initial base layer 103, wherein the mask layer exposes part of the surface of the initial base layer 103; and etching the initial base layer 103 by taking the mask layer as a mask until part of the surface of the initial collector layer 102 is exposed, thereby forming the base layer 108.
The etching method comprises the following steps: wet etching and dry etching.
The material of the base layer 108 includes gallium arsenide (GaAs).
The thermal conductivity of the base layer 108 material is: 45W/mk to 52W/mk.
The thickness of the base layer 108 ranges from: 40 nm to 80 nm.
The doping ions of the base layer 108 are P-type doping, and the doping ion concentration of the base layer 108 is 1.0×10 19atom/cm3 to 5.5×10 19atom/cm3.
The base layer 108 includes a single layer structure or a multi-layer stacked structure. Specifically, in this embodiment, the base layer 108 has a single-layer structure.
Referring to fig. 8, after the base layer 108 is formed, the initial collector layer 102 (as shown in fig. 7) is etched to form a collector layer 109.
The method for forming the collector layer 109 includes: forming a mask layer on the surface of the initial current collecting layer 102, wherein the mask layer exposes part of the surface of the initial current collecting layer 102; and etching the initial collector layer 102 by taking the mask layer as a mask to form the collector layer 109, wherein the collector layer 109 is provided with an extraction region I and a device region II, and the surface of the device region II is higher than that of the extraction region I.
The extraction region I is used for forming a collector electrode 110 later; the base layer 108 is located over the device region II.
The initial current collecting layer 102 is a multi-layer stacked structure, and the concentration of the doping ions in each layer of the initial current collecting layer 102 increases in sequence along the direction from the first side to the second side. The initial collector layer 102 has a low doping concentration near the base layer 108, so that a space charge region, i.e., a non-conductive region, is easily formed, if the collector 110 is formed on the initial collector layer 102, the collector 110 will contact with the space charge region, and the collector 110 and the initial collector layer 102 cannot form ohmic contact; the initial collector layer 102 has a high doping concentration near the side of the barrier layer 101, and the initial collector layer 102 is etched, so that the formed collector layer 109 has a lead-out area I, and then the collector 110 is formed on the lead-out area I, so that the collector 110 contacts the area with the higher doping concentration of the collector layer 109, thereby ensuring the normal operation of the transistor.
The thickness of the lead-out area I is less than 0.8 μm.
The etching method comprises the following steps: wet etching and dry etching.
The material of the collector layer 109 includes gallium arsenide (GaAs).
The thermal conductivity of the collector layer 109 material is: 45W/mk to 52W/mk.
The thickness range of the device region II is as follows: 1 μm to 1.5 μm.
The doping ions of the collector layer 109 are N-type doping, and the doping ion concentration of the collector layer 109 is 1.0×10 15atom/cm3 to 1.0×10 18atom/cm3.
The collector layer 109 includes a single-layer structure or a multi-layer stack structure. Specifically, in this embodiment, the current collecting layer 109 is a multi-layer stacked structure, and the doping ion concentration of each layer of the current collecting layer 109 increases sequentially along the direction from the first side to the second side.
The doping type of the collector layer 109 is opposite to the doping type of the base layer 108; the doping type of the base layer 108 is opposite to the doping type of the emissive layer 106.
Referring to fig. 9 and 10, fig. 9 is a top view of fig. 10, fig. 10 is a cross-sectional view of fig. 9 along YY' direction, and after forming the collector layer 109, a collector 110 is formed on the extraction region I, and the collector 110 is located on a first side of the collector layer 109. The top view shows only emitter electrode 105, base electrode 107, and collector electrode 110.
The method for forming the collector 110 includes: metal deposition or metal sputtering.
In this embodiment, the collector 110 is a multi-layered stack structure of gold, nickel, and cerium.
In other embodiments, the collector may also be a single metal structure.
In other embodiments, the base electrode and the collector electrode may be formed after the transistor is transferred to the first substrate, the base electrode is formed on a surface of the base layer facing the collector layer, and the collector electrode is formed on the second side of the collector layer.
Referring to fig. 11, after the transistor is formed, a first passivation layer 111 is formed, and the first passivation layer 111 covers the collector layer 109, the base layer 108, the emitter layer 106, the emitter electrode 105, the base electrode 107, and the collector 110.
The material of the first passivation layer 111 includes at least one of silicon oxide, silicon oxynitride, and silicon nitride.
The first passivation layer 111 is formed by a plasma chemical vapor deposition process.
Referring to fig. 12, a first substrate 112 is provided, and the first substrate 112 has a first surface and a second surface opposite to each other.
The first substrate 112 includes a number of active regions IV and a number of inactive regions V. The transistor after the subsequent first bonding process is located on the active region IV.
The passive region V provides a structural basis for subsequent formation of passive devices.
The passive device includes: at least one of capacitance, inductance and resistance.
The transistor is transferred from the second substrate 100 to the first substrate 112, so that the transistor, the low noise amplifier, the radio frequency switch and the radio frequency filter are integrated on the first substrate 112, and the integration level of the semiconductor radio frequency device is improved.
The material of the first substrate 112 includes silicon, gallium nitride, or silicon carbide.
The thermal conductivity of the first substrate 112 material is: 149W/mk to 380W/mk.
The thermal conductivity of the material of the first substrate 112 is greater than the thermal conductivity of the material of the current collector layer 109, the material of the base layer 108, and the material of the emissive layer 106.
The thermal conductivity of the first substrate 112 material is greater than the thermal conductivity of the second substrate 100 material.
Transferring the transistor from the second substrate 100 to the first substrate 112 may greatly improve the heat dissipation performance of the semiconductor device, and the transistor is inverted on the first substrate 112, and the emission layer 106 is close to the first substrate 112, so as to further improve the heat dissipation performance of the semiconductor device.
The first side of the collector layer 109 is directed to a first side of the first substrate 112, the transistor is subjected to a first bonding process with the first substrate 112, the first substrate 112 is located on the first side, and the base layer 108 and the emitter layer 106 are located between the first substrate 112 and the collector layer 109. Please refer to fig. 13 to 15.
Referring to fig. 13, the view angle of fig. 13 is identical to that of fig. 11, and the first bonding process includes a bonding process to form a first bonding layer 113 on the transistor.
The material of the first bonding layer 113 includes silicon oxide, silicon oxynitride, or silicon nitride.
The thickness of the first bonding layer 113 ranges from: 2 μm to 4 μm.
The first bonding layer 113 is used to improve the bonding performance between the subsequent transistor and the material of the first substrate 112.
Specifically, in this embodiment, in order to improve the bonding performance between the transistor and the first substrate 112, a planarization treatment is required to be performed on the first bonding layer 113, and the planarized first bonding layer 113 covers at least 60nm or more of the top emission electrode 105.
The planarization method comprises the following steps: mechanical polishing, chemical polishing, fluid polishing, chemical mechanical polishing, and the like. In this embodiment, the planarization process is a mechanical polishing process.
In this embodiment, a first bonding layer 113 is formed on the surface of the first passivation layer 111.
In other embodiments, the transistor surface is not formed with a first passivation layer, and a first bonding layer is formed on the transistor surface, wherein the first bonding layer covers the collector layer, the base layer, the emitter electrode, the base electrode, and the collector surface.
Referring to fig. 14, a second bonding layer 114 is formed on the surface of the first substrate 112.
The material of the second bonding layer 114 includes silicon oxide, silicon oxynitride, or silicon nitride.
The thickness of the second bonding layer 114 is 50nm.
The second bonding layer 114 functions to: the bonding performance of the subsequent transistor and the first substrate 112 is improved.
Referring to fig. 15, the transistor and the first substrate 112 are subjected to a first bonding process, the first substrate 112 is located on the first side, and the base layer 108 and the emission layer 106 are located between the first substrate 112 and the collector layer 109.
The first bonding process bonds the first bonding layer 113 to the second bonding layer 114.
The parameters of the first bonding process include: bonding temperature is 200 ℃; bonding was performed for 20 hours.
The first bonding process aims at: the transistor is transferred onto the first substrate 112.
The transistor after the first bonding process is located on the active region IV.
The transistor is transferred to the first substrate 112 after the transistor is formed on the second substrate 100, so that the operability of the preparation process of the transistor is improved, the problem that the edge of the epitaxial layer for forming the transistor exceeds the first substrate 112 after bonding transfer and cannot be etched to form the transistor after bonding transfer due to the fact that the size of the first substrate 112 is not matched with the size of the second substrate 100 for forming the epitaxial layer of the transistor is avoided, the process selection is increased, and the transistor transfer method is suitable for transistor transfer between substrates with different sizes and wide in application range.
After the first bonding process is performed, the second substrate 100 is removed. The method of removing the second substrate 100 includes: turning over the structure after the first bonding treatment, and thinning the second substrate 100 from the second side to the first side; etching is performed on the thinned second substrate 100 until the surface of the barrier layer 101 is exposed. Please refer to fig. 16 to 17.
Referring to fig. 16, the structure after the first bonding process is inverted, and the second substrate 100 is thinned from the second side to the first side.
The thinning process aims at removing the second substrate 100.
The thinning processing method comprises the following steps: mechanical polishing, chemical polishing, fluid polishing, chemical mechanical polishing, and the like. Specifically, in this embodiment, the thinning process is a chemical mechanical polishing process. Unlike traditional mechanical polishing method, chemical mechanical polishing method has the combined chemical and mechanical effect to avoid the damage of the surface caused by mechanical polishing and the low polishing speed, poor surface flatness and polishing consistency caused by chemical polishing.
The thickness of the thinned second substrate 100 is 5 μm.
The collector layer 109 of the transistor is located on the base layer 108 and the emitter layer 106, improving the high frequency performance of the semiconductor device.
Referring to fig. 17, the thinned second substrate 100 is etched until the surface of the barrier layer 101 is exposed.
The etching process is aimed at removing the second substrate 100. The etching treatment method comprises wet etching; the ratio of the etching rate of the second substrate 100 material to the etching rate of the barrier layer 101 material in the wet etching is in the range of 10:1-20: 1.
During the etching to remove the second substrate 100, the barrier layer 101 acts as an etching stop layer, protecting the collector layer 109 from damage and thus protecting the transistor from wear.
After the transistor is formed on the second substrate 100, the transistor is transferred to the first substrate 112, so that the operability of a preparation process of the transistor is improved, the problem that the edge of the epitaxial layer for forming the transistor exceeds the first substrate 112 after bonding transfer and cannot be etched to form the transistor after bonding transfer due to mismatching of the size of the first substrate 112 and the size of the second substrate 100 for forming the epitaxial layer of the transistor is avoided, the process selection is increased, and the transistor transfer method is suitable for transistor transfer between substrates with different sizes and wide in application range.
The collector layer 109 has a plurality of isolation regions III therein, and the isolation regions III are used to isolate adjacent active regions IV.
Referring to fig. 18, the collector layer 109 of the isolation region III is etched to form an isolation opening 115.
The method for forming the isolation opening 115 includes: forming a mask layer (not shown) on the surface of the barrier layer 101, wherein the mask layer exposes a part of the surface of the barrier layer 101; and etching the barrier layer 101, the collector layer 109, the first bonding layer 113 and the second bonding layer 114 with the mask layer as a mask until the surface of the first substrate 112 is exposed, thereby forming the isolation opening 115.
The purpose of the isolation opening 115 is to: electrical crosstalk between active devices and passive devices, and between adjacent active devices, is avoided.
Referring to fig. 19 and 20, fig. 19 is a top view of fig. 20, and fig. 20 is a cross-sectional view taken along XX' of fig. 19, the top view showing only emitter electrode 105, base electrode 107, and collector electrode 110.
Fig. 21 to 24 are schematic cross-sectional views illustrating a process of forming an interconnect layer structure according to an embodiment of the present invention. The interconnect layer structure includes: the first interconnect layer 126, the second interconnect layer 118, and the third interconnect layer 119, the first interconnect layer 126 and the second interconnect layer 118 being located on both sides of the emission layer 106, the first interconnect layer 126 and the third interconnect layer 119 being located on both sides of the emission layer 106.
Referring to fig. 21 on the basis of fig. 20, a mask layer is formed on the surface of the barrier layer 101, the mask layer exposes a portion of the surface of the barrier layer 101, and the barrier layer 101, the collector layer 109 and the base layer 108 are etched until the surface of the base electrode 107 is exposed, so as to form a second opening 116; a mask layer is formed on the surface of the barrier layer 101, the mask layer exposes a portion of the surface of the barrier layer 101, and the barrier layer 101 and the collector layer 109 are etched until the surface of the collector 110 is exposed, so as to form a third opening 117.
In this embodiment, the second opening 116 provides a structural basis for the subsequent formation of a second interconnect layer 118.
In this embodiment, the third opening 117 provides a structural basis for the subsequent formation of a third interconnect layer 119.
In another embodiment, the barrier layer and the collector layer are etched until the surface of the base layer is exposed, forming a second opening; forming a base electrode on the surface of the base layer exposed by the second opening, wherein the base electrode is positioned on the surface of the base layer facing the current collecting layer; a second interconnect layer is formed over the base electrode.
A diffusion barrier layer is also provided between the second interconnect layer and the base electrode.
In another embodiment, the barrier layer is etched until the surface of the collector layer is exposed, forming a third opening; forming a collector electrode on the surface of the collector layer exposed by the third opening, wherein the collector electrode is positioned on the second side of the collector layer; a third interconnect layer is formed over the collector.
A diffusion barrier layer is also provided between the third interconnect layer and the collector electrode.
Referring to fig. 22, a second interconnection layer 118 is formed in the second opening 116, and the second interconnection layer 118 is electrically connected to the base electrode 107; a third interconnect layer 119 is formed within the third opening 117, the third interconnect layer 119 being electrically connected to the collector 110.
The second interconnect layer 118 and the third interconnect layer 119 are in a multi-layered metal structure.
The material of the second interconnect layer 118 includes aluminum or copper.
The material of the third interconnect layer 119 includes aluminum or copper.
A diffusion barrier layer (not shown) is also provided between the second interconnect layer 118 and the base electrode 107.
The diffusion barrier layer serves to separate the base electrode 107 from the second interconnect layer 118, preventing diffusion of material of the second interconnect layer 118 through the base electrode 107 to the base layer 108.
A diffusion barrier (not shown) is also provided between the third interconnect layer 119 and the collector 110.
The diffusion barrier layer serves to separate the collector 110 from the third interconnect layer 119, preventing diffusion of material of the third interconnect layer 119 through the collector 110 to the collector layer 109.
While forming the second interconnect layer 118 and the third interconnect layer 119, it further includes: forming an inactive device on the inactive region V; the passive device includes: at least one of capacitance, inductance and resistance.
In this embodiment, the passive device is a capacitor.
The method for forming the passive device comprises the following steps: forming a first metal layer 120 on the surface of the first substrate 112; forming a first dielectric layer 121 on the surface of the first metal layer 120 and the surface of the first substrate 112; forming a second metal layer 122 on the surface of the first dielectric layer 121; a second dielectric layer 123 is formed on the surface of the second metal layer 122.
The material of the first metal layer 120 includes aluminum or copper.
The material of the second metal layer 122 includes aluminum or copper.
When the first and second metal layers 120 and 122 are formed on the material of the second substrate 100, aluminum and copper are easily diffused in gallium arsenide (GaAs) if they are used as materials; if gold is used as the material of the first metal layer 120 and the second metal layer 122, the cost of the semiconductor device is increased. When the first metal layer 120 and the second metal layer 122 are formed on the material of the first substrate 112, aluminum and copper will not diffuse in the material of the first substrate 112, and copper and aluminum are low in cost, and the thicknesses of the first metal layer 120 and the second metal layer 122 can be adjusted according to production requirements, so that the performance of the passive devices on the passive region V is improved.
In this embodiment, the material of the first dielectric layer 121 includes silicon nitride; the material of the second dielectric layer 123 includes silicon nitride.
The thickness range of the first dielectric layer 121 is: 0.3-0.8 μm; the thickness range of the second dielectric layer 123 is: 0.3 μm to 0.8 μm.
In this embodiment, the second interconnect layer 118 and the third interconnect layer 119 are two-layer metal structures, and one of the two-layer metal structures is formed corresponding to and simultaneously with the first metal layer 120 and the second metal layer 122 in the passive device, respectively.
The first dielectric layer 121 is further formed in the active region IV, where the first dielectric layer 121 covers the transistor surface and exposes a portion of the surface of the underlying metal structure of the second interconnect layer 118 and a portion of the surface of the underlying metal structure of the third interconnect layer 119.
A second dielectric layer 123 is formed on the first dielectric layer 121 and covers the surface of the upper metal structure of the second interconnect layer 118 and the surface of the upper metal structure of the third interconnect layer 119.
The first dielectric layer 121 and the second dielectric layer 123 protect the device from contamination by the external environment and prevent intrusion of moisture.
In one embodiment, one of the two metal structures in the second interconnect layer 118 is formed corresponding to and simultaneously with the first metal layer 120 and the second metal layer 122, respectively, in a passive device.
In other embodiments, one of the two metal structures in the third interconnect layer 119 is formed corresponding to and simultaneously with the first metal layer 120 and the second metal layer 122, respectively, in the passive device.
In one embodiment, one of the two metal structures in the second interconnect layer 118 is electrically connected to either the first metal layer 120 or the second metal layer 122 in the passive device.
The second interconnection layer 118 of the active area IV is electrically connected to the first metal layer 120 or the second metal layer 122 of the passive device, so that the active device of the active area IV is electrically connected to the passive device of the passive area V, and the passive device can store energy to support the active device and filter the signal generated by the active device.
In other embodiments, one of the two metal structures in the third interconnect layer 119 is electrically connected to the first metal layer 120 or the second metal layer 122 in the passive device.
The third interconnection layer 119 of the active area IV is electrically connected to the first metal layer 120 or the second metal layer 122 of the passive device, so that the active device of the active area IV is electrically connected to the passive device of the passive area V, the energy stored by the passive device can support the active device, and the passive device filters the signal generated by the active device.
Before forming the second interconnect layer 118 and the third interconnect layer 119, after forming the second opening 116 and the third opening 117, further includes: and forming an isolation layer 124 on the surface of the collector layer 109 exposed by the second opening 116 and the surface of the collector layer 109 exposed by the third opening 117.
The material of the isolation layer 124 includes silicon nitride.
The thickness of the isolation layer 124 ranges from: 50 nm to 200 nm.
The function of the isolation layer 124 is to prevent a short circuit between the collector layer 109 and the base layer 108 during subsequent metal interconnection.
Referring to fig. 23, the first substrate 112, the second bonding layer 114, the first bonding layer 113 and the first passivation layer 111 are etched until the surface of the emitter electrode 105 is exposed, so as to form a first opening 125.
The first openings 125 provide a structural basis for the subsequent formation of a first interconnect layer 126.
Referring to fig. 24, a first interconnection layer 126 is formed in the first opening 125, and the first interconnection layer 126 is electrically connected to the emission layer 106.
The material of the first interconnect layer 126 includes aluminum or copper.
A diffusion barrier (not shown) is also provided between the first interconnect layer 126 and the emitter electrode 105.
The diffusion barrier layer is used to separate the emitter electrode 105 from the first interconnect layer 126, avoiding diffusion of material of the first interconnect layer 126 through the emitter electrode 105 to the emitter layer 106.
The first interconnection layer 126 is electrically connected to the emission layer 106 from the second surface of the first substrate 112 and the emission layer 106 is grounded, so that the heat dissipation effect between the emission layer 106 and the first interconnection layer 126 can be improved.
In another embodiment, the first substrate is etched until the surface of the emission layer is exposed, forming a first opening; forming a transmitting electrode on the surface of the first opening; a first interconnect layer is formed over the emitter electrode.
A diffusion barrier layer is also provided between the first interconnect layer and the emitter electrode.
Fig. 25 to 28 are schematic cross-sectional views illustrating a process of forming an interconnect layer structure according to another embodiment of the present invention. The interconnect layer structure includes: the first interconnect layer 226, the second interconnect layer 218, and the third interconnect layer 219 are located on the same side of the emission layer 106 as the first interconnect layer 226, the second interconnect layer 218, and the third interconnect layer 219.
Referring to fig. 25 on the basis of fig. 20, etching the first substrate 112, the second bonding layer 114, the first bonding layer 113 and the first passivation layer 111 until the surface of the base electrode 107 is exposed, and forming a second opening 216; the first substrate 112, the second bonding layer 114, the first bonding layer 113, and the first passivation layer 111 are etched until the surface of the collector electrode 110 is exposed, forming a third opening 217.
In this embodiment, the second opening 216 provides a structural basis for the subsequent formation of a second interconnect layer 218.
In this embodiment, the third opening 217 provides a structural basis for the subsequent formation of a third interconnect layer 219.
In another embodiment, the first substrate is etched until the surface of the base layer is exposed, and a second opening is formed; forming a base electrode on the surface of the second opening; a second interconnect layer is formed over the base electrode.
A diffusion barrier layer is also provided between the second interconnect layer and the base electrode.
In another embodiment, the first substrate is etched until the surface of the current collecting layer is exposed, and a third opening is formed; forming a collector electrode on the third opening surface; a third interconnect layer is formed over the collector.
A diffusion barrier layer is also provided between the third interconnect layer and the collector electrode.
Referring to fig. 26, a second interconnect layer 218 is formed in the second opening 216, and the second interconnect layer 218 is electrically connected to the base electrode 107; a third interconnect layer 219 is formed within the third opening 217, the third interconnect layer 219 being electrically connected to the collector 110.
The material of the second interconnect layer 218 includes aluminum or copper.
The material of the third interconnect layer 219 includes aluminum or copper.
A diffusion barrier layer (not shown) is also provided between the second interconnect layer 218 and the base electrode 107.
The diffusion barrier layer serves to separate the base electrode 107 from the second interconnect layer 218, preventing diffusion of material of the second interconnect layer 218 through the base electrode 107 to the base layer 108.
A diffusion barrier (not shown) is also provided between the third interconnect layer 219 and the collector 110.
The diffusion barrier layer serves to separate the collector 110 from the third interconnect layer 219, preventing diffusion of material of the third interconnect layer 219 through the collector 110 to the collector layer 109.
In the present embodiment, the second interconnect layer 218 and the third interconnect layer 219 are formed out of synchronization with the first metal layer 220 and the second metal layer 222 in the passive device.
In this embodiment, before forming the second opening 216, the third opening 217, the second interconnect layer 218, and the third interconnect layer 219, the method further includes: forming an inactive device on the inactive region V; the passive device includes: at least one of capacitance, inductance and resistance.
In this embodiment, the passive device is a capacitor.
The method for forming the passive device comprises the following steps: forming a first metal layer 220 on the surface of the first substrate 112; forming a first dielectric layer 221 on the surface of the first metal layer 220 and the surface of the first substrate 112; forming a second metal layer 222 on the surface of the first dielectric layer 221; a second dielectric layer 223 is formed on the surface of the second metal layer 222.
The material of the first metal layer 220 includes aluminum or copper.
The material of the second metal layer 222 includes aluminum or copper.
When the first and second metal layers 220 and 222 are formed on the material of the second substrate 100, aluminum and copper are easily diffused in gallium arsenide (GaAs) if they are used as materials; if gold is used as the material of the first metal layer 220 and the second metal layer 222, the cost of the semiconductor device is increased. When the first metal layer 220 and the second metal layer 222 are formed on the material of the first substrate 112, aluminum and copper will not diffuse in the material of the first substrate 112, and copper and aluminum are low in cost, and the thickness of the first metal layer 220 and the second metal layer 222 can be adjusted according to the production requirement, so that the performance of the passive device on the passive region V is improved.
In this embodiment, the material of the first dielectric layer 221 includes silicon nitride; the material of the second dielectric layer 223 includes silicon nitride.
The thickness range of the first dielectric layer 221 is: 0.3-0.8 μm; the thickness range of the second dielectric layer 223 is as follows: 0.3 μm to 0.8 μm.
Specifically, in this embodiment, the first dielectric layer 221 and the second dielectric layer 223 further cover the transistor surface, and are formed on the surface of the barrier layer 101 of the active area IV, the surface of the sidewall of the barrier layer 101, the surface of the sidewall of the collector layer 109, the surface of the sidewall of the first passivation layer 111, the surface of the sidewall of the first bonding layer 113, and the surface of the sidewall of the second bonding layer 114, so as to protect the device from being polluted by the external environment and prevent moisture from invading.
Referring to fig. 27, the first substrate 112, the second bonding layer 114, the first bonding layer 113 and the first passivation layer 111 are etched until the surface of the emitter electrode 105 is exposed, so as to form a first opening 225.
The first opening 225 provides a structural basis for the subsequent formation of a first interconnect layer 226.
Referring to fig. 28, a first interconnect layer 226 is formed in the first opening 225, and the first interconnect layer 226 is electrically connected to the emission layer 106.
The material of the first interconnect layer 226 includes aluminum or copper.
A diffusion barrier (not shown) is also provided between the first interconnect layer 226 and the emitter electrode 105.
The diffusion barrier layer serves to separate the emitter electrode 105 from the first interconnect layer 226, preventing diffusion of material of the first interconnect layer 226 through the emitter electrode 105 to the emitter layer 106.
In another embodiment, the first substrate is etched until the surface of the emission layer is exposed, forming a first opening; forming a transmitting electrode on the surface of the first opening; a first interconnect layer is formed over the emitter electrode.
A diffusion barrier layer is also provided between the first interconnect layer and the emitter electrode.
Accordingly, an embodiment of the present invention further provides a semiconductor device, please continue to refer to fig. 24, including: a first substrate 112, the first substrate 112 having a first surface and a second surface opposite to each other; a transistor bonded to the first side, the transistor comprising: a barrier layer 101, a current collecting layer 109, a base layer 108 and an emission layer 106, wherein the current collecting layer 109 has a first side and a second side opposite to each other, the base layer 108 and the emission layer 106 are positioned on the first side, the barrier layer 101 is positioned on the second side, the first substrate 112 is positioned on the first side, the base layer 108 and the emission layer 106 are positioned between the first substrate 112 and the current collecting layer 109, the material of the barrier layer 101 is different from the material of the current collecting layer 109, the material of the barrier layer 101 is used for protecting the current collecting layer 109, and the material of the current collecting layer 109, the material of the base layer 108 and the material of the emission layer 106 are different from the material of the first substrate 112.
The semiconductor device includes: a first substrate 112, said first substrate 112 comprising a number of active areas IV.
The first substrate 112 further includes a plurality of inactive regions V, and the surface of the inactive regions V has inactive devices.
The passive device includes: at least one of capacitance, inductance and resistance.
Specifically, in this embodiment, the passive device is a capacitor. The passive device includes: a first metal layer 120 located on the inactive region V of the first substrate 112; a first dielectric layer 121 located on the surface of the first metal layer 120 and the surface of the first substrate 112; the second metal layer 122 is positioned on the surface of the first dielectric layer 121; and a second dielectric layer 123 located on the surface of the second metal layer 122.
The material of the first metal layer 120 includes aluminum or copper.
The material of the second metal layer 122 includes aluminum or copper.
In this embodiment, the material of the first dielectric layer 121 includes silicon nitride; the material of the second dielectric layer 123 includes silicon nitride.
The thickness range of the first dielectric layer 121 is: 0.3-0.8 μm; the thickness range of the second dielectric layer 123 is: 0.3 μm to 0.8 μm.
Specifically, in this embodiment, the first dielectric layer 121 is further located in the active area IV, and covers the transistor surface and exposes a portion of the surface of the second interconnect layer 118 and a portion of the surface of the third interconnect layer 119, and specifically, the first dielectric layer 121 is located on a sidewall surface of the second bonding layer 114, a sidewall surface of the first bonding layer 113, a sidewall surface of the first passivation layer 111, a sidewall surface of the base layer 108, a sidewall surface of the collector layer 109, a sidewall surface of the barrier layer 101, a surface of the isolation layer 124 exposed by the second interconnect layer 118, a surface of the isolation layer 124 exposed by the third interconnect layer 119, a portion of the surface of the second interconnect layer 118, a portion of the sidewall surface of the third interconnect layer 119, and a sidewall surface of the isolation layer 124.
Specifically, in this embodiment, the second dielectric layer 123 is further located on the first dielectric layer 121 and covers the surface of the second interconnect layer 118 and the surface of the third interconnect layer 119, and specifically, the second dielectric layer 123 is located on the surface of the first dielectric layer 121 of the active area IV, the top surface of the second interconnect layer 118, a part of the sidewall surface of the second interconnect layer 118, the top surface of the third interconnect layer 119 and a part of the sidewall surface of the third interconnect layer 119.
The material of the first substrate 112 has a thermal conductivity greater than the thermal conductivity of the material of the current collector layer 109, the material of the base layer 108, and the material of the emissive layer 106.
The material of the first substrate 112 includes silicon, gallium nitride, or silicon carbide.
The thermal conductivity of the first substrate 112 material is: 149W/mk to 380W/mk.
The material of the collector layer 109 includes gallium arsenide (GaAs); the material of the base layer 108 includes gallium arsenide (GaAs); the material of the emission layer 106 includes gallium arsenide (GaAs) or gallium indium arsenide (lnGaAs).
The thermal conductivity of the collector layer 109 material is: 45W/mk-52W/mk; the thermal conductivity of the base layer 108 material is: 45W/mk-52W/mk; the thermal conductivity of the material of the emission layer 106 is: 45W/mk to 52W/mk.
The thickness of the collector layer 109 ranges from: 1 μm to 1.5 μm; the thickness of the base layer 108 ranges from: 40nm to 80nm; the thickness of the emission layer 106 ranges from: 0.2 μm to 0.3 μm.
The collector layer 109 includes a single-layer structure or a multi-layer stack structure. Specifically, in this embodiment, the current collecting layer 109 is a multi-layer stacked structure, and the doping ion concentration of each layer of the current collecting layer 109 increases sequentially along the direction from the first side to the second side.
In this embodiment, the current collecting layer 109 has 4 layers, and the directions along the first side and the second side are respectively: a first collector layer (not shown), a second collector layer (not shown), a third collector layer (not shown), and a fourth collector layer (not shown).
The first current collector layer has a dopant ion concentration of 1.0X10 15atom/cm3.
The second current collector layer has a dopant ion concentration of 1.0x10 15atom/cm3 to 1.0x10 16atom/cm3.
The third current collector layer has a dopant ion concentration of 1.0x10 16atom/cm3 to 1.0x10 17atom/cm3.
The fourth current collector has a dopant ion concentration of 1.0x10 17atom/cm3 to 1.0x10 18atom/cm3.
The doping ion concentration of each layer of the current collecting layer 109 is sequentially increased along the direction from the first side to the second side, so that the width of the space charge region in the current collecting layer 109 is increased, and the carrier collecting efficiency is improved; meanwhile, the conductivity of the collector layer 109 increases gradually along the direction from the first side to the second side, so that the mobility of electrons is improved, and the performance of the transistor is further improved.
In other embodiments, the dopant ion concentration of each layer of the current collector is other values.
The base layer 108 includes a single layer structure or a multi-layer stacked structure. Specifically, in this embodiment, the base layer 108 has a single-layer structure.
The emission layer 106 includes a single layer structure or a multi-layer stack structure. Specifically, in this embodiment, the emission layer 106 is a multi-layer stacked structure, and the doping ion concentration of each layer of the emission layer 106 decreases in the direction from the first side to the second side.
In this embodiment, the emitting layer 106 has 3 layers, and the directions along the first side and the second side are respectively: a first emissive layer (not shown), a second emissive layer (not shown), and a third emissive layer (not shown).
The doping ion concentration of the third emission layer is 1.0x10 17atom/cm3, and the material of the third emission layer is gallium arsenide (GaAs).
The doping ion concentration of the second emission layer is 1.0x10 19atom/cm3, and the material of the second emission layer is gallium arsenide (GaAs).
The doping ion concentration of the first emission layer is 2.0x10 19atom/cm3, and the material of the first emission layer is gallium indium arsenide (ln 0.6Ga0.4 As).
The emission layer 106 decreases in sequence along the direction from the first side to the second side, so that the space charge region width of the emission layer 106 is controlled not to be too large while increasing the number of emitted carriers, and the loss of carriers is reduced.
In other embodiments, the dopant ion concentration of each layer of the emissive layer may be other values.
The doping type of the collector layer 109 is opposite to the doping type of the base layer 108; the doping type of the base layer 108 is opposite to the doping type of the emissive layer 106.
The doping ions of the collector layer 109 are N-type doping, and the doping ion concentration of the collector layer 109 is 1.0×10 15atom/cm3 to 1.0×10 18atom/cm3; the doping ions of the base layer 108 are P-type doping, and the doping ion concentration of the base layer 108 is 1.0×10 19atom/cm3 to 5.5×10 19atom/cm3; the doping ions of the emission layer 106 are N-type doping, and the doping ion concentration of the emission layer 106 is 1.0×10 17atom/cm3 to 2.0×10 19atom/cm3.
The collector layer 109 has an extraction region I (shown in fig. 13) and a device region II (shown in fig. 13), the surface of the device region II is higher than the surface of the extraction region I, and the base layer 108 is located on the device region II.
The thickness of the lead-out area I is less than 0.8 μm.
The thickness range of the device region II is as follows: 1 μm to 1.5 μm.
The collector layer 109 has a plurality of isolation regions III therein, and the isolation regions III are used to isolate adjacent active regions IV.
The semiconductor device includes: a collector electrode 110 positioned on the surface of the extraction region I of the collector layer 109; a base electrode 107 located on a part of the surface of the base layer 108 remote from the collector layer 109; an emitter electrode 105 located on the surface of the emitter layer 106.
In other embodiments, the base electrode is located on a surface of the base layer facing the collector layer and the collector electrode is located on a second side of the collector layer.
The collector 110 is a multi-layered stack structure of gold, nickel and cerium; the base electrode 107 is a multilayer stack structure of titanium, platinum and gold; the emitter electrode 105 is a multilayer stack structure of titanium, platinum, and gold.
The transistor structure further includes: a first opening 125 (as shown in fig. 23), the first opening 125 penetrates through the first substrate 112, and the first opening 125 exposes the surface of the emitter electrode 105.
The transistor structure further includes: a first interconnect layer 126 located in the second side and the first opening 125, the first interconnect layer 126 being electrically connected to the emission layer 106.
The materials of the first interconnect layer 126 include: copper or aluminum.
The transistor structure further includes: a second opening 116 (shown in fig. 21), the second opening 116 exposing a surface of the base electrode 107, the second opening 116 penetrating the collector layer 109 and the base layer 108.
In other embodiments, the second opening penetrates through the current collecting layer and exposes a surface of the base layer, and the base electrode is located on a surface of the base layer facing the current collecting layer.
The transistor structure further includes: and a second interconnect layer 118 located within the second opening 116, the second interconnect layer 118 being electrically connected to the base electrode 107.
The second interconnect layer 118 is a multi-layer metal structure.
In this embodiment, the second interconnection layer 118 is a two-layer metal structure, and one of the two-layer metal structures corresponds to the first metal layer 120 and the second metal layer 122 in the passive device, respectively.
In one embodiment, one of the two metal structures in the second interconnect layer 118 is electrically connected to either the first metal layer 120 or the second metal layer 122 in the passive device.
The materials of the second interconnect layer 118 include: copper or aluminum.
The transistor structure further includes: a third opening 117 (as shown in fig. 21), the third opening 117 exposing a surface of the collector 110, the third opening 117 penetrating the collector layer 109.
In other embodiments, the third opening exposes a portion of the surface of the collector layer, and the collector is located on the second side surface of the collector layer.
The transistor structure further includes: a third interconnect layer 119 located within the third opening 117, the third interconnect layer 119 being electrically connected to the collector 110.
The third interconnect layer 119 is a multi-layered metal structure.
In this embodiment, the third interconnection layer 119 is a two-layer metal structure, and the two-layer metal structure corresponds to the first metal layer 120 and the second metal layer 122 in the passive device, respectively.
In one embodiment, one of the two metal structures in the third interconnect layer 119 is electrically connected to either the first metal layer 120 or the second metal layer 122 in the passive device.
The materials of the third interconnect layer 119 include: copper or aluminum.
The transistor further includes: a spacer layer 124 between the collector layer 109 and the second interconnect layer 118, the second interconnect layer 118 extending through the collector layer 109 and the base layer 108, and/or the spacer layer 124 between the collector layer 109 and the third interconnect layer 119, the third interconnect layer 119 extending through the collector layer 109.
The material of the isolation layer 124 includes silicon nitride.
The thickness of the isolation layer 124 ranges from: 50 nm to 200 nm.
The transistor further includes: a barrier layer 101 on a second side of the collector layer 109, the material of the barrier layer 101 being different from the material of the collector layer 107, the base layer 106 and the emitter layer 106.
The barrier layer 101 material includes intrinsic state gallium indium phosphide (lnGaP), or intrinsic state gallium aluminum arsenide (AlGaAs).
The thickness range of the barrier layer 101 is as follows: 20nm to 0.5 μm.
The semiconductor device further includes: a bonding layer between the transistor and the first substrate 112.
The bonding layer includes a single-layer structure or a multi-layer stacked structure. Specifically, in this embodiment, the bonding layer includes a first bonding layer 113 and a second bonding layer 114.
The bonding layer comprises silicon nitride, silicon oxide and silicon oxynitride.
Specifically, in the present embodiment, the thickness of the first bonding layer 113 ranges from 2 μm to 4 μm.
Specifically, in the present embodiment, the thickness of the second bonding layer 114 is 50nm.
Accordingly, please continue to refer to fig. 28, another semiconductor device is provided in the technical solution of the present invention, which is different from the semiconductor device in fig. 24 in that: the interconnect layer structure is arranged in different ways.
The interconnect layer structure includes: a first interconnect layer 226, a second interconnect layer 218, and a third interconnect layer 219.
The semiconductor device includes: a first opening 225 (as shown in fig. 27), the first opening 225 penetrating the first substrate 112, the first opening 125 exposing the surface of the emitter electrode 105.
The semiconductor device includes: a first interconnect layer 226 located in the second side and the first opening 225, the first interconnect layer 226 being electrically connected to the emissive layer 106.
The materials of the first interconnect layer 226 include: copper or aluminum.
The semiconductor device includes: a second opening 216 (as shown in fig. 25), the second opening 216 exposing a surface of the base electrode 107, the second opening 216 penetrating the first substrate 112.
The semiconductor device includes: a second interconnect layer 218 located within the second opening 216, the second interconnect layer 218 being electrically connected to the base electrode 107.
The materials of the second interconnect layer 218 include: copper or aluminum.
The semiconductor device includes: a third opening 217 (as shown in fig. 25), the third opening 117 exposing a surface of the collector 110, the third opening 117 penetrating the first substrate 112.
The semiconductor device includes: and a third interconnection layer 219 located in the third opening 217, the third interconnection layer 219 being electrically connected to the collector electrode 110.
The material of the third interconnect layer 219 includes: copper or aluminum.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (25)
1. A semiconductor device, comprising:
A first substrate having opposite first and second sides;
A transistor, the transistor comprising: the transistor is bonded to the first surface through bonding treatment, the current collecting layer is provided with a first side and a second side which are opposite to each other, the base layer and the emission layer are located on the first side, the blocking layer is located on the second side, the first substrate is located on the first side, the base layer and the emission layer are located between the first substrate and the current collecting layer, the material of the blocking layer is different from that of the current collecting layer, the blocking layer is used for protecting the current collecting layer, and the material of the current collecting layer, the material of the base layer and the material of the emission layer are different from that of the first substrate.
2. The semiconductor device of claim 1, wherein the barrier layer material comprises intrinsic state gallium indium phosphide, or intrinsic state gallium aluminum arsenide.
3. The semiconductor device according to claim 1, wherein a thermal conductivity of the first base material is greater than thermal conductivities of the collector material, the base material, and the emitter material.
4. The semiconductor device of claim 3, wherein the material of the first substrate comprises silicon, gallium nitride, or silicon carbide; the material of the current collecting layer comprises gallium arsenide; the material of the base layer comprises gallium arsenide; the material of the emission layer comprises gallium arsenide or gallium indium arsenide.
5. The semiconductor device according to claim 1, further comprising: a collector electrode positioned on the surface of the collector layer; a base electrode located on the surface of the base layer; and an emitter electrode positioned on the surface of the emitter layer.
6. The semiconductor device according to claim 5, further comprising: and the first interconnection layer is positioned on the first side of the current collecting layer, penetrates through the first substrate and is electrically connected with the emitting electrode.
7. The semiconductor device according to claim 6, further comprising: and the second interconnection layer is electrically connected with the base electrode and is positioned on the same side of the emission layer as the first interconnection layer.
8. The semiconductor device according to claim 6, further comprising: and the second interconnection layer is electrically connected with the base electrode, and the second interconnection layer and the first interconnection layer are positioned on two sides of the emission layer.
9. The semiconductor device according to claim 6, further comprising: and a third interconnect layer electrically connected to the collector electrode, the third interconnect layer being on the same side of the emitter layer as the first interconnect layer.
10. The semiconductor device according to claim 6, further comprising: and the third interconnection layer is electrically connected with the collector electrode, and the third interconnection layer and the first interconnection layer are positioned on two sides of the emission layer.
11. The semiconductor device of claim 8, wherein the second interconnect layer extends through the collector layer, the semiconductor device further comprising: an isolation layer located between the collector layer and the second interconnect layer; the material of the isolation layer comprises silicon nitride.
12. A method of forming a semiconductor device, comprising:
providing a first substrate, wherein the first substrate is provided with a first surface and a second surface which are opposite;
Providing a second substrate;
Forming a transistor on the second substrate, the transistor comprising: a barrier layer, a current collector layer, a base layer, and an emissive layer, the current collector layer having opposite first and second sides, the base layer and the emissive layer being on the first side, the barrier layer and the second substrate being on the second side;
First bonding the transistor and the first substrate with a first side of the current collecting layer facing the first surface of the first substrate, the first substrate being located on the first side, the base layer and the emission layer being located between the first substrate and the current collecting layer;
After the first bonding process is performed, the second substrate is removed, so that the transistor on the second substrate is transferred onto the first substrate, and the semiconductor device is formed.
13. The method of forming a semiconductor device according to claim 12, wherein the transistor further comprises: an emitter electrode on the surface of the emitter layer, a base electrode on the surface of the base layer, and a collector electrode on the surface of the collector layer.
14. The method of forming a semiconductor device according to claim 12, wherein a thermal conductivity of the first substrate is greater than a thermal conductivity of the second substrate; the material of the first substrate comprises silicon, gallium nitride or silicon carbide; the material of the second substrate comprises gallium arsenide.
15. The method of forming a semiconductor device of claim 12, wherein the method of removing the second substrate comprises: turning over the structure after the first bonding treatment, and thinning the second substrate; and etching the thinned second substrate until the surface of the barrier layer is exposed.
16. The method of forming a semiconductor device according to claim 15, wherein the method of etching treatment comprises wet etching; the ratio of the etching rate of the second substrate material to the etching rate of the barrier layer material in the wet etching is 10:1-20:1.
17. The method of forming a semiconductor device according to claim 12, wherein the first bonding process comprises a bonding process, the method further comprising: forming a first bonding layer on the transistor; forming a second bonding layer on the first surface of the first substrate; the first bonding process bonds the first bonding layer to the second bonding layer.
18. The method of forming a semiconductor device according to claim 17, wherein a material of the first bonding layer comprises silicon oxide, silicon oxynitride, or silicon nitride; the material of the second bonding layer comprises silicon oxide, silicon oxynitride or silicon nitride.
19. The method of forming a semiconductor device according to claim 13, further comprising: and forming a first interconnection layer penetrating through the first substrate on the first side of the current collection layer, wherein the first interconnection layer is electrically connected with the emission electrode.
20. The method of forming a semiconductor device according to claim 19, further comprising: and forming a second interconnection layer, wherein the second interconnection layer is electrically connected with the base electrode, and the second interconnection layer and the first interconnection layer are positioned on the same side of the emission layer.
21. The method of forming a semiconductor device according to claim 19, further comprising: and forming a second interconnection layer, wherein the second interconnection layer is electrically connected with the base electrode, and the second interconnection layer and the first interconnection layer are positioned on two sides of the emission layer.
22. The method of forming a semiconductor device of claim 21, wherein the second interconnect layer extends through the collector layer, the method further comprising: an isolation layer is formed between the collector layer and the second interconnect layer.
23. The method of forming a semiconductor device according to claim 19, further comprising: a third interconnect layer is formed, the third interconnect layer being electrically connected to the collector electrode, the third interconnect layer being on the same side of the emitter layer as the first interconnect layer.
24. The method of forming a semiconductor device according to claim 19, further comprising: and forming a third interconnection layer, wherein the third interconnection layer is electrically connected with the collector electrode, and the third interconnection layer and the first interconnection layer are positioned on two sides of the emission layer.
25. The method of forming a semiconductor device of claim 14, wherein the barrier layer material comprises intrinsic state gallium indium phosphide or intrinsic state gallium aluminum arsenide.
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