CN215896406U

CN215896406U - Semiconductor device with a plurality of transistors

Info

Publication number: CN215896406U
Application number: CN202120704365.8U
Authority: CN
Inventors: 杨彦涛; 隋晓明; 李云飞; 杨青森; 楚婉怡; 王岁虎
Original assignee: Hangzhou Shilan Jixin Microelectronics Co ltd
Current assignee: Hangzhou Shilan Jixin Microelectronics Co ltd
Priority date: 2021-04-07
Filing date: 2021-04-07
Publication date: 2022-02-22
Anticipated expiration: 2031-04-07

Abstract

Disclosed is a semiconductor device including: the device comprises a substrate, wherein a cellular device structure for realizing the function of the device is arranged in the substrate; a step-like device structure located over the substrate, the step-like device structure covering a portion of the substrate; the barrier layer is positioned above the medium layer, the medium layer and the barrier layer cover the stepped device structure and the exposed substrate, and contact holes are formed in the medium layer and the barrier layer and penetrate through the medium layer and the barrier layer. The semiconductor device of the embodiment of the utility model improves the reliability of the semiconductor device.

Description

Semiconductor device with a plurality of transistors

Technical Field

The utility model relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device.

Background

In a very large scale integrated circuit, the pattern density of a semiconductor device is higher and higher, the number of process layers is higher and higher, and the size of the device is smaller and smaller. The smaller the size of the semiconductor device, the greater the pattern density, and the higher the resolution of the photoresist required by the photolithography process. Wherein, the higher the resolution of the photoresist is, the thinner the thickness of the photoresist is; the photoresist needs to have good step coverage to a sufficient thickness to ensure structural integrity of the semiconductor surface. For a semiconductor device with a step-shaped structure, the surface flatness of the semiconductor structure is poor, the step coverage of a thin photoresist is poor, particularly, the situation that the photoresist is too thin is easily generated at the step, so that the etching resistance of the photoresist at the step is poor, in the process of patterning the semiconductor device, the photoresist at the corner of the step is easily etched through, so that a dielectric layer and other semiconductor structures below the corner of the step are etched and even etched through, the performance abnormity of the semiconductor device, such as short circuit, electric leakage and the like, is caused, and the reliability of the semiconductor device is reduced.

SUMMERY OF THE UTILITY MODEL

In view of the above problems, an object of the present invention is to provide a semiconductor device having improved reliability.

According to a first aspect of embodiments of the present invention, there is provided a semiconductor device including:

a substrate having a cellular device structure therein for performing a device function;

at least one stepped device structure located over the substrate, the stepped device structure covering a portion of the substrate;

the barrier layer is positioned above the medium layer, the medium layer and the barrier layer cover the step-shaped device structure and the exposed substrate, contact holes are formed in the medium layer and the barrier layer, and the contact holes penetrate through the medium layer and the barrier layer.

Optionally, the semiconductor device further includes:

and the metal wiring layer is positioned above the barrier layer and fills the contact hole, and the metal wiring layer comprises a terminal area electrode and a cellular area electrode.

Optionally, the step-like device structure is a device or a film step with a certain height on the surface of the substrate.

Optionally, the contact holes comprise a first type of contact holes and a second type of contact holes,

the first contact hole penetrates through the dielectric layer and the barrier layer to expose the step-shaped device structure;

the second contact hole penetrates through the dielectric layer and the barrier layer and exposes the substrate.

Optionally, the semiconductor device further includes:

an ion implantation region located in the stepped device structure and the substrate.

Optionally, the step-like device structure is higher than the substrate by more than or equal to 0.001 um.

Optionally, the material of the barrier layer includes one or more of undoped polysilicon, silicon nitride and silicon oxynitride.

Optionally, the material of the barrier layer comprises one or a combination of Ti, TiN, W, Al, Cu, Pt and Co.

Optionally, the thickness of the dielectric layer is greater than or equal to 0.001 um.

Optionally, the cellular device structure comprises P-type or N-type doping, capacitance, resistance, metal oxide semiconductor field effect transistor, insulated gate bipolar transistor, integrated circuit, flash memory, complementary metal oxide semiconductor, bipolar-complementary metal oxide semiconductor-double diffused metal oxide semiconductor, micro electro mechanical system, and schottky device.

According to the semiconductor device provided by the embodiment of the utility model, due to the existence of the barrier layer, the barrier layer is kept complete in the process of patterning the dielectric layer material, the barrier layer is used as the barrier, the situation that the dielectric layer material which does not need to be etched is etched, and the thickness of the dielectric layer positioned at the corner of the step is not changed is avoided. The cell area electrode positioned at the corner of the step is isolated from the polycrystalline silicon layer, so that the possibility of parameter abnormity such as short circuit between the grid electrode and the source electrode, current leakage between the grid electrode and the source electrode and the like is reduced, and the reliability of the semiconductor device is improved. The distance between the cell area electrode and the second oxide layer at the corner of the step is unchanged, so that the possibility of the occurrence of parasitic capacitance, parasitic diodes and other effects at the corner of the step is reduced, the stability of capacitance and frequency characteristics of the semiconductor device is improved, and the reliability of the semiconductor device is improved.

Due to the existence of the barrier layer, the thickness of the dielectric layer at the corner of the step is not changed. After a barrier layer is formed above the step-shaped device structure, ion implantation is performed through the first contact hole and the second contact hole, so that the contact resistance of the device is reduced, and the single pulse avalanche Energy (EAS) of the device is enhanced. The ion injection region is formed in the substrate and the step-shaped device structure, so that the formation of a doped region in the semiconductor device in the region where impurity ions do not need to be injected is avoided, the possibility of abnormal doping concentration of the first oxide layer, the polycrystalline silicon layer and the second oxide layer of the semiconductor device is reduced, the problems of voltage resistance, abnormal threshold value and the like are avoided, the possibility of abnormal performance of the cellular device structure in the substrate is reduced, and the reliability of the semiconductor device is improved. Due to the existence of the barrier layer, a small line width manufacturing process with high steps and thinner photoresist can be realized under the existing process conditions, the process realization difficulty is reduced, and the manufacturing cost is reduced. The semiconductor device of the embodiment of the utility model can be popularized and used in high-step power devices and circuit products.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic cross-sectional view of a semiconductor device in the related art;

FIG. 2 illustrates a schematic cross-sectional view of a semiconductor device of an embodiment of the present invention;

FIGS. 3a to 3h are schematic cross-sectional views of various stages of a method of manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 4 shows a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.

Fig. 1 shows a schematic cross-sectional view of a semiconductor device in the related art. As shown in fig. 1, the semiconductor device 100 includes: a substrate 110, in which substrate 110 a cellular device structure (not shown in the figure) implementing a device function is disposed; the cellular device structure comprises a P type or N type doping structure, a capacitance structure, a resistance structure, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure, a sensor structure and the like. The substrate 110 includes a semiconductor base 111 and an epitaxial layer 112 over the semiconductor base 111. A stepped device structure located over the substrate 110, the stepped device structure covering a portion of the substrate 110; the step-like device structure comprises a first step-like device structure and a second step-like device structure, the first step-like device structure comprises a first oxidation layer 121 and a polysilicon layer 122, the first oxidation layer 121 covers a part of the substrate 110, the polysilicon layer 122 is positioned above the first oxidation layer 121, and the first oxidation layer 121 isolates the polysilicon layer 122 from the substrate 110. The second stepped device structure includes a second oxide layer 123, and the second oxide layer 123 covers a portion of the substrate 110. A dielectric layer 130 positioned above the stepped device structure, the dielectric layer 130 covering the stepped device structure and the exposed substrate 110, a contact hole provided in the dielectric layer 130, the contact hole penetrating through the dielectric layer 130; the material of the dielectric layer 130 includes silicon dioxide or silicon dioxide doped with impurity ions, such as silicon dioxide doped with boron element and silicon dioxide doped with phosphorus element. The contact holes include a first type contact hole 131, a second type contact hole 132 and a first type contact hole 133, and the first type contact hole 131 penetrates through the dielectric layer 130 to expose the polysilicon layer 122 of the first step-like device structure. The second type contact hole 132 penetrates the dielectric layer 130 to expose the substrate 110. The first-type contact hole 133 penetrates through the dielectric layer 130 to expose the second oxide layer 123 of the second stepped device structure. And an ion implantation region 160 located in the polysilicon layer 122 of the first stepped device structure, the substrate 110 and the second oxide layer 123 of the second stepped device structure. And a metal wiring layer 170 positioned above the dielectric layer 130, the metal wiring layer 170 filling the contact hole.

Note that the semiconductor device 100 includes a die and a scribe lane region (not shown in the figure). The die includes a cell region 101 and a terminal region 102, the terminal region 102 includes a gate electrode region, a voltage divider ring region and a stop ring region (not shown), the voltage divider ring region is located at the periphery of the cell region 101, and the stop ring region is located at the periphery of the voltage divider ring region. The metal wiring layer 170 includes a cell region electrode 172, a terminal region electrode 171, and a terminal region electrode 173. The cell device structure and cell region electrode 172 are located in the cell region 101 and the termination region electrode 171 and the termination region electrode 173 are located in the termination region 102.

Taking the semiconductor device 100 as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) as an example, the first oxide layer 121 is a gate oxide layer or a pad oxide layer, and the second oxide layer 123 is a field oxide layer. The first and second stepped device structures are located in the termination region 102. The semiconductor device located between the first stepped device structure and the second stepped device structure is a cell region 101. The termination region electrode 171 located above the polysilicon layer 122 forms a gate electrode of the semiconductor device 100, the cell region electrode 172 located above the cell region 101 forms a source electrode of the semiconductor device 100, the substrate 110 forms a drain electrode of the semiconductor device 100, and the termination region electrode 173 located above the second oxide layer 123 forms a voltage dividing structure of the semiconductor device 100.

It should be noted that, in order to meet the design requirements of the very large scale integrated circuit, the semiconductor device 100 has smaller and smaller dimensions, larger and larger pattern density, and more process layers. The greater the pattern density of the semiconductor device 100, the higher the resolution of the photoresist required for the process. The resolution of the photoresist is the ability to distinguish between adjacent patterns generated in the process layer after patterning the process layer using the photoresist as a mask. The resolution of the photoresist is generally measured by the Critical Dimension (CD), and the smaller the CD formed, the higher the resolution. The thickness of the photoresist directly affects the resolution, the thinner the thickness, the higher the resolution.

In the fabrication of semiconductor device 100, the step of forming dielectric layer 130 over the stepped device structure includes: depositing a dielectric layer material above the stepped device structure, coating photoresist on the dielectric layer material, and patterning the dielectric layer material to form a dielectric layer 130 by using the photoresist as a mask, wherein the dielectric layer 130 comprises a first-type contact hole 131, a second-type contact hole 132 and a first-type contact hole 133. However, due to the resolution of the photoresist, the thickness of the photoresist applied over the dielectric layer material is very thin. In addition, for the semiconductor device 100 provided with the stepped device structure, the higher the height of the stepped device structure is, the thinner the thickness of the photoresist applied to the sidewall, the corner between the sidewall and the upper surface of the stepped device structure (step corner 134 and step corner 135) is. In the process of further patterning the material of the dielectric layer by using the photoresist as a mask, the photoresist is also etched. Since the thickness of the photoresist coated on the step corner 134 and the step corner 135 is thinner than that of the photoresist coated on other positions, the photoresist coated on the step corner 134 and the step corner 135 is easily etched, the dielectric layer material is etched through the through holes of the photoresist coated on the step corner 134 and the step corner 135, and the thickness of the dielectric layer material at the step corner 134 and the thickness of the dielectric layer material at the step corner 135 are reduced. In addition, since the height of the first step-like device structure is higher than that of the second step-like device structure, the photoresist at the step corner 134 is thinner than that at the step corner 135, and the photoresist at the step corner 134 is more easily etched and perforated, so that the dielectric layer material at the step corner 134 is etched and even etched and perforated, and the polysilicon layer 122 below the dielectric layer material at the step corner 134 is exposed. The cell region electrode 172 at the step corner 134 is connected to the polysilicon layer 122, which causes abnormal parameters such as short circuit between the gate electrode and the source electrode, current leakage between the gate electrode and the source electrode, and the like, and reduces the reliability of the semiconductor device 100. The distance between the cell region electrode 172 located at the step corner 135 and the second oxide layer 123 is reduced, so that parasitic capacitance, parasitic diode and other effects are easily generated at the step corner 135, the capacitance and frequency characteristics of the semiconductor device 100 are affected, and the reliability of the semiconductor device 100 is reduced.

In some embodiments, in order to reduce the contact resistance of the device and enhance the Single Pulse Avalanche Energy (EAS) of the device, after the dielectric layer 130 is formed over the stepped device structure, ion implantation needs to be performed through the first-type contact hole 131, the second-type contact hole 132 and the first-type contact hole 132 of the dielectric layer 130, and the ion implantation region 160 is formed in the polysilicon layer 122, the substrate 110 and the second oxide layer 123. However, since the dielectric layer material at the step corner 134 is etched and perforated, the thickness of the dielectric layer material at the step corner 135 is reduced, and during the ion implantation process through the first-type contact hole 131, the second-type contact hole 132 and the first-type contact hole 132 of the dielectric layer 130, the implanted ions enter the polysilicon layer 122 through the dielectric layer perforation at the step corner 134, enter the second oxide layer 123 through the reduced-thickness dielectric layer 130 at the step corner 135, and enter the substrate 110 through the reduced-thickness dielectric layer 130 at the cell region 101, so that a doped region is formed in the semiconductor device 100 in a region where impurity ions do not need to be implanted, such that the doping concentrations of the first oxide layer 121, the polysilicon layer 122 and the second oxide layer 123 of the semiconductor device 100 are abnormal, the performance of the cell device structure in the substrate 110 is abnormal, and a voltage withstanding voltage, a voltage, and a voltage are generated, Threshold abnormality, etc., which reduces the reliability of the semiconductor device 100.

Based on this, embodiments of the present invention provide a semiconductor device, which is described in detail below with reference to the accompanying drawings.

Fig. 2 shows a schematic structural diagram of a semiconductor device of an embodiment of the present invention. As shown in fig. 2, the semiconductor device 200 includes: a substrate 210, in which substrate 210 a cellular device structure (not shown in the figure) implementing a device function is disposed; the cellular device structure comprises a P-type or N-type doped, capacitor, resistor, Metal Oxide Semiconductor Field Effect Transistor (MOSFET), Insulated Gate BIPOLAR Transistor (IGBT), Integrated Circuit (IC), Flash memory (Flash), Complementary Metal Oxide Semiconductor (CMOS), BIPOLAR-complementary metal oxide semiconductor-double-diffused metal oxide semiconductor (BCD, BIPOLAR-CMOS-DMOS), micro-electro-mechanical system (MEMS), Schottky device and the like. The substrate 210 includes a semiconductor base 211 and an epitaxial layer 212 over the semiconductor base 211. In some embodiments, the substrate 210 may not include the epitaxial layer 212, but only include the semiconductor base 211 of a specific doping type (e.g., N-type or P-type), according to product requirements. The material of the substrate 210 includes group III-V semiconductors such as GaAs, InP, GaN, SiC, and group IV semiconductors such as Si, Ge, etc. A stepped device structure located over substrate 210, the stepped device structure covering a portion of substrate 210; the step-like device structure is a device or a film-like step having a certain height on the surface of the substrate 210. The height of the step-like device structure above the substrate 210 is greater than or equal to 0.001 um. The step-like device structure comprises a first step-like device structure and a second step-like device structure, the first step-like device structure comprises a first oxidation layer 221 and a polysilicon layer 222, the first oxidation layer 221 covers a part of the substrate 210, the polysilicon layer 222 is positioned above the first oxidation layer 221, and the first oxidation layer 221 isolates the polysilicon layer 222 from the substrate 210. The second stepped device structure includes a second oxide layer 223, the second oxide layer 223 covering a portion of the substrate 210. And the dielectric layer 230 and the barrier layer 240 are positioned above the stepped device structure, the barrier layer 240 is positioned above the dielectric layer 230, the dielectric layer 230 and the barrier layer 240 cover the stepped device structure and the exposed substrate 210, and contact holes are formed in the dielectric layer 230 and the barrier layer 240 and penetrate through the dielectric layer 230 and the barrier layer 240. The material of the dielectric layer 230 includes silicon dioxide or silicon dioxide doped with impurity ions, such as silicon dioxide doped with boron, silicon dioxide doped with phosphorus, and silicon dioxide doped with boron and phosphorus. The thickness h1 of the dielectric layer 230 is greater than or equal to 0.001 um. The material of the barrier layer 240 includes one or a combination of undoped polysilicon, silicon nitride, and silicon oxynitride. In some embodiments, the material of barrier layer 240 includes one or a combination of Ti, TiN, W, Al, Cu, Pt, and Co. The metal material is selected as the barrier layer 240, so that the etching resistance of the barrier layer 240 is higher, but the barrier layer metal etching process is often required to be added in the contact hole etching and metal etching processes. The etching selectivity of the dielectric layer 230 and the barrier layer 240 is relatively high, that is, when the dielectric layer 230 is completely etched, the barrier layer 240 remains at any position on the surface of the dielectric layer 230, and the dielectric layer 230 is not exposed. The height h2 of the step formed by barrier layer 240 at step corner 234 is greater than or equal to 0.05 um. The contact holes include a first type contact hole 231, a second type contact hole 232 and a first type contact hole 233, the first type contact hole 231 penetrates through the dielectric layer 230 and the barrier layer 240, and the polysilicon layer 222 of the first step-like device structure is exposed. The second type contact hole 232 penetrates the dielectric layer 230 and the barrier layer 240 to expose the substrate 210. The first-type contact hole 233 penetrates the dielectric layer 230 and the barrier layer 240 to expose the second oxide layer 223 of the second step-like device structure. An ion implantation region 260 located in the polysilicon layer 222 of the first stepped device structure, the substrate 210, and the second oxide layer 223 of the second stepped device structure. And a metal wiring layer 270 over the barrier layer 240, the metal wiring layer 270 filling the contact hole.

It should be noted that although two stepped device structures are shown in fig. 2, there may be 1, 3 or even more stepped device structures, and the number of stepped device structures is not limited herein. The step-like device structure is provided in the semiconductor device 200 in order to make various structures, such as electrostatic discharge (ESD) requiring wiring extraction on the front surface of the device or isolation layer. The step-like device structure may be provided at any location of the semiconductor device, wherein the termination region 202 typically requires the provision of the step-like device structure for voltage division. The material composing the stepped device structure may include a dielectric layer, a metal layer, and the like, and may be a combination of various dielectric layers and metal layers, which is not limited herein.

Note that the semiconductor device 200 includes a die and a scribe line region (not shown in the figure). The die includes a cell region 201 and a terminal region 202, the terminal region 202 includes a gate electrode region, a voltage divider ring region and a stop ring region (not shown), the voltage divider ring region is located at the periphery of the cell region 201, and the stop ring region is located at the periphery of the voltage divider ring region. The metal wiring layer 270 includes a cell region electrode 272, a terminal region electrode 271, and a terminal region electrode 273. The cell device structure and cell region electrodes 272 are located in the cell region 201, and the

terminal region electrodes

271 and 273 are located in the terminal region 202.

Taking the semiconductor device 200 as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) as an example, the first oxide layer 221 is a gate oxide layer or a pad oxide layer, and the second oxide layer 223 is a field oxide layer. The first and second stepped device structures are located in the termination region 202. The semiconductor device located between the first stepped device structure and the second stepped device structure is a cell region 201. The termination region electrode 271 located above the polysilicon layer 222 forms a gate electrode of the semiconductor device 200, the cell region electrode 272 located above the cell region 201 forms a source electrode of the semiconductor device 200, the substrate 210 forms a drain electrode of the semiconductor device 200, and the termination region electrode 273 located above the second oxide layer 223 forms a voltage dividing structure of the semiconductor device 200.

It should be noted that, due to the existence of the barrier layer 240, during the process of patterning the dielectric layer material, the barrier layer 240 remains intact, the barrier layer 240 serves as a barrier to prevent the dielectric layer material from being etched, and the thickness of the dielectric layer 230 at the step corner 234 and the thickness of the dielectric layer 230 at the step corner 235 are not changed. The cell region electrode 272 at the step corner 234 is isolated from the polysilicon layer 222, thereby reducing the possibility of parameter abnormality such as short circuit between the gate electrode and the source electrode, current leakage between the gate electrode and the source electrode, and the like, and improving the reliability of the semiconductor device 200. The distance between the cell region electrode 272 and the second oxide layer 223 at the step corner 235 is not changed, so that the possibility of the occurrence of parasitic capacitance, parasitic diode and other effects at the step corner 235 is reduced, the stability of capacitance and frequency characteristics of the semiconductor device 200 is improved, and the reliability of the semiconductor device 200 is improved.

The thickness of dielectric layer 230 at stepped corner 234 and the thickness of dielectric layer 230 at stepped corner 235 are constant due to the presence of barrier layer 240. After the barrier layer 240 is formed above the stepped device structure, ion implantation is performed through the first-type contact hole 231, the second-type contact hole 232 and the first-type contact hole 233, and the ion implantation region 260 is formed in the polycrystalline silicon layer 222 of the first stepped device structure, the substrate 210 and the second oxide layer 223 of the second stepped device structure, so that a doped region is prevented from being formed in a region in which impurity ions are not required to be implanted in the semiconductor device 200, the possibility of abnormal doping concentrations of the first oxide layer 221, the polycrystalline silicon layer 222 and the second oxide layer 223 of the semiconductor device 200 is reduced, the possibility of abnormal performance of the cellular device structure in the substrate 210 is reduced, and the reliability of the semiconductor device 200 is improved.

Fig. 3a to 3h show schematic cross-sectional views of different stages of a method of manufacturing a semiconductor device according to an embodiment of the utility model. Referring to fig. 3a to 3h, the method of manufacturing the semiconductor device 200 includes the following steps.

As shown in fig. 3a, a substrate 210 is provided, and a cellular device structure (not shown) for implementing the device function is disposed in the substrate 210. The cellular device structure comprises structures such as a P-type or N-type doping, a capacitor, a resistor, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an Insulated Gate BIPOLAR Transistor (IGBT), an Integrated Circuit (IC), a Flash memory (Flash), a Complementary Metal Oxide Semiconductor (CMOS), a BIPOLAR-complementary metal oxide semiconductor-double-diffused metal oxide semiconductor (BCD, BIPOLAR-CMOS-DMOS), a Micro Electro Mechanical System (MEMS) and a Schottky device. The substrate 210 includes a semiconductor base 211 and an epitaxial layer 212 over the semiconductor base 211. In some embodiments, the substrate 210 may not include the epitaxial layer 212, but only include the semiconductor base 211 of a specific doping type (e.g., N-type or P-type), according to product requirements. The material of the substrate 210 includes, for example, a group III-V semiconductor such as GaAs, InP, GaN, SiC, and a group IV semiconductor such as Si, Ge, etc. Those skilled in the art can define various cell device structures included in the substrate and various constituent structures of the substrate surface according to the characteristics of the product.

Further, a stepped device structure is formed over the substrate 210, the stepped device structure covering a portion of the substrate 210. The step-like device structure is a device or a film-like step having a certain height on the surface of the substrate 210. The height of the step-like device structure above the substrate 210 is greater than or equal to 0.001 um. The step-like device structure comprises a first step-like device structure and a second step-like device structure. The first stepped device structure includes a first oxide layer 221 and a polysilicon layer 222. The second stepped device structure includes a second oxide layer 223. Those skilled in the art can define various device structures included in the semiconductor substrate 210, and the heights, constituent materials, and the like of various stepped device structures on the surface of the semiconductor substrate 210 according to the characteristics of the product. In some embodiments, a height of the first stepped device structure is greater than a height of the second stepped device structure. Specifically, a first oxide layer 221 is formed over the substrate 210, the first oxide layer 221 covering a portion of the substrate 210; a polysilicon layer 222 is formed over the first oxide layer 221, the first oxide layer 221 isolating the polysilicon layer 222 from the substrate 210. A second oxide layer 223 is formed over the substrate 210, the second oxide layer 223 covering a portion of the substrate 210.

Note that the semiconductor device 200 includes a die and a scribe line region (not shown in the figure). The die includes a cell region 201 and a terminal region 202, the terminal region 202 includes a gate electrode region, a voltage divider ring region and a stop ring region (not shown), the voltage divider ring region is located at the periphery of the cell region 201, and the stop ring region is located at the periphery of the voltage divider ring region.

As shown in fig. 3b, dielectric layer materials are sequentially deposited over the stepped device structure by a chemical vapor deposition process such as a combination of one or more of Low Pressure Chemical Vapor Deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), HTO, SRO. And forming a barrier layer material above the dielectric layer material by a chemical vapor deposition process. A dielectric layer material and a barrier layer material cover the stepped device structure and the exposed substrate 210. The material of the dielectric layer 230 includes silicon dioxide or silicon dioxide doped with impurity ions, such as silicon dioxide doped with boron, silicon dioxide doped with phosphorus, and silicon dioxide doped with boron and phosphorus. The thickness h1 of the dielectric layer 230 on the stepped device structure and the exposed substrate 210 is greater than or equal to 0.001 um. The material of the barrier layer 240 includes one or a combination of undoped polysilicon, silicon nitride, and silicon oxynitride. In some embodiments, the material of barrier layer 240 includes one or a combination of Ti, TiN, W, Al, Cu, Pt, and Co. If the barrier layer 240 is made of a metal material, the etch resistance of the barrier layer 240 is stronger, but an additional barrier metal etching process is often required in the contact hole etching and metal etching processes. The height h2 of the step formed by barrier layer 240 at step corner 234 is greater than or equal to 0.05 um. The dielectric layer 230 at the stepped corner 235 has a thickness d 1.

As shown in fig. 3c, a photoresist 250 is coated over the barrier material. The thickness of photoresist 250 over the barrier material is h3, the thickness of photoresist 250 at step corner 234 is d2, and the thickness of photoresist 250 at step corner 235 is d 3. Typically, the thickness of the photoresist applied at

step corners

234 and 235 is thinner than the thickness of the photoresist applied elsewhere 250. In addition, since the height of the first stepped device structure is higher than the height of the second stepped device structure, the photoresist at the step corners 234 is thinner than the photoresist at the step corners 235. That is, h3 is greater than d3, and d3 is greater than d 2.

In this step, the photoresist 250 is coated by a coating and rotating method, so that the photoresist 250 has a certain thickness and meets the requirement of light transmittance. The coating process can be one-time coating or multiple coating processes, and the spraying mode can also be adopted. When the spray coating is used, the photoresist 250 falls onto the barrier material in a gaseous form, and its thickness can be controlled to be thinner.

As shown in fig. 3d, a desired lithography window is formed in the photoresist 250 by exposure, development, and the like. The width of the lithography window meets the design requirements, and is usually the minimum line width.

As shown in fig. 3e, the photoresist 250 is used as a mask, and the barrier layer material is patterned by photolithography, etching, and the like to form the barrier layer 240, where the barrier layer 240 includes the first-type contact hole 231, the second-type contact hole 232, and the first-type contact hole 233. The photoresist 250 is removed.

As shown in fig. 3f, the barrier layer 240 is used as a mask, and a material of the dielectric layer is patterned by an etching process (usually, a dry etching process) to form the dielectric layer 230, where the dielectric layer 230 includes the first type contact hole 231, the second type contact hole 232, and the first type contact hole 233, and the first type contact hole 231, the second type contact hole 232, and the first type contact hole 233 penetrate through the dielectric layer 230 and the barrier layer 240. The first type contact hole 231 penetrates through the dielectric layer 230 and the barrier layer 240 to expose the polysilicon layer 222 of the first step-like device structure. The second type contact hole 132 penetrates the dielectric layer 230 and the barrier layer 240 to expose the substrate 210. The first-type contact holes 133 penetrate the dielectric layer 230 and the barrier layer 240 to expose the second oxide layer 223 of the second step-like device structure. The thickness h1 of the dielectric layer 230 on the stepped device structure and the substrate 210 and the thickness d1 of the dielectric layer 230 at the stepped corners 235 are unchanged.

Ion implantation is performed through the first-type contact hole 231, the second-type contact hole 232 and the first-type contact hole 233, and an ion implantation region 260 is formed in the polysilicon layer 222 of the first stepped device structure, the substrate 210 and the second oxide layer 223 of the second stepped device structure to reduce contact resistance and enhance single pulse avalanche Energy (EAS). Ion implantation is typically performed using B + and B11, with implantation energies including 20 to 800Kev, implantation doses including 1E11 to 1E16, and annealing temperatures including 600 to 1200 degrees. The barrier layer 240 prevents a doped region from being formed in a region where impurity ions do not need to be implanted in the semiconductor device 200, reduces the possibility of abnormal doping concentrations of the first oxide layer 221, the polysilicon layer 222 and the second oxide layer 223 of the semiconductor device 200, reduces the possibility of abnormal performance of the cell device structure in the substrate 210, and improves the reliability of the semiconductor device 200.

In some embodiments, after the photoresist 250 is used as a mask and the barrier layer material is patterned by photolithography, etching, and the like to form the barrier layer 240, the photoresist 250 may not be removed first. The photoresist 250 is still used as a mask in the process of patterning the dielectric layer material to form the dielectric layer 230 through processes of photoetching, etching and the like, and the photoresist 250 is removed after the dielectric layer 230 is formed.

As shown in fig. 3g, a layer of metal wiring layer material is deposited over the barrier layer 240 by conventional semiconductor processing techniques such as sputtering or evaporation, and fills the first type of contact hole 231, the second type of contact hole 232, and the first type of contact hole 233.

In some embodiments, barrier layer 240 may be removed prior to forming metal wiring layer 270.

In some embodiments, barrier layer 240 is maintained prior to deposition of the metal wiring layer material, and barrier layer 240 may enhance passivation protection of semiconductor device 200, enhance hermeticity, reduce moisture ingress, and improve device reliability in harsh environments.

As shown in fig. 3h, the metal wiring layer material is patterned by photolithography, etching, or the like to form a metal wiring layer 270. The metal wiring layer 270 includes a cell region electrode 272, a terminal region electrode 271, and a terminal region electrode 273. The cell device structure and cell region electrodes 272 are located in the cell region 201, and the

terminal region electrodes

271 and 273 are located in the terminal region 202.

Fig. 4 shows a schematic structural diagram of a semiconductor device according to another embodiment of the present invention. The semiconductor device 400 shown in fig. 4 has a structure substantially identical to that of the semiconductor device 200 shown in fig. 2, except that in the semiconductor device 400, ion implantation regions are not formed in the polysilicon layer 422 of the first stepped device structure, the substrate 410, and the second oxide layer 423 of the second stepped device structure. The manufacturing process of the semiconductor device 400 is substantially the same as the manufacturing method of the semiconductor device 200 shown in fig. 3a to 3h, except that in the manufacturing process of the semiconductor device 400, after the barrier layer 440 is used as a mask and the dielectric layer material is patterned by an etching process (usually, a dry etching process) to form the dielectric layer 430, a metal wiring layer material is deposited on the barrier layer 440 by a conventional semiconductor process technology such as sputtering or evaporation without ion implantation, and the metal wiring layer material fills the first-type contact hole 431, the second-type contact hole 432 and the first-type contact hole 432. The metal wiring layer material is patterned by photolithography, etching, or the like, to form a metal wiring layer 470.

In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the utility model to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the utility model and the practical application, to thereby enable others skilled in the art to best utilize the utility model and various embodiments with various modifications as are suited to the particular use contemplated. The utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, comprising:

2. The semiconductor device of claim 1, further comprising:

3. The semiconductor device of claim 1, wherein the stepped device structure is a device or a film step with a certain height on the surface of the substrate.

4. The semiconductor device according to claim 1, wherein the contact holes include a first type of contact holes and a second type of contact holes,

5. The semiconductor device of claim 1, further comprising:

6. The semiconductor device of claim 1, wherein the step-like device structure has a height greater than or equal to 0.001um above the substrate.

7. The semiconductor device of claim 1, wherein the material of the barrier layer comprises one of undoped polysilicon, silicon nitride, and silicon oxynitride.

8. The semiconductor device according to claim 1, wherein a material of the barrier layer comprises one of Ti, TiN, W, Al, Cu, Pt, and Co.

9. The semiconductor device according to claim 1, wherein a thickness of the dielectric layer is 0.001um or more.

10. The semiconductor device of claim 1, wherein the cellular device structure comprises a semiconductor substrate of a P-type or N-type doping type, and a capacitor, a resistor, a mosfet, an igbt, an integrated circuit, a flash memory, a cmos, a bipolar-cmos-dmos, a mems, and a schottky device.