CN115985956A - Annular gate SiC MOSFET power device and manufacturing method thereof - Google Patents
Annular gate SiC MOSFET power device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a ring grid SiC MOSFET power device and a manufacturing method thereof, relating to the technical field of semiconductors and comprising a drain electrode metal layer, a SiC substrate, a drift layer and two ring-shaped well regions arranged on the drift layer, wherein two source regions are respectively arranged in the ring-shaped well regions; a first source region of the MOSFET power device is arranged inside the inner well region, and a second source region of the MOSFET power device is arranged inside the outer well region; a source metal region is arranged above the first source region and the second source region; the grid electrode is arranged between the source electrode metal regions above the inner well region and the outer well region; the inner well region and the first source region form a first PN junction, and the outer well region and the second source region form a second PN junction. The conducting channel formed by the device is of a structure surrounding the grid, so that the longitudinal current distribution is annular, the current concentration is avoided, the current density in the device is reduced, the current distribution condition in the device is improved, the current concentration in the device is reduced, and the on-resistance of the device is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a ring grid SiC MOSFET power device and a manufacturing method thereof.
Background
Silicon carbide SiC materials have been widely paid attention to and studied because of their excellent physical properties. The high-temperature high-power electronic device has the advantages of high input impedance, high switching speed, high working frequency, high temperature and high pressure resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high-frequency heating, automobile electronics, power amplifiers and the like.
However, in the related art, the gate, the drain and the source of a common SiC device are both concentrated inside, and there are situations that the current is concentrated inside the device, the current density is high in a part of the region, and no current exists in a part of the region, which has some influence on the device performance. In addition, because the conducting channels of the conventional MOS devices are all located in the central region, there is also a case that the device current is distributed inside and heat dissipation is not easy.
Disclosure of Invention
The application provides a ring-shaped gate SiC MOSFET power device and a manufacturing method thereof, which solve the problems of uneven current density distribution and difficult heat dissipation of a semiconductor device.
On one hand, the application provides a ring-shaped gate SiC MOSFET power device, which comprises a drain electrode metal layer, a silicon carbide SiC substrate positioned above the drain electrode metal layer, a drift layer positioned above the SiC substrate, and two ring-shaped well regions arranged on the drift layer, wherein the two source regions are respectively arranged in the ring-shaped well regions; the inner well region is a first source region of the MOSFET power device, and the outer well region is a second source region of the MOSFET power device;
a source metal region is arranged above the first source region and the second source region; the grid electrode is arranged between the source electrode metal regions above the inner well region and the outer well region to form a ring-shaped structure; the inner well region and the first source region form a first PN junction, and the outer well region and the second source region form a second PN junction.
Specifically, the inner well region and the outer well region are concentric structures, and have the same longitudinal depth; the inner well region forms a circular structure in the center of the MOSFET power device to form a first source electrode of the MOSFET power device; the outer well region surrounds the inner well region inside to form a ring structure, and the ring structure forms a second source electrode of the MOSFET power device.
Specifically, a circular first source electrode metal region is arranged above the first source electrode, and an annular second source electrode metal region is arranged above the second source electrode.
Specifically, the drift layer between the first source electrode and the second source electrode forms a ring-shaped conductive channel.
Specifically, a gate insulation region is arranged above the annular conductive channel to form an annular structure, and the inner side and the outer side of the gate insulation region respectively extend to the upper parts of the two annular well regions and are in contact with the two source regions of the MOSFET power device.
Specifically, the gate is located above the gate insulating region to form an annular planar gate structure.
Specifically, the two annular well regions are P-type regions.
In another aspect, the present application provides a method for manufacturing a ring-shaped gate SiC MOSFET power device, which is used for the ring-shaped planar gate SiC vertical MOSFET power device in the above aspect, and the method includes:
s1, arranging a first barrier layer above a drift layer of an MOSFET power device, etching the first barrier layer, and performing ion implantation on an epitaxial layer to generate two ring-shaped well structures on the drift layer;
s2, generating a second barrier layer on the drift layer again, etching, and performing ion implantation on the two annular well structures to generate a first source region and a second source region;
s3, growing an oxide layer and a third barrier layer above the drift layer in sequence, and forming a gate insulation region by removing deposition through gate insulation;
s4, forming a fourth barrier layer on the oxide layer again, and etching and depositing source metal to form a source metal area;
and S5, reforming a fifth barrier layer on the oxide layer, and etching and depositing gate metal to form a gate metal region.
Specifically, S1 includes: generating a circular hole and an annular hole with the same longitudinal depth above the drift layer; the circular hole is positioned in the center of the MOSFET power device, and the circular hole surrounds the central circular hole;
respectively carrying out ion implantation on the epitaxial layer through the inner circular hole and the outer circular hole to form an inner trap structure and an outer trap structure; the horizontal heights of the inner well structure, the outer well structure and the drift layer are consistent;
s2 comprises the following steps: arranging the second barrier layer on the drift layer, and etching the inner well structure and the outer well structure to form an inner well region with a circular center and an outer well region surrounding the inner well region; the formed depressed part is an active area hole;
and respectively carrying out ion implantation on the inner well region and the outer well region, and correspondingly generating the first source region and the second source region in the respective concave parts.
Specifically, S3 includes: generating the oxide layer and the third barrier layer on the horizontal plane of the drift layer, etching the third barrier layer, and forming a gate insulation hole above the annular conductive channel between the inner well region and the outer well region;
forming the gate insulating region by performing gate insulation removal deposition on the gate insulating hole; two ends of the grid insulation region transversely extend to the upper parts of the two annular well regions and are in contact with two source regions of the MOSFET power device;
s4 comprises the following steps: forming the fourth barrier layer above the oxide layer again, etching, and forming a source region metal hole above the first source region and the second source region;
performing source metal precipitation on the source region metal hole to form a source metal region;
s5 comprises the following steps: generating the fifth barrier layer on the oxide layer again, etching the fifth barrier layer, and generating a gate hole on the gate insulation region;
and generating the gate metal area by performing gate metal deposition on the gate insulation hole.
The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise: the structure is provided with two source electrode structures which are nested inside and outside, and the two source electrode structures which are nested inside and outside can shunt the source electrode of the MOSFET power device, so that the current density of the source electrode is reduced; the grid structure is arranged into a ring shape to form an inner ring PN junction and an outer ring PN junction which are longitudinally and nested, so that the control of a ring-shaped conductive channel between the inner and outer double wells is realized. The conductive channel is moved to the outside of the device from the traditional center and is designed into an annular structure, so that longitudinal current can be annularly changed, the current flowing area is increased, current concentration is avoided, and the current density in the device is reduced; not only reduces the on-resistance of the device, but also improves the heat dissipation performance of the device.
Drawings
FIG. 1 is a schematic cross-sectional view of a ring gate SiC MOSFET power device provided herein;
FIG. 2 is an enlarged partial view of a ring gate SiCMOS power device;
FIG. 3 isbase:Sub>A cross-sectional A-A and B-B views ofbase:Sub>A ring gate SiC MOSFET power device as provided herein;
FIG. 4 is a schematic view of the current distribution of a ring gate SiC MOSFET power device provided by the present application;
FIG. 5 is a flow chart of a method for manufacturing a ring gate SiC MOSFET power device according to an embodiment of the present application;
FIG. 6 is a schematic cross-sectional view of a device for creating a ring-shaped well structure;
FIG. 7 is a schematic cross-sectional view of a device creating a first source region and a second source region;
FIG. 8 is a schematic cross-sectional view of a device resulting in the formation of gate insulator regions;
FIG. 9 is a schematic cross-sectional view of a device for forming a source metal region;
fig. 10 is a schematic cross-sectional view of a device for forming a gate.
Reference numerals are as follows: the transistor comprises a 1-drain metal layer, a 2-SiC substrate, a 3-drift layer, a 31-annular conducting channel, a 4-well region, a 41-inner well region, a 42-outer well region, a 5-source region, a 51-first source region, a 52-second source region, a 6-grid insulating region, a 7-source metal region, a 71-first source metal region, a 72-second source metal region, an 8-grid, a 91-first barrier layer, a 92-second barrier layer, a 93-third barrier layer, a 94-fourth barrier layer and a 95-fifth barrier layer.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Reference herein to "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
FIG. 1 is a schematic cross-sectional view of a ring gate SiC MOSFET power device provided herein; the semiconductor device comprises a drain metal layer 1, a SiC substrate 2, a drift layer 3, an annular well region 4, a source region 5, a gate insulation region 6, a source metal region 7 and a top gate 8 from bottom to top. The drain metal layer 1 is located at the bottommost part, the silicon carbide SiC substrate 2 is located at the upper part of the drain metal layer 1, the drift layer 3 is further arranged above the SiC substrate 2, and the annular well region 4 and the source region 5 are both arranged at the topmost part of the drift layer 3. Specifically, two annular well regions are arranged at the top of the drift layer 3, and two source regions are respectively arranged in the annular well regions. The two annular well regions are an inner well region 41 and an outer well region 42, the inner well region 41 and the outer well region 42 are concentric circles, a first source region 51 (inner layer) of the MOSFET power device is inside the inner well region 41, and a second source region 52 (outer layer) of the MOSFET power device is inside the outer well region 41.
A source metal region 7 is disposed above each of the first source region 51 and the second source region 52, and a gate 8 is disposed between the source metal regions 7 above the inner well region 41 and the outer well region 42 to form a ring structure. The inner well region 41 forms a first PN junction 91 with the first source region 51 and the outer well region 42 forms a second PN junction 92 with said second source region 52.
As shown in fig. 2, which is a partial enlarged view of a ring-gate SiC MOSFET power device, since the SiC MOSFET power device is structurally configured in a circular shape, the first source region 51 is disposed at the center of the device, and the second source region 52 is configured in a structure surrounding the first source region 51, so that the present application designs the inner well region 41 and the outer well region 42 as concentric circular structures with the same longitudinal depth. The inner well region 41 forms a circular structure in the center of the MOSFET power device to form a first source electrode of the MOSFET power device; the outer well region 42 surrounds the inner well region 41 to form a ring structure, which constitutes a second source of the MOSFET power device.
Since the first source is located at the center, the first source metal region 71 disposed thereabove is also disposed in a circular shape, and the second source metal region 72 disposed annularly above the second source region 52. The inner layer has a smaller well region radius than the outer layer so that a ring-shaped conductive channel 31 is formed between the two well regions, i.e. the drift layer between the first source and the second source.
Above the annular conductive channel 31 is a gate insulating region 6, which is also arranged in a ring-shaped configuration, and the inner and outer sides of the gate insulating region 6 extend laterally over the two annular well regions, respectively, in contact with the two source regions of the MOSFET power device. The gate 8 is located above the gate insulating region 6 and has a level higher than the two source metal regions 7 of the inner layer and the outer layer for realizing the gate control capability.
In the structure of the MOSFET power device, the SiC substrate 2 and the drift layer 3 at the bottom are of a first conductivity type, two well regions and source regions arranged at the topmost layer of the drift layer 3 are of a second conductivity type, and the conductivity of the device can be improved by the arrangement mode of the interval and the inner and outer layers.
As shown in fig. 3, since the SiCMOSFET power device is disposed in a cylindrical shape from a vertical three-dimensional structure, each of the layer regions is disposed in a circular or ring-shaped structure. Cross section 1 isbase:Sub>A cross sectionbase:Sub>A-base:Sub>A (at the gate insulator region 6) in fig. 1 and cross section 2 isbase:Sub>A cross section at the level of the source region 5 and the conduction channel 3 in fig. 1. As can be seen from the cross section 2, the ring-shaped gate structure has a source-gate-source structure and a ring-shaped planar structure alternately distributed left and right. As can be seen from the screenshot 2, the annular conductive channel 31 is located between two well regions, a single cell structure forms two PN junctions nested inside and outside in the longitudinal direction in the radial direction, including a first PN junction 91 formed by the inner well region 41 and the first source region 51 in an annular shape, and a second PN junction 92 formed by the outer well region 42 and the second source region 52 in an annular shape.
In a possible embodiment, two well regions are set as P-type regions, the first PN junction of the inner layer forms a gate control capability for the inner circular source region (first source), and the second PN junction of the outer layer realizes a gate control capability for the outer annular source region (second source). The annular grid between the two PN junctions realizes the control of the conductive channel under the grid of the central circular source region and the outer layer annular source region.
From the longitudinal structure, the two source electrode structures nested inside and outside can shunt the source electrode of the MOSFET power device, and the current density of the source electrode is reduced. The annular grid structure independently forms a grid electrode of the device, and forms an inner annular PN junction and an outer annular PN junction which are longitudinally and nested, so that the control of an annular conducting channel between the inner double well and the outer double well is realized. After the conductive channel is changed into a ring shape, the area for current flowing is increased, and therefore the current density and the on-resistance of the device are reduced. As shown in fig. 4, since the ring-shaped gate structure is adopted, the conduction channel of the ring-shaped gate structure is moved from the center of the conventional device to the outer layer of the device, and the internal current of the device is transferred to the periphery of the device in an operating state, so that heat is generated at the periphery of the device, and the heat dissipation performance of the device is correspondingly improved.
Fig. 5 is a flowchart of a method for manufacturing a ring gate SiC MOSFET power device according to an embodiment of the present application, including the following steps:
s1, arranging a first barrier layer above a drift layer of the MOSFET power device, etching the first barrier layer, and performing ion implantation on an epitaxial layer to generate two ring-shaped well structures on the drift layer.
As shown in fig. 6, there is provided a MOSFET power device including a drain metal layer 1 at the bottom, a SiC substrate 2 located longitudinally above the drain metal layer 1, and a drift layer 3 located longitudinally above the SiC substrate 2. A first barrier layer 91 is provided above the drift layer 3, and etching is performed according to a predetermined requirement, thereby forming a circular hole and a ring hole having the same longitudinal depth above the drift layer 3. The circular hole is located in the center of the MOSFET power device, and the annular hole surrounds the central circular hole. Respectively carrying out ion implantation on the epitaxial layer through the inner circular hole and the outer circular hole to form an inner trap structure and an outer trap structure; the horizontal heights of the inner well structure, the outer well structure and the drift layer are consistent. The inner well structure and the outer well in fig. 1 are circular and ring-shaped structures.
And S2, generating a second barrier layer on the drift layer again, etching, and performing ion implantation on the two ring-shaped well structures to generate a first source region and a second source region.
As shown in fig. 7, a second barrier layer 92 is provided on the drift layer 3, and the inner and outer well structures are etched to form an inner well region 41 having a circular center and an outer well region 42 surrounding the inner well region. The recess formed is an active area hole. Then, ion implantation is performed on the inner well region 41 and the outer well region 42, and a first source region 51 and a second source region 52 are correspondingly formed in the respective recessed portions. The first source region 51 and the second source region 52 are located in the inner and outer well regions, respectively, and are at the same level as the drift layer 3. In the step, two internally and externally surrounded annular PN junctions are formed between the inner well region and the outer well region.
And S3, growing an oxide layer and a third barrier layer above the drift layer in sequence, and forming a gate insulation region by removing deposition through gate insulation.
As shown in fig. 8, an oxide layer (not shown) and a third barrier layer 93 are grown on the level of the drift layer 3, and the third barrier layer 93 is etched, forming gate insulating holes over the annular conductive channel 41 between the inner well region 41 and the outer well region 42. Then, the gate insulating hole is subjected to gate insulating depreciation to form an annular gate insulating region 6. The two ends of the gate insulating region 6 extend laterally over the two annular well regions and contact the two source regions of the MOSFET power device. The purpose of using the oxide layer in this step is to form a barrier layer and protect the sacrificial oxide layer when forming an etching pattern, thereby ensuring the function of the device.
And S4, reforming the fourth barrier layer on the oxide layer, and etching and depositing source metal to form a source metal area.
As shown in fig. 9, a fourth barrier layer 94 is formed over the oxide layer again and etched, forming a source metal hole over the first source region 51 and the second source region 52. A source metal region 7 is then formed by source metal deposition to the source region metal hole. The first source metal region 71 in the center of the device in this step is a circular structure, and the second source metal region 72 in the outer portion is a ring structure.
And S5, reforming the fifth barrier layer on the oxide layer, and etching and depositing the gate metal to form a gate metal area.
As shown in fig. 10, a fifth barrier layer 95 is grown on the oxide layer and etched again to form a gate metal hole in the gate insulating region 6. And then carrying out gate metal deposition on the gate metal hole to generate a gate metal area. The gate metal region is a ring-shaped gate structure located between two source metal regions.
In summary, the SiC MOSFET power device provided by the present application has two source electrode structures nested inside and outside, and can shunt the source electrode of the MOSFET power device; the grid structure is arranged into a ring shape, and the inner part and the outer part of the ring-shaped grid structure are provided with source electrodes of devices. The conductive channel is transferred to the outside of the device from the traditional center and is designed into an annular structure, so that the longitudinal current can be annularly changed, the current concentration is avoided, and the current density in the device is reduced; not only reduces the on-resistance of the device, but also improves the heat dissipation performance of the device.
Claims (10)
1. A ring grid SiC MOSFET power device is characterized by comprising a drain metal layer (1), a silicon carbide SiC substrate (2) located above the drain metal layer (1), a drift layer (3) located above the SiC substrate (2), and two ring-shaped well regions (4) arranged on the drift layer (3), wherein two source regions (5) are respectively arranged in the ring-shaped well regions (4); wherein, inside the inner well region (41) is a first source region (51) of the MOSFET power device, and inside the outer well region (42) is a second source region (52) of the MOSFET power device;
a source metal region (7) is arranged above the first source region (51) and the second source region (52); the grid (8) is arranged between the source metal region (7) above the inner well region (41) and the outer well region (42) to form a ring-shaped structure; the inner well region (41) forms a first PN junction (91) with the first source region (51), and the outer well region (42) forms a second PN junction (92) with the second source region (52).
2. The ring-gate SiC MOSFET power device according to claim 1, characterized in that the inner well region (41) and the outer well region (42) are concentric structures with the same longitudinal depth; the inner well region (41) forms a circular structure in the center of the MOSFET power device to form a first source electrode of the MOSFET power device; the outer well region (42) surrounds the inner well region (41) inside to form a ring structure, and the ring structure forms a second source electrode of the MOSFET power device.
3. The ring-gate SiC MOSFET power device of claim 2, wherein a circular first source metal region (71) is disposed over the first source and a ring-shaped second source metal region (72) is disposed over the second source.
4. The ring-gate SiC MOSFET power device according to claim 3, characterized in that the drift layer (3) between the first source and the second source forms a ring-shaped conducting channel (31).
5. The ring-gate SiC MOSFET power device according to claim 4, wherein a gate insulating region (6) is disposed above the annular conductive channel (31) to form a ring structure, and the inner and outer edges of the gate insulating region (6) laterally extend above the two annular well regions, respectively, to contact the two source regions of the MOSFET power device.
6. The ring-gate SiC MOSFET power device according to claim 5, wherein the gate (8) is located over the gate insulating region (6) forming a ring-shaped planar gate structure.
7. Ring gate SiC MOSFET power device according to one of the claims 1 to 6, wherein the two ring well regions (4) are P-type regions.
8. A method for manufacturing a ring-shaped gate SiC MOSFET power device, which is applied to the ring-shaped plane gate SiC longitudinal MOSFET power device of any one of claims 1 to 7, and is characterized by comprising the following steps:
s1, arranging a first barrier layer above a drift layer of an MOSFET power device, etching the first barrier layer, and performing ion implantation on an epitaxial layer to generate two ring-shaped well structures on the drift layer;
s2, generating a second barrier layer on the drift layer again, etching, and performing ion implantation on the two ring-shaped well structures to generate a first source region and a second source region;
s3, growing an oxide layer and a third barrier layer above the drift layer in sequence, and forming a gate insulation region by removing deposition through gate insulation;
s4, forming a fourth barrier layer on the oxide layer again, and etching and depositing source metal to form a source metal area;
and S5, reforming a fifth barrier layer on the oxide layer, and etching and depositing gate metal to form a gate metal region.
9. The method of fabricating a ring gate SiC MOSFET power device of claim 8, wherein S1 includes: generating a circular hole and an annular hole with the same longitudinal depth above the drift layer; the circular hole is positioned in the center of the MOSFET power device, and the circular hole surrounds the central circular hole;
respectively carrying out ion implantation on the epitaxial layer through the inner circular hole and the outer circular hole to form an inner trap structure and an outer trap structure; the horizontal heights of the inner well structure, the outer well structure and the drift layer are consistent;
s2 comprises the following steps: arranging the second barrier layer on the drift layer, and etching the inner well structure and the outer well structure to form an inner well region with a circular center and an outer well region surrounding the inner well region; the formed depressed part is an active area hole;
and respectively carrying out ion implantation on the inner well region and the outer well region, and correspondingly generating the first source region and the second source region in the respective concave parts.
10. The method of fabricating a ring gate SiC MOSFET power device of claim 9, wherein S3 includes: generating the oxide layer and the third barrier layer on the horizontal plane of the drift layer, etching the third barrier layer, and forming a gate insulation hole above the annular conductive channel between the inner well region and the outer well region;
forming the gate insulating region by performing gate insulation removal deposition on the gate insulating hole; two ends of the grid electrode insulation region transversely extend to the upper parts of the two annular well regions and are in contact with two source regions of the MOSFET power device;
s4 comprises the following steps: forming the fourth barrier layer above the oxide layer again, etching, and forming a source region metal hole above the first source region and the second source region;
forming a source metal region by performing source metal deposition on the source region metal hole;
s5 comprises the following steps: generating the fifth barrier layer on the oxide layer again, etching the fifth barrier layer, and generating a gate metal hole on the gate insulation region;
and carrying out gate metal deposition on the gate metal hole to generate the gate metal area.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51134076A (en) * | 1975-05-15 | 1976-11-20 | Sony Corp | Insultation gate-type field- effect transistor |
| US4376286A (en) * | 1978-10-13 | 1983-03-08 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
| CN1366710A (en) * | 2000-04-06 | 2002-08-28 | Apd半导体公司 | Method of fabricating power rectifier device to vary operating parameters and resulting device |
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- 2023-03-20 CN CN202310266260.2A patent/CN115985956B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51134076A (en) * | 1975-05-15 | 1976-11-20 | Sony Corp | Insultation gate-type field- effect transistor |
| US4376286A (en) * | 1978-10-13 | 1983-03-08 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
| US4376286B1 (en) * | 1978-10-13 | 1993-07-20 | Int Rectifier Corp | |
| CN1366710A (en) * | 2000-04-06 | 2002-08-28 | Apd半导体公司 | Method of fabricating power rectifier device to vary operating parameters and resulting device |
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