CN115985956B - Annular grid SiC MOSFET power device and manufacturing method - Google Patents

Abstract

The invention discloses an annular grid SiC MOSFET power device and a manufacturing method thereof, which relate to the technical field of semiconductors and comprise a drain electrode metal layer, a SiC substrate, a drift layer and two annular well regions arranged on the drift layer, wherein the two annular well regions are respectively arranged in the annular well regions; the inner part of the inner well region is a first source region of the MOSFET power device, and the inner part of the outer well region is a second source region of the MOSFET power device; a source metal region is arranged above the first source region and the second source region; the grid electrode is arranged between the source electrode metal region above the inner well region and the outer well region; the inner well region and the first source region form a first PN junction, and the outer well region and the second source region form a second PN junction. The conducting channel formed by the device is of a structure surrounding the grid electrode, so that longitudinal current distribution is annular, current concentration is avoided, current density in the device is reduced, current distribution in the device is improved, current concentration in the device is reduced, and on-resistance of the device is reduced.

Description

Annular grid SiC MOSFET power device and manufacturing method

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a ring-shaped grid SiC MOSFET power device and a manufacturing method thereof.

Background

Silicon carbide SiC materials are widely studied and paid attention to because of their excellent physical properties. The high-temperature high-power electronic device has the advantages of high input impedance, high switching speed, high working frequency, high temperature and high pressure resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high-frequency heating, automobile electronics, power amplifiers and the like.

However, in the related art, the gate drain electrode and the source electrode of the common SiC device are concentrated internally, there is a situation that the current is concentrated in the device, the current density of a partial area is high, and the partial area has no current, which has some influence on the performance of the device. In addition, because the conducting channels of the traditional MOS tube device are all in the central area, the current of the device is distributed inside, and the heat dissipation is not easy.

Disclosure of Invention

The application provides a ring-shaped grid SiC MOSFET power device and a manufacturing method thereof, which solve the problems of uneven current density distribution and difficult heat dissipation of a semiconductor device.

On one hand, the application provides an annular grid SiC MOSFET power device which comprises a drain electrode metal layer, a silicon carbide SiC substrate positioned above the drain electrode metal layer, a drift layer positioned above the SiC substrate, and two annular well regions arranged on the drift layer, wherein the two annular well regions are respectively arranged in the annular well regions; the inner part of the inner well region is a first source region of the MOSFET power device, and the inner part of the outer well region is a second source region of the MOSFET power device;

a source metal region is arranged above the first source region and the second source region; the grid electrode is arranged between the source electrode metal region above the inner well region and the outer well region to form an annular structure; the inner well region and the first source region form a first PN junction, and the outer well region and the second source region form a second PN junction.

Specifically, the inner well region and the outer well region are of concentric circle structures, and the longitudinal depths are the same; the inner well region forms a circular structure at the center of the MOSFET power device to form a first source electrode of the MOSFET power device; and the outer well region surrounds the inner well region inside to form a ring structure so as to form a second source electrode of the MOSFET power device.

Specifically, a circular first source metal region is arranged above the first source electrode, and a circular second source metal region is arranged above the second source electrode.

Specifically, the drift layer between the first source and the second source forms a circular conductive channel.

Specifically, a gate insulating region is arranged above the annular conducting channel to form an annular structure, and the inner side and the outer side of the gate insulating region transversely extend to the upper parts of the two annular well regions respectively and are in contact with the two source regions of the MOSFET power device.

Specifically, the gate is located above the gate insulation region to form a ring-shaped planar gate structure.

Specifically, the two annular well regions are P-type regions.

On the other hand, the application provides a manufacturing method of the annular grid SiC MOSFET power device, which is used for the annular plane grid SiC vertical MOSFET power device in the aspect, and comprises the following steps:

s1, a first barrier layer is arranged above a drift layer of a MOSFET power device, and two annular well structures are generated on the drift layer by etching the first barrier layer and performing ion implantation on an epitaxial layer;

s2, generating a second barrier layer on the drift layer again, etching the second barrier layer, and performing ion implantation on the two annular well structures to generate a first source region and a second source region;

s3, growing an oxide layer and a third barrier layer above the drift layer in sequence, and removing deposition through gate insulation to form a gate insulation region;

s4, re-forming a fourth barrier layer on the oxide layer, and etching and source metal deposition are carried out to form a source metal region;

s5, re-forming a fifth barrier layer on the oxide layer, and etching and depositing gate metal to form a gate metal region.

Specifically, S1 includes: generating a circular hole and an annular hole with the same longitudinal depth above the drift layer; the circular hole is positioned at the center of the MOSFET power device, and the annular hole surrounds the circular hole at the center;

performing ion implantation on the epitaxial layer through the inner circular hole and the outer annular hole respectively to form an inner well structure and an outer well structure; the horizontal heights of the inner well structure, the outer well structure and the drift layer are consistent;

s2 comprises the following steps: the second barrier layer is arranged on the drift layer, and the inner well structure and the outer well structure are etched to form an inner well region with a round center and an outer well region surrounding the inner well region; the formed concave part is an active area hole;

and respectively carrying out ion implantation on the inner well region and the outer well region, and correspondingly generating the first source region and the second source region in the respective concave parts.

Specifically, S3 includes: generating the oxide layer and the third barrier layer on the horizontal plane of the drift layer, etching the third barrier layer, and forming a gate insulation hole above an annular conductive channel between the inner well region and the outer well region;

forming the gate insulating region by performing gate insulation to remove the precipitate from the gate insulating hole; and two ends of the gate insulation region transversely extend to the upper parts of the two annular well regions and are in contact with two source regions of the MOSFET power device.

S4 comprises the following steps: re-forming the fourth barrier layer over the oxide layer and etching to form source metal holes over the first source region and the second source region;

forming a source metal region by performing source metal precipitation on the source metal hole;

s5 comprises the following steps: re-forming the fifth barrier layer on the oxide layer and etching to form a gate hole on the gate insulating region;

the gate metal region is created by gate metal deposition of the gate insulating hole.

The beneficial effects that technical scheme that this application embodiment provided include at least: the structure is provided with two source electrode structures which are nested inside and outside, and the two source electrode structures which are nested inside and outside can shunt the source electrode of the MOSFET power device, so that the current density of the source electrode is reduced; the grid structure is arranged in a ring shape, so that two ring PN junctions which are longitudinally arranged inside and outside and are distributed in a nested manner are formed, and the control of the ring-shaped conducting channel between the inner well and the outer well is realized. The conductive channel is migrated from the traditional center to the outside of the device and is designed into an annular structure, so that longitudinal current can be changed into an annular shape, the current flowing area is increased, current concentration is avoided, and the current density in the device is reduced; not only reduces the on-resistance of the device, but also improves the heat dissipation performance of the device.

Drawings

Fig. 1 is a schematic cross-sectional view of a ring gate SiC MOSFET power device provided herein;

FIG. 2 is a partial enlarged view of a ring gate SiC MOSFET power device;

FIG. 3 is a cross-sectional view of A-A and B-B of a ring gate SiC MOSFET power device provided herein;

fig. 4 is a schematic diagram of current distribution of a circular gate SiC MOSFET power device provided herein;

fig. 5 is a flowchart of a method for manufacturing a ring gate SiC MOSFET power device according to an embodiment of the present application;

FIG. 6 is a schematic cross-sectional view of a device creating a ring-shaped well structure;

FIG. 7 is a schematic cross-sectional view of a device creating a first source region and a second source region;

FIG. 8 is a schematic cross-sectional view of a device resulting in the formation of a gate insulation region;

FIG. 9 is a schematic cross-sectional view of a device forming a source metal region;

fig. 10 is a schematic cross-sectional view of a device in which a gate is formed.

Reference numerals: 1-drain metal layer, 2-SiC substrate, 3-drift layer, 31-annular conductive channel, 4-well region, 41-inner well region, 42-outer well region, 5-source region, 51-first source region, 52-second source region, 6-gate insulation region, 7-source metal region, 71-first source metal region, 72-second source metal region, 8-gate, 910-first barrier layer, 920-second barrier layer, 930-third barrier layer, 940-fourth barrier layer, 950-fifth barrier layer.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

References herein to "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

Fig. 1 is a schematic cross-sectional view of a ring gate SiC MOSFET power device provided herein; the semiconductor device comprises, from bottom to top, a drain metal layer 1, a SiC substrate 2, a drift layer 3, a ring-shaped well region 4, a source region 5, a gate insulation region 6 and a source metal region 7, and a top gate electrode 8. The drain metal layer 1 is located at the bottommost part, the silicon carbide SiC substrate 2 is located at the upper part of the drain metal layer 1, the drift layer 3 is further arranged above the SiC substrate 2, and the annular well region 4 and the source region 5 are both arranged at the topmost part of the drift layer 3. Specifically, two annular well regions are provided on top of the drift layer 3, and two source regions are respectively provided inside the annular well regions. The two annular well regions are divided into an inner well region 41 and an outer well region 42, the inner well region 41 and the outer well region 42 are in a concentric circle structure, a first source region 51 (inner layer) of the MOSFET power device is arranged inside the inner well region 41, and a second source region 52 (outer layer) of the MOSFET power device is arranged inside the outer well region 42.

Source metal regions 7 are respectively arranged above the first source region 51 and the second source region 52, and a grid electrode 8 is arranged between the source metal regions 7 above the inner well region 41 and the outer well region 42 to form a ring-shaped structure. The inner well region 41 forms a first PN junction 91 with the first source region 51, and the outer well region 42 forms a second PN junction 92 with the second source region 52.

As shown in fig. 2, which is a partial enlarged view of a ring gate SiC MOSFET power device, since the SiC MOSFET power device is structurally configured in a circular shape, the first source region 51 is disposed at a device center position, and the second source region 52 is configured to surround the first source region 51, so that the present application designs the inner well region 41 and the outer well region 42 in a concentric circular structure with the same longitudinal depth. The inner well region 41 forms a circular structure in the center of the MOSFET power device to form a first source electrode of the MOSFET power device; the outer well region 42 encloses the inner well region 41 inside to form a ring structure, constituting a second source of the MOSFET power device.

Because the first source is centered, the first source metal region 71 disposed above it is also disposed as a circle, while the annular second source metal region 72 is disposed above the annular second source region 52. The inner well region has a smaller radius than the outer well region, so that a drift layer between the two well regions, i.e. between the first source and the second source, forms a circular conductive channel 31.

Above the annular conductive channel 31 is a gate insulation region 6, which is also arranged in an annular configuration, and the inner and outer sides of the gate insulation region 6 extend laterally over two annular well regions, respectively, in contact with two source regions of the MOSFET power device. The gate electrode 8 is located above the gate insulating region 6 and has a level higher than the levels of the two source metal regions 7 of the inner and outer layers for achieving gate control capability.

In the MOSFET power device structure, the SiC substrate 2 and the drift layer 3 at the bottom are of a first conductivity type, and the two well regions and the source region arranged at the topmost layer of the drift layer 3 are of a second conductivity type, so that the conductivity of the device can be improved by arranging the interval and the inner and outer layers.

As shown in fig. 3, since the SiC MOSFET power device is arranged in a cylindrical shape from a longitudinal perspective, each layer region is arranged in a circular or annular structure. Section 1 is a cross-sectional view of A-A (located in gate insulation region 6) in fig. 1 and section 2 is a cross-sectional view of B-B (located in source region 5 and conductive channel 31 region) in fig. 1. As can be seen from the cross section 2, the circular gate structure has a source-gate-source structure, and has a circular planar structure alternately distributed from left to right. As can be seen from fig. 2, the annular conductive channel 31 is located between two well regions, and the single cell structure forms two PN junctions nested inside and outside longitudinally in the radial direction, including a first PN junction 91 formed by the inner well region 41 and the first source region 51 in an annular shape, and a second PN junction 92 formed by the outer well region 42 and the second source region 52 in an annular shape.

In one possible implementation, two well regions are provided as P-type regions, the first PN junction of the inner layer forming a gate control capability for the inner circular source region (first source) and the second PN junction of the outer layer forming a gate control capability for the outer annular source region (second source). The annular gate between the two PN junctions realizes the control of the conductive channel under the gate of the central circular source region and the outer annular source region.

From the longitudinal structure, the two source electrode structures nested inside and outside can shunt the source electrode of the MOSFET power device, and the current density of the source electrode is reduced. The annular grid structure independently forms a grid of the device, forms two annular PN junctions which are longitudinally and nestedly distributed inside and outside, and realizes the control of an annular conductive channel between the inner well and the outer well. After the conductive channel becomes annular, the area of current flow is increased, thereby reducing the current density and on-resistance of the device. As shown in fig. 4, since the ring gate structure is adopted, the conductive channel moves from the center of the traditional device to the outer layer of the device, and the internal current of the device is migrated to the periphery of the device in the working state, so that heat is generated at the periphery of the device, and therefore, the heat dissipation performance of the device is correspondingly improved.

Fig. 5 is a flowchart of a method for manufacturing a ring gate SiC MOSFET power device according to an embodiment of the present application, including the following steps:

s1, a first barrier layer is arranged above a drift layer of a MOSFET power device, and two annular well structures are generated on the drift layer through etching the first barrier layer and ion implantation of an epitaxial layer.

As shown in fig. 6, a MOSFET power device is provided, which includes a drain metal layer 1 at the bottom, a SiC substrate 2 located longitudinally above the drain metal layer 1, and a drift layer 3 located longitudinally above the SiC substrate 2. A first barrier layer 910 is provided above the drift layer 3, etching is performed according to a set requirement, and a circular hole and a ring hole having the same longitudinal depth are formed above the drift layer 3. The circular hole is located in the center of the MOSFET power device and the annular hole surrounds the circular hole in the center. Performing ion implantation on the epitaxial layer through the inner circular hole and the outer annular hole respectively to form an inner well structure and an outer well structure; the level of the inner well structure, the outer well structure and the drift layer are consistent. The inner and outer well structures in fig. 1 are circular and ring-shaped structures.

S2, generating a second barrier layer on the drift layer again, etching the second barrier layer, and performing ion implantation on the two annular well structures to generate a first source region and a second source region.

As shown in fig. 7, a second barrier layer 920 is provided on the drift layer 3, and the inner and outer well structures are etched to form an inner well region 41 having a circular center, and an outer well region 42 surrounding the inner well region. The formed concave part is an active area hole. Then, ion implantation is performed to the inner well region 41 and the outer well region 42, respectively, and the first source region 51 and the second source region 52 are correspondingly generated in the respective recesses. The first source region 51 and the second source region 52 are located in the inner and outer well regions, respectively, and remain at the same level as the drift layer 3. In this step, two ring-shaped PN junctions surrounding the inside and outside are formed between the inner well region and the outer well region.

And S3, growing an oxide layer and a third barrier layer above the drift layer in sequence, and removing deposition through gate insulation to form a gate insulation region.

As shown in fig. 8, an oxide layer (not shown) and a third barrier layer 930 are grown on the horizontal plane of the drift layer 3, and the third barrier layer 930 is etched, forming a gate insulating hole over the annular conductive channel 31 between the inner well region 41 and the outer well region 42. Then, the gate insulating hole is subjected to gate insulation to remove the precipitate, thereby forming a ring-shaped gate insulating region 6. Both ends of the gate insulation region 6 extend laterally over the two annular well regions and are in contact with the two source regions of the MOSFET power device. The purpose of using the oxide layer in this step is to protect the oxide layer during formation of the barrier layer and formation of the etch pattern, ensuring the function of the device.

S4, re-forming a fourth barrier layer on the oxide layer, and etching and source metal deposition are carried out to form a source metal region.

As shown in fig. 9, a fourth barrier layer 940 is formed again over the oxide layer and etched to form source metal holes over the first source region 51 and the second source region 52. Source metal regions 7 are then formed by source metal precipitation of the source metal holes. The first source metal region 71 at the center of the device in this step is a circular structure and the second source metal region 72 at the outer portion is a ring-shaped structure.

S5, re-forming a fifth barrier layer on the oxide layer, and etching and depositing gate metal to form a gate metal region.

As shown in fig. 10, a fifth barrier layer 950 is newly formed on the oxide layer and etched to form a gate metal hole on the gate insulating region 6. And then forming a gate metal region by performing gate metal deposition on the gate metal hole. The gate metal region is a ring-shaped gate structure located between two source metal regions.

In summary, the SiC MOSFET power device provided in the present application has two source structures nested inside and outside in the structure, so that the source of the MOSFET power device can be split; the gate structure is arranged in a ring shape, and the inside and the outside of the ring-shaped gate structure are provided with the source electrode of the device. The conductive channel is migrated from the traditional center to the outside of the device and is designed into an annular structure, so that longitudinal current can be changed into an annular shape, current concentration is avoided, and the current density in the device is reduced; not only reduces the on-resistance of the device, but also improves the heat dissipation performance of the device.

Claims (7)

1. The annular grid SiC MOSFET power device is characterized by comprising a drain metal layer (1), a silicon carbide SiC substrate (2) positioned above the drain metal layer (1), a drift layer (3) positioned above the SiC substrate (2), two annular well regions (4) formed on the drift layer (3), wherein two source regions (5) are respectively arranged inside the annular well regions (4); wherein, the inside of the inner well region (41) is a first source region (51) of the MOSFET power device, and the inside of the outer well region (42) is a second source region (52) of the MOSFET power device;

a source metal region (7) is arranged above the first source region (51) and the second source region (52); the grid electrode (8) is arranged between the inner well region (41) and the source metal region (7) above the outer well region (42) to form a ring-shaped structure; the inner well region (41) and the first source region (51) form a first PN junction (91), and the outer well region (42) and the second source region (52) form a second PN junction (92);

the inner well region (41) and the outer well region (42) are of concentric circle structures, and the longitudinal depth is the same; the inner well region (41) forms a circular structure at the center of the MOSFET power device to form a first source electrode of the MOSFET power device; the outer well region (42) surrounds the inner well region (41) inside to form a ring-shaped structure, so that a second source electrode of the MOSFET power device is formed;

the drift layer (3) between the first source and the second source forms a circular conductive channel (31).

2. The ring gate SiC MOSFET power device of claim 1, wherein a circular first source metal region (71) is disposed over the first source and a ring second source metal region (72) is disposed over the second source.

3. The annular gate SiC MOSFET power device of claim 2, characterized in that a gate insulating region (6) is provided above the annular conductive channel (31) forming an annular structure, and the inner and outer edges of the gate insulating region (6) extend laterally over the two annular well regions, respectively, in contact with the two source regions of the MOSFET power device.

4. A ring gate SiC MOSFET power device according to claim 3, characterized in that the gate (8) is located above the gate insulation region (6) forming a ring shaped planar gate structure.

5. A ring gate SiC MOSFET power device according to any of claims 1-4, characterised in that the two ring-shaped well regions (4) are P-type regions.

6. A method for manufacturing a ring gate SiC MOSFET power device, applied to the ring gate SiC MOSFET power device of any one of claims 1 to 5, comprising:

s1, a first barrier layer is arranged above a drift layer of a MOSFET power device, and two annular well structures are generated on the drift layer by etching the first barrier layer and performing ion implantation on an epitaxial layer;

generating a circular hole and an annular hole with the same longitudinal depth above the drift layer; the circular hole is positioned at the center of the MOSFET power device, and the annular hole surrounds the circular hole at the center;

performing ion implantation on the epitaxial layer through the inner circular hole and the outer annular hole respectively to form an inner well structure and an outer well structure; the horizontal heights of the inner well structure, the outer well structure and the drift layer are consistent;

s2, generating a second barrier layer on the drift layer again, etching the second barrier layer, and performing ion implantation on the two annular well structures to generate a first source region and a second source region;

the second barrier layer is arranged on the drift layer, and the inner well structure and the outer well structure are etched to form an inner well region with a round center and an outer well region surrounding the inner well region; the formed concave part is an active area hole;

respectively carrying out ion implantation on the inner well region and the outer well region, and correspondingly generating the first source region and the second source region at the respective concave parts;

s3, growing an oxide layer and a third barrier layer above the drift layer in sequence, and removing deposition through gate insulation to form a gate insulation region;

generating the oxide layer and the third barrier layer on the horizontal plane of the drift layer, etching the third barrier layer, and forming a gate insulation hole above an annular conductive channel between the inner well region and the outer well region; the inner well region and the outer well region are of concentric circle structures;

forming the gate insulating region by performing gate insulation to remove the precipitate from the gate insulating hole; two ends of the grid insulation region transversely extend to the upper parts of the two annular well regions and are in contact with two source regions of the MOSFET power device;

s4, re-forming a fourth barrier layer on the oxide layer, and etching and source metal deposition are carried out to form a source metal region;

s5, re-forming a fifth barrier layer on the oxide layer, and etching and depositing gate metal to form a gate metal region.

7. The method for manufacturing the annular gate SiC MOSFET power device of claim 6, wherein S4 comprises: re-forming the fourth barrier layer over the oxide layer and etching to form source metal holes over the first source region and the second source region;

forming a source metal region by performing source metal precipitation on the source metal hole;

s5 comprises the following steps: re-forming the fifth barrier layer on the oxide layer and etching the fifth barrier layer, and forming a gate metal hole on the gate insulating region;

the gate metal region is created by gate metal deposition of the gate metal hole.

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