JPS6027191B2 - Insulated gate field effect transistor - Google Patents
Insulated gate field effect transistorInfo
- Publication number
- JPS6027191B2 JPS6027191B2 JP50058316A JP5831675A JPS6027191B2 JP S6027191 B2 JPS6027191 B2 JP S6027191B2 JP 50058316 A JP50058316 A JP 50058316A JP 5831675 A JP5831675 A JP 5831675A JP S6027191 B2 JPS6027191 B2 JP S6027191B2
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- JP
- Japan
- Prior art keywords
- region
- drain
- conductivity type
- base
- facing
- Prior art date
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Description
【発明の詳細な説明】
本発明は絶縁ゲート形電界効果トランジスタ(肌S−F
ET)に係わる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (S-F
ET).
通常の肌S−FETは、第1図に示す如く1の導電形を
有するベース領域となる半導体基体1、例えばP形のシ
リコン基体上に、他の導電形、例えばN形のソース領域
2s及びドレィン領域2dが所要の間隔を保持して例え
ば選択的拡散によって形成され、両領域2s及び2d間
上に両領域2s及び2d上に跨って薄いゲート絶縁膜4
、例えばSi02膜が被看形成され、之の上にゲート電
極5が同様に両領域2s及び2d上にゲート絶縁膜4を
介してその両端が跨る如く形成されて成る。As shown in FIG. 1, a normal skin S-FET has a semiconductor substrate 1 serving as a base region having one conductivity type, for example, a P-type silicon substrate, and a source region 2s having another conductivity type, for example, N-type. A drain region 2d is formed by, for example, selective diffusion with a required spacing, and a thin gate insulating film 4 is formed between both regions 2s and 2d, spanning over both regions 2s and 2d.
For example, a Si02 film is formed under observation, and a gate electrode 5 is similarly formed on both regions 2s and 2d so that both ends of the film straddle the gate insulating film 4.
又、ソース及びドレィン各領域2s及び2d上には、夫
々ソース及びドレイン各電極5s及び5dが被着される
。3は基体1の表面に形成されたSj02のようなゲー
ト絶縁膜4に比し厚いパツシベーション用の絶縁層であ
る。Furthermore, source and drain electrodes 5s and 5d are deposited on the source and drain regions 2s and 2d, respectively. Reference numeral 3 denotes an insulating layer for passivation, which is thicker than the gate insulating film 4 such as Sj02 formed on the surface of the substrate 1.
このような構成による肌S−FETにおいては、ドレィ
ン電圧が与えられるドレィン領域2dのゲート側の端部
とゲート電極5とが近接対向しているがためにこの部分
、云い換えれば基体1より成るベース領域8のドレィン
側の端縁aとその近傍において電界の集中が生じ、此処
においてブレークダウンが生じその耐圧を低めている。In the skin S-FET having such a configuration, since the gate-side end of the drain region 2d to which the drain voltage is applied and the gate electrode 5 are closely opposed to each other, this portion, in other words, consists of the base body 1. Electric field concentration occurs at and near the edge a on the drain side of the base region 8, and breakdown occurs here, lowering the withstand voltage.
この欠点は、いわゆる2重拡散形のMIS−FETにお
いても生ずる。この2重拡散形のMIS−FETとは、
第2図に示すように、1の導露形の半導体サブストレィ
トー例えばP形のシリコンサブストレィト上に、他の導
電形の低い不純物濃度の半導体層7、例えばN形の抵濃
度シリコン層をェピタキシャル成長し、この半導体層7
の一部に、共通の拡散マスクの拡散窓を通じてベース領
域8と、ソース領域2sとを順次選択的に拡散して形成
して成るものである。この場合、ベース領域8は、半導
体層7と異なる導電形即ちP形を有し、半導体層7を横
切りサブストレイト6に達する深さに拡散して成り、ソ
ース領域2sは、領域8と異る導電形のN形を有し、そ
の拡散の深さはベース領域8の拡散の深さより浅く選ば
れる。かくして半導体層7の他部を低濃度ドレィン領域
2d,とし、更にその一部に高濃度のドレィソ領域2も
を形成して、ベース領域8を挟んでソース領域2sと対
向するドレィン領域2dを形成する。そして、ベース領
域8上にゲート絶縁膜4を形成し之の上にゲート電極5
を形成する。ソース領域2s上にはソース電極5sが被
着され、ドレィン領域2dの高濃度領域2も上にドレィ
ン電極5dが被着される。このような構成による2重拡
散形のMIS−FETは、そのチャンネル長L即ち、ソ
ース及びドレィン各領域2s及び2d間の間隔が、ベー
ス領域8と、ソース領域2sとの拡散の深さの差によっ
て規定されるので、このチャンネル長Lは十分小に且つ
正確に設定できるという利益がある。This drawback also occurs in so-called double diffusion type MIS-FETs. What is this double diffusion type MIS-FET?
As shown in FIG. 2, a low impurity concentration semiconductor layer 7 of another conductivity type, for example an N type silicon substrate, is formed on a semiconductor substrate 1 of a dew conductivity type, for example a P type silicon substrate. This semiconductor layer 7 is grown pitaxially.
A base region 8 and a source region 2s are sequentially and selectively diffused into a portion of the semiconductor device through a diffusion window of a common diffusion mask. In this case, the base region 8 has a conductivity type different from that of the semiconductor layer 7, that is, the P type, and is diffused across the semiconductor layer 7 to a depth reaching the substrate 6, and the source region 2s is different from the region 8. The conductivity type is N type, and its diffusion depth is selected to be shallower than that of the base region 8 . In this way, the other part of the semiconductor layer 7 is made into a lightly doped drain region 2d, and a highly doped drain region 2 is also formed in a part thereof, thereby forming a drain region 2d facing the source region 2s with the base region 8 in between. do. Then, a gate insulating film 4 is formed on the base region 8, and a gate electrode 5 is formed thereon.
form. A source electrode 5s is deposited on the source region 2s, and a drain electrode 5d is deposited on the high concentration region 2 of the drain region 2d. In the double-diffused MIS-FET with such a configuration, the channel length L, that is, the distance between the source and drain regions 2s and 2d, is equal to the difference in diffusion depth between the base region 8 and the source region 2s. Therefore, there is an advantage that this channel length L can be set sufficiently small and accurately.
しかしながらこの場合においても、ベース領域8のドレ
イソ側端緑aにおいて耐圧が破れ易いという欠点がある
。本発明は、このような欠点を回避したMIS−FET
を提供するものである。However, even in this case, there is a drawback that the withstand voltage is likely to be broken at the drain side end green a of the base region 8. The present invention provides a MIS-FET that avoids such drawbacks.
It provides:
本発明の理解を容易にするために第3図及び第4図を参
照にして説明する。In order to facilitate understanding of the present invention, the present invention will be explained with reference to FIGS. 3 and 4.
本発明においては、1の導電形を有する半導体基体、例
えばN形のシリコン基体10を設ける。In the present invention, a semiconductor substrate 10 having one conductivity type, for example, an N-type silicon substrate 10 is provided.
この基体1川ま、高濃度ドレィン領域12d2を構成す
るN形の高濃度シリコン層と、之の上に低濃度ドレィン
領域12d,を形成する同様にN形の低濃度シリコン層
を有して成る。基体10の表面には、Si02のような
、例えば拡散マスクとして用いることができるパッシベ
ーション用の絶縁層13が被着されている。そして、こ
の絶縁層13の一部には拡散窓を開け、この拡散窓を通
じて、両領域12d,及び12もより成るドレイン領域
12dと異なる導電形、例えばP形を有するベース領域
18と、之の上にこの領域18より浅く且つ之とは異る
導電形則ちN形のソース領域12sを夫々少くとも位置
aに面して同一マスク端の2重拡散によって順次形成す
る。This base body 1 has an N-type high concentration silicon layer forming a high concentration drain region 12d2, and a similarly N type low concentration silicon layer forming a low concentration drain region 12d thereon. . A passivation insulating layer 13, such as Si02, which can be used as a diffusion mask, for example, is deposited on the surface of the base body 10. A diffusion window is formed in a part of this insulating layer 13, and through this diffusion window, both regions 12d and the base region 18 having a conductivity type different from that of the drain region 12d consisting of 12, for example P type, are formed. Above, source regions 12s of a conductivity type different from this region 18, that is, N type, which are shallower than this region 18 and facing at least the position a, are successively formed by double diffusion at the edge of the same mask.
かくして、基体10の一方の主面10aに臨んでドレィ
ン領域12dと、ソース領域12sと、両領域12d及
び12s間にベース領域18とが配列される。そして、
之等領域12d,12s及び18が臨む基体10の表面
10aに臨んで、ベース領域18のゲート絶縁膜14と
ゲート電極15とを有して成るゲート部のドレィン側の
端縁aと所要の間隔1を保持して全端緑aに渡って対向
する如く「ベース領域18と同導電形の領域17を、例
えばリング状に選択的拡散によって形成する。Thus, facing one main surface 10a of the base body 10, the drain region 12d, the source region 12s, and the base region 18 are arranged between the two regions 12d and 12s. and,
Facing the surface 10a of the base body 10 facing the equal regions 12d, 12s, and 18, a required distance from the edge a on the drain side of the gate portion comprising the gate insulating film 14 of the base region 18 and the gate electrode 15. A region 17 having the same conductivity type as the base region 18 is formed, for example, in a ring shape by selective diffusion so as to hold 1 and face each other across the entire green a.
ベース領域18上には、例えばSi02より成るゲート
絶縁膜14を形成し「之の上にゲート電極15を被着す
る。又、ソース領域12s上にはソース電極15sをオ
ーミックに被着すると共に、領域17上にも電極19を
オーミツクに被着し、両電極15s及び19を電気的に
接続する。尚、ベース領域18とソース領域12sとは
、その−部において電気的に短絡する。この短絡は、例
えば、ソース領域12sの一部を貫通する如く基体表面
のソース電極15s下に露出するようにすることによっ
て行い得る。G及びSはゲート端子及びソース端子を示
す。そして、ドレイン端子Dは、例えば図示のようにド
レィンの高濃度領域12もにドレィン電極15dをオー
ミツクに被着して、之より導出するとか、或いは電極1
5dを設けて若しくは設けることなく図示しないが、例
えばへツダー上に基体10を、その領域i2もをへッダ
ーに電気的にコンタクトするように例えば蝋付けによっ
て取着し、このへッダーより端子○の導出を行うことも
できる。A gate insulating film 14 made of Si02, for example, is formed on the base region 18, and a gate electrode 15 is deposited thereon. Also, a source electrode 15s is ohmically deposited on the source region 12s, and An electrode 19 is also ohmicly deposited on the region 17, and both the electrodes 15s and 19 are electrically connected.The base region 18 and the source region 12s are electrically short-circuited at the negative part. This can be done, for example, by penetrating a part of the source region 12s and exposing it below the source electrode 15s on the surface of the substrate.G and S indicate a gate terminal and a source terminal.The drain terminal D is For example, as shown in the figure, the drain electrode 15d may be ohmicly applied to the drain high concentration region 12, or the drain electrode 15d may be led out from the drain electrode 15d.
Although not shown in the drawings, with or without 5d, for example, the base 10 is mounted on a header by brazing, for example, so that its area i2 is also in electrical contact with the header, and a terminal ○ is connected to the header from the header. It is also possible to derive
上述の第3図及び第4図では、ベース領域18とは別の
領域17を設けた場合であるが、本発明においては、こ
のような領域17を特設することなく、第5図に示すよ
うに、ベース領域98と之の上に形成するソース領域1
2sとを夫々リング状パターンに形成し、ベース領域1
8のゲート絶縁膜14及びゲート電極15を有するゲー
ト部のドレィン側の端縁aが互にその一部に間隔1を以
つて対向するようになすこともできる。In the above-mentioned FIGS. 3 and 4, a region 17 separate from the base region 18 is provided, but in the present invention, such a region 17 is not specially provided, and as shown in FIG. In addition, a source region 1 is formed over the base region 98.
2s are formed in a ring-shaped pattern, and the base region 1
The edges a on the drain side of the gate portion having the gate insulating film 14 and the gate electrode 15 of 8 may be partially opposed to each other with an interval of 1.
或いは、例えば第7図に示すように領域18と之の上に
形成する領域12sを面10a側からみてメッシュ状パ
ターンとなし、そのメッシュの網目内にドレィン領域1
2dが臨むようになすこともできるし「複数(例えば2
つ)の帯状パターンとなして互に対向させて構成するこ
ともできる。尚、第5図に示した例では、互に対向する
べ一ス領域18上に共通のゲート絶縁膜14とゲート電
極15を差し渡って設けた場合であるが、各ベース領域
のパターンに沿ってリング状、メッシュ状、帯状等にゲ
ート絶縁膜14とゲート電極15を形成することもでき
る。Alternatively, as shown in FIG. 7, for example, the region 12s formed above the region 18 may be formed into a mesh pattern when viewed from the surface 10a side, and the drain region 1 may be formed within the mesh.
You can also make it so that 2d is facing you, or you can make it so that 2d faces
It is also possible to form two band-like patterns and make them face each other. In the example shown in FIG. 5, the common gate insulating film 14 and gate electrode 15 are provided across the base regions 18 facing each other, but the common gate insulating film 14 and gate electrode 15 are provided along the pattern of each base region. The gate insulating film 14 and gate electrode 15 can also be formed in a ring shape, a mesh shape, a band shape, or the like.
そして、特に本発明においては、いずれの例においても
、互に対向する領域18間或いは領域18及び17間の
間隔1は、各領域18及び17とドレィン領域12d,
との間のPN接合J及びJsよりの空乏層の拡がりが、
様縁aにおけるブレークダウン電圧以下で互に蓮らなる
ように則ちピンチオフするような間隔に選定する。Particularly in the present invention, in any case, the distance 1 between the regions 18 facing each other or between the regions 18 and 17 is the distance between each region 18 and 17 and the drain region 12d,
The expansion of the depletion layer from the PN junction J and Js between
The spacing is selected so that they are pinched off to each other below the breakdown voltage at the edge a.
上述の本発明構成によるMIS−FETは、その等価回
路が第6図に示す如くなる。The equivalent circuit of the MIS-FET according to the configuration of the present invention described above is shown in FIG.
即ちゲート絶縁膜14とゲート電極15を有する絶縁ゲ
ートを有するMIS−FETのドレイン側に互に対向す
る領域18同志或いは領域18と17とをゲート領域と
する云わば接合形FET(J−FET)がカスコード接
続された構成となる。上述したような本発明構成によれ
ば、MIS−FETのゲート部のドレィン側の表面の電
位例えば、第4図及び第6図における点Poの電位は、
その両側の接合J及びJs、又はJ同志よりの空乏層に
よってピンチオフされることによって則ちJ−FETが
ピンチオフされることによって、或いはピンチオフに近
ず〈にしたがって、ドレイソ領域12dの高濃度領域1
2も側より与えられるドレイン電圧の影響が遮断若しく
は緩和されるので、端縁aにかかる電界が、この部分に
おいてブレークダウンに至るような電界となるを回避で
き耐圧が向上する。That is, it is a so-called junction FET (J-FET) in which the gate regions are regions 18 or regions 18 and 17 facing each other on the drain side of a MIS-FET having an insulated gate having a gate insulating film 14 and a gate electrode 15. are connected in cascode. According to the configuration of the present invention as described above, the potential on the drain side surface of the gate portion of the MIS-FET, for example, the potential at point Po in FIGS. 4 and 6 is:
By being pinched off by the junctions J and Js on both sides, or by the depletion layer from the J-FET, or by the J-FET being pinched off, or close to being pinched off, the high concentration region 1 of the drain isolation region 12d
Since the influence of the drain voltage applied from the side 2 is blocked or alleviated, the electric field applied to the edge a can be prevented from becoming an electric field that would lead to breakdown in this portion, and the withstand voltage is improved.
又、上述の本発明構成によれば、J−FETがカスコー
ド接続されて付加されたと等価となることによって帰還
容量Cdgが小となり、周波数特性を向上でき、高周波
用として好適なるものである。Further, according to the above-described configuration of the present invention, the feedback capacitance Cdg is reduced because it is equivalent to adding a J-FET connected in cascode, and the frequency characteristics can be improved, making it suitable for high frequency applications.
又、上述したようにドレイン端子Dを基体10の裏面側
からとり出すことによって、一定面積に於けるチャンネ
ルのべリフェリ長(チャンネル中)を大とすることがで
き、また、MIS−FETのドレィン、すなわちJ−F
ETのチャンネル部を挟んでその両側から電流が流れる
構成としたことによって大電流用として好適となるもの
である。In addition, as described above, by taking out the drain terminal D from the back side of the base 10, the verifiability length of the channel (in the channel) in a certain area can be increased, and the drain terminal D of the MIS-FET can be increased. , i.e. J-F
The configuration in which current flows from both sides of the ET channel section makes it suitable for use with large currents.
更にドレィン電流は基体10の厚み方向に流れるもので
、表面近傍に流れる電流量が小さくされることによって
電気的強度が増し、大電流用として好適となる。尚、第
3図及び第4図に示すように例えば領域17に対する電
極19を絶縁層13を介して接合Jsの、ベース領域1
8と対向する側とは反対側の端緑上に張り出すように形
成するときは、この電極19に与えられる電位によって
この接合Jsの外側の端緑より広がるN形基体10の表
面10aにおける空乏層の中を増大させることができ、
この接合Jsの表面耐圧を高める効果を奏することがで
きる。Furthermore, the drain current flows in the thickness direction of the base 10, and by reducing the amount of current flowing near the surface, the electrical strength increases, making it suitable for use with large currents. Incidentally, as shown in FIGS. 3 and 4, for example, the electrode 19 for the region 17 is connected to the base region 1 of the bonding Js via the insulating layer 13.
8, the potential applied to this electrode 19 causes a depletion in the surface 10a of the N-type substrate 10 that spreads from the outer edge of the junction Js. The inside of the layer can be increased,
This can have the effect of increasing the surface breakdown voltage of the joint Js.
又、第5図に示す如くベース領域18の外側を全体的に
とり囲んで(第3図及び第4図の例に適用する場合は領
域17の更に外側をとり囲んで)に領域18及び17と
同導電形の周知の高耐圧化用ガードリング領域20を1
重若しくは図示しないが多重に設けるときは、各接合J
s,Jの互に対向する側とは反対側の外側の耐圧の向上
をはかることもできる。Further, as shown in FIG. 5, areas 18 and 17 are formed by surrounding the entire outside of the base area 18 (if applied to the examples in FIGS. 3 and 4, surrounding the area 17 further outside). The well-known guard ring region 20 for high withstand voltage of the same conductivity type is
When installing multiple joints (not shown), each joint J
It is also possible to improve the withstand voltage on the outer side opposite to the mutually opposing sides of s and J.
尚、上述した例は、基体10の一主面より成る表面に各
領域12s,18,12dの各一部が配列された場合で
あるが、例えば基体10に溝を形成し、この構内の表面
に各領域又は一部の領域が臨むようになされた構成とす
ることもできる。In the above example, a portion of each region 12s, 18, 12d is arranged on the surface of one main surface of the base 10, but for example, grooves may be formed in the base 10 and the surface of this area It is also possible to adopt a configuration in which each area or a part of the area faces the area.
又、上述した例は、本発明を単体のNチャンネル形のM
IS−FETに適用した場合であるが、Pチャンネル形
のMIS一FETに適用することもできる。Moreover, the above-mentioned example shows that the present invention can be applied to a single N-channel type M
Although this example is applied to an IS-FET, it can also be applied to a P-channel MIS-FET.
第1図及び第2図は夫々従来のMIS−FETの拡大断
面図、第3図及び第4図は本発明の説明に供するMIS
−FETの一例の拡大平面図及びその断面図「第5図及
び第7図は本発明によるMIS−FETの他の例の拡大
断面図「第6図はその等価回路図である。
12sはソース領域、18はベース領域、17はこの領
域18と同導電形の領域、12dはドレイン領域、12
d,はその低濃度領域、12d2はその高濃度領域、1
4はゲート絶縁膜、15はゲート電極である。
第1図
第2図
第4図
第3図
第5図
第6図
図
ト
縦FIGS. 1 and 2 are enlarged sectional views of conventional MIS-FETs, and FIGS. 3 and 4 are MIS-FETs used to explain the present invention.
- An enlarged plan view and a cross-sectional view of an example of an FET; FIGS. 5 and 7 are an enlarged cross-sectional view of another example of a MIS-FET according to the present invention. FIG. 6 is an equivalent circuit diagram thereof. 12s is a source 18 is a base region, 17 is a region of the same conductivity type as this region 18, 12d is a drain region, 12
d, is its low concentration region, 12d2 is its high concentration region, 1
4 is a gate insulating film, and 15 is a gate electrode. Figure 1 Figure 2 Figure 4 Figure 3 Figure 5 Figure 6
Claims (1)
1主面に臨む第2導電型の第1領域と、該第1領域中に
あり上記第1主面に臨む第1導電型の第2領域と、上記
第1領域及び第2領域に接続されたソース電極と、上記
半導体基体の第2主面に接続されたドレイン電極とを具
備し、上記第1領域及び第2領域は、上記第1主面に臨
む上記半導体基体領域よりなる第3領域を囲む閉じた形
状の部分を有し、上記第1領域の部分及び第3領域上に
差し渡り、絶縁層を介して設けられたゲート電極を具備
し、上記第3領域の幅は、第1領域及び上記基体領域間
の接合から延びる空乏層がプレークダウン電圧以下の逆
バイアス電圧でみたすような大きさである絶縁ゲート形
電界効果トランジスタ。1 having a semiconductor substrate of a first conductivity type, a first region of a second conductivity type facing the first main surface of the semiconductor substrate, and a first region of the second conductivity type located in the first region facing the first main surface; a second region, a source electrode connected to the first region and the second region, and a drain electrode connected to the second main surface of the semiconductor substrate, the first region and the second region , having a closed-shaped portion surrounding a third region made of the semiconductor substrate region facing the first main surface, extending over the first region and the third region, and provided with an insulating layer interposed therebetween. an insulated gate type electric field, wherein the third region has a width such that a depletion layer extending from the junction between the first region and the base region is filled with a reverse bias voltage equal to or less than a breakdown voltage; effect transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50058316A JPS6027191B2 (en) | 1975-05-15 | 1975-05-15 | Insulated gate field effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50058316A JPS6027191B2 (en) | 1975-05-15 | 1975-05-15 | Insulated gate field effect transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS51134076A JPS51134076A (en) | 1976-11-20 |
JPS6027191B2 true JPS6027191B2 (en) | 1985-06-27 |
Family
ID=13080845
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50058316A Expired JPS6027191B2 (en) | 1975-05-15 | 1975-05-15 | Insulated gate field effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6027191B2 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4055884A (en) * | 1976-12-13 | 1977-11-01 | International Business Machines Corporation | Fabrication of power field effect transistors and the resulting structures |
JPS545674A (en) * | 1977-06-15 | 1979-01-17 | Sony Corp | Semiconductor device |
JPS5424583A (en) * | 1977-07-26 | 1979-02-23 | Victor Co Of Japan Ltd | Mos field effect transistor |
JPS5553462A (en) * | 1978-10-13 | 1980-04-18 | Int Rectifier Corp | Mosfet element |
JPS62122175A (en) * | 1986-08-22 | 1987-06-03 | Nec Corp | Semiconductor device |
EP0689238B1 (en) * | 1994-06-23 | 2002-02-20 | STMicroelectronics S.r.l. | MOS-technology power device manufacturing process |
US5817546A (en) * | 1994-06-23 | 1998-10-06 | Stmicroelectronics S.R.L. | Process of making a MOS-technology power device |
CN115985956B (en) * | 2023-03-20 | 2023-06-13 | 苏州锴威特半导体股份有限公司 | Annular grid SiC MOSFET power device and manufacturing method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4913119A (en) * | 1972-06-05 | 1974-02-05 | ||
JPS5046081A (en) * | 1973-08-28 | 1975-04-24 |
-
1975
- 1975-05-15 JP JP50058316A patent/JPS6027191B2/en not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4913119A (en) * | 1972-06-05 | 1974-02-05 | ||
JPS5046081A (en) * | 1973-08-28 | 1975-04-24 |
Also Published As
Publication number | Publication date |
---|---|
JPS51134076A (en) | 1976-11-20 |
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