CN115966548B

CN115966548B - Inductor and chip

Info

Publication number: CN115966548B
Application number: CN202111091046.5A
Authority: CN
Inventors: 徐洪光; 刘水华
Original assignee: Shanghai Boxincheng Microelectronics Technology Co ltd
Current assignee: Shanghai Boxincheng Microelectronics Technology Co ltd
Priority date: 2021-09-17
Filing date: 2021-09-17
Publication date: 2024-03-12
Anticipated expiration: 2041-09-17
Also published as: CN115966548A

Abstract

The embodiment of the application provides an inductor and a chip, wherein a first insulating layer of a first substrate is arranged between a first conductive layer and a second conductive layer, a first connecting wire in the first conductive layer is electrically connected with a peripheral endpoint of a first conductive coil in the first conductive layer, and a second connecting wire included in the second conductive layer is electrically connected with an inner peripheral endpoint of the first conductive coil; the second insulating layer of the second substrate is arranged between the third conductive layer and the fourth conductive layer, a third connecting wire in the third conductive layer is electrically connected with the peripheral end point of the second conductive coil in the third conductive layer, and a fourth connecting wire included in the fourth conductive layer is electrically connected with the inner peripheral end point of the second conductive coil; wherein the first insulating substrate in the first substrate is located between the third conductive layer and the first conductive layer. The inductor in the application adopts insulation as a substrate, and has the advantages of high preparation efficiency, small process difficulty, high yield and good coupling performance.

Description

Inductor and chip

[ field of technology ]

The present application relates to the field of microelectronics, and more particularly, to an inductor and a chip.

[ background Art ]

Along with the rapid development of the electronic information industry, the updating iteration speed of the electronic product is higher, and the electronic product is developed towards higher and higher speed, microminiaturization and intellectualization, so as to meet the requirements of fast response, low cost, low power consumption, portability and the like of the electronic product in the market. Therefore, the adoption of low-cost and highly integrated electronic components has become a major approach to solving the above problems.

Because of the difficulty and high cost of integrating high performance passive devices, and in particular high performance inductors, how to obtain low cost high performance inductors is a problem in the development of the electronic information industry. Current inductors mainly include discrete inductors, board-level inductors, and on-chip inductors. The discrete inductor is mostly manufactured by adopting a mechanical winding mode to wind a coil and the board-level inductor is based on a printed circuit board, so that the discrete inductor and the board-level inductor are not suitable for the development trend of miniaturization and microminiaturization of electronic products.

On-chip inductors are the preferred electronic components for satisfying the development of the electronic information industry, but on-chip inductors are prepared with monocrystalline silicon as the substrate, on the one hand, the monocrystalline silicon has small resistivity and large relative dielectric constant, and the on-chip inductors have large substrate loss and substrate parasiticsCapacitance and other problems, the performance of the on-chip inductor is seriously affected; on the other hand, most on-chip inductors employ Benzocyclobutene (BCB), polyimide (PI), silicon dioxide (SiO ₂ ) The material is used as an inductance layer material between coils, so that the problems of low breakdown field strength of the inductor and the like are caused.

[ MEANS FOR SOLVING PROBLEMS ]

In view of the foregoing, embodiments of the present application provide an inductor and a chip to solve the above problems.

In a first aspect, embodiments of the present application provide an inductor comprising a first substrate and a second substrate; the first substrate comprises a first insulating substrate, a first conductive layer, a second conductive layer and a first insulating layer arranged between the first conductive layer and the second conductive layer, wherein the first conductive layer comprises a first conductive coil and a first connecting wire, the first connecting wire is electrically connected with the peripheral end point of the first conductive coil, and the second conductive layer comprises a second connecting wire, and the second connecting wire is electrically connected with the inner peripheral end point of the first conductive coil; the second substrate comprises a second insulating substrate, a third conductive layer, a fourth conductive layer and a second insulating layer arranged between the third conductive layer and the fourth conductive layer, wherein the third conductive layer comprises a second conductive coil and a third connecting wire, the third connecting wire is electrically connected with the peripheral end point of the second conductive coil, and the fourth conductive layer comprises a fourth connecting wire, and the fourth connecting wire is electrically connected with the inner peripheral end point of the second conductive coil; the second substrate is arranged on one side of the first substrate, and the first insulating substrate is positioned between the second conductive layer and the first conductive layer.

In one implementation manner of the first aspect, the first insulating substrate is one of glass, ceramic, glass fiber board and polyimide film; the second insulating substrate is one of glass, ceramic, glass fiber board and polyimide film.

In one implementation manner of the first aspect, the thickness of each of the first insulating substrate and the second insulating substrate is less than or equal to 0.5mm.

In one implementation manner of the first aspect, the material of the first conductive layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium, and copper, and the material of the second conductive layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium, and copper; the third conductive layer is made of at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper, and the fourth conductive layer is made of at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper.

In one implementation manner of the first aspect, the thicknesses of the first conductive layer and the third conductive layer are greater than or equal to 600nm.

In one implementation manner of the first aspect, the first conductive coil includes N circles of first conductive wires, where a width of the first conductive wires is less than or equal to 100 μm, and N is greater than or equal to 1; the second conductive coil comprises M circles of second conductive wires, the width of the second conductive wires is less than or equal to 100 mu M, and M is more than or equal to 1.

In one implementation manner of the first aspect, N is greater than or equal to 2, and a minimum distance between adjacent first conductive lines is less than or equal to 100 μm; m is more than or equal to 2, and the minimum distance between the adjacent second conductive wires is less than or equal to 100 mu M.

In one implementation manner of the first aspect, the first conductive coil includes a first spiral coil and a second spiral coil, and the first spiral coil is connected in parallel with the second spiral coil; the second conductive coil comprises a third spiral coil and a fourth spiral coil, and the third spiral coil is connected with the fourth spiral coil in parallel.

In one implementation manner of the first aspect, the first connecting line, the second connecting line, the third connecting line and the fourth connecting line are all of an integral structure.

In an implementation manner of the first aspect, the first conductive layer further includes a first bonding pad, and the first connection line and the second connection line are electrically connected to different first bonding pads respectively; the third conductive layer further comprises a second binding pad, and the third connecting wire and the fourth connecting wire are respectively and electrically connected with different second binding pads.

In one implementation manner of the first aspect, the second conductive layer is disposed on a side of the first conductive layer near the first insulating substrate, the first insulating substrate includes a first scribe line and the second connection line is disposed in the first scribe line; the fourth conducting layer is arranged on one side, close to the second insulating substrate, of the third conducting layer, the second insulating substrate comprises a second notch, and the second connecting line is arranged in the second notch.

In one implementation of the first aspect, the second conductive layer is located on a side of the first conductive layer remote from the first insulating substrate, and the fourth conductive layer is located on a side of the third conductive layer remote from the second insulating substrate.

In one implementation manner of the first aspect, the first conductive layer and the second conductive layer are located on a side of the first insulating substrate away from the second insulating substrate; the third conductive layer and the fourth conductive layer are positioned on one side of the second insulating substrate far away from the first insulating substrate.

In a second aspect, embodiments of the present application provide a chip comprising an inductor as provided in the first aspect.

The substrate of the inductor provided by the embodiment of the application adopts the insulating substrate as the substrate, so that the inductor can be formed by adopting a cutting process of the insulating substrate, and the inductor has the advantages of high preparation efficiency, small process difficulty and high yield of finished products. Compared with the prior art, the insulating substrate is a silicon substrate, so that the cost can be obviously saved, and the substrate loss and the substrate parasitic capacitance can be greatly reduced, so that the coupling performance of the inductor is greatly improved, and the coupling voltage of the inductor can be more than 10000V.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic cross-sectional view of an inductor according to one embodiment of the present application;

FIG. 2 is another cross-sectional schematic diagram of an inductor provided in one embodiment of the present application;

FIG. 3 is a schematic plan view of an inductor according to one embodiment of the present application;

fig. 4 is a schematic cross-sectional view of an inductor according to another embodiment of the present disclosure;

fig. 5 is a schematic cross-sectional view of an inductor according to yet another embodiment of the present disclosure;

fig. 6 is a schematic cross-sectional view of an inductor according to yet another embodiment of the present application;

FIG. 7 is a schematic diagram of a first conductive coil and a second conductive coil in an inductor according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a first conductive coil in an inductor according to another embodiment of the present application;

fig. 9 is a schematic diagram of a second conductive coil in an inductor according to another embodiment of the present disclosure;

fig. 10 is a schematic diagram of a chip according to an embodiment of the present application.

[ detailed description ] of the invention

For a better understanding of the technical solutions of the present application, embodiments of the present application are described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

In the description of the present specification, it is to be understood that the terms "substantially," "approximately," "about," "approximately," "substantially," and the like as used in the claims and examples herein refer to values that are generally agreed upon, rather than exact, within reasonable process operating ranges or tolerances.

It should be understood that although the terms first, second, third, etc. may be used in embodiments of the present application to describe the connection lines, etc., these connection lines, etc. should not be limited to these terms. These terms are only used to distinguish one connection line or the like from another. For example, a first connection line may also be referred to as a second connection line, and similarly, a second connection line may also be referred to as a first connection line, without departing from the scope of embodiments of the present application.

The applicant has provided a solution to the problems existing in the prior art by intensive studies.

Fig. 1 is a schematic cross-sectional view of an inductor according to an embodiment of the present application, fig. 2 is another schematic cross-sectional view of an inductor according to an embodiment of the present application, and fig. 3 is a schematic plan-view exploded view of an inductor according to an embodiment of the present application. It should be noted that fig. 1 and fig. 2 are schematic cross-sectional views of an inductor along cutting lines at different positions

Referring to fig. 1, fig. 2 and fig. 3, the inductor provided in the embodiment of the present application includes a first substrate 10 and a second substrate 20, where the first substrate 10 is located on one side of the second substrate 20, and as shown in fig. 1 and fig. 2, the first substrate 10 is located on an upper side of the second substrate 20.

Referring to fig. 1 and 2, the first substrate 10 includes a first insulating substrate 11, a first conductive layer 12, a second conductive layer 13, and a first insulating layer 14, and the first conductive layer 12, the second conductive layer 13, and the first insulating layer 14 may be located on the same side of the first insulating substrate 11 and the first insulating layer 14 is located between the first conductive layer 12 and the second conductive layer 13.

Further, referring to fig. 1, 2 and 3, the first conductive layer 12 includes a first conductive coil 121 and a first connection line 122, wherein, as shown in fig. 3, the first conductive coil 121 may be a spiral coil, and the first connection line 122 is electrically connected to a peripheral end point of the first conductive coil 121.

Further, referring to fig. 1, 2 and 3, the second conductive layer 13 includes a second connection line 131, where, as shown in fig. 3, the second connection line 131 is electrically connected to an inner peripheral end of the first conductive coil 121.

Referring to fig. 1 and 2, the second substrate 20 includes a second insulating substrate 21, a third conductive layer 22, a fourth conductive layer 23, and a second insulating layer 24, and the third conductive layer 22, the fourth conductive layer 23, and the second insulating layer 24 may be located on the same layer of the second insulating substrate 21 and the second insulating layer 24 is located between the third conductive layer 22 and the fourth conductive layer 23.

Further, referring to fig. 1, 2 and 3, the third conductive layer 22 includes a second conductive coil 221 and a third connection line 222, wherein, as shown in fig. 3, the second conductive coil 221 may be a spiral coil, and the third connection line 222 is electrically connected to a peripheral end point of the second conductive coil 221.

Further, referring to fig. 1, 2 and 3, the fourth conductive layer 23 includes a fourth connection line 231, wherein, as shown in fig. 3, the fourth connection line 231 is electrically connected to an inner peripheral end of the second conductive coil 221.

In the embodiment of the present application, as shown in fig. 1 and 2, the first insulating substrate 11 is located between the third conductive layer 221 and the first conductive layer 121, that is, the first insulating substrate 11 is disposed between the first conductive coil 121 and the second conductive coil 221.

The present embodiment provides a planar inductor in a stacked form of at least two substrates, and the substrates constituting the planar inductor adopt an insulating substrate as a substrate, so that the planar inductor in the present application may be formed by a dicing process of the insulating substrate, for example, the first conductive coil 121/second conductive coil 221, the first connecting line 122/second connecting line 131 arranged in an array may be prepared on a large glass, then the large glass prepared with the first conductive coil 121 and the first connecting line 122 and the large glass prepared with the second conductive coil 221 and the third connecting line 222 are stacked, and then the stacked large glass is diced to form a plurality of inductors.

Because the cost of the insulating substrate with the same area is far lower than that of the silicon-based substrate, the inductor provided by the embodiment of the application adopts the insulating substrate as the substrate, and compared with the prior art which adopts the silicon-based substrate, the cost can be obviously saved. In addition, the embodiment of the application adopts an insulating substrate cutting process, for example, tens of thousands of inductors can be formed by cutting overlapped large glass, thus improving the manufacturing efficiency and reducing the cost. The cost of the inductor provided by the embodiment of the application is about one tenth of the cost of the silicon-based substrate inductor in the prior art.

In addition, in the embodiment of the application, compared with a silicon-based substrate, the insulating substrate has larger resistivity and smaller dielectric constant, so that the substrate loss and the substrate parasitic capacitance can be greatly reduced, and the performance of the inductor is greatly improved.

The insulating layers between adjacent conductive coils of the inductor using the silicon-based substrate in the prior art are generally formed by adopting a thin film deposition technology, and the thickness of the insulating layers is generally in the order of micrometers, so that the limit of isolation voltage of the inductor in the prior art is 6000V. The thickness of the insulating substrate is in millimeter order, and the first insulating substrate 11 is included between the first conductive coil 121 and the second conductive coil 221, so that the inductor has a larger breakdown field strength, and therefore, the isolation voltage of the inductor provided by the embodiment of the application may be greater than 10000V.

In one embodiment of the present application, the first conductive layer 12 further includes a first bonding pad 123, and the first connection line 122 and the second connection line 131 are electrically connected to different first bonding pads 123, respectively. The third conductive layer 22 further includes second bonding pads 223, and the third connection line 222 and the fourth connection line 231 are electrically connected to different second bonding pads 223, respectively.

The first bonding pad 123 and the first conductive coil 121 and the first connecting line 122 may be simultaneously prepared when the first bonding pad 123 and the first conductive layer 12 are arranged in the same layer. The second bonding pad 223 is disposed on the same layer as the third conductive layer 22, and thus the second bonding pad 223 and the second conductive coil 221 and the third connection line 222 may be prepared at the same time.

And the first bonding pad 123 is disposed in a different layer from the second conductive layer 13.

In one implementation, as shown in fig. 1, the second conductive layer 13 is disposed on a side of the first conductive layer 12 away from the first insulating substrate 11, and the second connection line 131 may be electrically connected to the inner peripheral end of the first conductive coil 121 through a via hole in the first insulating layer 14 and may be electrically connected to the first bonding pad 123 through a via hole in the first insulating layer 14.

Fig. 4 is a schematic cross-sectional view of an inductor according to another embodiment of the present application.

In another implementation, as shown in fig. 4, the second conductive layer 13 is disposed on a side of the first conductive layer 12 near the first insulating substrate 11, and the first insulating substrate 11 includes a first scribe line and the second connection line 131 is disposed in the first scribe line.

In addition, in order to ensure that the first conductive layer 12 has a flat bearing surface, the first scribe line needs to be filled with the first insulating layer 14 after the second connection line 131 is prepared in the first scribe line. The inner peripheral end of the first conductive coil 121 and the first bonding pad 123 may be electrically connected to the second connection line 131 through a via hole included in the first insulating layer 14 filled in the first scribe line.

And the second bonding pad 223 is disposed different from the fourth conductive layer 23.

In one implementation, as shown in fig. 1, the fourth conductive layer 23 is disposed on a side of the third conductive layer 22 away from the second insulating substrate 21, and the fourth connection line 231 may be electrically connected to the inner peripheral end of the second conductive coil 221 through a via hole in the second insulating layer 24 and may be electrically connected to the second bonding pad 223 through a via hole in the second insulating layer 24.

In another implementation, as shown in fig. 4, the fourth conductive layer 23 is disposed on a side of the third conductive layer 22 near the second insulating substrate 21, and the second insulating substrate 21 includes a second scribe line and the fourth connection line 231 is disposed in the second scribe line.

In addition, in order to ensure that the third conductive layer 22 has a flat bearing surface, the second scribe line needs to be filled with the second insulating layer 24 after the fourth connection line 231 is prepared in the second scribe line. The inner peripheral end of the second conductive coil 221 and the second bonding pad 223 may be electrically connected to the fourth connection line 231 through a via hole included in the second insulating layer 24 filled in the second scribe line.

Fig. 5 is a schematic cross-sectional view of an inductor according to another embodiment of the present application.

In the embodiment of the present application, as shown in fig. 5, the second conductive layer 13 in the first substrate 10 is located on the side of the first conductive layer 12 away from the first insulating substrate 11, and the fourth conductive layer 23 in the second substrate 20 is located on the second insulating substrate 21 side of the third conductive layer 22. The first conductive coil 121 is located on the side of the second conductive layer 13 adjacent to the second conductive coil 221 and the second conductive coil 221 is located on the side of the fourth conductive layer 23 adjacent to the first conductive coil 121.

I.e. no other conductive layer is included between the first conductive coil 121 and the second conductive coil 221, avoiding that the signal between the first conductive coil 121 and the second conductive coil 221 is protected from the interference of other signal lines.

In a specific embodiment, as shown in fig. 5, the third conductive layer 22 and the fourth conductive layer 23 are disposed between the first insulating substrate 11 and the second insulating substrate 21, and the fourth signal line 231 in the fourth conductive layer 23 is in the scribe line of the second insulating substrate 21.

In one embodiment of the present application, as shown in fig. 1-2 and fig. 4-5, the third conductive layer 22 and the fourth conductive layer 23 are disposed between the first insulating substrate 11 and the second insulating substrate 21.

Fig. 6 is a schematic cross-sectional view of an inductor according to yet another embodiment of the present application.

In another embodiment of the present application, as shown in fig. 6, the first conductive layer 12 and the second conductive layer 13 are located on a side of the first insulating substrate 11 away from the second insulating substrate 21, and the third conductive layer 22 and the fourth conductive layer 23 are located on a side of the second insulating substrate 21 away from the first insulating substrate 11. The first insulating substrate 11 and the second insulating substrate 21 are included between the first conductive layer 12, the second conductive layer 13, the third conductive layer 22, and the fourth conductive layer 23, that is, the first insulating substrate 11 and the second insulating substrate 21 are included between the first conductive coil 121 and the second conductive coil 221, so that the inductor has better coupling performance and larger coupling voltage.

In a specific embodiment, further, as shown in fig. 6, the first conductive layer 12 and the second conductive layer 13 are located on a side of the first insulating substrate 11 away from the second insulating substrate 21, the second conductive layer 13 is located on a side of the first conductive layer 12 away from the first insulating substrate 11, the third conductive layer 22 and the fourth conductive layer 23 are located on a side of the second insulating substrate 21 away from the first insulating substrate 11, and the fourth conductive layer 23 is located on a side of the third conductive layer 22 away from the second insulating substrate 11. The first insulating substrate 11 and the second insulating substrate 21 are included between the first conductive layer 12 and the third conductive layer 22 and the second conductive layer 13 and the fourth conductive layer 23 are not included, that is, the first insulating substrate 11 and the second insulating substrate 21 are included between the first conductive coil 121 and the second conductive coil 221 and the second conductive layer 13 and the fourth conductive layer 23 are not included, so that the inductor has a larger coupling voltage, and signals between the first conductive coil 121 and the second conductive coil 221 are prevented from being interfered by other signal lines.

In one embodiment of the present application, the first insulating substrate 11 is one of glass, ceramic, glass fiber board, polyimide film, and the second insulating substrate 21 is one of glass, ceramic, glass fiber board, polyimide film. Wherein the first insulating substrate 11 and/or the second insulating substrate 21 may be one of aluminum oxide ceramic and epoxy glass fiber board.

Further, the first insulating substrate 11 may be one of alkali-free glass, aluminosilicate glass, soda glass, and the second insulating substrate 21 may be one of alkali-free glass, aluminosilicate glass, soda glass. The glass has the advantages of good chemical stability, electrical insulation, mechanical strength and the like, and further ensures the performance of the inductor provided by the embodiment of the application. The glasses are dimensionally stable, have the ability to fine pitch vias, stability to temperature and humidity, coefficient of Thermal Expansion (CTE) matching the device, and large area low cost availability.

In one embodiment of the present application, the thicknesses of the first insulating substrate 11 and the second insulating substrate 21 are all less than or equal to 0.5mm, for example, the thicknesses of the first insulating substrate 11 and the second insulating substrate 21 are 0.1mm or 0.2mm, and the thicknesses give consideration to the good coupling coefficient and the higher voltage-resistant performance of the device, and meanwhile, the large-area production can be realized, and the cost is reduced.

The material of the first conductive layer 12 is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper, and the material of the second conductive layer 13 is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper; the material of the third conductive layer 22 is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium, and copper, and the material of the fourth conductive layer 23 is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium, and copper.

In a specific embodiment, the materials of the first conductive layer 12, the second conductive layer 13, the third conductive layer 22, and the fourth conductive layer 23 may be the same. The first conductive layer 12, the second conductive layer 12, the third conductive layer 22, and the fourth conductive layer 23 can be prepared in the same film forming apparatus.

In one implementation, the first conductive layer 12, the second conductive layer 13, the third conductive layer 22, and the fourth conductive layer 23 may all be conductive film layers of a single material.

In one implementation, the first conductive layer 12, the second conductive layer 13, the third conductive layer 22, and the fourth conductive layer 23 may be conductive films of various materials, for example, stacked composite films of molybdenum, aluminum, and molybdenum.

In one implementation, portions of the first conductive layer 12, the second conductive layer 13, the third conductive layer 22, and the fourth conductive layer 23 may be conductive films of a single material, and another portion may be conductive films of multiple materials.

In one embodiment of the present application, the thicknesses of the first conductive layer 12 and the third conductive layer 22 are each 600nm or more. Since the first conductive layer 12 and the third conductive layer 22 include the first bonding pad 123 and the second bonding pad 223, respectively, the inventors have found that when the thicknesses of the first bonding pad 123 and the second bonding pad 223 in the thickness direction of the inductor are equal to or greater than 600nm, both have excellent bonding characteristics with the external signal line.

Further, the thicknesses of the second conductive layer 13 and the fourth conductive layer 23 may be 600nm or more.

In one embodiment of the present application, the thickness of the inductor may be about 0.5mm, and the length and width thereof may be about 2mm by 2mm, and the inductor adopting the inventive concept of the present application may also be of a microstructure.

Fig. 7 is a schematic diagram of a first conductive coil and a second conductive coil in an inductor according to an embodiment of the present application.

In one embodiment of the present application, as shown in FIG. 3 and FIG. 7, the first conductive coil 121 includes N turns of the first conductive wire, where N is equal to or greater than 1; and the width of the first conductive line is w1, w1 is 100 μm or less, for example, w1 is 30 μm or less. Wherein, specifically, 20 μm. Gtoreq.w1. Gtoreq.2μm, for example, w1=5μm or w1=15μm. The line width can achieve higher yield and excellent electrical performance.

And the second conductive coil 221 comprises M circles of second conductive wires, wherein M is more than or equal to 1; and the width of the second conductive line is w2, w2 is 100 μm or less, for example, w2 is 30 μm or less. Wherein, in particular, 20 μm.gtoreq.w2.gtoreq.2μm, for example w2=5μm or w2=15μm.

Further, N.gtoreq.2, that is, the first conductive wire 121 includes a plurality of turns of the first conductive wire therein; the minimum distance between adjacent first conductive lines is d1, d1.ltoreq.100. Mu.m, for example d1.ltoreq.30. Mu.m. Wherein, in particular, 20 μm.gtoreq.d1.gtoreq.2μm, for example d1=5μm or d1=15μm.

And M.gtoreq.2, that is, the second conductive wire 221 includes a plurality of turns of the second conductive wire; the minimum distance between adjacent second conductive lines is d2, d2.ltoreq.100 μm, for example d2.ltoreq.30 μm. . Wherein, in particular, 20 μm.gtoreq.d2.gtoreq.2μm, for example d2=5 μm or d2=15 μm.

In one embodiment of the present application, as shown in fig. 3 and 7, the first conductive coil 121 is a spiral coil including at least one turn of a first conductive wire, and the second conductive coil 221 is a spiral coil including at least one turn of a second conductive wire.

Fig. 8 is a schematic diagram of a first conductive coil in an inductor according to another embodiment of the present application, and fig. 9 is a schematic diagram of a second conductive coil in an inductor according to another embodiment of the present application.

As shown in fig. 8, the first conductive coil 121 includes a first spiral coil 121a and a second spiral coil 121b therein, and the first spiral coil 121a is connected in parallel with the second spiral coil 121 b. That is, the first conductive coil 121 is formed by connecting at least two parallel spiral coils in parallel.

Further, the first spiral coil 121a includes a plurality of turns of the first conductive wire, and the second spiral coil 121b includes a plurality of turns of the first conductive wire. Among the plurality of first conductive lines in the first spiral coil 121a, the width of the first conductive line is also w1, and the minimum distance between adjacent first conductive lines is also d1; of the plurality of turns of the first conductive lines in the second spiral coil 121b, the width of the first conductive line is also w1, and the minimum distance between adjacent first conductive lines is also d1.

As shown in fig. 9, the third spiral coil 221a and the fourth spiral coil 221b are included in the second conductive coil 221, and the third spiral coil 221a is connected in parallel with the fourth spiral coil 221 b. That is, the second conductive coil 221 is formed by connecting at least two parallel spiral coils in parallel.

Further, the third spiral coil 221a includes a plurality of turns of the first conductive wire, and the fourth spiral coil 221b includes a plurality of turns of the second conductive wire. In addition, among the plurality of turns of the second conductive wire in the third spiral coil 221a, the width of the second conductive wire is also w2, and the minimum distance between adjacent second conductive wires is also d2; of the plurality of turns of the second conductive wire in the fourth spiral coil 221b, the width of the second conductive wire is also w2, and the minimum distance between adjacent second conductive wires is also d2.

In one implementation, at least two spiral coils of the first conductive coil 121 are electrically connected at an outer peripheral end point and an inner peripheral end point of the first conductive coil 121, respectively.

In one implementation, at least two spiral coils of the second conductive coil 221 are electrically connected at an outer peripheral end point and an inner peripheral end point of the second conductive coil 221, respectively.

The spiral coils are connected in parallel to form the conductive coil, so that the inductance value is further improved, and the coupling performance is improved.

In one embodiment of the present application, the first conductive coil 121 includes a first spiral coil 121a and a second spiral coil 121b connected in parallel, and the second conductive coil 221 includes a third spiral coil 221a and a fourth spiral coil 221b connected in parallel, but the first connection line 122 and the second connection line 131 electrically connected to the first conductive coil 121 are all of an entire structure, and the third connection line 222 and the fourth connection line 231 electrically connected to the second conductive coil 221 are all of an entire structure.

Namely, a first connecting line 122 of continuous whole-surface design is electrically connected with the first spiral coil 121a and the second spiral coil 121b at the same time, and a second connecting line 131 of continuous whole-surface design is electrically connected with the first spiral coil 121a and the second spiral coil 121b at the same time; a third connecting wire 222 of continuous whole-surface design is electrically connected to the third spiral coil 221a and the fourth spiral coil 221b at the same time, and a fourth connecting wire 231 of continuous whole-surface design is electrically connected to the third spiral coil 221a and the fourth spiral coil 221b at the same time.

As shown in fig. 10, the embodiment of the present application further provides a chip 01, where the chip 01 includes the inductor provided in any one of the embodiments above, and in addition, other electronic components, for example, a resistor, a capacitor, and the like, may be further included in the chip 01. The inductor provided by the embodiment of the application and other electronic components can be packaged to form the chip 01 provided by the embodiment of the application.

In the embodiment of the application, the manufacturing process of the inductor is simple and the cost is low, so that the manufacturing difficulty and cost of the chip can be reduced; in addition, the coupling performance of the inductor is obviously improved compared with the prior art, so that the performance of the chip can be obviously improved.

The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. An inductor, comprising:

a first substrate, the first substrate comprising:

a first insulating substrate;

the first conductive layer comprises a first conductive coil and a first connecting wire, and the first connecting wire is electrically connected with a peripheral endpoint of the first conductive coil;

the second conductive layer comprises a second connecting wire, and the second connecting wire is electrically connected with the inner peripheral end point of the first conductive coil;

a first insulating layer disposed between the first conductive layer and the second conductive layer;

a second substrate comprising:

a second insulating substrate;

the third conductive layer comprises a second conductive coil and a third connecting wire, and the third connecting wire is electrically connected with the peripheral endpoint of the second conductive coil;

the fourth conductive layer comprises a fourth connecting wire, and the fourth connecting wire is electrically connected with the inner peripheral end point of the second conductive coil;

a second insulating layer disposed between the third conductive layer and the fourth conductive layer;

the second substrate is arranged on one side of the first substrate, and the first insulating substrate is positioned between the third conductive layer and the first conductive layer;

the first conductive layer and the second conductive layer are positioned on one side of the first insulating substrate away from the second insulating substrate;

the third conductive layer and the fourth conductive layer are positioned on one side of the second insulating substrate away from the first insulating substrate.

2. The inductor of claim 1, wherein the first insulating substrate is one of glass, ceramic, fiberglass board, polyimide film; the second insulating substrate is one of glass, ceramic, glass fiber board and polyimide film.

3. The inductor of claim 1, wherein the thickness of the first insulating substrate and the second insulating substrate are each 0.5mm or less.

4. The inductor of claim 1, wherein the first conductive layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium, and copper, and the second conductive layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium, and copper;

the material of the third conductive layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper, and the material of the fourth conductive layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium and copper.

5. The inductor of claim 1, wherein the thickness of the first conductive layer and the third conductive layer is 600nm or greater.

6. The inductor of claim 1, wherein the first conductive coil comprises N turns of first conductive wire, the first conductive wire having a width of 100 μm or less, N being 1 or more;

the second conductive coil comprises M circles of second conductive wires, the width of each second conductive wire is less than or equal to 100 mu M, and M is more than or equal to 1.

7. The inductor of claim 6, wherein N is equal to or greater than 2 and a minimum distance between adjacent first conductive lines is 100 μm or less;

m is more than or equal to 2, and the minimum distance between the adjacent second conductive wires is less than or equal to 100 mu M.

8. The inductor of claim 1 or 6, wherein the first conductive coil comprises a first spiral coil and a second spiral coil, the first spiral coil being connected in parallel with the second spiral coil;

the second conductive coil comprises a third spiral coil and a fourth spiral coil, and the third spiral coil is connected with the fourth spiral coil in parallel.

9. The inductor of claim 8, wherein the first connection line, the second connection line, the third connection line, and the fourth connection line are all of a full-face structure.

10. The inductor of claim 1, wherein the first conductive layer further comprises a first bond pad, the first and second connection lines being electrically connected to different ones of the first bond pads, respectively;

the third conductive layer further comprises a second binding pad, and the third connecting wire and the fourth connecting wire are respectively and electrically connected with different second binding pads.

11. The inductor of claim 1, wherein the second conductive layer is located on a side of the first conductive layer remote from the first insulating substrate and the fourth conductive layer is located on a side of the third conductive layer remote from the second insulating substrate.

12. An inductor, comprising:

a first substrate, the first substrate comprising:

a first insulating substrate;

a second substrate comprising:

a second insulating substrate;

the second conductive layer is arranged on one side of the first conductive layer, which is close to the first insulating substrate, the first insulating substrate comprises a first notch, and the second connecting line is arranged in the first notch;

the fourth conductive layer is arranged on one side, close to the second insulating substrate, of the third conductive layer, the second insulating substrate comprises a second notch, and the second connecting line is arranged in the second notch.

13. The inductor of claim 12, wherein the first insulating substrate is one of glass, ceramic, fiberglass board, polyimide film; the second insulating substrate is one of glass, ceramic, glass fiber board and polyimide film.

14. The inductor of claim 12, wherein the thickness of the first insulating substrate and the second insulating substrate are each 0.5mm or less.

15. The inductor of claim 12, wherein the first conductive layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium, and copper, and the second conductive layer is at least one of aluminum, molybdenum, silver, chromium, nickel, titanium, and copper;

16. The inductor of claim 12, wherein the first conductive layer and the third conductive layer each have a thickness of 600nm or greater.

17. The inductor of claim 12, wherein the first conductive coil comprises N turns of first conductive wire, the first conductive wire having a width of 100 μm or less, N being 1 or more;

18. The inductor of claim 17, wherein N is ≡2 and the minimum distance between adjacent first conductive lines is 100 μm or less;

19. The inductor of claim 12 or 17, wherein the first conductive coil comprises a first spiral coil and a second spiral coil, the first spiral coil being connected in parallel with the second spiral coil;

20. The inductor of claim 19, wherein the first connection line, the second connection line, the third connection line, and the fourth connection line are all of a full-face structure.

21. The inductor of claim 12, wherein the first conductive layer further comprises a first bond pad, the first and second connection lines being electrically connected to different ones of the first bond pads, respectively;

22. A chip comprising an inductor according to any one of claims 1-21.