CN1604299A - On-chip inductance design method for multiple current path suppression current congestion effect - Google Patents
On-chip inductance design method for multiple current path suppression current congestion effect Download PDFInfo
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- CN1604299A CN1604299A CN 200410067599 CN200410067599A CN1604299A CN 1604299 A CN1604299 A CN 1604299A CN 200410067599 CN200410067599 CN 200410067599 CN 200410067599 A CN200410067599 A CN 200410067599A CN 1604299 A CN1604299 A CN 1604299A
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Abstract
This invention belongs to microelectronics technique field, which in detail is a standard integration circuit process to improve the design method of inductance through the multiple-path circuit design to lower current jam effect. To design the current path is to split the regular single coil metal into multiple parallel wire in one same plane. The vertical overlap layer of 2 is to connect the head and local part instead of through holes.
Description
Technical field
The invention belongs to microelectronics technology, relate to a kind of method with standard integrated circuit technology design high-performance on-chip inductor.
Background technology
Semiconductor technology fast development, monolithic integrated circuit have become possibility.Because a series of advantages such as the intrinsic low-power consumption of monolithic integrated circuit, high-performance, low cost, high finished product rate make original sheet external component, realize becoming the focus of a research in (as the inductance) etc., sheet.
The basic definition of the quality factor of inductance is the ratio of inductance at one-period stored energy and loss of energy:
The loss of inductance comprises: the 1) ohmic loss of inductance wire coil; 2) substrate loss; 3) radiation of electromagnetic field etc.The ohmic loss of inductance metal refers to inductance polyphone dead resistance, loses the electric energy of inductance with the form of heat energy.
In DC circuit, the electric current on the homogeneous conductor cross section is uniform.But in alternating current circuit, along with the increase of frequency, the CURRENT DISTRIBUTION on conductive wire cross-section is more and more in the set of surfaces of guiding line.This phenomenon is called skin effect.Skin effect has reduced effective cross-sectional area, thereby its equivalent resistance has been increased.
For the size of quantitative description skin effect, introduce remembering with gratitude of skin depth.The degree of depth that makes the d representative count from conductive surface, current density j is:
j＝j
0e
-d/δ
j
0Represent the current density of conductive surface; δ is an amount with length dimension, and on behalf of current density j, it reduced to j
01/e the time the degree of depth, be called skin depth (δ).
The square root of skin depth and frequency f, conductivity and magnetic permeability μ is inversely proportional to.See that qualitatively the frequency of alternating current is high more, the electromotive force of inducting is big more; The conductivity of conductor is big more, and the eddy current of generation is also just big more.This all can make skin effect remarkable, and promptly skin depth diminishes.
The electric current of inductance can concentrate on the top layer of inductance metal along with the increase of frequency, because general substrate all is a ground connection, the electric current of inductance coil can be concentrated on downward top layer like this.The method that solves generally is the metal thickness that technology manufacturer increases the top layer, but after increasing to a certain degree, because the cause of skin depth, thickness tends towards stability gradually for the reduction of polyphone metallic resistance.Equally, multiple layer metal by the method that a large amount of logical skies couples together, has not only been increased the parasitic capacitance of inductance to substrate, reduced the self-oscillation frequency of inductance, and electric current can concentrate to underlying metal, at high frequency, can not play a part good reduction inductance polyphone metallic resistance equally.
In proximity effect, whether no matter have electric current to flow through in this section metal wire, the AC magnetic field that is produced by adjacent wires can cause eddy current in this section metal wire.The existence of these eddy current makes the CURRENT DISTRIBUTION in the metal wire inhomogeneous, and in the inductance metal of outmost turns, outer peripheral electric current is big, and the electric current of inward flange is little; Inner ring, the primary current direction of inward flange is identical with the eddy current direction and increase, outer peripheral primary current reduces mutually on the contrary with the eddy current direction, eddy current even occur the opposite direction of electric current greater than the electric current of former inductance under extreme case, but effectively inductance polyphone metallic resistance increases greatly, this situation is strong more near the center of inductance more, thus generally adopt the inductance of hollow, and also the number of turns is limited; Also having a kind of method is exactly to adopt not wide metal wire, the coupling between the relatively narrow method increase coil of the metal wire of inner ring.
Summary of the invention
The objective of the invention is to propose a kind of standard integrated circuit technology of using, by design multiple current path, suppress current-crowding effect, thereby improve the on-chip inductor method for designing of inductance performance, this method can reduce the increasing degree of the polyphone metallic resistance of inductance along with frequency, reduce metal loss, improve the quality factor of inductance.
Method in the past is to adopt hollow or the middle narrow method of metal wire, and the metal of each coil all is a complete metal wire.When adopting the multiple layer metal parallel connection, often adopt a large amount of through holes to connect.
The present invention adopts the multiple current route method, exactly aspect horizontal on: same metal wire is divided into a plurality of in parallel, narrow relatively end to end wide metal wires, the metal width of the minimum that the distance between the lines can adopting process factory allows.In the approach effect of not considering electric current, the electric current of each line-dividing is evenly to flow, and equate substantially.When the electric current approach effect was arranged, electric current only can be crowded to the edge of each coil, can not crowd again to the edge of original single metal coil, but the crowded respectively edge that arrives lines separately of less current.So just reduce the increase of the inductance serial resistance that causes owing to approach effect, and then improved the quality factor of inductance.
On the vertical direction: the parallel connection of the multiple layer metal interconnection line of traditional inductance, whole winding are to adopt a large amount of through holes to connect.Make between the different levels it is an integral body like this, the electric current in the middle of coil under the effect of skin effect, can flow to the bottom of whole metal in parallel by through hole.In high frequency, can not realize well that thick metal layers reduces the original intention of resistance.
The present invention is with from beginning to end or local link to each other of multiple layer metal interconnection line at inductance, and other place connects without through hole.When electric current flows in coil like this, under the effect of skin effect, can not concentrate to lower metal because the metal interconnected of through hole and lower floor arranged yet.
In other words be exactly the surface area that has increased level and vertical metal coil, skin effect will reduce, and the series resistance of inductance is along with the speed of the increase of frequency will reduce, and then the quality factor of raising inductance.
Description of drawings
The standard CMOS hierarchical relationship example of Fig. 1 metal interconnecting wires inductance;
The inductance example of Fig. 2 conventional method design;
The level view example of the inductance in Fig. 3 multiple current path;
The profile of Fig. 4 multiple current path inductance and do not wait the inductor design example of number of path;
Number in the figure: 20 is metal, and 21 is second layer metal, and 22 is through hole, and 30 is metal wire, 31 is metal wire, and 32 is the end of inductance, and 33 is through hole, and 34 is second layer metal, 40 is oxide layer, and 41 is the section of first lap, and 42 is second circle of inductance, and 43 is the 3rd circle of inductance.
Embodiment
Further specifically describe the present invention below in conjunction with the accompanying drawing example.
The standard CMOS hierarchical relationship example of Fig. 1 metal interconnecting wires inductance; Different metal levels can couple together by through hole, realize the parallel connection or the series arrangement of inductance coil.Below just design the method that the multiple current path reduces the inductive current crowding effect for example with this technology
Fig. 2 is the single-ended planar spiral inductor of hollow of conventional method design, and 3 circles are arranged, and the metal 20 of every circle all is independent one, 4. 3. adopts a large amount of through hole 22 to be connected in parallel with metal by metal.The port of inner ring connects to come out by second layer metal 21.
The level view example of the inductance in Fig. 3 multiple current path; Planar spiral inductor 3 encloses totally, and the metal of each circle is composed in parallel by the metal wire 30 that 4 width equate, 4. each metal is 3. in parallel by metal for each metal wire 31, but only adopts 33 connections of a large amount of through holes at the two ends 32 of inductance.The port of inner ring connects to come out by second layer metal 34.
The profile of Fig. 4 multiple current path inductance and do not wait the inductor design example of number of path.Inductance is 3 circle planar inductors.Wherein m represents metal, the number of plies of digitized representation metal.The 40th, oxide layer.The 41st, the section of first lap have only 4. (m4 among the figure) layer of metal of metal, but whole winding is an independent metal; The 42nd, 4. 3. second circle of inductance be formed in parallel at the two ends end to end of inductance with metal by metal by vertical direction, and horizontal direction is by two metal wire parallel connections; The 43rd, the 3rd circle of inductance, by vertical direction by metal 2., 4. 3. metal be formed in parallel at the two ends end to end of inductance with metal, horizontal direction is by three metal wire parallel connections.
Only passing through the through hole parallel connection end to end between the multilayer of inductance, the middle through hole of not beating connects.Along with the increase of the inside number of turns of inductance, the number of lines of the level parallel connection of same coil or the vertical number of plies in parallel increase, and determine maximum number of lines according to the spacing that the width and the technology of lines allows.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (1)
1, a kind of on-chip inductor method for designing of multiple current current path suppression current congestion effect is characterized in that with standard integrated circuit technology design multiple current path:
(1) in the horizontal direction: same metal wire is divided into a plurality of in parallel end to end, narrow relatively wide metal wires, the metal width of the minimum that the distance between the lines can adopting process factory allows;
(2) in vertical direction: with from beginning to end or local link to each other of multiple layer metal interconnection line at inductance, other place connects without through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410067599 CN1604299A (en) | 2004-10-28 | 2004-10-28 | On-chip inductance design method for multiple current path suppression current congestion effect |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410067599 CN1604299A (en) | 2004-10-28 | 2004-10-28 | On-chip inductance design method for multiple current path suppression current congestion effect |
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| CN1604299A true CN1604299A (en) | 2005-04-06 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113012909A (en) * | 2021-03-01 | 2021-06-22 | 安徽安努奇科技有限公司 | Inductor |
| CN115966548A (en) * | 2021-09-17 | 2023-04-14 | 上海玻芯成微电子科技有限公司 | Inductor and chip |
-
2004
- 2004-10-28 CN CN 200410067599 patent/CN1604299A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113012909A (en) * | 2021-03-01 | 2021-06-22 | 安徽安努奇科技有限公司 | Inductor |
| CN115966548A (en) * | 2021-09-17 | 2023-04-14 | 上海玻芯成微电子科技有限公司 | Inductor and chip |
| CN115966548B (en) * | 2021-09-17 | 2024-03-12 | 上海玻芯成微电子科技有限公司 | Inductor and chip |
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