CN100395882C - A small-area high-performance differential inductor with laminated construction - Google Patents

Abstract

The present invention belongs to the field of microelectronic technology and particularly relates to a high-performance differential driven symmetrical inductor with a laminated construction, which is designed by standard integrated circuit technology. Different single-circle metallic interconnecting line coils are connected in series by through holes to keep two signal ports of the inductor symmetrical so as to form a differential inductor with high performance and small area. The coupling coefficient between the laminated coils connected in series is larger than the coupling coefficient between flat spiral inductors, and thus, large inductance can be realized by small area. The parasitic capacitance between the coils with a laminated construction has the relation of serial connection, the ac voltage of the bottommost coil is lowest, and the voltage difference between the bottommost coil and a substrate is smallest, which means the parasitic capacitance of the inductor is further reduced.

Description

A kind of small-area high-performance differential inductor with laminated construction

Technical field

The invention belongs to microelectronics technology, be specifically related to a kind of small-area high-performance sheet superimposed layer structure differential driving symmetry inductance with the design of standard integrated circuit technology.

Background technology

Semiconductor technology fast development, monolithic integrated circuit have become possibility.Because a series of advantages such as the intrinsic low-power consumption of monolithic integrated circuit, high-performance, low cost, high finished product rates, make the focus of realizing becoming a research in original sheet external component (as the inductance etc.) sheet.

The on-chip inductor of standard integrated circuit adopts the multiple layer metal interconnection line to be entwined.The research of inductance mainly concentrates on quality factor (Q) and the self-oscillation frequency (f that improves inductance _SR) and the foundation of model.

The basic definition of the quality factor of inductance is the ratio of inductance at one-period stored energy and loss of energy:

Q is defined as the most widely:

$Q_L\left(\mathrm{\ω}\right)=-\frac{\mathrm{Im}\left(y11\right)}{\mathrm{Re}\left(y11\right)}=2\mathrm{\ω}\·\frac{(E_m^{\mathrm{av}}-E_e^{\mathrm{av}})}{P_l^{\mathrm{av}}}---\left(2\right)$

Wherein, E _m ^Av, E _e ^Av, P _l ^AvRepresent magnetic energy, electric energy and the loss of the average storage of one-period internal inductance respectively.Self-oscillation frequency (the f of inductance _SR) be defined as in second definition of inductance Q the inductance operating frequency when Q is:

$f_{\mathrm{SR}}={\left(2\mathrm{\π}\sqrt{L_{\mathrm{eq}}{C}_{\mathrm{eq}}}\right)}^{-1}---\left(3\right)$

L wherein _EqAnd C _EqBe respectively the inductance value and the capacitance of equivalence.

As seen need only Q and the f that the parasitic capacitance that reduces inductance just can improve inductance from (2) and (3) _SR

Along with the continuous progress of technology, size of component is scaled, yet the area of inductance is very huge, can not be scaled, and performance neither be fine simultaneously.One of chief reason is that the coupling coefficient between the different coils of planar inductor is very low, mean magnetic field deposit can and the loss that causes of series resistance, reduce along with the increase of number of inductor.But save certain area when realizing big relatively inductance, people have to adopt the inductance form of multi-turn, rather than the long radius version of individual pen.

Along with the progress of technology, the number of plies of interconnection line increases gradually, and the through hole of the connection between the different metal levels also adopts the metal identical with interconnection line, has reduced the resistance of through hole like this.Designed the inductance of lamination for this reason, be exactly inductance between the different layers be series arrangement, but such structure all is single-ended, a port that is exactly inductance is ground connection for AC signal, another termination AC signal.Be not suitable for the needs of difference channel, have to adopt two single-ended inductance, caused the waste area of chip like this.Design at the integrated electricity of radio frequency, generally adopt the difference channel topological structure in order to suppress DC maladjustment and Signal Spacing, people find out the method that two differential inductances are merged, utilize the multiple layer metal interconnection line to design differential inductance, the equal and opposite in direction amplitude of signal of two ports input that is exactly inductance is opposite, and inductance is centrosymmetric, geometric center at inductance coil is exactly virtual ground, differential inductance is exactly two independently piecing together of single-ended inductance like this, has promptly saved area and has also reduced the parasitic capacitance of inductance to substrate.When the electric capacity of the differential inductance on plane when difference is used uses as inductance is single-ended 1/4th.

P _l ^AvComprise the metal polyphone loss of substrate loss and inductance.Wherein substrate loss comprises substrate eddy current loss and substrate field coupling loss.At the inductance of the minor radius inductance with respect to long radius, the penetration depth of substrate is superficial, this means that the loss of substrate is also just low.And the employing laminated inductance, because coupling coefficient is bigger, the radius of inductance is also just smaller, corresponding substrate loss is also just low.But the differential inductance of lamination is not also seen report.

Summary of the invention

The objective of the invention is to propose a kind of high-performance sheet superimposed layer structure differential driving symmetry inductance with the design of standard integrated circuit technology.

The high-performance inductance of the usefulness standard integrated circuit technology design that the present invention proposes adopts lamination differential driving symmetrical structure form, and wherein, the induction structure at same metal interconnecting layer employing individual pen adopts the polyphone type of attachment between the different layers.

Among the present invention, the zigzag fluting is adopted in bilevel junction, and the width of groove satisfies the design rule requirement.Two horizontal basic hanging down of Z word as for the edge of coil; The slash of Z word is basically parallel to the edge of coil, is positioned at the center of coil width.The whippletree of the Z word of two interconnection layers fluting direction is opposite up and down, guarantees the consistency of different induction the direction of the winding current.The Z character segment is by through hole and two-layer connection up and down.Here so-called standard integrated circuit technology is a kind of standard C OMS multiple layer metal interconnection line technology.

Laminated inductance is by improving the coupling coefficient between the inductance coil, increase the method for the ratio of inductance value and wire coil serial resistance, improving the performance of inductance.Coupling coefficient between the inductance that the vertical stack polyphone connects is greatly about about 0.9, under the identical situation of every circle inductance value, inductance value be approximately equal to laminated inductance the number of plies (n) square, and ignoring under the situation of approach effect, the serial resistance of inductance be approximately equal to each layer inductance coil series resistance and, be directly proportional with n, inductance value is n in other words ²Doubly increase, and resistance value n doubly increases.And then the performance of increase inductance.

Because the coupling coefficient between the adjacent windings of identical layer is less, in the differential configuration, the voltage difference between the adjacent windings is bigger, causes the parasitic capacitance of inductance bigger.Among the present invention, adopt the individual pen structure on the same metal level of inductance, connect downwards by the through hole between the different metal layer then, up to the bottom; Also can be to be connected in parallel between the adjacent layer,, reduce the polyphone dead resistance of individual pen metal so once more with other shunt layer or individual layer polyphone; Also can be to skip some layer polyphone to connect, such as individual pen inductance and the metal level 3 and metal level 1 polyphone of metal level 5, middle metal level 2 and metal level 4 be skipped, and then increase the distance between the adjacent laminates, reduce the parasitic capacitance of closing on wire coil.

Laminated construction, originally the electric capacity between inductance coil and the substrate becomes the structure that the polyphone of the electric capacity between parasitic capacitance between the different interconnection line metal level inductance coils and lowermost layer coil and the substrate is connected.And the core of the coil of lowermost layer is the zero potential junction of two single-ended inductance alternating currents of differential driving, that is to say, potential difference minimum between the current potential of the lowermost layer inductance coil of this kind structure and the conventional ground connection substrate, consider from the angle of capacity plate antenna, mean that the parasitic capacitance between this layer line circle and the substrate is very little.The parasitic capacitance of so in general bottom inductance is very little.Compare with planar inductor, under the identical inductance value, laminated inductance has little radius, means little area, little parasitic capacitance.And this vertical stack series arrangement has reduced between the inductance and the parasitic capacitance between inductance and the substrate, and then improves the quality factor and the self-oscillation frequency of inductance.

Description of drawings

Fig. 1 is the standard CMOS hierarchical relationship of four layers of metal interconnecting wires;

Fig. 2 is the differential inductance that the 4th layer of metal inductance coil is connected in series to ground floor metal inductance coil;

Fig. 3 is the inductance coil of the 4th layer of metal of inductance among Fig. 2;

Fig. 4 is the inductance coil of inductance three-layer metal among Fig. 2;

Fig. 5 is the inductance coil of inductance second layer metal among Fig. 2;

Fig. 6 is the inductance coil of inductance ground floor metal among Fig. 2;

Fig. 7 is the polyphone of the inductance coil of the inductance coil of the 4th layer of metal of inductance among Fig. 2 and three-layer metal;

Fig. 8 is the polyphone of the inductance coil of the inductance coil of inductance three-layer metal among Fig. 2 and second layer metal;

Fig. 9 is the polyphone of the inductance coil of the inductance coil of inductance second layer metal among Fig. 2 and ground floor metal;

Number in the figure: 11 is the substrate layer of inductance, and 12 is epitaxial loayer, and 13 is field oxide, and 14 is active area, and 15 is polysilicon, 30 be metal level 4., 40 be metal level 3., 50 be metal level 2., 60 be metal level 1.; 1-8 is the dotted line of the expression sense of current.

Embodiment

Further specifically describe the present invention below in conjunction with accompanying drawing.

The monolithic inductance utilizes metal interconnecting wires to be entwined, Fig. 1 is the standard CMOS hierarchical relationship of four layers of metal interconnecting wires, its be followed successively by from top to bottom substrate 11, epitaxial loayer 12, field oxide 13 and active area 14, polysilicon 15, field oxide 1., metal level 1. ... field oxide 4. with metal level 4..Different metal levels can connect by through hole.Below just be the method for the small-area high-performance differential inductance of example introduction design individual pen with this technology.

Fig. 2 is the differential inductance block diagram that the 4th layer of metal inductance coil is connected in series to ground floor metal inductance coil.Below detailed the explanation shape and the annexation of wire coil each time.Fig. 3 is the inductance coil of the 4th layer of metal of inductance among Fig. 2.Wherein 30 represent the 4th layer of metal interconnecting wires, and 31 is two ports of differential inductance, the 32nd, and the zigzag slit of coil is with the 4th layer of wire coil separated into two parts.Fig. 4 is the inductance coil of inductance three-layer metal among Fig. 2.Wherein 40 represent the three layer metal interconnect lines.41 and 42 is that two zigzag slits of swinging to are with wire coil 3 separated into two parts.Among Fig. 3 33 and 34 parts are connected by through hole with 44 parts with 43 of Fig. 4 respectively.Fig. 5 is the inductance coil of inductance second layer metal among Fig. 2.Wherein 50 represent the second layer metal interconnection lines.51 and 52 is that two zigzag slits of swinging to are with wire coil 2 separated into two parts.Among Fig. 4 46 and 46 parts are connected by through hole with 56 parts with 55 of Fig. 5 respectively.Fig. 6 is the inductance coil of inductance ground floor metal among Fig. 2.Wherein 60 represent the ground floor metal interconnecting wires.61 is the zigzag slit.Among Fig. 5 53 and 54 parts are connected by through hole with 63 parts with 62 of Fig. 6 respectively.Two transverse directions in the zigzag slit of adjacent layer are opposite, connect to guarantee the polyphone between two-layer up and down.

Fig. 7 is the polyphone of the inductance coil of the inductance coil of the 4th layer of metal of inductance among Fig. 2 and three-layer metal, and wherein 70 is the through holes that connect the 4th layer of metal interconnecting wires and three layer metal interconnect line.Fig. 8 is the polyphone of the inductance coil of the inductance coil of inductance three-layer metal among Fig. 2 and second layer metal, and wherein 80 is the through holes that connect three layer metal interconnect line and second layer metal interconnection line.Fig. 9 is the polyphone of the inductance coil of the inductance coil of inductance second layer metal among Fig. 2 and ground floor metal, and wherein 90 is the through holes that connect second layer metal interconnection line and ground floor metal interconnecting wires.

The dotted line 1-8 of band arrow represents sense of current or opposite direction among Fig. 3-6.Such zigzag slit has guaranteed that bilevel polyphone connects when having guaranteed same layer line circle separated, and electric current is identical direction.

It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.

Claims (1)

1. small-area high-performance differential inductor with laminated construction with standard integrated circuit technology design is characterized in that: adopt the induction structure of individual pen at same metal interconnecting layer, adopt the polyphone type of attachment between the different layers; The zigzag fluting is adopted in bilevel junction, two horizontal hanging down as for the edge of coil of Z word; The slash of Z word is parallel to the edge of coil, is positioned at the center of coil width; The whippletree of the Z word of two interconnection layers fluting direction is opposite up and down.

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