CN101840774A - Small-area transformer with on-chip laminated structure - Google Patents

Abstract

The invention belongs to the technical field of microelectronics, in particular to a small-area high-performance transformer with an on-chip laminated structure, which is designed by a standard integrated circuit technology. In the invention, coupling transmission of the transformer is realized by a through-hole laminated layer, and two metal layers are connected in parallel through a skip layer, thus the low resistance character and the low parasitic capacitance character of two signal ports of the transformer are realized, and the transformer achieves high performance and small area. The transformer of the invention has the advantage that the insertion loss of a laminated parallel coil thereof is smaller than that of planar spiral transformer.

Description

On-chip small-area laminated structure transformer

technical field

The invention belongs to the technical field of microelectronics and relates to an on-chip transformer. It specifically relates to a transformer with a small-area high-performance on-chip laminated structure designed by standard integrated circuit technology.

Background technique

With the rapid development of semiconductor technology, monolithic integrated circuits have become possible. Due to a series of advantages such as low power consumption, high performance, low cost, and high yield inherent in monolithic integrated circuits, the on-chip implementation of the original off-chip components (such as transformers, etc.) has become a research hotspot.

At present, the research on standard integrated circuit on-chip transformers mainly focuses on improving the self-excited oscillation frequency (f _SR ) of the transformer, reducing the insertion loss (IL) of the transformer and establishing the model.

With the continuous progress of the technology, the size of the components is reduced in proportion. However, the area of the transformer is too large to be reduced in proportion, and the performance is not very good. One of the main reasons is that the coupling coefficient of the planar transformer is very low, and the loss caused by eddy current and series resistance is large. However, in order to achieve relatively large self-inductance and mutual inductance values, low insertion loss and save a certain area, people have to adopt a stacked structure.

Transformer losses include substrate losses and metal series losses. The substrate loss includes substrate eddy current loss and substrate electric field coupling loss. For transformers with small radii, the penetration depth of the substrate is relatively shallow compared to transformers with large radii, which means that the losses in the substrate are also low.

Contents of the invention

The purpose of the present invention is to overcome the defects of the prior art and provide a small-area laminated structure transformer on a chip. In particular, a low-parasitic transformer with a high-performance on-chip parallel stacked structure is designed by using a standard integrated circuit process. The transformer has low impedance to reduce insertion loss; meanwhile, it has the characteristics of low parasitic capacitance and increased resonance frequency.

Specifically, the high-performance transformer designed by the standard integrated circuit technology proposed by the present invention adopts a laminated structure, wherein a single-turn coil structure is used on the same metal interconnection layer, and there is no vertical gap between the primary and secondary coils. Overlap reduces the parasitic capacitance between the two coils. The different layers of the secondary coil are connected in parallel. In order to reduce the parasitic capacitance of the secondary coil and increase the resonance frequency, the two layers of the secondary coil are connected in parallel by skipping layers, that is, the fifth layer and the third layer are connected in parallel. The connection between the upper and lower layers is connected by a through hole, and the width of the through hole meets the requirements of the design rules.

In the laminated structure adopted in the present invention, since the coupling coefficient is relatively large, the radius of the transformer is relatively small, and the corresponding substrate loss is also low. With the advancement of technology, the number of layers of interconnection lines gradually increases, and the through holes connecting different metal layers also use the same metal as the interconnection lines, which can reduce the resistance of the through holes.

The laminated transformer of the present invention improves the performance of the transformer by increasing the respective coupling coefficients of the primary and secondary coils, increasing the self-inductance and mutual inductance values. The coupling coefficient between vertically stacked parallel connected transformers is around 0.9.

In the present invention, the transformer adopts a single-turn structure on the same metal layer, and then connects downwards through through holes between different metal layers; it can also be connected in parallel between adjacent layers, and then connected in series with other parallel layers or single layers. In this way, the series parasitic resistance of the single-turn metal can be reduced; some layers can also be skipped and connected in series, thereby increasing the distance between adjacent stacked layers and reducing the parasitic capacitance of adjacent metal coils.

In the stacked structure, the original capacitance between the coil and the substrate becomes a serial connection structure of the parasitic capacitance between the coils of different interconnected metal layers and the capacitance between the lowest layer coil and the substrate. Moreover, the potential difference between the potential of the lowest layer coil of the laminated structure and the conventional grounded substrate is the smallest. From the perspective of plate capacitance, it means that the parasitic capacitance between the layer coil and the substrate is very small. Generally speaking, such The parasitic capacitance of the low-level coil is very small. Compared with the planar spiral transformer, under the same self-inductance value, the laminated transformer has a small radius, which means small area and small parasitic capacitance. The vertically stacked parallel structure reduces the parasitic capacitance between transformers and between the transformer and the substrate, thereby improving the quality factor.

Description of drawings

Figure 1 shows the standard CMOS hierarchical relationship of six-layer metal interconnection lines, in which, from top to bottom, 11 is the substrate layer of the transformer, 12 is the epitaxial layer, 13 is the field oxide layer, 14 is the edge region, 15 is polysilicon, 21 is Metal layers 6 , 22 are metal layers 5 , and 31 are metal layers 3 .

Fig. 2 is a transformer of the sixth-layer metal coil and the fifth-layer and third-layer metal coils, wherein, 21 is the coil of the sixth-layer metal, and 22 is the coil of the fifth-layer metal of the transformer.

Figure 3 is a perspective view of the transformer in Figure 2

Figure 4 is the parallel connection of the coils of the fifth layer and the third layer of metal in the transformer in Figure 2

Figure 5 is a cross-sectional view of the port of the transformer in Figure 2

Figure 6 is the port where the coils of the fifth layer metal and the third layer metal of the transformer in Figure 2 are connected in parallel

Figure 7 is a plan view of the transformer in Figure 2

Figure 8 shows the third layer metal coil of the transformer in Figure 2 and the through holes of the fourth layer and the third layer

Figure 9 is the third layer metal coil of the transformer in Figure 2

Numbers in the figure: 11 is the substrate layer of the transformer, 12 is the epitaxial layer, 13 is the field oxide layer, 14 is the edge region, 15 is polysilicon, 21 is the metal layer 6, 22 is the metal layer 5, 31 is the metal layer 3.

The present invention is further specifically described below in conjunction with the accompanying drawings. It should be noted that the following examples are only used to illustrate the technical solutions of the present invention, although the present invention has been described in detail with reference to preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalent Replacement, without departing from the spirit and scope of the technical solutions of the present invention, should be covered by the scope of the claims of the present invention.

Specific implementation method

Example 1

Metal interconnection wires are used to wind a monolithic transformer coil. Combined with Figure 1, Figure 1 shows the standard CMOS layer relationship of six-layer metal interconnection wires. From top to bottom, 11 is the substrate layer of the transformer, 12 is the epitaxial layer, and 13 is the In the field oxide layer, 14 is the active region, 15 is the polysilicon, 21 is the metal layer 6, 22 is the metal layer 5, and 31 is the metal layer 3. Different metal levels can be connected by vias. Combined with Figure 2, the shape and connection relationship of each metal coil is described in detail:

In Fig. 2, 21 is the coil of the sixth-layer metal, and 22 is the coil of the fifth-layer metal of the transformer. The metal on the fifth layer and the metal on the sixth layer are staggered vertically and do not overlap. In this way, there is only sidewall capacitance between the five layers and the process metal, and this connection greatly reduces the influence of parasitic capacitance on the resonant frequency of the transformer. Among them, 31 represents the third-layer metal interconnection line, 51 and 52 are the input ports of the primary and secondary coils in the transformer, 61 is the fourth-layer metal, and the fifth-layer and third-layer metal coils are connected in parallel through through holes 71 and 72. Together. Fig. 9 is the coil of the third layer metal of the transformer in Fig. 2 . Parts 53 and 54 in FIG. 5 are respectively connected to parts 62 and 63 in FIG. 6 through through holes. Every quarter turn connects the third and fifth metal layers through vias to reduce series resistance. The fifth layer of metal and the third layer of metal are skipped in parallel to reduce the problem of increased resistance due to the narrowing of the metal line thickness. At the same time, the skipped connection also reduces the capacitance between the two coils and increases the resonance frequency.

Claims (4)

1. A small-area laminated structure transformer on a chip, including a metal interconnection layer, is characterized in that: a single-turn coil structure is used on the same metal interconnection layer, the primary and secondary coils do not overlap at all, and layer jumping is used between different layers Parallel connection form. 2. The on-chip small-area laminated structure transformer according to claim 1, wherein said primary and secondary coils do not overlap at all in the vertical direction. 3. The on-chip small-area laminated structure transformer according to claim 1, characterized in that: said different metal layers are connected downward through through holes or connected in parallel between adjacent layers, and then connected with other parallel layers Or a single layer in series. 4. The on-chip small-area laminated structure transformer according to claim 1, wherein the coupling coefficient between said laminated structure transformers is 0.9.

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