CN104409441A - Three-dimensional solenoid type inductor and transformer structure formed through utilizing multi-conductor silicon through holes - Google Patents
Three-dimensional solenoid type inductor and transformer structure formed through utilizing multi-conductor silicon through holes Download PDFInfo
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- CN104409441A CN104409441A CN201410617853.XA CN201410617853A CN104409441A CN 104409441 A CN104409441 A CN 104409441A CN 201410617853 A CN201410617853 A CN 201410617853A CN 104409441 A CN104409441 A CN 104409441A
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Abstract
The invention discloses a three-dimensional solenoid type inductor and transformer structure formed through utilizing multi-conductor silicon through holes. The on-chip solenoid type inductor component formed through utilizing the multi-conductor silicon through holes is characterized in that metal lines pass through a base through the multi-conductor silicon through holes so as to wind the base, and as a result, a solenoid structure can be formed. Similarly, the invention also provides a solenoid type transformer component formed through utilizing the multi-conductor silicon through holes. According to the three-dimensional solenoid type inductor and transformer structure formed through utilizing the multi-conductor silicon through holes of the invention, the multi-conductor silicon through holes are set in a dummy manner, so that the inductor component or the transformer component can be formed, and therefore, the area of a chip can be decreased; compared with traditional silicon through holes, four metal lines can be vertically connected with one another in the same multi-conductor through hole, and influence of spacing limiting conditions of the silicon through holes can be decreased, and therefore, an occupied area can be further decreased; with the solenoid type structure provided by the invention adopted, homodromous current in the multi-conductor silicon through holes can be realized; and the base is utilized to isolate a top metal layer and a bottom, so that inter-layer heterodromous current can be arranged again, and a mutual inductance value can be maximally improved, and overall performance can be improved.
Description
Technical field
The invention belongs to passive electronic technical field, relate to a kind of inductance and transformer element, particularly relate to a kind of use many Semiconductor Silicons through hole to realize three-dimensional spiral line tubular type inductance and transformer device structure.
Background technology
The more and more inductance element that embeds of current integrated circuit is on chip, and in prior art, general employing on-chip spiral inductor structure, namely by turning to inductance coil by metal wire, and is drawn internal port by through hole from next metal level.In order to obtain high inductance value, usually needing to increase coil quantity, which results in on-chip inductor element and occupy larger chip area.In addition, two (or multiple) inductance elements can construct transformer by coupled magnetic flux, and namely when primary coil is by electric current, secondary coil can produce induced voltage, thus from primary coil, obtains Energy transfer to load.Traditional on-chip transformer adopts tapped, staggered form or run-in index transformer device structure usually, can occupy larger chip area equally.
In recent years, along with the development of three dimensional integrated circuits, silicon through hole technology is subject to extensive concern, and it can provide larger design freedom and better electric property.Therefore, silicon through hole technology is also applied to element on sheet such as structure solenoid type inductance and transformer etc., to promote chip performance.And for ensureing chip reliability, work in-process can make the illusory silicon through hole of part, if the three-dimensional inductance of these illusory silicon hole configuration and transformer device structure can be utilized, will greatly reduce chip area footprints, improve integrated level, improving chip performance.
U.S. Patent number the 8th, 143,952 B2 patents describe a kind of three-dimensional spiral line tubular type inductance and the transformer element structure of using silicon through hole technical construction.In order to provide larger current path, this inductor structure utilize silicon through hole, metal level and again layout layer at base top and bottom cross wiring, thus obtain the solenoid type induction structure of high inductance.And then, utilize two to use the chain structure of silicon through hole to construct transformer device structure.But there is a large amount of heterodromes in this connected mode and weaken inductance value, and then have impact on the quality factor of inductance.In addition, due to the restriction of silicon via process, need to ensure certain distance between adjacent silicon through hole, and silicon through hole sectional area is much larger than metal level on sheet and the metal wire again in layout layer, its inductance value is less, contributes limited to overall inductance value.And the transformer proposed in this patent is subject to the impact of silicon through-hole spacing equally, mutual inductance between elementary and secondary coil is less, excellent electric property cannot be provided, even and if adopt symmetric figure transformer device structure can be subject to the impact of silicon through-hole spacing restrictive condition too.
Summary of the invention
An object of the present invention is for the deficiencies in the prior art, a kind of solenoid type inductance element using many Semiconductor Silicons through hole to realize is provided, it is characterized in that metal wire by many Semiconductor Silicons through hole through substrate, thus winding substrate realizes solenoid structure, and same direction current is realized in each many Semiconductor Silicons through hole, and metal level and the metal wire again in layout layer also keep same direction current path on sheet, and utilize substrate to isolate the heterodrome of metal layer at top and bottom layout interlayer again, farthest improve mutual inductance value, to obtain the induction structure of high inductance.
Inductance element of the present invention is made up of multiple cell, and the two ends of inductance element are respectively provided with Single port, and described port is positioned at the metal level M1 of base top;
Described cell comprise be positioned at base top metal level M1, Semiconductor Silicon through hole more than two, be positioned at the layer of layout again bottom substrate; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the first metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole the 4th metal wire, or as Single port; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the second metal wire holds and holds be connected with the metal level M1 that is positioned at of the through hole of Semiconductor Silicon more than second the 3rd metal wire, the metal level M1 that is positioned at of the 3rd metal wire holds and holds be connected with the metal level M1 that is positioned at of the through hole second of Semiconductor Silicon more than second metal wire, and the metal level M1 that is positioned at being positioned at metal level M1 end and the through hole first of Semiconductor Silicon more than second metal wire of the 4th metal wire holds and is connected; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the 4th metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole first metal wire, or as Single port; In the through hole of Semiconductor Silicon more than first, the layout layer end that be positioned at again of the first metal wire is connected with the layout layer end again that be positioned at of the through hole first of Semiconductor Silicon more than second metal wire, the layout layer end that be positioned at again of the second metal wire is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second the 4th metal wire, the layout layer end that be positioned at again of the 3rd metal wire is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second the 3rd metal wire, and the layout layer end that be positioned at again of the 4th metal wire is connected with the layout layer end again that be positioned at of the through hole second of Semiconductor Silicon more than second metal wire.
Another object of the present invention proposes solenoid type Two-port netwerk transformer element on a kind of sheet, same connect base top metal level and the bottom metal wire again in layout layer by silicon through hole, compared to U.S. Patent number the 8th, 143, the transformer device structure that 952 B2 patents describe, the present invention can reduce the impact of silicon through-hole spacing restrictive condition in technique, promotes primary coil and secondary coil coupling each other, thus lifting transformer performance, reduce chip area footprints.
On sheet of the present invention, solenoid type Two-port netwerk transformer element is made up of multiple cell;
Described cell comprise be positioned at base top metal level M1, Semiconductor Silicon through hole more than two, be positioned at the layer of layout again bottom substrate; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the first metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole second metal wire, or as the upper end port of primary coil; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the 4th metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole the 3rd metal wire, or as the upper end port of secondary coil; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the second metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole first metal wire, or as the lower end port of primary coil; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the 3rd metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole the 4th metal wire, or as the lower end port of secondary coil; In the through hole of Semiconductor Silicon more than first, the layout layer end that be positioned at again of the first metal wire is connected with the layout layer end again that be positioned at of the through hole second of Semiconductor Silicon more than second metal wire; In the through hole of Semiconductor Silicon more than first, the layout layer end that be positioned at again of the 4th metal wire is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second the 3rd metal wire;
The upper end port of described primary coil connects drive circuit, lower end port ground connection; The lower end port of described secondary coil connects load circuit, upper end port ground connection; And the lower end port of the upper end port of primary coil and secondary coil lays respectively at transformer two ends to reduce port coupling capacitance, increase cut-off frequency.
Another object of the present invention is to provide solenoid type four port transformer element on a kind of sheet, same connects base top metal level and the bottom metal wire again in layout layer by silicon through hole.Compared to U.S. Patent number the 8th, the transformer device structure that 143,952 B2 patents describe, the present invention can reduce the impact of silicon through-hole spacing restrictive condition in technique, promote primary coil and secondary coil coupling each other, thus promote transformer performance, reduce chip area footprints.
On sheet of the present invention, solenoid type four port transformer element is made up of multiple cell;
Described cell comprise be positioned at base top metal level M1, Semiconductor Silicon through hole more than two, be positioned at the layer of layout again bottom substrate; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the first metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole second metal wire, or as the upper end port of primary coil; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the second metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole first metal wire, or as the upper end port of secondary coil II; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the 3rd metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole the 4th metal wire, or as the upper end port of secondary coil III; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the 4th metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole the 3rd metal wire, or as the upper end port of secondary coil I; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the first metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole second metal wire, or as the lower end port of secondary coil II; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the second metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole first metal wire, or as the lower end port of primary coil; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the 3rd metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole the 4th metal wire, or as the lower end port of secondary coil I; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the 4th metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole the 3rd metal wire, or as the lower end port of secondary coil III; In the through hole of Semiconductor Silicon more than first, the layout layer end that be positioned at again of the first metal wire is connected with the layout layer end again that be positioned at of the through hole second of Semiconductor Silicon more than second metal wire, the layout layer end that be positioned at again of the second metal wire is connected with the layout layer end again that be positioned at of the through hole first of Semiconductor Silicon more than second metal wire, the layout layer end that be positioned at again of the 3rd metal wire is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second the 4th metal wire, and the layout layer end that be positioned at again of the 4th metal wire is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second the 3rd metal wire;
The upper end port of described primary coil connects drive circuit, and the lower end port of the upper end port of secondary coil I, the lower end port of secondary coil II and secondary coil III connects load circuit, all the other port ground connection.
Beneficial effect of the present invention:
The present invention utilizes illusory many Semiconductor Silicons hole configuration inductance and transformer element, reduces chip area.Use many Semiconductor Silicons through hole to connect base top metal level and the bottom metal wire again in layout layer, the induction structure compared to traditional silicon hole configuration can improve self-inductance value, makes full use of positive mutual inductance value simultaneously, strengthens overall inductance value.In addition, use many Semiconductor Silicons hole configuration solenoid type transformer device structure, the magnetic flux that can improve between primary coil with secondary coil is coupled, and improves transformer electric property.
Accompanying drawing explanation
Fig. 1 is existing cylindrical silicon through-hole structure;
Fig. 2 is the inductance element according to the utilization silicon hole configuration shown by U.S. Patent number the 8th, 143,952 B2 patent;
Fig. 3 by the transformer element of utilization silicon hole configuration shown by foundation U.S. Patent number the 8th, 143,952 B2 patent;
Fig. 4 is many Semiconductor Silicons through-hole structure schematic diagram, and wherein Fig. 4 A is the schematic perspective view of many Semiconductor Silicons through-hole structure, and Fig. 4 B is the profile of many Semiconductor Silicons through-hole structure;
Fig. 5 is that many Semiconductor Silicons via-hole applications of Fig. 4 is in the structural representation of solenoidal inductor element, wherein Fig. 5 A is this inductor structure base top schematic diagram, Fig. 5 B is this inductor structure substrate bottom schematic view, and Fig. 5 C is the schematic perspective view of some cells in this inductance element;
Fig. 6 is that many Semiconductor Silicons via-hole applications of Fig. 4 is in solenoid type transformer element embodiment 1(Two-port netwerk transformer) structural representation; Wherein Fig. 6 A is structural substrates schematical top view, and Fig. 6 B is structural substrates bottom schematic view, and Fig. 6 C is the schematic perspective view of the some cells of this transformer element;
Fig. 7 is nut tubular type transformer element embodiment 2(tetra-port transformer that the present invention uses many Semiconductor Silicons hole configuration) structural representation; Wherein Fig. 7 A is structure top basal part schematic diagram, and Fig. 7 B is structural substrates bottom schematic view, and Fig. 7 C is the schematic perspective view of the some cells of this transformer element.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
Be illustrated in figure 1 the tangent plane schematic diagram of existing cylindrical silicon through hole 100, it runs through substrate 103 by metal cylinder 101, and this metal can be copper, tungsten or polysilicon and forms.Consider thermal stress and problems of Signal Integrity, also can adopt annular or coaxial shape through-silicon via structure.For preventing leakage current, layer of oxide layer 102 can be formed as insulating barrier between metal and substrate.Noticing according to copper filling silicon through holes, for preventing the diffusion of copper atom, also can dose one deck separator between copper and oxide layer.Substrate 103 also can grow one deck dielectric material 104, be connected with silicon through hole to form metal wire.
Fig. 2 is according to U.S. Patent number the 8th, 143, the inductance element 200 of the utilization silicon hole configuration shown by 952 B2 patents, it comprises input port 201 and 202, runs through the silicon through hole 203 of substrate, metal wire 205 in the metal wire 204 in base top metal level M1 and the layer of layout again bottom substrate.It utilizes silicon through hole technology to extend wire lengths as seen from the figure, thus obtains larger inductance value.But be limited to silicon clear size of opening, its self-induction is less, and there is a large amount of heterodromes in metal wire in metal level M1 and again layout layer, overall inductance value can be reduced.
Fig. 3 is the transformer element 300 according to the utilization silicon hole configuration shown by U.S. Patent number the 8th, 143,952 B2 patent, and it comprises primary and secondary inductance, respective ports having 301 and 303.Primary inductance with port 302 and 304 ground connection of secondary circuit.This transformer make use of the silicon through hole 305, metal wire 306 in base top metal level M1 and the bottom metal wire 307 again in layout layer that run through substrate.Identical with inductance element, this structure also exists the lower problem of inductance value equally, and it is more weak to be coupled between two inductance, is difficult to provide good electric property.
Fig. 4 A and 4B shows schematic perspective view and the profile thereof of many Semiconductor Silicons through-hole structure of the present invention.
Many Semiconductor Silicons through-hole structure 400 of the present invention comprises substrate 403, metal wire, oxide layer 402; Through hole 401 is had in the centre of substrate 403, and be provided with oxide layer 402 in the upper and lower surface of substrate 403 and the inwall of through hole 401, the first metal wire 404, second metal wire 405, the 3rd metal wire 406, the 4th metal wire 407 is provided with, this four metal line 402 Central Symmetry in oxide layer 402;
Described through hole 401 upper end is inverted cone-shaped, and lower end is upright cone-shaped;
The technical process of described many Semiconductor Silicons through-hole structure: first by this structure thinning, in substrate 403 surface deposition oxide layer 402, then obtains conical through-hole corresponding up and down from top and bottom etching respectively, thus obtains the through hole 401 running through substrate; In silicon through hole, grow oxide layer 402 to isolate electric current, and at oxide layer 402 forming metal layer on surface, obtain metal wire to form many Semiconductor Silicons through-hole structure finally by etching.
Fig. 5 illustrates and uses the many Semiconductor Silicons through-hole structure shown in Fig. 4, constructable solenoid type induction structure top and bottom schematic view.
Shown in Fig. 5 A, 5B, 5C, inductance element of the present invention is made up of multiple cell 500, and the two ends of inductance element are respectively provided with Single port, and described port is positioned at the metal level M1 of base top;
Described cell 500 comprises the metal level M1 being positioned at base top, two many Semiconductor Silicons through holes as described in Figure 4, is positioned at the layer of layout again bottom substrate, in the through hole of Semiconductor Silicon more than first 501, the metal level M1 that is positioned at of the first metal wire 504 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole 503 the 4th metal wire 512, or as Single port, in the through hole of Semiconductor Silicon more than first 501, the metal level M1 that is positioned at of the second metal wire 505 holds and holds be connected with the metal level M1 that is positioned at of the through hole 502 of Semiconductor Silicon more than second the 3rd metal wire 510, the metal level M1 that is positioned at of the 3rd metal wire 506 holds and holds be connected with the metal level M1 that is positioned at of the through hole of Semiconductor Silicon more than second 502 second metal wire 509, and the metal level M1 that is positioned at being positioned at metal level M1 end and the through hole of Semiconductor Silicon more than second 502 first metal wire 508 of the 4th metal wire 507 holds and is connected, in the through hole of Semiconductor Silicon more than second 502, the metal level M1 that is positioned at of the 4th metal wire 511 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole 512 first metal wire 513, or as Single port, in the through hole of Semiconductor Silicon more than first 501, the layout layer end that be positioned at again of the first metal wire 504 is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second 502 first metal wire 508, the layout layer end that be positioned at again of the second metal wire 505 is connected with the layout layer end again that be positioned at of the through hole 502 of Semiconductor Silicon more than second the 4th metal wire 511, the layout layer end that be positioned at again of the 3rd metal wire 506 is connected with the layout layer end again that be positioned at of the through hole 502 of Semiconductor Silicon more than second the 3rd metal wire 510, the layout layer end that be positioned at again of the 4th metal wire 507 is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second 502 second metal wire 509,
The course of work of this inductance element: first electric current to flow to bottom substrate layout layer again from the metal wire base top metal level M1 by the first metal wire 504 in the through hole of Semiconductor Silicon more than first 501 in cell 500, and be returned to base top metal level M1 by the first metal wire 508 of the through hole of Semiconductor Silicon more than second 502, layout layer is again flow to bottom substrate by the 4th metal wire 507 in base top metal level M1 Semiconductor Silicon more than first through hole 501, by bottom substrate again in layout layer Semiconductor Silicon more than second through hole 502 second metal wire 509 be returned to base top metal level M1, layout layer is again flow to bottom substrate by the 3rd metal wire 506 in base top metal level M1 Semiconductor Silicon more than first through hole 501, by bottom substrate again in layout layer Semiconductor Silicon more than second through hole 502 the 3rd metal wire 510 be returned to base top metal level M1, layout layer is again flow to bottom substrate by the second metal wire 505 in base top metal level M1 Semiconductor Silicon more than first through hole 501, by bottom substrate again in layout layer Semiconductor Silicon more than second through hole 502 the 4th metal wire 511 be returned to base top metal level M1 metal wire, then next cell is flow to.So repeatedly be wound around with swelling current path, improve self-inductance value.Notice that the self-inductance value of traditional cylindrical silicon through hole 100 is less, many Semiconductor Silicons through-hole structure that the present invention adopts can provide larger self-inductance value, make full use of mutual inductance to each other to increase total inductance value simultaneously, thus reach the object of structure high inductance solenoid type inductance element.For the solenoid type induction structure that the present invention proposes better is described.
Similarly, utilize solenoid type transformer device structure on many Semiconductor Silicons hole configuration high-performance sheet, the base top of first embodiment (Two-port netwerk transformer) of the transformer element that the present invention as shown in Fig. 6 A and 6B proposes and substrate bottom schematic view, and element cell structure schematic diagram as shown in Figure 6 C.On this sheet, solenoid type Two-port netwerk transformer element has primary coil and secondary coil.
As shown in Fig. 6 A, 6B, 6C, on sheet of the present invention, solenoid type Two-port netwerk transformer element is made up of multiple cell 600;
Described cell 600 comprises the metal level M1 being positioned at base top, two many Semiconductor Silicons through holes as described in Figure 4, is positioned at the layer of layout again bottom substrate; In the through hole of Semiconductor Silicon more than first 601, the metal level M1 that is positioned at of the first metal wire 605 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole 603 second metal wire 609, or as the upper end port of primary coil; In the through hole of Semiconductor Silicon more than first 601, the metal level M1 that is positioned at of the 4th metal wire 606 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole 603 the 3rd metal wire 610, or as the upper end port of secondary coil; In the through hole of Semiconductor Silicon more than second 602, the metal level M1 that is positioned at of the second metal wire 607 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole 604 first metal wire 611, or as the lower end port of primary coil; In the through hole of Semiconductor Silicon more than second 602, the metal level M1 that is positioned at of the 3rd metal wire 608 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole 604 the 4th metal wire 612, or as the lower end port of secondary coil; In the through hole of Semiconductor Silicon more than first 601, the layout layer end that be positioned at again of the first metal wire 605 is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second 602 second metal wire 607; In the through hole of Semiconductor Silicon more than first 601, the layout layer end that be positioned at again of the 4th metal wire 606 is connected with the layout layer end again that be positioned at of the through hole 602 of Semiconductor Silicon more than second the 3rd metal wire 608;
The upper end port of described primary coil connects drive circuit, lower end port ground connection; The lower end port of described secondary coil connects load circuit, upper end port ground connection; And the lower end port of the upper end port of primary coil and secondary coil lays respectively at transformer two ends to reduce port coupling capacitance, increase cut-off frequency.
The course of work of solenoid type Two-port netwerk transformer element on this sheet: in primary coil, electric current flows into the metal wire of base top metal level M1 from the upper end port of primary coil, and to flow into bottom substrate layout layer again by the first metal wire 605 in the through hole of Semiconductor Silicon more than first 601 in cell 600, and by bottom substrate again in layout layer Semiconductor Silicon more than second through hole 602 second metal wire 607 be returned to base top metal level M1, then flow into next cell; In secondary coil, electric current flows into the metal wire of base top metal level M1 from the lower end port of secondary coil, and to flow into bottom substrate layout layer again by the 3rd metal wire 608 in the through hole of Semiconductor Silicon more than second 602 in cell 600, and by bottom substrate again in layout layer Semiconductor Silicon more than first through hole 601 the 4th metal wire 606 be returned to base top metal level M1, then flow into next cell.
Fig. 7 represents that the present invention proposes the schematic diagram of second embodiment (four port transformer) of transformer element.This transformer element has primary coil and secondary coil I, secondary coil II, secondary coil III.
As shown in Fig. 7 A, 7B, 7C, the present invention four port transformer element is made up of multiple cell 700;
Described cell 700 comprises the metal level M1 being positioned at base top, two many Semiconductor Silicons through holes as described in Figure 4, is positioned at the layer of layout again bottom substrate, in the through hole of Semiconductor Silicon more than first 701, the metal level M1 that is positioned at of the first metal wire 705 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole 703 second metal wire 714, or as the upper end port of primary coil, in the through hole of Semiconductor Silicon more than first 701, the metal level M1 that is positioned at of the second metal wire 706 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole 703 first metal wire 713, or as the upper end port of secondary coil II, in the through hole of Semiconductor Silicon more than first 701, the metal level M1 that is positioned at of the 3rd metal wire 707 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole 703 the 4th metal wire 716, or as the upper end port of secondary coil III, in the through hole of Semiconductor Silicon more than first 701, the metal level M1 that is positioned at of the 4th metal wire 708 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole 703 the 3rd metal wire 715, or as the upper end port of secondary coil I, in the through hole of Semiconductor Silicon more than second 702, the metal level M1 that is positioned at of the first metal wire 709 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole 704 second metal wire 718, or as the lower end port of secondary coil II, in the through hole of Semiconductor Silicon more than second 702, the metal level M1 that is positioned at of the second metal wire 710 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole 704 first metal wire 717, or as the lower end port of primary coil, in the through hole of Semiconductor Silicon more than second 702, the metal level M1 that is positioned at of the 3rd metal wire 711 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole 704 the 4th metal wire 720, or as the lower end port of secondary coil I, in the through hole of Semiconductor Silicon more than second 702, the metal level M1 that is positioned at of the 4th metal wire 712 holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole 704 the 3rd metal wire 719, or as the lower end port of secondary coil III, in the through hole of Semiconductor Silicon more than first 701, the layout layer end that be positioned at again of the first metal wire 705 is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second 702 second metal wire 710, the layout layer end that be positioned at again of the second metal wire 706 is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second 702 first metal wire 709, the layout layer end that be positioned at again of the 3rd metal wire 707 is connected with the layout layer end again that be positioned at of the through hole 702 of Semiconductor Silicon more than second the 4th metal wire 712, the layout layer end that be positioned at again of the 4th metal wire 708 is connected with the layout layer end again that be positioned at of the through hole 702 of Semiconductor Silicon more than second the 3rd metal wire 711,
The upper end port of described primary coil connects drive circuit, and the lower end port of the upper end port of secondary coil I, the lower end port of secondary coil II and secondary coil III connects load circuit, all the other port ground connection.
The course of work of this four port transformer structure: in primary coil, electric current flows into the metal wire of base top metal level M1 from the upper end port of primary coil, and to flow into bottom substrate layout layer again by the first metal wire 705 in the through hole of Semiconductor Silicon more than first 701 in cell 700, and by bottom substrate again in layout layer Semiconductor Silicon more than second through hole 702 second metal wire 710 be returned to base top metal level M1, then flow into next adjacent elements unit; In secondary coil I, electric current flows into the metal wire of base top metal level M1 from the upper end port of secondary coil I, and to flow into bottom substrate layout layer again by the 4th metal wire 708 in the through hole of Semiconductor Silicon more than first 701 in cell 700, and by bottom substrate again in layout layer Semiconductor Silicon more than second through hole 702 the 3rd metal wire 711 be returned to base top metal level M1, then flow into next adjacent elements unit; In secondary coil II, electric current flows into the metal wire of base top metal level M1 from the lower end port of secondary coil II, and to flow into bottom substrate layout layer again by the first metal wire 709 in base top Semiconductor Silicon more than second through hole 702, and by bottom substrate again in layout layer Semiconductor Silicon more than first through hole the second metal wire 706 be returned to base top metal level M1, then flow into next adjacent elements unit; In secondary coil III, electric current flows into the metal wire of base top metal level M1 from the lower end port of secondary coil III, and to flow into bottom substrate layout layer again by the 4th metal wire 712 in base top metal level M1 Semiconductor Silicon more than second through hole 702, and be returned to base top metal level M1 by the 3rd metal wire 707 bottom substrate again in layout layer Semiconductor Silicon more than first through hole 701, then flow into next adjacent elements unit.
By using the three-dimensional nut tubular type inductance of many Semiconductor Silicons through hole technical construction and transformer element, the space of base top and bottom can be made full use of, reduce the chip area footprints of passive device; Utilize mutual inductance to strengthen total inductance value simultaneously, reduce the process conditions such as silicon through-hole spacing to the restriction of device performance, obtain passive device on high-performance sheet.
Claims (6)
1. use the solenoid type inductance element that many Semiconductor Silicons through hole realizes, it is characterized in that being made up of multiple cell, the two ends of inductance element are respectively provided with Single port, and described port is positioned at the metal level M1 of base top;
Described cell comprise be positioned at base top metal level M1, Semiconductor Silicon through hole more than two, be positioned at the layer of layout again bottom substrate; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the first metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole the 4th metal wire, or as Single port; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the second metal wire holds and holds be connected with the metal level M1 that is positioned at of the through hole of Semiconductor Silicon more than second the 3rd metal wire, the metal level M1 that is positioned at of the 3rd metal wire holds and holds be connected with the metal level M1 that is positioned at of the through hole second of Semiconductor Silicon more than second metal wire, and the metal level M1 that is positioned at being positioned at metal level M1 end and the through hole first of Semiconductor Silicon more than second metal wire of the 4th metal wire holds and is connected; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the 4th metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole first metal wire, or as Single port; In the through hole of Semiconductor Silicon more than first, the layout layer end that be positioned at again of the first metal wire is connected with the layout layer end again that be positioned at of the through hole first of Semiconductor Silicon more than second metal wire, the layout layer end that be positioned at again of the second metal wire is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second the 4th metal wire, the layout layer end that be positioned at again of the 3rd metal wire is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second the 3rd metal wire, and the layout layer end that be positioned at again of the 4th metal wire is connected with the layout layer end again that be positioned at of the through hole second of Semiconductor Silicon more than second metal wire.
2. a solenoid type Two-port netwerk transformer element on the sheet using many Semiconductor Silicons through hole to realize, is characterized in that being made up of multiple cell;
Described cell comprise be positioned at base top metal level M1, Semiconductor Silicon through hole more than two, be positioned at the layer of layout again bottom substrate; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the first metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole second metal wire, or as the upper end port of primary coil; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the 4th metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole the 3rd metal wire, or as the upper end port of secondary coil; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the second metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole first metal wire, or as the lower end port of primary coil; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the 3rd metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole the 4th metal wire, or as the lower end port of secondary coil; In the through hole of Semiconductor Silicon more than first, the layout layer end that be positioned at again of the first metal wire is connected with the layout layer end again that be positioned at of the through hole second of Semiconductor Silicon more than second metal wire; In the through hole of Semiconductor Silicon more than first, the layout layer end that be positioned at again of the 4th metal wire is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second the 3rd metal wire.
3. a solenoid type four port transformer element on the sheet using many Semiconductor Silicons through hole to realize, is characterized in that being made up of multiple cell;
Described cell comprise be positioned at base top metal level M1, Semiconductor Silicon through hole more than two, be positioned at the layer of layout again bottom substrate; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the first metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole second metal wire, or as the upper end port of primary coil; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the second metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole first metal wire, or as the upper end port of secondary coil II; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the 3rd metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole the 4th metal wire, or as the upper end port of secondary coil III; In the through hole of Semiconductor Silicon more than first, the metal level M1 that is positioned at of the 4th metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than second through hole the 3rd metal wire, or as the upper end port of secondary coil I; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the first metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole second metal wire, or as the lower end port of secondary coil II; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the second metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole first metal wire, or as the lower end port of primary coil; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the 3rd metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole the 4th metal wire, or as the lower end port of secondary coil I; In the through hole of Semiconductor Silicon more than second, the metal level M1 that is positioned at of the 4th metal wire holds and holds be connected with the metal level M1 that is positioned at of adjacent elements unit Semiconductor Silicon more than first through hole the 3rd metal wire, or as the lower end port of secondary coil III; In the through hole of Semiconductor Silicon more than first, the layout layer end that be positioned at again of the first metal wire is connected with the layout layer end again that be positioned at of the through hole second of Semiconductor Silicon more than second metal wire, the layout layer end that be positioned at again of the second metal wire is connected with the layout layer end again that be positioned at of the through hole first of Semiconductor Silicon more than second metal wire, the layout layer end that be positioned at again of the 3rd metal wire is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second the 4th metal wire, and the layout layer end that be positioned at again of the 4th metal wire is connected with the layout layer end again that be positioned at of the through hole of Semiconductor Silicon more than second the 3rd metal wire.
4. as claimed in claim 1 a kind of use many Semiconductor Silicons through hole to realize solenoid type inductance element or a kind of sheet using many Semiconductor Silicons through hole to realize as claimed in claim 2 on solenoid type four port transformer element on solenoid type Two-port netwerk transformer element or a kind of sheet using many Semiconductor Silicons through hole to realize as claimed in claim 3, it is characterized in that described many Semiconductor Silicons through hole comprises substrate, metal wire, oxide layer; Have through hole in the centre of substrate, and be provided with oxide layer in the upper and lower surface of substrate and the inwall of through hole, in oxide layer, be provided with the first metal wire, the second metal wire, the 3rd metal wire, the 4th metal wire, this four metal line Central Symmetry; Described through hole upper end is inverted cone-shaped, and lower end is upright cone-shaped.
5. solenoid type Two-port netwerk transformer element on a kind of sheet using many Semiconductor Silicons through hole to realize as claimed in claim 2, is characterized in that the upper end port of described primary coil connects drive circuit, lower end port ground connection; The lower end port of described secondary coil connects load circuit, upper end port ground connection; And the lower end port of the upper end port of primary coil and secondary coil lays respectively at transformer two ends to reduce port coupling capacitance, increase cut-off frequency.
6. solenoid type four port transformer element on a kind of sheet using many Semiconductor Silicons through hole to realize as claimed in claim 3, it is characterized in that the upper end port of described primary coil connects drive circuit, the lower end port of the upper end port of secondary coil I, the lower end port of secondary coil II and secondary coil III connects load circuit, all the other port ground connection.
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| CN110581219A (en) * | 2019-08-09 | 2019-12-17 | 杭州电子科技大学 | Area-saving spiral inductor structure |
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