CN110459535B - Manufacturing method of laminated inductor and manufactured device - Google Patents
Manufacturing method of laminated inductor and manufactured device Download PDFInfo
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- CN110459535B CN110459535B CN201910658933.2A CN201910658933A CN110459535B CN 110459535 B CN110459535 B CN 110459535B CN 201910658933 A CN201910658933 A CN 201910658933A CN 110459535 B CN110459535 B CN 110459535B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
Abstract
The invention discloses a manufacturing method of a laminated inductor and a manufactured device, wherein the method comprises the following steps: coating a first photoresist, and carrying out photoetching process on the bottom of the enhanced grid and the bottom of the first metal layer of the inductor; coating a second photoresist, and carrying out photoetching process on the top of the enhanced grid and the top of the inductor first metal layer; depositing metal to form an enhanced grid and an inductance first metal layer; carrying out a passivation process on the enhanced gate and the inductor first metal layer to form a first passivation layer; etching openings of the depletion type grid electrode and the nitride first passivation layer connected with the second metal layer of the inductor; coating a third photoresist, and performing a depletion type grid and inductor second metal layer photoetching process; and depositing metal to form a depletion type grid electrode and an inductance second metal layer. The spiral laminated inductor prepared by the scheme has a good quality factor under a high-frequency condition and also has a large inductance value. And the method is performed simultaneously with the existing transistor process, so that the process cost is not increased.
Description
Technical Field
The invention relates to the field of integrated inductor manufacturing, in particular to a manufacturing method of a laminated inductor and a manufactured device.
Background
In the prior art, most of the integrated inductors are of a planar structure, and because the integrated inductors are manufactured on a plane parallel to a substrate, Eddy Current (Eddy Current) can be formed in the substrate under a high-frequency condition, the direction of the Eddy Current is opposite to that of Current in an inductance coil, which leads to reduction of magnetic flux of the inductance coil, extra energy loss is large, and the Q value of the whole inductor is reduced. In addition, in the prior art, due to the limitation of the manufacturing process and materials of the integrated circuit, it is difficult to achieve high inductance and high Q factor at the same time. The inductor in the prior art is prepared by the following steps: firstly, evaporating an inductance main body metal (first metal) on a substrate, and simultaneously leading out two ends of the inductance main body; secondly, covering a protective layer under the condition that the metal evaporation of the inductor main body is finished; thirdly, a planarization process is performed on the basis of the second step. Fourth, a deposition process of a second metal is performed, which connects the individual first metal layers of each segment along the contour path of the planarization layer material.
Disclosure of Invention
Therefore, it is desirable to provide a method for manufacturing a multilayer inductor and a device manufactured by the method, which solve the problems of poor quality factor and low inductance of the inductor manufactured by the prior art.
In order to achieve the above object, the inventor provides a method for manufacturing a laminated inductor, comprising the following steps:
depositing source and drain metals on the surface of the epitaxial wafer;
coating a first photoresist, and carrying out photoetching process on the bottom of the enhanced grid and the bottom of the first metal layer of the inductor;
coating a second photoresist, and carrying out photoetching process on the top of the enhanced grid and the top of the inductor first metal layer;
depositing metal to form an enhanced grid and an inductance first metal layer;
carrying out a passivation process on the enhanced gate and the inductor first metal layer to form a first passivation layer;
etching openings of the depletion type grid electrode and the nitride first passivation layer connected with the second metal layer of the inductor;
coating a third photoresist, and performing a depletion type grid and inductor second metal layer photoetching process;
and depositing metal to form a depletion type grid electrode and an inductance second metal layer, wherein the inductance second metal layer is arranged on the inductance first metal layer.
Further, the method also comprises the following steps:
passivating the depletion type grid electrode and the second metal layer of the inductor to form a second passivation layer;
etching openings of the source/drain level and a second passivation layer connected with the third metal layer of the inductor;
coating a fourth photoresist, and performing a photoetching process of the source-drain first metal connecting line and the inductor third metal layer;
and depositing metal to form a source-drain first metal connecting wire and an inductance third metal layer.
Further, the method also comprises the following steps:
performing a passivation layer covering and isolating process to form a third passivation layer;
etching openings of the source drain level second metal connecting line and a third passivation layer at the position connected with the fourth metal layer of the inductor;
coating a fifth photoresist, and performing a photoetching process on the source-drain second metal connecting line and the inductor fourth metal layer;
and depositing metal to form a source-drain second metal connecting line and an inductor fourth metal layer.
Further: the third passivation layer further comprises the following steps after the opening is etched: and carrying out a planarization process to form a flat layer.
Further, the first passivation layer is a nitride layer.
Furthermore, the first metal layer of the inductor is a circular metal layer with a notch.
The invention provides a device manufactured by the manufacturing method of the laminated inductor.
Different from the prior art, the inductor prepared by the technical scheme is a spiral laminated inductor, has a better quality factor under a high-frequency condition and also has a larger inductance value. The occupation of the surface area of the wafer is reduced, the chip integration level is improved, and the production cost of the chip is reduced. And the method is carried out simultaneously with the existing transistor process, so that the transistor and the inductor can be simultaneously manufactured without increasing the process cost.
Drawings
FIG. 1 is a schematic diagram of a first metal layer structure of an inductor according to an embodiment of the invention;
FIG. 2 is a schematic structural diagram of a first passivation layer according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a second metal layer structure of an inductor according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a second passivation layer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a third metal layer structure of an inductor according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a third passivation layer according to an embodiment of the present invention;
FIG. 7 is a schematic view of a planar layer structure according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating a fourth metal layer structure of an inductor according to an embodiment of the present invention;
fig. 9 is a schematic perspective view of a stacked inductor according to an embodiment of the invention.
Description of reference numerals:
1. an inductor first metal layer;
2. a first passivation layer;
3. the connection part of the second metal layer of the inductor;
4. an inductor second metal layer;
5. a second passivation layer;
6. connecting the inductor third metal layer;
7. an inductor third metal layer;
8. a third passivation layer;
9. the connection part of the inductor fourth metal layer;
10. a planarization layer;
11. and the inductance fourth metal layer.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to 9, in the present embodiment, a method for manufacturing a stacked inductor is provided, in which a transistor can be manufactured simultaneously when manufacturing the inductor, and the transistor can be a PHEMT (pseudomorphic doped heterojunction field effect transistor), so that the process steps of the inductor and the process steps of the transistor are performed in the same process step, and the process cost is not increased. The process steps of the transistor are the process steps of the existing transistor, the formed structure is also the existing transistor structure, the key point of the invention is not to form the transistor structure, the invention does not illustrate the transistor, only the text is used for illustration, and the inductance forming process of the invention is illustrated by adopting the mode of illustration and text.
The inductor formation of the present invention comprises the steps of: and depositing source and drain metals on the surface of the epitaxial wafer, wherein the source and drain metals comprise source and drain metals of an enhancement transistor and a depletion transistor. And then coating a first photoresist, and carrying out photoetching process on the bottom of the enhanced grid electrode and the bottom of the first metal layer 1 of the inductor, namely developing the bottom of the enhanced grid electrode of the first photoresist and the position of the first metal layer of the inductor. And then coating a second photoresist, and carrying out photoetching technology on the top of the enhanced grid and the top of the inductor first metal layer 1, namely developing at the bottom of the enhanced grid of the second photoresist and the position of the inductor first metal layer. Depositing metal to form an enhanced grid and an inductance first metal layer 1; the inductor first metal layer is shown in fig. 1. The structure of the inductance first metal layer comprises a left lead and a right inductance ring structure, and a Y-shaped enhanced gate can be formed through bottom and top processes. Generally, after the metal is formed, metal lift-off and photoresist removal processes are performed, which are common processes and are not important in the present application, and are not described herein again.
And then, carrying out a passivation process on the enhanced grid electrode and the first metal layer of the inductor to form a first passivation layer 2 covering the whole device, wherein the passivation layer plays a role in isolating the two metal layers, can be a nitride layer, and plays a role in protecting the enhanced grid electrode and the first metal layer of the inductor. The first passivation layer of nitride at the junction 3 with the second metal layer of the inductor and the depletion-mode gate are then etched open. The etching openings may be formed by ion etching, and the etched inductor structure is shown in fig. 2. The first passivation layer forms an opening at the location of the connection 3 with the second metal layer of the inductor, and the bottom of the opening is the first metal layer of the inductor.
And then coating a third photoresist, and carrying out a photoetching process of the depletion type grid electrode and the inductor second metal layer, namely developing at the positions of the depletion type grid electrode and the inductor second metal layer of the third photoresist. The position of the depletion type grid is between the source electrode metal and the drain electrode metal, the source electrode metal and the drain electrode metal of the enhancement type grid are not in the same group, and the position of the second inductance metal layer is right above the annular region of the first inductance metal layer. And then depositing metal to form a depletion type grid and an inductance second metal layer 4, wherein the inductance second metal layer is connected and conducted with the first inductor through an opening at a connecting part 3 of the inductance second metal layer, and the inductance second metal layer is arranged on the inductance first metal layer. Subsequent processing steps of the transistor can then be performed to form depletion and enhancement transistors. In the inductor manufactured by the method, the second metal layer is positioned on the first metal layer, so that the spiral laminated inductor can be formed, the quality factor is better under the high-frequency condition, and the inductance value is larger. The occupation of the surface area of the wafer is reduced, the chip integration level is improved, and the production cost of the chip is reduced. And the method is carried out simultaneously with the existing transistor process, so that the transistor and the inductor can be simultaneously manufactured without increasing the process cost.
In some embodiments, a three-layer inductor may be further formed. Specifically, the method further comprises the following steps: passivating the depletion type grid electrode and the second metal layer of the inductor to form a second passivation layer 5; and etching openings of a source drain electrode and a second passivation layer at the connection part 6 with the third metal layer of the inductor, wherein the source drain electrode is the source drain electrode of an enhancement transistor and a depletion transistor, and the opening structure of the inductor is shown in fig. 4. The second passivation layer forms an opening at the source and drain metal, and the bottom of the opening is the source and drain metal. The second passivation layer forms an opening at the location of the connection 3 with the third metal layer of the inductor, and the bottom of the opening is the second metal layer of the inductor. And coating a fourth photoresist, and carrying out photoetching processes of the source-drain first metal connecting line and the inductor third metal layer, namely developing at the source-drain position of the fourth photoresist and the inductor third metal layer position. Metal is deposited to form a source-drain first metal line and an inductor third metal layer 7, which is disposed above the second metal layer, as shown in fig. 5. Therefore, the third metal layer of the inductor can be formed at the same time of forming the first metal connecting wire of the transistor source and drain, and the inductance value of the inductor can be further increased.
Further, the method also comprises the following steps: performing a passivation layer covering and isolating process to form a third passivation layer 8; etching openings of the source drain level second metal connecting line and a third passivation layer at a position 9 connected with the fourth metal layer of the inductor; as shown in fig. 6. The third passivation layer forms an opening at the position above the source-drain level and the position 9 connected with the fourth metal layer of the inductor, the bottom of the opening at the position above the source-drain level is a first metal connecting line of the source-drain level, and the bottom of the opening at the position 9 connected with the fourth metal layer of the inductor is a third metal layer 7 of the inductor. At this time, since the inductor is located at a higher position, in order to facilitate subsequent processes, the method may further include the steps of: and (3) performing a planarization process to form a planarization layer 10, wherein as shown in fig. 7, the planarization layer may be made of polyimide, may cover the surface of the device, and is opened at a position above the source/drain level and a position connected with the fourth metal layer of the inductor, so as to facilitate subsequent metal deposition connection. And then coating a fifth photoresist, and carrying out photoetching processes of a source-drain second metal connecting line and an inductor fourth metal layer, namely developing the positions of the source-drain second metal connecting line and the inductor fourth metal layer of the fifth photoresist. And depositing metal to form a source-drain second metal connecting line and an inductor fourth metal layer 11, wherein the inductor fourth metal layer is positioned above the inductor third metal layer, as shown in fig. 8, and thus a final inductor structure is formed as shown in fig. 9. Therefore, the fourth metal layer of the inductor can be formed at the same time of forming the second metal connecting wire of the transistor source and drain, and the inductance value of the inductor can be further increased.
In order to realize the leading-out of the inductor, the metal lead is connected with the metal at the bottommost layer of the inductor and the metal at the topmost layer of the inductor, so that the inductor can be electrically connected with other device structures conveniently. The overall shape of the inductor may be cylindrical, as in the embodiments described above. Each metal layer of the inductor should have a gap, so that the current can flow to the previous metal layer or the next metal layer after circulating on each metal layer. And in order to realize the surrounding, the gaps of the two adjacent metal layers are in different positions, namely in a staggered state. And the notches on each metal layer are sequentially arranged along one direction of the inductor metal layer according to the stacking sequence of the metal layers, such as the clockwise direction or the anticlockwise direction of the inductor. The connection position of two adjacent metal layers is the end position of each metal layer, so that the length of the metal can be utilized as much as possible to realize the inductance value as much as possible. And the connection position of two adjacent metal layers is between the gaps of two adjacent metal layers, so that the inductor structure shown in fig. 9 is formed.
The invention provides a device manufactured by the manufacturing method of the laminated inductor. The inductor on the device is a spiral laminated inductor, has better quality factor under high frequency condition and also has larger inductance value. The occupation of the surface area of the wafer is reduced, the chip integration level is improved, and the production cost of the chip is reduced. And the method is carried out simultaneously with the existing transistor process, so that the transistor and the inductor can be simultaneously manufactured without increasing the process cost.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (7)
1. A manufacturing method of a laminated inductor is characterized by comprising the following steps:
depositing source and drain metals on the surface of the epitaxial wafer;
coating a first photoresist, and carrying out photoetching process on the bottom of the enhanced grid and the bottom of the first metal layer of the inductor;
coating a second photoresist, and carrying out photoetching process on the top of the enhanced grid and the top of the inductor first metal layer;
depositing metal to form an enhanced grid and an inductance first metal layer;
carrying out a passivation process on the enhanced gate and the inductor first metal layer to form a first passivation layer;
etching openings of the depletion type grid electrode and the nitride first passivation layer connected with the second metal layer of the inductor;
coating a third photoresist, and performing a depletion type grid and inductor second metal layer photoetching process;
and depositing metal to form a depletion type grid electrode and an inductance second metal layer, wherein the inductance second metal layer is arranged on the inductance first metal layer to form the spiral stacked inductor.
2. The method for manufacturing a multilayer inductor according to claim 1, further comprising the steps of:
passivating the depletion type grid electrode and the second metal layer of the inductor to form a second passivation layer;
etching openings of the source/drain level and a second passivation layer connected with the third metal layer of the inductor;
coating a fourth photoresist, and performing a photoetching process of the source-drain first metal connecting line and the inductor third metal layer;
and depositing metal to form a source-drain first metal connecting wire and an inductance third metal layer.
3. The method for manufacturing a multilayer inductor according to claim 1, further comprising the steps of:
performing a passivation layer covering and isolating process to form a third passivation layer;
etching openings of the source drain level second metal connecting line and a third passivation layer at the position connected with the fourth metal layer of the inductor;
coating a fifth photoresist, and performing a photoetching process on the source-drain second metal connecting line and the inductor fourth metal layer;
and depositing metal to form a source-drain second metal connecting line and an inductor fourth metal layer.
4. The method for manufacturing a multilayer inductor according to claim 3, wherein: the third passivation layer further comprises the following steps after the opening is etched: and carrying out a planarization process to form a flat layer.
5. The method of claim 1, wherein the first passivation layer is a nitride layer.
6. The method of claim 1, wherein the first metal layer of the inductor is a circular metal layer with a gap.
7. A device, characterized by: the device is manufactured by the manufacturing method of the laminated inductor as claimed in any one of claims 1 to 6.
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| CN201910658933.2A CN110459535B (en) | 2019-07-22 | 2019-07-22 | Manufacturing method of laminated inductor and manufactured device |
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| CN201910658933.2A CN110459535B (en) | 2019-07-22 | 2019-07-22 | Manufacturing method of laminated inductor and manufactured device |
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| CN110459535B true CN110459535B (en) | 2021-03-09 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6426267B2 (en) * | 1998-06-19 | 2002-07-30 | Winbond Electronics Corp. | Method for fabricating high-Q inductance device in monolithic technology |
| US6566731B2 (en) * | 1999-02-26 | 2003-05-20 | Micron Technology, Inc. | Open pattern inductor |
| US6480086B1 (en) * | 1999-12-20 | 2002-11-12 | Advanced Micro Devices, Inc. | Inductor and transformer formed with multi-layer coil turns fabricated on an integrated circuit substrate |
| DE10257321A1 (en) * | 2001-12-06 | 2003-06-26 | Ekkehard D Hans | Manufacture of electronic components such as inductors or transformers, by applying structured layers of conductive and insulating materials in form of viscose paste, so that connection points are in contact |
| US6614093B2 (en) * | 2001-12-11 | 2003-09-02 | Lsi Logic Corporation | Integrated inductor in semiconductor manufacturing |
| CN100395882C (en) * | 2005-01-24 | 2008-06-18 | 复旦大学 | A small-area high-performance differential inductor with laminated construction |
| US8860180B2 (en) * | 2012-10-26 | 2014-10-14 | Xilinx, Inc. | Inductor structure with a current return encompassing a coil |
| CN109860147B (en) * | 2019-02-22 | 2021-08-27 | 福建省福联集成电路有限公司 | Stacked capacitor manufacturing method and semiconductor device |
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