JP2017092275A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device that is small in variation of a capacitance value of an MIM capacitor in a multilayer wiring structure, and that can be easily connected with the other circuit element on a semiconductor substrate.SOLUTION: In an MIM region 8, a second wiring layer 5 doubles as an upper electrode 9 of an MIM structure, and a dielectric film 4 doubles as a capacitance film of the MIM structure, and a first wiring layer 2 doubles as a lower electrode 10 of the MIM structure. The upper electrode 9 of the MIM structure, is formed inside a first opening 11a so as to be separated from an end part of the opening 11a. The upper electrode 9 of the MIM structure is connected with the other circuit element by a third wiring layer 7, via a second opening 12a. The lower electrode 10 (the first wiring layer 2) of the MIM structure is connected with the other circuit element by the third wiring layer 7 through a relay electrode 13, via the second opening 12b.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device having a multilayer wiring structure and a MIM structure using a resin.

  MMIC (monolithic microwave integrated circuit) using a field effect transistor (MESFET) and a high electron mobility transistor (HEMT) capable of amplifying a high frequency such as a microwave band has been improved. The MMIC uses an MIM structure (Metal-Insulator-metal) as a capacitor, and the MIM capacitor and other circuit elements on the semiconductor substrate are connected by a multilayer wiring structure. (For example, see Patent Documents 1 to 3).

JP 2008-282997 A (paragraphs 0021 to 0026, FIG. 10) JP-A-9-92786 (paragraph 0019, FIG. 1) JP 2002-118233 A (summary, FIG. 1)

In the conventional MIM structure, as in Patent Document 1, an opening is provided in the interlayer insulating layer, and the upper electrode of the MIM structure is formed in and around the opening, and the size of the opening in the interlayer insulating layer depends on the dimensions of the MIM structure. The area of the upper electrode was determined. For this reason, when the area of the MIM structure varies due to variations in processing of the interlayer insulating layer, there is a problem that the capacitance value as the MIM capacitor varies. In particular, an MMIC having a high frequency often uses an MIM capacitor having a small capacitance value, and the influence of the variation in area on the capacitance value is large.
On the other hand, as in Patent Document 3, it is conceivable to form the upper electrode away from the end of the opening, but when there is an interlayer insulating layer, there is a problem that it is difficult to connect to other circuit elements. there were. Further, when the transistor is adjacent to the MIM capacitor, there is a problem that it is difficult to maintain moisture resistance at the stepped portion.

  The present invention has been made to solve the above problems, and a first object thereof is that the variation in the capacitance value of the MIM capacitor in the multilayer wiring structure is small, and connection with other circuit elements on the semiconductor substrate is possible. An object is to obtain an easy semiconductor device.

  Another object of the present invention is to obtain a semiconductor device in which the variation in the capacitance value of the MIM capacitor in the multilayer wiring structure is small and the moisture resistance of the transistor adjacent to the MIM capacitor can be maintained.

  The semiconductor device of the present invention includes a semiconductor substrate, an MIM capacitor formed on the semiconductor substrate, and a circuit element. The MIM capacitor has a capacitance region and a lower electrode extraction region, and the capacitance region is formed on the semiconductor substrate. The first wiring layer, the first interlayer insulating layer formed so as to cover the first wiring layer, and a portion of the first wiring layer are exposed in the first interlayer insulating layer. A first opening, a dielectric film formed so as to cover the first interlayer insulating layer and the first opening, and a dielectric film spaced from the opening end inside the first opening A second wiring layer formed in contact with the dielectric layer, a second interlayer insulating layer formed so as to cover the dielectric film and the second wiring layer, and a second wiring layer formed on the second interlayer insulating layer. A second opening formed to be partially exposed, and formed in contact with the second wiring layer in the second opening. And a lower electrode lead-out region is disposed adjacent to the first opening, and includes a first wiring layer, a first interlayer insulating layer, a dielectric film, and a second wiring. The layer, the second interlayer insulating layer, and the third wiring layer are shared with the capacitor region, an opening is provided in the dielectric film, and the first wiring layer and the second wiring layer are in contact with each other. .

  According to the present invention, it is possible to obtain a semiconductor device in which the variation in the capacitance value of the MIM capacitor is small and the connection with other circuit elements is easy.

It is sectional drawing of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing of the semiconductor device in Embodiment 2 and 3 of this invention. It is sectional drawing of the semiconductor device in Embodiment 4 of this invention.

  A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1
1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. In FIG. 1, 1 is a semiconductor substrate made of GaAs, GaN or the like, 2 is a first wiring layer made of Ti / Au, Ni / Au, or the like, 3 is a first interlayer insulating layer made of a resin such as polyimide or epoxy, 4 dielectric film made of SiN or SiO _2, the second wiring layer 5 is made of Ti / Au, Ni / Au, etc., 6 polyimide, a second interlayer insulating layer made of a resin such as epoxy, 7 Ti A third wiring layer made of / Au, Ni / Au or the like is shown.

  Reference numeral 8 denotes an MIM region (capacitance region) of the MIM structure. In the MIM region 8, the second wiring layer 5 is the upper electrode 9 of the MIM structure, the dielectric film 4 is the capacitance film of the MIM structure, and the first wiring layer 2 Also serves as the lower electrode 10 of the MIM structure. Further, 11a and 11b are first openings, 12a and 12b are second openings, 13 is a relay electrode, and 14 is a lower electrode extraction region.

The upper electrode 9 having the MIM structure is formed on the inner side of the first opening portion 11a and separated from the end portion of the opening portion 11a.
The upper electrode 9 having the MIM structure is connected to other circuit elements by the third wiring layer 7 through the second opening 12a. The lower electrode 10 (first wiring layer 2) of the MIM structure is connected to other circuit elements by the third wiring layer 7 through the relay electrode 13 through the second opening 12b.

In order to manufacture the semiconductor device of this embodiment, first, the first wiring layer 2 to be the lower electrode 10 of the MIM capacitor is formed on the semiconductor substrate 1.
Next, polyimide to be the first interlayer insulator layer 3 is formed on the entire surface, and the interlayer insulator layer 3 is etched using a mask having a predetermined pattern to form first openings 11a and 11b.
Next, a dielectric film 4 serving as a capacitance film of the MIM capacitor is formed on the entire surface, and a mask having a predetermined pattern is used to open the dielectric film 4 in the region where the relay electrode 13 of the first opening 11b is to be formed. Form.

  Subsequently, a photoresist is formed on the entire surface, and using a mask having a predetermined pattern, the photoresist in the region where the upper electrode 9 having the MIM structure and the relay electrode 13 are to be formed is removed, and Ti / Au is then vacuumed on the entire surface. Deposit by evaporation. After depositing Ti / Au, the photoresist is dissolved and washed, and at the same time, Ti / Au on the photoresist is removed, and the upper electrode 9 and the relay electrode 13 are formed by a lift-off method that leaves Ti / Au in other regions. To do.

  By this method, the upper electrode 9 can be formed inside the first opening portion 11a while being separated from the end portion of the opening portion 11a.

Subsequently, a second interlayer insulator layer 6 is formed on the entire surface, and the second interlayer insulator layer 6 is etched back and planarized until the thickness of the second interlayer insulator layer 6 reaches a predetermined value. . The etched second interlayer insulating layer 6 is etched using a mask having a predetermined pattern to form second openings 12a and 12b.
Next, Ti / Au is deposited on the entire surface by sputtering, and after deposition, unnecessary portions of Ti / Au are removed by ion milling or the like using a mask having a predetermined pattern to form a third wiring layer 7; The semiconductor device of FIG. 1 is manufactured.

According to the present embodiment, the upper electrode 9 having the MIM structure is formed inside the first opening portion 11a of the first interlayer insulating layer 3 and separated from the end portion of the first opening portion 11a. Therefore, the size of the electrode of the upper electrode 9 having the MIM structure is not affected by the opening size and shape of the interlayer insulator layer 3, and variation in capacitance value can be reduced. Thereby, an MMIC with uniform characteristics can be realized.
In addition, since the upper electrode 9 having the MIM structure and the third wiring layer 7 are directly connected and the lower electrode 10 having the MIM structure and the third wiring layer 7 are connected via the relay electrode 13, Connection with other circuit elements is easy.

In the above example, the lift-off method is used. However, after opening the first opening 11a, Ti / Au is deposited on the entire surface by sputtering or the like, and the upper electrode 9 is formed by etching or ion milling instead of the lift-off method. You can also. In this case, since a mask having a size smaller than that of the first opening 11a is used, the dielectric film 4 outside the region where the upper electrode 9 is formed may be over-etched or damaged. .
When the lift-off method is used, there is no concern about over-etching or damage of the dielectric film 4, and there is an effect that a highly reliable MIM capacitor can be obtained.

Processing of a resin film such as polyimide used for the first interlayer insulator layer 3 is generally performed using RIE, and etching spreads in the lateral direction. Therefore, not only the opening becomes larger than the mask design dimension, but also the size of the opening varies depending on the film thickness of the resin film and the etching process variation. In addition, the shape of the resin opening may become unstable due to the reverse taper shape or the etching residue, which may cause a decrease in the breakdown voltage of the MIM capacitor. Such a problem does not occur in the present application.

Embodiment 2
FIG. 2 is a cross-sectional view showing the semiconductor device according to the second embodiment. In FIG. 2, 20 is a MESFET disposed adjacent to the MIM region 8, 21 is a gate electrode of the MESFET 20, 22 is a drain electrode (or source electrode) of the MESFET 20, and 23 is a source electrode (or drain electrode) of the MESFET 20. ). The drain electrode 22 also serves as the first wiring layer and is electrically connected to the lower electrode 10 of the MIM capacitor.
Reference numeral 24 denotes a dielectric film, which uses an ALD film manufactured by an atomic layer deposition (ALD). The atomic layer deposition apparatus is a film deposition apparatus that deposits atomic layers one by one, and can obtain a film with high step coverage. As the atomic layer ALD film, Ta ₂ O ₅ or the like can be used in addition to SiN and SiO ₂ exemplified in the first embodiment. Although the example of MESFET was shown above, other transistors, such as HEMT, can be used. Other components are the same as or equivalent to those of the first embodiment.

In Embodiment 2, since the periphery of the MESFET 20 is covered with the highly moisture-resistant dielectric film 24 using an ALD film, the moisture resistance of the MESFET 20 is improved.
When moisture enters from the outside, the interlayer insulator layers 3 and 6 easily transmit moisture, so that the moisture reaches the MESFET 20 and the transistor may be deteriorated. 24 can suppress the intrusion of moisture. In particular, by applying an ALD film having good coverage and high moisture resistance, moisture intrusion from a stepped portion such as a boundary with the first opening 11a can be suppressed, and the moisture resistance of the transistor is improved. .

Embodiment 3
In the third embodiment, the dielectric film 24 is a film having a two-layer structure of a lower dielectric film made of an ALD film and an upper protective film made of a plasma CVD film formed by plasma CVD. The rest is the same as in the second embodiment.
In this embodiment, the lower dielectric film is Ta ₂ O _{5 and the} upper protective film is SiN. The upper and lower relationship between the ALD film and the plasma CVD film may be reversed.

  The ALD film may cause a leak current depending on the film type and film quality. On the other hand, a plasma CVD film, particularly a SiN film, has a very small leakage current, and an MIM having good electrical characteristics can be obtained. With the two-layer structure of the ALD film and the plasma CVD film, the leakage current of the MIM capacitor can be suppressed and the moisture resistance of the transistor can be ensured.

Embodiment 4
FIG. 3 is a cross-sectional view showing a semiconductor device according to the third embodiment. In FIG. 3, 31 is a step protective film formed so as to cover the step portion of the protective film 24 covering the periphery of the MESFET. The step protective film 31 is formed as the second wiring layer 5 like the upper electrode 9. The rest is the same as in the second embodiment.

In this embodiment, the coverage of the dielectric film 24 at the step portion of the dielectric film 24 covering the periphery of the MESFET 20 is improved.
When moisture enters from the outside, moisture may enter from a stepped portion such as a boundary with the first opening 11a and the MESFET 20 may deteriorate. However, the step protection film 31 suppresses the entry of moisture. Thus, the moisture resistance of the transistor is improved.
In the above example, the ALD film is used as the dielectric film 24. However, when another film such as a plasma CVD film is used, it can be applied to improve the moisture resistance of the stepped portion.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st wiring layer 3 1st interlayer insulation layer 4 Dielectric film 5 2nd wiring layer 6 2nd interlayer insulation layer 7 3rd wiring layer 8 MIM area | region 9 Upper electrode
DESCRIPTION OF SYMBOLS 10 Lower electrode 11a, 11b 1st opening part 12a, 12b 2nd opening part 13 Relay electrode 14 Lower electrode extraction area | region 20 MESFET
21 Gate electrode 22 Drain electrode 23 Source electrode 31 Step protective film

Claims (4)

A semiconductor substrate;
An MIM capacitor formed on the semiconductor substrate and a circuit element;
The MIM capacitor has a capacitance region and a lower electrode extraction region,
The capacitance region includes a first wiring layer formed on the semiconductor substrate,
A first interlayer insulating layer formed to cover the first wiring layer;
A first opening formed in the first interlayer insulating layer so as to expose a part of the first wiring layer;
A dielectric film formed to cover the first interlayer insulating layer and the first opening;
A second wiring layer formed on the inner side of the first opening and in contact with the dielectric film and spaced from the opening end;
A second interlayer insulating layer formed to cover the dielectric film and the second wiring layer;
A second opening formed in the second interlayer insulating layer so that a part of the second wiring layer is exposed;
A third wiring layer formed in contact with the second wiring layer in the second opening,
The lower electrode extraction region is disposed adjacent to the first opening;
Sharing the first wiring layer, the first interlayer insulating layer, the dielectric film, the second wiring layer, the second interlayer insulating layer, and the third wiring layer with the capacitor region;
An opening is provided in the dielectric film, and the first wiring layer and the second wiring layer are in contact with each other,
The semiconductor device is characterized in that the circuit element is connected to the third wiring layer. A semiconductor substrate;
A MIM capacitor and a transistor formed on the semiconductor substrate;
The MIM capacitor includes a first wiring layer formed on the semiconductor substrate;
A first interlayer insulating layer formed to cover the first wiring layer;
A first opening formed in the first interlayer insulating layer so as to expose a part of the first wiring layer;
A dielectric film formed to cover the first interlayer insulating layer and the first opening;
A second wiring layer formed on the inner side of the first opening and in contact with the dielectric film and spaced from the opening end;
A second interlayer insulating layer formed to cover the dielectric film and the second wiring layer;
A second opening formed in the second interlayer insulating layer so that a part of the second wiring layer is exposed;
A third wiring layer formed in contact with the second wiring layer in the second opening,
The transistor is disposed adjacent to the first opening;
The upper and side portions of the transistor are sequentially surrounded and covered by the first interlayer insulating layer, the dielectric film, and the second interlayer insulating layer,
The drain electrode and the source electrode of the transistor share the first wiring layer,
The semiconductor device, wherein the dielectric film is an ALD film in which atomic layers are sequentially deposited. The semiconductor device according to claim 2, wherein the dielectric film further includes a dielectric film made of a plasma CVD film. 3. The second wiring layer according to claim 2, wherein the second wiring layer is formed at a step portion of the dielectric film that sequentially surrounds and covers the upper portion and the side surface portion of the transistor so as to cover the step portion. Semiconductor device.

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