CN110660781A - Metal-insulator-metal capacitor - Google Patents

Abstract

The present disclosure relates to a metal-insulator-metal capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a stepped region continuously extending from the top surface of the top electrode to the sidewall of the top electrode and continuously contacting the top surface and the sidewall of the top electrode. The metal frame is coated on the passivation layer. The metal frame continuously extends from the top surface of the passivation layer to the upper sidewall of the passivation layer in the mesa region and continuously contacts the top surface of the passivation layer and the upper sidewall. The metal frame has a protrusion extending through the passivation layer and contacting the top surface of the top electrode.

Description

Metal-insulator-metal capacitor

Technical Field

Embodiments of the present invention relate to a metal-insulator-metal capacitor.

Background

Today's integrated chips include millions or billions of transistor devices configured to enable the logic functions of the integrated chip (e.g., to form a processor configured to perform the logic functions). Often, the integrated chips may also include passive devices (e.g., capacitors, resistors, inductors, varactors, etc.). Metal-insulator-Metal (MIM) capacitors are a common type of passive device that is often integrated into back-end-of-the-line (BEOL) Metal interconnects of an integrated chip. For example, MIM capacitors may be used as decoupling capacitors configured to mitigate power supply or switching noise (e.g., input/output (I/O) switches and core circuit switches) due to current variations flowing through various parasitic inductances (parasitic inductances) associated with an integrated chip and a package in which the integrated chip is located.

Disclosure of Invention

Embodiments of the present invention provide a metal-insulator-metal capacitor including a top electrode, a passivation layer, and a metal frame. The top electrode overlies the substrate. A passivation layer overlies the top electrode. The passivation layer has a stepped region continuously extending from the top surface of the top electrode to the sidewall of the top electrode and continuously contacting the top surface and the sidewall of the top electrode. The metal frame is coated on the passivation layer. The metal frame continuously extends from the top surface of the passivation layer to the upper sidewall of the passivation layer in the step region and continuously contacts the top surface and the upper sidewall of the passivation layer. The metal frame has a protrusion. The protrusion extends through the passivation layer and contacts a top surface of the top electrode.

Embodiments of the present invention provide a metal-insulator-metal capacitor including a bottom electrode, a dielectric layer, a top electrode, a passivation layer, and a metal frame. The bottom electrode is disposed over the substrate. A dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer. A passivation layer is disposed over the top electrode. The passivation layer extends continuously over the top surface and sidewalls of the top electrode, over the sidewalls of the dielectric layer, and over the sidewalls of the bottom electrode. The metal frame is disposed over an upper surface of the passivation layer and along sidewalls of the passivation layer. The metal frame has a protrusion. The protrusion extends through the passivation layer and contacts a top surface of the top electrode.

An embodiment of the present invention provides a method for forming a metal-insulator-metal capacitor, including: forming a bottom electrode layer over a substrate; forming a dielectric film over the bottom electrode layer; forming a top electrode layer over the dielectric film; performing a removal process to remove a portion of the top electrode layer, a portion of the dielectric film, and a portion of the bottom electrode layer to form a top electrode, a dielectric layer, and a bottom electrode; forming a passivation layer over the top electrode and the bottom electrode, wherein the passivation layer has a first opening over the top surface of the top electrode, and wherein the passivation layer has a second opening over the top surface of the bottom electrode; and forming a metal frame over the passivation layer, wherein the metal frame fills the first opening and contacts the top surface of the top electrode through the first opening.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-2 illustrate cross-sectional views of some embodiments of metal-insulator-metal (MIM) capacitors with passivation layers and metal frames according to some embodiments.

Fig. 3A illustrates a perspective view of some embodiments of MIM capacitors with passivation layers and metal frames according to the present disclosure, showing cross-sectional cut-away views of some MIM capacitors.

Fig. 3B illustrates a top view of some embodiments of a MIM capacitor with a passivation layer and a metal frame according to the present disclosure.

Fig. 4A illustrates a cross-sectional view of some embodiments of a MIM device including a MIM capacitor overlying a Printed Circuit Board (PCB) substrate according to the present disclosure.

Figure 4B illustrates a cross-sectional view of some embodiments of an integrated chip including a MIM capacitor overlying a substrate according to the present disclosure.

Fig. 5-10 illustrate some cross-sectional views of an exemplary method of forming a MIM capacitor with a passivation layer and a metal frame according to the present disclosure.

Fig. 11 illustrates a method in flow chart format showing some embodiments of a method of forming a MIM capacitor including a passivation layer and a metal frame according to the present disclosure.

Detailed Description

The present disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of illustration, spatially relative terms such as "below …", "below", "lower", "above …", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

Metal-insulator-metal (MIM) capacitors are often implemented into back end of the line (BEOL) metal interconnect layers of integrated chips. MIM capacitors typically have a top metal plate and a bottom metal plate separated by a capacitor dielectric layer. To protect the MIM capacitor from the operating environment, a passivation layer is disposed over the MIM capacitor, wherein a metal protective frame is disposed over a top portion of the passivation layer. However, when such an integrated chip is introduced into a wet (wet), damp (damp) or humid (humid) environment, water molecules are driven through the passivation layer to the top metal plate due to the potential difference (potential difference) between the metal protective frame and the top metal plate. Water molecules will cause the voltage breakdown down value of the MIM capacitor to decrease.

The present disclosure relates in some embodiments to a MIM capacitor comprising: a top metal plate and a bottom metal plate separated by a capacitor dielectric layer; a passivation layer disposed over the top metal plate; and a metal protection frame disposed over the passivation layer. The passivation layer includes sidewalls defining an opening over the top surface of the top metal plate. The metal protection frame contacts the top surface of the top metal plate through an opening in the passivation layer. The contact between the metal protection frame and the top metal plate causes an equal electrical potential difference (equal electrical potential difference) between the metal protection frame and the top metal plate. The equipotential potential prevents water molecules from penetrating the passivation layer to the top metal plate. There is no electrical gradient between the top metal plate and the metal protective frame in a wet, humid or humid environment. This prevents the voltage breakdown value from decreasing.

Fig. 1 illustrates a cross-sectional view of some embodiments of a metal-insulator-metal (MIM) capacitor 100, the metal-insulator-metal (MIM) capacitor 100 including a bottom electrode 106 disposed over a substrate 102. A dielectric layer 108 having sloped sidewalls is disposed over the bottom electrode 106. A top electrode 112 is disposed over the dielectric layer 108. A passivation layer 110 is disposed over the bottom electrode 106, the dielectric layer 108, and the top electrode 112. The passivation layer 110 contacts the top surface of the top electrode 112, the sidewalls of the dielectric layer 108, and the sidewalls of the bottom electrode 106. The metal frame 104 overlies the passivation layer 110. The metal frame 104 has a protrusion 104a, and the protrusion 104a extends to the top surface of the top electrode 112 through the passivation layer 110. The protrusion 104a of the metal frame 104 directly contacts the top surface of the top electrode 112. The metal frame 104 extends continuously over the top surface of the passivation layer 110, the sidewalls of the top electrode 112, and the sidewalls of the dielectric layer 108.

On the first side 120 of MIM capacitor 100, metal frame 104 extends continuously from the top surface of passivation layer 110 to sidewall 110a of passivation layer 110. On a first side 120 of MIM capacitor 100, a first electrical lead (electrical lead)116 overlies metal frame 104. On second side 122 of MIM capacitor 100, metal frame 104 extends continuously from the top surface of passivation layer 110 beyond sidewall 108a of dielectric layer 108. On the second side 122 of MIM capacitor 100, a second electrical lead 114 overlies passivation layer 110. The second electrical lead 114 has a protrusion 114a, the protrusion 114a extending through the passivation layer 110 to the bottom electrode 106. The second electrical lead 114 is laterally offset from the metal frame 104 by a non-zero distance.

The dielectric layer 108 has sidewalls 108a, 108b, the sidewalls 108a, 108b being laterally disposed between sidewalls of the bottom electrode 106 in a top view. In a top view, the sidewall of the top electrode 112 is laterally disposed between the sidewall 108a and the sidewall 108b of the dielectric layer 108. The protrusion 104a of the metal frame 104 is laterally disposed between the sidewalls of the top electrode 112. The second electrical lead 114 is electrically coupled to the bottom electrode 106. On a first side 120 of MIM capacitor 100, bottom electrode 106 extends laterally a first length L from sidewall 108b of dielectric layer 108₁. On second side 122 of MIM capacitor 100, bottom electrode 106 extends laterally a second length L from sidewall 108a of dielectric layer 108₂. In some embodiments, the second length L₂Is greater than the first length L₁。

The metal frame 104 is electrically coupled to the top electrode 112 and facilitates achieving an equipotential between the metal frame 104 and the top electrode 112. When MIM capacitor 100 is introduced to a wet, humid or humid environment, there is no electrical gradient between top electrode 112 and metal frame 104. Since there is an equipotential between the metal frame 104 and the top electrode 112, the metal frame 104 prevents water molecules from penetrating the passivation layer 110 to reach the top electrode 112. This will prevent the MIM capacitor 100 from experiencing a breakdown voltage drop in wet, humid or humid environments.

For example, if the metal frame 104 were not present, a large electric field would be present at the outer edge of the top electrode 112 because electrons tend to collect near the edges/corners on the outer surface of the conductor. Even if the passivation layer 110 covers the outer edge of the top electrode 112, without the metal frame 104, the passivation layer 110 would be susceptible to the situation where water molecules (or other molecules) are driven through the stepped region 110s of the passivation layer due to the large electric field in the stepped region 110s of the passivation layer. Thus, in some embodiments according to the present disclosure, metal frame 104 covers step region 110s to provide another physical barrier and limit the electrical gradient encountered by polar molecules (polar molecules) in step region 110s, such that metal frame 104 enhances the breakdown voltage of MIM capacitor 100.

Fig. 2 illustrates a cross-sectional view of some embodiments of a MIM capacitor 200, the MIM capacitor 200 comprising a bottom electrode 106 overlying a substrate 102. A dielectric layer 108 is disposed over the bottom electrode 106. A top electrode 112 is disposed over the dielectric layer 108. A passivation layer 110 is disposed over the bottom electrode 106, the dielectric layer 108, and the top electrode 112. The passivation layer 110 contacts the top surface of the top electrode 112, the sidewalls 108a, 108b of the dielectric layer 108, and the sidewalls of the bottom electrode 106. A metal frame 104 is disposed over the passivation layer 110. The protrusion 104a of the metal frame 104 extends through the passivation layer 110 to the top electrode 112. The metal frame 104 extends continuously over the top surface of the passivation layer 110, the sidewalls of the top electrode 112, and the sidewalls of the dielectric layer 108. In some embodiments, the sidewalls 108a and 108b of the dielectric layer 108 are substantially straight and parallel to each other. In other embodiments, the sidewalls 110a of the passivation layer 110 are substantially straight and form a 90 degree angle with a line parallel to the top surface of the substrate 102.

On the first side 120 of the MIM capacitor 200, the metal frame 104 extends continuously from the top surface of the passivation layer 110 to the sidewalls 110a of the passivation layer 110. On the first side 120 of the MIM capacitor 200, a first electrical lead 116 is disposed over the top surface of the metal frame 104. On the second side 122 of the MIM capacitor 200, the metal frame 104 extends continuously from the top surface of the passivation layer 110 beyond the sidewall 108a of the dielectric layer 108 and continues over the top surface of the bottom electrode 106. On the second side 122 of the MIM capacitor 200, a second electrical lead 114 is provided over the bottom electrode 106 and the passivation layer 110. The second electrical lead 114 has a protrusion 114a, the protrusion 114a extending through the passivation layer 110 to the bottom electrode 106.

In top view, the sidewalls 108a, 108b of the dielectric layer 108 are laterally disposed between the sidewalls of the bottom electrode 106. Of the top electrode 112The sidewalls are aligned with the sidewalls 108a, 108b of the dielectric layer 108. The protrusion 104a of the metal frame 104 is laterally disposed between the sidewalls of the top electrode 112 in a plan view. The second electrical lead 114 is electrically coupled to the bottom electrode 106. On the first side 120 of the MIM capacitor 200, the bottom electrode 106 extends a first length L from the sidewall 108b of the dielectric layer 108₁. On second side 122 of MIM capacitor 200, bottom electrode 106 extends a second length L from sidewall 108a of dielectric layer 108₂. In some embodiments, the second length L₂Can be greater than the first length L₁Such that the second electrical lead 114 may be disposed over the bottom electrode 106 on the second side 122.

In some embodiments, the width of the protrusion 104a of the metal frame 104 may be in the range of 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 500 μm, 500 μm to 10mm, or 10mm to 100 mm. In some embodiments, the thickness of passivation layer 110 is in the range of 10 angstroms to 100 angstroms, 100 angstroms to 1000 angstroms, 0.1 μm to 1 μm, 1 μm to 100 μm, or 100 μm to 1 mm. In some embodiments, the thickness of the top electrode 112 is in the range of 10 angstroms to 100 angstroms, 100 angstroms to 1000 angstroms, 0.1 μm to 1 μm, 1 μm to 100 μm, or 100 μm to 1 mm. In some embodiments, the thickness of the bottom electrode 106 is in the range of 10 angstroms to 100 angstroms, 100 angstroms to 1000 angstroms, 0.1 μm to 1 μm, 1 μm to 100 μm, or 100 μm to 1 mm.

In some embodiments, the top electrode 112 is composed of the following materials: copper, galvanized iron, lead, nickel-chromium, zinc, aluminum, platinum, gold, ruthenium, copper alloys, graphite, calcium, cesium carbonate, lithium fluoride, molybdenum (VI) oxide, silver, carbon, palladium, tin, titanium, vanadium, chromium, manganese, cobalt, gallium, indium, scandium, mixed metal oxides, titanium nitride, tantalum nitride, thallium, doped silicon, polysilicon, germanium, antimony, tungsten, hafnium, iridium, alloys thereof, combinations thereof, or the like.

In some embodiments, the bottom electrode 106 is composed of the following materials: copper, galvanized iron, lead, nickel-chromium, zinc, phosphor bronze, aluminum, platinum, gold, ruthenium, copper alloys, graphite, calcium, cesium carbonate, lithium fluoride, molybdenum (VI) oxide, silver, carbon, palladium, tin, titanium, vanadium, chromium, manganese, cobalt, gallium, indium, scandium, mixed metal oxides, titanium nitride, tantalum nitride, thallium, doped silicon, polysilicon, germanium, antimony, tungsten, hafnium, iridium, alloys thereof, combinations thereof, or the like.

In some embodiments, the dielectric layer 108 is composed of: ceramics, metal oxides, aluminum nitride, lead zirconate titanate, carbides, silica, nitrides, or the like. In some embodiments, the passivation layer 110 may be or include, for example, the following materials: silicon nitride (e.g., Si)₃N₄) Ceramic, metal oxide, carbide, silicon dioxide, nitride or the like. In some embodiments, the metal frame may be or comprise, for example, the following materials: copper, galvanized iron, lead, nickel-chromium, zinc, aluminum, platinum, gold, ruthenium, copper alloys, graphite, calcium, cesium carbonate, lithium fluoride, molybdenum (VI) oxide, silver, carbon, palladium, tin, titanium, vanadium, chromium, manganese, cobalt, gallium, indium, scandium, mixed metal oxides, titanium nitride, tantalum nitride, thallium, doped silicon, polysilicon, germanium, antimony, tungsten, hafnium, iridium, alloys thereof, combinations thereof, or the like. The substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate.

Fig. 3A illustrates a perspective view of some embodiments of a MIM capacitor 300 a. MIM capacitor 300a includes substrate 102 positioned below bottom electrode 106. A dielectric layer 108 is disposed over the bottom electrode 106. A top electrode 112 is disposed over the dielectric layer 108. A passivation layer 110 is disposed over the top electrode 112. The passivation layer 110 contacts some of the sidewalls of the top electrode 112, the sidewalls of the dielectric layer 108, and the sidewalls of the bottom electrode 106. A metal frame 104 is disposed over the passivation layer 110. The metal frame 104 has a protrusion 104a, and the protrusion 104a extends to the top surface of the top electrode 112 through the passivation layer 110. The metal frame 104 may not cover the entire upper surface of the passivation layer 110.

On the first side 120 of the MIM capacitor 300a, the metal frame 104 extends continuously from the top surface of the top electrode 112 to the sidewalls of the passivation layer 110 and continues over the substrate 102. On the first side 120 of MIM capacitor 300a, a first electrical lead 116 is disposed over the top surface of metal frame 104. On the second side 122 of the MIM capacitor 300a, the metal frame 104 extends continuously from the top surface of the passivation layer 110 beyond the sidewalls of the dielectric layer 108 and continues over the top surface of the bottom electrode 106. On the second side 122 of the MIM capacitor 300a, a second electrical lead 114 is provided over the bottom electrode 106. The second electrical lead 114 has a protrusion 114a, the protrusion 114a extending through the passivation layer 110 and contacting the top surface of the bottom electrode 106.

Fig. 3B shows a top view of some additional embodiments of MIM capacitor 300B. MIM capacitor 300b has a length L and a width W. MIM capacitor 300b includes passivation layer 110 partially surrounded by metal frame 104. The protrusion 104a of the metal frame 104 protrudes into the passivation layer 110. A portion 110c of the passivation layer 110 is laterally disposed outside the metal frame 104. A first electrical lead 116 is disposed over the metal frame 104. Laterally beside said portion 110c of the passivation layer 110a second electrical lead 114 is provided. The portion 110c of the passivation layer 110 is located between the second electrical lead 114 and the metal frame 104. The first section 102a of the substrate 102 is disposed laterally beside the first electrical lead 116 and the second section 102b of the substrate 102 is disposed laterally beside the second electrical lead 114. In some embodiments, the protruding portion 114a of the second electrical lead 114 extends across the entire width W of the MIM capacitor 300B, as indicated by the dashed box labeled 114a in figure 3B. In other embodiments, the center of the protrusion 114a 'of the electrical lead 114 is disposed at the center of the width of the MIM capacitor 300B and does not extend across the entire width W of the MIM capacitor 300B, as shown by the other dashed box labeled 114 a' in figure 3B.

Fig. 4A illustrates a cross-sectional view of some embodiments of a MIM device 400 a. MIM device 400a includes a Printed Circuit Board (PCB) substrate 402 and MIM capacitor 119. MIM capacitor 119 includes dielectric layer 108 disposed over bottom electrode 106. A top electrode 112 is disposed over the dielectric layer 108. A passivation layer 110 is disposed over the top electrode 112. Passivation layer 110 contacts sidewalls of top electrode 112, sidewalls of dielectric layer 108, and sidewalls of bottom electrode 106. A metal frame 104 is disposed over the passivation layer 110. The metal frame 104 has a protrusion 104a, and the protrusion 104a extends through the passivation layer 110 and directly contacts the top surface of the top electrode 112. A second electrical lead 114 contacts the bottom electrode 106 through the passivation layer 110. A portion of the bottom surface of the second electrical lead 114 directly contacts the top surface of the bottom electrode 106, and another portion of the bottom surface of the second electrical lead 114 may contact the passivation layer 110 on the sidewall of the bottom electrode 106.

PCB substrate 402 includes metal lines 404. The metal line 404 has an electrical connection pad 404a to provide a wire bonding location for the metal line 404. A first solder ball 408a is disposed over the metal frame 104. A second solder ball 408b is disposed over the second electrical lead 114. The first solder ball 408a and the second solder ball 408b provide contact points for the metal lines 406. In some embodiments, metal line 406 electrically contacts metal line 404 through electrical connection pad 404 a. In other embodiments, the metal lines 406 are electrically coupled to different independent devices (not shown).

Referring to fig. 4B, a cross-sectional view of an integrated chip 400B according to some embodiments is provided.

Integrated chip 400b includes MIM capacitor 119 disposed between adjacent metal layers in interconnect structure 410 of integrated chip 400 b. Integrated chip 400b includes a substrate 411. The substrate 411 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. The illustrated embodiment depicts one or more Shallow Trench Isolation (STI) regions 412, which one or more shallow trench isolation regions 412 may comprise a dielectric-filled trench within a substrate 411.

An access transistor 413 is disposed between the STI regions 412. Access transistor 413 includes access gate electrode 414, access gate dielectric 418, access sidewall spacers 422, and source/drain regions 424. Source/drain regions 424 are disposed within the substrate 411 between the access gate electrode 414 and the STI regions 412 and are doped to have a first conductivity type that is opposite a second conductivity type of a channel region underlying the gate dielectric 418. The access gate electrode 414 may be, for example, doped polysilicon, silicide, or a metal (e.g., tungsten, titanium, or a combination thereof). The gate dielectric 418 may be, for example, an oxide (e.g., silicon dioxide) or a high dielectric constant dielectric material. Between access side wallsThe spacers 422 may be made of, for example, silicon nitride (e.g., Si)₃N₄) And (4) preparing.

Interconnect structure 410 is arranged over substrate 411 and couples devices (e.g., access transistor 413 and MIM capacitor 119) to one another. The interconnect structure 410 includes a plurality of inter-metal dielectric (IMD) layers 426, 428, 430 and a plurality of metallization layers 432, 434, 436, the plurality of IMD layers 426, 428, 430 and the plurality of metallization layers 432, 434, 436 being stacked on top of each other in an alternating manner. The IMD layers 426, 428, 430 can be made of, for example, low dielectric constant dielectrics, such as undoped silicate glass or oxides (e.g., silicon dioxide), or very low dielectric constant dielectric layers. The metallization layers 432, 434, 436 comprise metal lines 438, 440, 442, which metal lines 438, 440, 442 are formed in trenches and may be made of metal, such as copper or aluminum. Contact 444 extends from bottom metallization layer 432 to source/drain region 424 and/or gate electrode 414; and vias 446 extend between the metallization layers 432,434, 436. Via 447 extends between MIM capacitor 119 and metal line 440. The contacts 444 and vias 446 may be made of, for example, a metal (e.g., copper or tungsten).

Fig. 5-10 illustrate cross-sectional views 500-1000 of some embodiments of a method of forming a MIM capacitor including a passivation layer and a metal frame according to the present disclosure. Although the cross-sectional views 500 through 1000 shown in fig. 5 through 10 are described with reference to a method, it is to be understood that the structure shown in fig. 5 through 10 is not limited to the method but may be separately provided as a structure independent of the method. While fig. 5-10 are illustrated as a series of acts, it will be appreciated that the acts are not limiting, as the order of the acts may be varied in other embodiments and the disclosed methods are applicable to other configurations. In other embodiments, some acts shown and/or described may be omitted, in whole or in part.

As shown in cross-sectional view 500 of fig. 5, a substrate 102 is provided. A bottom electrode layer 502 is formed over the substrate 102. A dielectric film 504 is formed over the bottom electrode layer 502. A top electrode layer 506 is formed over the dielectric film 504. In some embodiments, the bottom electrode layer 502 and/or the top electrode layer 506 may be deposited and/or grown by electroless plating, electroplating, or other suitable deposition process. In some embodiments, the dielectric film 504 can be deposited and/or grown by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), thermal oxidation, or other suitable deposition processes.

In some embodiments, the bottom electrode layer 502 and/or the top electrode layer 506 are composed of the following materials: copper, galvanized iron, lead, nickel-chromium, zinc, aluminum, platinum, gold, ruthenium, copper alloys, graphite, calcium, cesium carbonate, lithium fluoride, molybdenum (VI) oxide, silver, carbon, palladium, tin, titanium, vanadium, chromium, manganese, cobalt, gallium, indium, scandium, mixed metal oxides, titanium nitride, tantalum nitride, thallium, doped silicon, polysilicon, germanium, antimony, tungsten, hafnium, iridium, alloys thereof, combinations thereof, or the like.

As shown in cross-sectional view 600 of fig. 6, a removal process is performed to remove portions of the bottom electrode layer (502 of fig. 5), portions of the dielectric film (504 of fig. 5), and portions of the top electrode layer (506 of fig. 5) and define the bottom electrode 106, the dielectric layer 108, and the top electrode 112, respectively. In some embodiments, the removal process may be performed by forming a mask layer (not shown) over the top electrode layer (506 of fig. 5) and then exposing the unmasked regions of the top electrode layer (506 of fig. 5) to one or more etchants 602. In some embodiments, the removal process includes multiple etching processes with different patterns to form the features with different regions.

On the first side 120, the bottom electrode 106 extends laterally from the sidewall 108b of the dielectric layer 108 by a first length L₁. On the second side 122, the bottom electrode 106 extends laterally a second length L from the sidewall 108a of the dielectric layer 108₂. In some embodiments, the second length L₂Is greater than the first length L₁Such that the bottom electrode 106 has sufficient space on the second side 122 to form an electrical contact over the top surface of the bottom electrode 106 that is laterally offset from the overlying metal frame by a non-zero distance (e.g., anE.g., see fig. 10).

As shown in the cross-sectional view 700 of fig. 7, a passivation film 702 is deposited over the upper surface of the top electrode 112, the bottom electrode 106, and the substrate 102. The passivation film 702 may be deposited, for example, by PVD, CVD, plasma-enhanced chemical vapor deposition (PECVD), ALD, or other suitable deposition process.

As shown in cross-sectional view 800 of fig. 8, an etching process is performed to etch away portions of the passivation film (702 of fig. 7) and define the passivation layer 110. The etching process removes a portion of the passivation film (702 of fig. 7) located above the top surface of the substrate 102, thereby exposing the top surface of the substrate 102. The etching process forms a first opening 802 in the passivation layer 110. The first opening 802 is located directly above the top surface of the top electrode 112. In addition, the etching process forms a second opening 804 in the passivation layer 110. The second opening 804 is located directly above the top surface of the bottom electrode 106. In some embodiments, the etching process may be performed by forming a mask layer (not shown) over the passivation film (702 of fig. 7) and then exposing the unmasked regions of the passivation film (702 of fig. 7) to one or more etchants 806.

The first opening 802 has a width w₁. In some embodiments, the width w₁In the range of 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 500 μm, 500 μm to 10mm, or 10mm to 100 mm. In some embodiments, the thickness of passivation layer 110 is in the range of 10 angstroms to 100 angstroms, 100 angstroms to 1000 angstroms, 0.1 μm to 1 μm, 1 μm to 100 μm, or 100 μm to 1 mm.

As shown in cross-sectional view 900 of fig. 9, a metal layer 902 is deposited over the substrate 102, the bottom electrode 106, the top electrode 112, and the passivation layer 110. The metal layer 902 fills the first opening (802 of fig. 8) and the second opening (804 of fig. 8) such that the metal layer 902 directly contacts the top electrode 112 and directly contacts the bottom electrode 106.

As shown in cross-sectional view 1000 of fig. 10, an etching process is performed to etch away portions of the metal layer (902 of fig. 9) and define the metal frame 104 and the second electrical lead 114. A second electrical lead 114 is located on the second side 122 and has a protrusion 114a, the protrusion 114a extending through the passivation layer 110 to the top surface of the bottom electrode 106. In some embodiments, the second electrical lead 114 is not formed because the electrical contact connected to the bottom electrode is made of an interconnect structure located below the bottom electrode. In some embodiments, the etching process may be performed by forming a mask layer (not shown) over the metal layer (902 of fig. 9) and then exposing the unmasked regions of the metal layer (902 of fig. 9) to one or more etchants 1002. After performing the etching process, a first electrical lead 116 is deposited over the metal frame 104. The first electrical lead 116 can be deposited and/or grown, for example, by electroless plating, electroplating, or other suitable deposition process.

In some embodiments, the etching process removes a portion of the metal layer (902 of fig. 9) directly above the top surface of the top electrode 112, thereby exposing a portion of the top surface of the passivation layer 110. For example, referring to the top view of fig. 3B, in the top view of fig. 3B, the top surface of the passivation layer 110 is not covered by the metal frame 104. Further, the etching process removes a portion of the metal layer (902 of fig. 9) on the second side 122 that is above the top surface of the bottom electrode 106. For example, referring to the top view of fig. 3B, in the top view of fig. 3B, the portion 110c of the passivation layer 110 is not covered by the metal frame 104. In addition, the etching process also removes the metal layer (902 of fig. 9) from the edge of the device to expose the substrate 102 (see, e.g., the first and second sections 102a, 102B of the substrate 102 of fig. 3B).

Fig. 11 illustrates a method 1100 of forming a MIM capacitor according to some embodiments. While method 1100 is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited by the illustrated ordering or acts. Thus, in some embodiments, the actions may be performed in a different order than shown, and/or may be performed concurrently. Further, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events, which may be performed at different times or concurrently with other actions or sub-actions. In some embodiments, some illustrated acts or events may be omitted, and other acts or events not illustrated may also be included.

At act 1102, a bottom electrode is formed over a substrate. Fig. 5 illustrates a cross-sectional view 500 corresponding to some embodiments of act 1102.

At act 1104, a dielectric layer is formed over the bottom electrode. Fig. 5 illustrates a cross-sectional view 500 corresponding to some embodiments of act 1104.

At act 1106, a top electrode is formed over the dielectric layer. Fig. 5 illustrates a cross-sectional view 500 corresponding to some embodiments of act 1106.

At act 1108, a removal process is performed to remove a portion of the top electrode, a portion of the dielectric layer, and a portion of the bottom electrode. Fig. 6 illustrates a cross-sectional view 600 corresponding to some embodiments of act 1108.

At act 1110, a passivation layer is formed over the top and bottom electrodes, the passivation layer having a first opening over a top surface of the top electrode. Fig. 7-8 illustrate cross-sectional views 700 and 800 corresponding to some embodiments of act 1110.

At act 1112, a metal frame is formed over the passivation layer, the metal frame filling the first opening and contacting the top surface of the top electrode. Fig. 9 illustrates a cross-sectional view 900 corresponding to some embodiments of act 1112.

Accordingly, in some embodiments, the present disclosure is directed to a method of forming a MIM capacitor comprising a passivation layer and a metal frame directly contacting a top electrode.

In some embodiments, the present disclosure relates to a metal-insulator-metal (MIM) capacitor comprising: a top electrode overlying the substrate; a passivation layer overlying the top electrode, wherein the passivation layer has a stepped region that continuously extends from a top surface of the top electrode to a sidewall of the top electrode and continuously contacts the top surface and sidewall of the top electrode; and a metal frame overlying the passivation layer, wherein the metal frame continuously extends from a top surface of the passivation layer to an upper sidewall of the passivation layer in the mesa region and continuously contacts the top surface and the upper sidewall of the passivation layer, and wherein the metal frame has a protrusion extending through the passivation layer and contacting the top surface of the top electrode.

In the above metal-insulator-metal capacitor, wherein the protrusion is laterally offset from the step region by a non-zero distance.

In the above metal-insulator-metal capacitor, further comprising: a bottom electrode located below the top electrode; a dielectric layer disposed between the top electrode and the bottom electrode; wherein the passivation layer extends continuously along sidewalls of the dielectric layer and sidewalls of the bottom electrode, wherein the metal frame extends continuously along inner sidewalls of the passivation layer to the top surface and the upper sidewalls of the passivation layer.

In the above metal-insulator-metal capacitor, wherein in the step region, the passivation layer has a first horizontal section located above the inclined section and a second horizontal section located below the inclined section.

In the above metal-insulator-metal capacitor, wherein in the step region, the passivation layer has a first horizontal section located above a vertical section.

In the above mim capacitor, wherein the dielectric layer comprises a first dielectric sidewall and a second dielectric sidewall opposite the first dielectric sidewall, wherein the bottom electrode comprises a first electrode sidewall and a second electrode sidewall opposite the first electrode sidewall, wherein the first dielectric sidewall and the second dielectric sidewall are laterally located between the first electrode sidewall and the second electrode sidewall, wherein the first dielectric sidewall is laterally offset from the first electrode sidewall by a first distance, and wherein the second dielectric sidewall is laterally offset from the second electrode sidewall by a second distance, the second distance being greater than the first distance.

In the above metal-insulator-metal capacitor, further comprising: an electrical lead overlying the bottom electrode, the electrical lead contacting a top surface of the bottom electrode at: the point is laterally offset from the second dielectric sidewall by a non-zero distance in a direction away from the dielectric layer.

In the above metal-insulator-metal capacitor, wherein the electrical lead has a protrusion extending through the passivation layer and directly contacting the top surface of the bottom electrode.

In the above metal-insulator-metal capacitor, wherein the metal frame continuously surrounds and contacts an outer periphery of the passivation layer from a first point located below a bottom surface of the top electrode to a second point located above the top surface of the top electrode.

In other embodiments, the present disclosure relates to a metal-insulator-metal (MIM) capacitor comprising: a bottom electrode disposed over the substrate; a dielectric layer disposed over the bottom electrode; a top electrode disposed over the dielectric layer; a passivation layer disposed over the top electrode, wherein the passivation layer extends continuously over a top surface and sidewalls of the top electrode, over sidewalls of the dielectric layer, and over sidewalls of the bottom electrode; and a metal frame disposed over an upper surface of the passivation layer and along sidewalls of the passivation layer, wherein the metal frame has a protrusion extending through the passivation layer and contacting a top surface of the top electrode.

In the above metal-insulator-metal capacitor, wherein the protrusion directly contacts an inner sidewall of the passivation layer and is located laterally between the sidewalls of the top electrode.

In the above metal-insulator-metal capacitor, wherein in a top view, an outermost sidewall of the dielectric layer extends beyond an outermost sidewall of the top electrode.

In the above metal-insulator-metal capacitor, wherein the metal frame continuously extends from an inner sidewall of the passivation layer to a top surface and an upper sidewall of the passivation layer.

In the above metal-insulator-metal capacitor, wherein the metal frame is discontinuous over a central portion of the top surface of the passivation layer.

In the above metal-insulator-metal capacitor, further comprising: an electrical contact overlying the passivation layer and the bottom electrode, wherein the electrical contact has a protrusion extending through the passivation layer and directly contacting a top surface of the bottom electrode.

In the above metal-insulator-metal capacitor, wherein the metal frame continuously surrounds and extends from an outer periphery of a bottom surface of the dielectric layer to a point above the top surface of the top electrode.

In the above-described metal-insulator-metal capacitor, wherein the protruding portion of the metal frame is rectangular in shape when viewed from above.

In still other embodiments, the present disclosure relates to a method of forming a metal-insulator-metal (MIM) capacitor. The method comprises the following steps: forming a bottom electrode layer over a substrate; forming a dielectric film over the bottom electrode layer; forming a top electrode layer over the dielectric film; performing a removal process to remove a portion of the top electrode layer, a portion of the dielectric film, and a portion of the bottom electrode layer to form a top electrode, a dielectric layer, and a bottom electrode; forming a passivation layer over the top electrode and the bottom electrode, wherein the passivation layer has a first opening over a top surface of the top electrode, and wherein the passivation layer has a second opening over a top surface of the bottom electrode; and forming a metal frame over the passivation layer, wherein the metal frame fills the first opening and contacts the top surface of the top electrode through the first opening.

In the above method of forming a metal-insulator-metal capacitor, wherein forming the metal frame comprises: depositing a metal layer over the passivation layer and the bottom electrode; and performing an etching process on the metal layer to define the metal frame and a first electrical lead, wherein the first electrical lead fills the second opening and contacts a top surface of the bottom electrode.

In the above method of forming a metal-insulator-metal capacitor, wherein the etching process exposes a top surface of the passivation layer overlying the top electrode.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (1)

1. A metal-insulator-metal capacitor comprising:

a top electrode overlying the substrate;

a passivation layer overlying the top electrode, wherein the passivation layer has a stepped region that extends continuously from a top surface of the top electrode to a sidewall of the top electrode and continuously contacts the top surface and the sidewall of the top electrode; and

a metal frame overlying the passivation layer, wherein the metal frame extends continuously from a top surface of the passivation layer to an upper sidewall of the passivation layer in the mesa region and continuously contacts the top surface and the upper sidewall of the passivation layer, and wherein the metal frame has a protrusion extending through the passivation layer and contacting the top surface of the top electrode.

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