WO2017057542A1 - Probe card-use laminate wiring substrate and probe card equipped with same - Google Patents

Probe card-use laminate wiring substrate and probe card equipped with same Download PDF

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Publication number
WO2017057542A1
WO2017057542A1 PCT/JP2016/078770 JP2016078770W WO2017057542A1 WO 2017057542 A1 WO2017057542 A1 WO 2017057542A1 JP 2016078770 W JP2016078770 W JP 2016078770W WO 2017057542 A1 WO2017057542 A1 WO 2017057542A1
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Prior art keywords
wiring board
laminated
resin portion
probe card
core substrate
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PCT/JP2016/078770
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French (fr)
Japanese (ja)
Inventor
酒井 範夫
川上 弘倫
竹村 忠治
喜人 大坪
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株式会社村田製作所
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Priority to JP2017543539A priority Critical patent/JP6589990B2/en
Publication of WO2017057542A1 publication Critical patent/WO2017057542A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/073Multiple probes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits

Definitions

  • the present invention relates to a multilayer wiring board having a ceramic layer and a probe card using the multilayer wiring board.
  • a laminated wiring board is used for rewiring a probe pin and a mother board.
  • this type of multilayer wiring board there is a ceramic substrate formed by laminating a plurality of ceramic layers.
  • a thin film wiring portion is further provided on a ceramic substrate to form fine wiring.
  • a ceramic wiring substrate 100 described in Patent Document 1 includes a ceramic layer 101 in which a plurality of ceramic insulating layers 101a are stacked and a resin layer in which a plurality of insulating resin layers 102a are stacked. 102, and the resin layer 102 is laminated on the ceramic layer 101.
  • the resin layer 102 insulating resin layers 102a and wiring layers 103 are alternately laminated, and the wiring layers 103 positioned above and below the insulating resin layer 102a are connected by via conductors 104.
  • the via conductor 104 formed in the lowermost insulating resin layer 102 a and the end of the internal wiring 105 exposed on the upper surface of the ceramic wiring substrate 100 are electrically connected.
  • a convex portion 109 is formed on the upper surface of the ceramic layer 101 so as to surround and surround the connection portion between the via conductor 104 and the internal wiring 105.
  • the convex portion 109 is formed of a material having a Young's modulus greater than that of the resin forming the insulating resin layer 102a.
  • connection portion between the via conductor 104 and the end portion of the internal wiring 105 is surrounded and protected by the convex portion 109 formed of a material having a high Young's modulus.
  • the laminated wiring board used for the probe card may require a thickness of about several mm.
  • the resin layer is a thin film layer in which resins such as polyimide are laminated, and it is difficult to increase the thickness of the resin layer from the viewpoint of cost. Therefore, it is conceivable to form a laminated wiring board by thickening the ceramic layer.
  • the present invention has been made in view of the above-described problems, and reduces the occurrence of defects such as misalignment and chipping that can occur with an increase in the thickness of the ceramic layer, and improves the heat dissipation of the multilayer wiring board.
  • the purpose is to plan.
  • a multilayer wiring board for a probe card is a ceramic in which a plurality of ceramic layers are laminated in a multilayer wiring board for a probe card to which a plurality of probe pins are connected.
  • a core substrate having a laminated portion, wherein the plurality of probe pins are connected to one main surface; a first resin portion laminated on the other main surface of the core substrate; and the first resin portion, One end surface is provided on a surface of the first resin portion that faces the surface on the core substrate side, and includes metal pins that are electrically connected to the plurality of probe pins.
  • the multilayer wiring board can be formed thin while maintaining a predetermined thickness.
  • the thickness of the first resin portion can be adjusted by polishing the surface. For this reason, the occurrence of misalignment due to the thickness of the ceramic laminated portion can be reduced, and the laminated wiring board can be easily fired and cut.
  • the heat dissipation of the multilayer wiring board can be improved, and the temperature rise of the board when the probe card is used can be prevented.
  • the flatness of the board which is important as a laminated wiring board for probe cards, can be ensured by polishing the metal pins and the resin portion.
  • the core substrate further includes a second resin portion laminated on a surface of the ceramic laminate portion that faces the surface on the first resin portion side, and the second resin portion includes a second resin portion on the first resin portion side.
  • a surface facing the surface may form the one main surface of the core substrate.
  • the second resin portion is formed of a resin such as polyimide capable of forming a fine wiring, the wiring can be easily thinned.
  • the probe card is brought into contact with the semiconductor element to be inspected many times, but by laminating the second resin part on the ceramic laminated part, the stress and impact can be alleviated, and deformation of the laminated wiring board is prevented. can do.
  • a component may be built in the first resin portion. It is desirable to place components such as bypass capacitors near the probe pins in order to improve the ability to remove noise generated during inspection. Conventionally, such components are separated from the probe pins. Often placed on top. Therefore, by incorporating a component such as a bypass capacitor in the first resin portion laminated on the core substrate, the component can be arranged at a position closer to the probe pin than in the prior art. Further, by incorporating the components that have been mounted on the mother board into the multilayer wiring board, the mounting area of the mother board can be saved.
  • a via conductor formed inside the core substrate may be provided, and a cross-sectional area in a direction perpendicular to the axis of the metal pin may be larger than a cross-sectional area in a direction perpendicular to the axis of the via conductor.
  • the metal pin disposed in the first resin portion is a columnar conductor that is thicker than the via conductor disposed in the ceramic laminated portion, and the electrical resistivity of the metal pin is greater than the electrical resistivity of the via conductor. small. Therefore, by forming the wiring of the first resin portion with metal pins, the electrical resistance of the entire laminated wiring board is lowered, and the mother board and the probe pins can be connected with low resistance.
  • the structure provided with resin around the metal pin can relieve stress applied by the contact when the multilayer wiring board contacts the IC when used as a probe.
  • a pad electrode formed on a surface of the first resin portion facing the core substrate side and connected to the one end surface of the metal pin may be provided.
  • the laminated wiring board and the mother board are connected by soldering, but by providing a pad electrode on the end face of the metal pin, it is easier to attach the plating to the pad electrode than plating the end face of the metal pin directly.
  • the solderability is improved, and the connection reliability between the multilayer wiring board and the mother board is improved. Further, by increasing the pad electrode, it is possible to easily perform alignment when connecting the laminated wiring board to the mother board.
  • the above laminated wiring board for a probe card for performing an electrical inspection of an object to be inspected.
  • a probe card having high durability and high connection reliability with the mother board.
  • the ceramic laminated portion can be formed thin while maintaining the entire thickness of the probe card laminated wiring board, so that the stacking deviation caused by the thick ceramic laminated portion can be reduced.
  • the problems at the time of cutting and firing the laminated wiring board can be solved.
  • the metal pins in the resin portion the heat dissipation of the multilayer wiring board is improved, and the temperature rise of the board when using the probe card can be prevented.
  • FIGS. 1 and 2 are cross-sectional views of the probe card 1
  • FIG. 2 is a cross-sectional view of a laminated wiring board 3a mounted on the probe card 1 of FIG.
  • the probe card 1 includes a mother board 2, a laminated wiring board 3a mounted on one main surface of the mother board 2, and one end connected to the laminated wiring board 3a.
  • a plurality of probe pins 5, a probe head 4 that supports each probe pin 5, and a cover body 32 that fixes the probe head 4 are provided, and are used for, for example, an electrical inspection of an object to be inspected 50 such as a semiconductor element.
  • the mother substrate 2 has a plurality of mounting electrodes 6 for mounting the multilayer wiring board 3a on one main surface, and a plurality of external electrodes 7 for external connection formed on the other main surface.
  • each mounting electrode 6 is connected to a predetermined external electrode 7 by a wiring electrode 30 and a plurality of via conductors 31 formed inside the mother substrate.
  • the mother substrate 2 is made of, for example, glass epoxy resin.
  • the probe head 4 that holds each probe pin 5 is fixed to a cover body 32 that is fixed to the mother board 2.
  • the laminated wiring board 3 a includes a core substrate 8, a first resin portion 9 laminated on the core substrate 8, and a plurality of metal pins 12 disposed inside the first resin portion 9.
  • the core substrate 8 includes a ceramic laminated portion 10 disposed on the first resin portion 9 side and a second resin portion 18 laminated on a main surface 19 opposite to the main surface 14 on the mother substrate 2 side in the ceramic laminated portion 10. And have. At this time, the ceramic laminated portion 10 is formed by alternately laminating ceramic layers 10a and wiring layers 10b.
  • Each ceramic layer 10a is formed of various ceramics such as a low-temperature co-fired ceramic (LTCC) or a high-temperature fired ceramic (HTCC) mainly composed of a ceramic (for example, alumina) containing borosilicate glass. be able to.
  • the ceramic laminated portion 10 is formed of four ceramic layers 10a and three wiring layers 10b. However, the number of these layers can be changed as appropriate.
  • Each ceramic layer 10a is formed with a plurality of via conductors 16 that connect the wiring electrodes 15 formed in different wiring layers 10b.
  • Each wiring electrode 15 and each via conductor 16 are each formed of a metal such as Cu, Ag, or Al.
  • the various wiring electrodes 15 formed in each wiring layer 10b are formed by screen printing using a conductive paste containing the metal (Cu, Ag, Al, etc.), for example.
  • the second resin portion 18 is a laminated body composed of a plurality of resin layers 18a, and is laminated on the main surface 19 on the opposite side of the ceramic laminated portion 10 from the mother substrate 2 side.
  • a plurality of connection electrodes 21 to which the probe pins 5 are connected are formed on the main surface 11 of the second resin portion 18 located on the opposite side of the main surface 19 of the ceramic laminated portion 10.
  • Each connection electrode 21 can be formed by, for example, a base electrode formed of Cu or the like and a surface electrode obtained by performing Ni / Au plating on the base electrode.
  • each wiring electrode 20 forms a Ti film as a base electrode on the main surface of the resin layer 18a by sputtering or the like, and similarly forms a Cu film on the Ti film by sputtering or the like. And it can form by forming a Cu film
  • Each wiring electrode 15 formed in the ceramic laminated portion 10 is formed by screen printing or the like and thus has a thick film pattern, whereas each wiring electrode 20 formed in the second resin portion 18 is sputtered. Since the film is formed by a method such as that, a thin film pattern is formed. In addition, each wiring electrode 20 formed in the second resin portion 18 is thinned by photolithography.
  • connection electrode 21 is electrically connected to a plurality of external electrodes 7 formed on the other main surface of the mother substrate 2. Specifically, as shown in FIGS. 1 and 2, each connection electrode 21 is formed on each wiring electrode 20 and each via conductor 22 formed on the second resin portion 18, and on the ceramic laminated portion 10, respectively. Each wiring electrode 15 and each via conductor 16 are connected to each predetermined external electrode 7 via the wiring electrode 30 and each via conductor 31 formed on the mother substrate 2.
  • the first resin portion 9 is laminated on the main surface 14 of the core substrate 8 on the mother substrate 2 side, and has an opposite surface 13 that faces the main surface 14.
  • the first resin portion 9 is provided with the metal pins 12 standing in the thickness direction of the core substrate 8, fixing them, laminating the resin so as to cover the metal pins 12, curing, and then adjusting the thickness.
  • the surface 13 of the first resin portion 9 opposite to the main surface 14 is polished and molded.
  • a resin such as an epoxy resin can be used.
  • techniques such as a coating method, a printing method, a transfer mold method, and a compression mold method can be used for forming the first resin portion 9.
  • the opposite surface 13 of the first resin portion 9 and the mother substrate 2 are connected by solder.
  • the plurality of metal pins 12 are disposed in the first resin portion 9 so as to be joined to the plurality of electrodes 17 provided on the main surface 14 of the core substrate 8 on the mother substrate 2 side, and are formed by the wiring layer 10 b of the core substrate 8.
  • Each probe pin 5 is electrically connected.
  • Each metal pin 12 can be formed by, for example, shearing a wire formed of a metal such as Cu, Ag, or Al. Further, the end surface 12 a that is the exposed portion of each metal pin 12 on the opposite surface 13 of the first resin portion 9 may be plated.
  • each metal pin 12 is formed larger than the cross-sectional area in the direction perpendicular to the axis (length direction) of each metal pin 12 is formed larger than the cross-sectional area in the direction perpendicular to the axis of each via conductor 16.
  • Each electrode 17 is formed on the main surface 14 of the core substrate 8 in accordance with the size of the cross-sectional area of each metal pin 12, and each metal pin 12 is disposed so as to be joined to each electrode 17.
  • Each electrode 17 is formed of a metal such as Cu, Ag, or Al. Note that the size of the cross-sectional area of each metal pin 12 can be changed as appropriate, such as the same as the cross-sectional area of the via conductor 16.
  • the first resin portion 9 by providing the first resin portion 9 on the multilayer wiring substrate 3a, it is possible to suppress the thickness of the ceramic multilayer portion 10 while forming the multilayer wiring substrate 3a with a predetermined thickness.
  • it can. 1 and 2 show a configuration in which the first resin portion 9 is thinner than the ceramic laminated portion 10, the first resin portion 9 is formed thicker than the ceramic laminated portion 10. Also good.
  • the thickness of the first resin portion 9 may be larger than the total thickness of the ceramic laminated portion 10 and the second resin portion 18. According to the present embodiment, since the thickness of the ceramic multilayer portion 10 can be suppressed, the occurrence of misalignment due to the increase in the thickness of the ceramic multilayer portion 10 can be reduced, and the multilayer wiring board 3a.
  • the connection of the multilayer wiring substrate 3a to the mother substrate 2 can be performed on the first resin portion 9 side where the difference in thermal expansion coefficient from the mother substrate 2 is small, the connection between the multilayer wiring substrate 3a and the mother substrate 2 is possible. Reliability can be improved. Furthermore, since the thickness of the laminated wiring board 3a can be adjusted by polishing the first resin part 9, the polishing process is more than the conventional method of adjusting the thickness by polishing the ceramic laminated part 10. It becomes easy.
  • each metal pin 12 has higher thermal conductivity than each via conductor 16 in the core substrate 8, it is possible to improve heat dissipation of the multilayer wiring board 3a, and the multilayer wiring board 3a when the probe card is used. Temperature rise can be prevented. Furthermore, since the electrical resistivity of each metal pin 12 is smaller than the electrical resistivity of each via conductor 16, compared to the case where the wiring of the first resin portion 9 is formed of a via conductor, the electrical resistance of the entire multilayer wiring board 3 a is increased. The resistance decreases, and the mother board 2 and each probe pin 5 can be connected with low resistance. Further, by forming the cross-sectional area of each metal pin 12 to be larger than the cross-sectional area of each via conductor 16, the electrical resistance of the multilayer wiring board 3a can be further reduced.
  • the second resin portion 18 on the core substrate 8 facilitates thinning of the wiring, so that it is possible to provide the multilayer wiring substrate 3a that can be used for electrical inspection of semiconductor elements having a narrow terminal pitch.
  • both the resin portions 9 and 18 function as a cushioning material, and the physical properties when the probe card is used. Stress and impact due to mechanical contact can be reduced. Therefore, deformation and breakage of the ceramic laminated portion 10 can be reduced, durability of the laminated wiring board 3a can be improved, and occurrence of disconnection of each wiring electrode 15 can be reduced.
  • FIG. 3 is a cross-sectional view of the multilayer wiring board 3b.
  • the laminated wiring board 3b according to this embodiment differs from the first embodiment described with reference to FIGS. 1 and 2 in that a component 23 is built in the first resin portion 9 as shown in FIG. It is that you are. Since other configurations are the same as those of the multilayer wiring board 3a of the first embodiment, description thereof is omitted by attaching the same reference numerals.
  • a component 23 is mounted on one main surface 14 of the core substrate 8, and the component 23 is built in the first resin portion 9.
  • the component 23 includes, for example, a chip capacitor, a chip inductor, a chip resistor, a fuse chip, and the like.
  • the component 23 is configured by a bypass capacitor (chip capacitor) that connects the power supply line and the ground.
  • the component 23 when the component 23 is built in the first resin portion 9, the component 23 can be arranged at a position closer to each probe pin 5 than the conventional mounting on the mother board 2. The removal ability can be improved.
  • the mounting area of the mother board 2 can be reduced by incorporating components previously mounted on the mother board 2 in the multilayer wiring board 3b, the probe card 1 can be reduced in size.
  • FIG. 4 is a cross-sectional view of the multilayer wiring board 3c.
  • the laminated wiring board 3c according to this embodiment differs from the first embodiment described with reference to FIGS. 1 and 2 in that pad electrodes 24 are provided on the end surfaces 12a of the respective metal pins 12, as shown in FIG. It is provided. Since other configurations are the same as those of the multilayer wiring board 3a of the first embodiment, description thereof is omitted by attaching the same reference numerals.
  • a plurality of pad electrodes 24 are arranged so as to cover the end surfaces 12a of the respective metal pins 12 on the opposite surface 13 of the first resin portion 9.
  • Each pad electrode 24 is formed larger than the end surface 12a of each metal pin 12 to be connected.
  • Each pad electrode 24 may be formed by plating, or may be a conductive paste that has been plated. Further, another electrode may be provided on the opposite surface 13 of the first resin portion 9.
  • each pad electrode 24 is plated. Since it adheres easily, the solderability can be improved. Further, by forming each pad electrode 24 larger than the end face 12a of each metal pin 12, the connection reliability between the multilayer wiring board 3c and the mother board 2 is improved, and the multilayer wiring board 3c is connected to the mother board 2. Position alignment can be easily performed.
  • the core substrate 8 includes the ceramic laminated portion 10 and the second resin portion 18, but the portion of the second resin portion 18 may also be formed of ceramic.
  • the present invention can be widely applied to various probe cards used for electrical inspection of an object to be inspected.

Abstract

Provided is a probe card-use laminate wiring substrate that includes a laminate of resin layers, wherein the probe card laminate wiring substrate reduces the occurrence of defects such as lamination deviations and chipping caused by an increase in the thickness of a ceramic laminate part, and improves a heat dissipating property of the laminate wiring substrate. A laminate wiring substrate 3a is provided with: a core substrate 8; a first resin part 9 that is stacked on the core substrate 8; and a plurality of metal pins 12 that are disposed inside the first resin part 9. The core substrate 8 includes a ceramic laminate part 10 that is arranged on the first resin part 9 side and a second resin part 18 that is stacked on a main surface 19 of the ceramic laminate part 10, the main surface 19 being opposite a main surface 14 of the ceramic laminate 10 on the mother substrate 2 side. The metal pins 12 are disposed so as to be connected to a plurality of electrodes 17 that are provided on the mother substrate 2 side main surface 14 of the core substrate 8 and are electrically connected to probe pins 5 via a wiring layer 10b of the core substrate 8.

Description

プローブカード用積層配線基板およびこれを備えるプローブカードLaminated wiring board for probe card and probe card having the same
 本発明は、セラミック層を有する積層配線基板およびこの積層配線基板を用いたプローブカードに関する。 The present invention relates to a multilayer wiring board having a ceramic layer and a probe card using the multilayer wiring board.
 従来、半導体素子の電気的な検査に用いられるプローブカードでは、プローブピンとマザー基板の再配線を行うために積層配線基板が用いられる。この種の積層配線基板のなかに、複数のセラミック層が積層されてなるセラミック基板がある。また、近年の半導体素子の狭ピッチ化に伴い、セラミック基板上に薄膜配線部をさらに設け、微細な配線を形成するものがある。 Conventionally, in a probe card used for electrical inspection of a semiconductor element, a laminated wiring board is used for rewiring a probe pin and a mother board. Among this type of multilayer wiring board, there is a ceramic substrate formed by laminating a plurality of ceramic layers. In addition, with the recent narrowing of the pitch of semiconductor elements, there is a type in which a thin film wiring portion is further provided on a ceramic substrate to form fine wiring.
 例えば、図5に示すように、特許文献1に記載のセラミック配線基板100は、複数のセラミック絶縁層101aが積層されてなるセラミック層101と、複数の絶縁樹脂層102aが積層されてなる樹脂層102とを備え、セラミック層101上に樹脂層102が積層された構造となる。樹脂層102は、絶縁樹脂層102aと配線層103が交互に積層され、絶縁樹脂層102aの上下に位置する各配線層103間がビア導体104で接続される。また、最下層の絶縁樹脂層102aに形成されたビア導体104と、セラミック配線基板100の上面に露出した内部配線105の端部とが電気的に接続される。 For example, as shown in FIG. 5, a ceramic wiring substrate 100 described in Patent Document 1 includes a ceramic layer 101 in which a plurality of ceramic insulating layers 101a are stacked and a resin layer in which a plurality of insulating resin layers 102a are stacked. 102, and the resin layer 102 is laminated on the ceramic layer 101. In the resin layer 102, insulating resin layers 102a and wiring layers 103 are alternately laminated, and the wiring layers 103 positioned above and below the insulating resin layer 102a are connected by via conductors 104. In addition, the via conductor 104 formed in the lowermost insulating resin layer 102 a and the end of the internal wiring 105 exposed on the upper surface of the ceramic wiring substrate 100 are electrically connected.
 セラミック層101の上面に、ビア導体104と内部配線105との接続部を離間して取り囲むように凸部109が形成される。凸部109は、絶縁樹脂層102aを形成する樹脂よりもヤング率の大きい材料で形成される。 A convex portion 109 is formed on the upper surface of the ceramic layer 101 so as to surround and surround the connection portion between the via conductor 104 and the internal wiring 105. The convex portion 109 is formed of a material having a Young's modulus greater than that of the resin forming the insulating resin layer 102a.
 このような配線基板によれば、ビア導体104と内部配線105の端部との接続部は、ヤング率が大きい材料で形成された凸部109によって周囲を取り囲まれて保護される。これにより、当該接続部に加わる熱応力が低減され、断線の可能性が低減され信頼性が高まる。 According to such a wiring board, the connection portion between the via conductor 104 and the end portion of the internal wiring 105 is surrounded and protected by the convex portion 109 formed of a material having a high Young's modulus. Thereby, the thermal stress added to the said connection part is reduced, the possibility of a disconnection is reduced, and reliability increases.
特開2011-108959号公報(段落0027~0030、図1等参照)Japanese Patent Laying-Open No. 2011-108959 (see paragraphs 0027 to 0030, FIG. 1, etc.)
 プローブカードに用いられる積層配線基板は数mm程度の厚さが必要な場合がある。樹脂層は、ポリイミド等の樹脂を積層した薄膜状の層であり、この樹脂層を厚くすることはコストの面などから困難である。そのため、セラミック層を厚くして、積層配線基板を形成することが考えられる。 The laminated wiring board used for the probe card may require a thickness of about several mm. The resin layer is a thin film layer in which resins such as polyimide are laminated, and it is difficult to increase the thickness of the resin layer from the viewpoint of cost. Therefore, it is conceivable to form a laminated wiring board by thickening the ceramic layer.
 しかしながら、積層配線基板を所定の厚さに形成するためにセラミック層の積層数を増加させると、積層された上下のセラミックグリーンシート間で互いに位置がずれる、いわゆる積層ずれが発生したり、積層配線基板の平坦性が損なわれるリスクが高くなる。また、積層配線基板をカットする際に、セラミック層の厚さのためにカットが困難になり、チッピング等の不具合が発生する可能性がある。さらに、これらの積層配線基板を用いたプローブカードは、使用時に高周波電流が流れて発熱し、高温によりプローブカードが変形するおそれがある。 However, when the number of laminated ceramic layers is increased in order to form a multilayer wiring board with a predetermined thickness, the so-called stacking misalignment occurs between the upper and lower ceramic green sheets that are stacked, The risk that the flatness of the substrate is impaired increases. In addition, when cutting the laminated wiring board, it becomes difficult to cut due to the thickness of the ceramic layer, which may cause problems such as chipping. Furthermore, probe cards using these multilayer wiring boards generate heat when high-frequency current flows during use, and the probe card may be deformed due to high temperatures.
 本発明は、上記した課題に鑑みてなされたものであり、セラミック層の厚さの増加に伴って生じうる積層ずれやチッピング等の不具合の発生を低減し、積層配線基板の放熱性の向上を図ることを目的とする。 The present invention has been made in view of the above-described problems, and reduces the occurrence of defects such as misalignment and chipping that can occur with an increase in the thickness of the ceramic layer, and improves the heat dissipation of the multilayer wiring board. The purpose is to plan.
 上記した目的を達成するために、本発明の一態様に係るプローブカード用積層配線基板は、複数のプローブピンが接続されるプローブカード用積層配線基板において、複数のセラミック層が積層されてなるセラミック積層部を有し、一方主面に前記複数のプローブピンが接続されるコア基板と、前記コア基板の他方主面に積層された第1樹脂部と、前記第1樹脂部に配設され、一方の端面が前記第1樹脂部における前記コア基板側の面と対向する面に設けられ、前記複数のプローブピンと電気的に接続される金属ピンとを備えることを特徴とする。 In order to achieve the above object, a multilayer wiring board for a probe card according to one aspect of the present invention is a ceramic in which a plurality of ceramic layers are laminated in a multilayer wiring board for a probe card to which a plurality of probe pins are connected. A core substrate having a laminated portion, wherein the plurality of probe pins are connected to one main surface; a first resin portion laminated on the other main surface of the core substrate; and the first resin portion, One end surface is provided on a surface of the first resin portion that faces the surface on the core substrate side, and includes metal pins that are electrically connected to the plurality of probe pins.
 この構成によると、第1樹脂部に厚さを持たせることで、積層配線基板は所定の厚さを維持しつつ、セラミック積層部を薄く形成することができる。なお、第1樹脂部は表面の研磨により、厚さの調節が可能である。このため、セラミック積層部の厚さに起因する積層ずれの発生を低減することができるとともに、積層配線基板の焼成やカットが容易となる。また、ビア導体よりも熱伝導率の高い金属ピンを使用することで、積層配線基板の放熱性を向上させることができ、プローブカードの使用時の基板の温度上昇を防ぐことができる。さらにプローブカード用積層配線基板として重要な基板の平坦性も、金属ピンおよび樹脂部の研磨により確保する事が出来る。 According to this configuration, by giving the first resin portion a thickness, the multilayer wiring board can be formed thin while maintaining a predetermined thickness. Note that the thickness of the first resin portion can be adjusted by polishing the surface. For this reason, the occurrence of misalignment due to the thickness of the ceramic laminated portion can be reduced, and the laminated wiring board can be easily fired and cut. Further, by using a metal pin having a higher thermal conductivity than the via conductor, the heat dissipation of the multilayer wiring board can be improved, and the temperature rise of the board when the probe card is used can be prevented. Furthermore, the flatness of the board, which is important as a laminated wiring board for probe cards, can be ensured by polishing the metal pins and the resin portion.
 また、前記コア基板は、前記セラミック積層部における前記第1樹脂部側の面と対向する面に積層された第2樹脂部をさらに備え、前記第2樹脂部において、前記第1樹脂部側の面と対向する面が、前記コア基板の前記一方主面をなすことを特徴としていてもよい。この場合、例えば、第2樹脂部を微細な配線形成が可能なポリイミドなどの樹脂で形成すると、配線の細線化が容易になる。また、プローブカードは検査対象の半導体素子に何度も接触させるが、セラミック積層部に第2樹脂部を積層することで、その応力や衝撃を緩和させることができ、積層配線基板の変形を防止することができる。 The core substrate further includes a second resin portion laminated on a surface of the ceramic laminate portion that faces the surface on the first resin portion side, and the second resin portion includes a second resin portion on the first resin portion side. A surface facing the surface may form the one main surface of the core substrate. In this case, for example, if the second resin portion is formed of a resin such as polyimide capable of forming a fine wiring, the wiring can be easily thinned. In addition, the probe card is brought into contact with the semiconductor element to be inspected many times, but by laminating the second resin part on the ceramic laminated part, the stress and impact can be alleviated, and deformation of the laminated wiring board is prevented. can do.
 また、前記第1樹脂部に部品が内蔵されていてもよい。バイパスコンデンサ等の部品は検査中に発生するノイズの除去能力の向上を図る上で、プローブピンの近傍に配置することが望ましいが、従来では、このような部品が、プローブピンから離れたマザー基板上に配置されることが多かった。そこで、バイパスコンデンサ等の部品を前記コア基板に積層された第1樹脂部に内蔵することにより、従来よりもプローブピンに近い位置に部品を配置することができる。また、従来マザー基板へ実装していた部品を積層配線基板に内蔵させることで、マザー基板の実装領域を節約することができる。 Further, a component may be built in the first resin portion. It is desirable to place components such as bypass capacitors near the probe pins in order to improve the ability to remove noise generated during inspection. Conventionally, such components are separated from the probe pins. Often placed on top. Therefore, by incorporating a component such as a bypass capacitor in the first resin portion laminated on the core substrate, the component can be arranged at a position closer to the probe pin than in the prior art. Further, by incorporating the components that have been mounted on the mother board into the multilayer wiring board, the mounting area of the mother board can be saved.
 また、前記コア基板の内部に形成されるビア導体を備え、前記金属ピンの軸心と垂直な方向の断面積が、前記ビア導体の軸心と垂直な方向の断面積よりも大きくてもよい。この場合、第1樹脂部に配設された金属ピンは、セラミック積層部に配設されたビア導体よりも太い柱状の導体であり、金属ピンの電気抵抗率はビア導体の電気抵抗率よりも小さい。したがって、第1樹脂部の配線を金属ピンで形成することで、積層配線基板全体の電気抵抗が下がり、マザー基板とプローブピンとを低抵抗で接続することができる。また、金属ピン周囲に樹脂を備えた構造により、プローブとして使用時に多層配線基板がICに接触する際に接触によってかかる応力を緩和する事が出来る。 In addition, a via conductor formed inside the core substrate may be provided, and a cross-sectional area in a direction perpendicular to the axis of the metal pin may be larger than a cross-sectional area in a direction perpendicular to the axis of the via conductor. . In this case, the metal pin disposed in the first resin portion is a columnar conductor that is thicker than the via conductor disposed in the ceramic laminated portion, and the electrical resistivity of the metal pin is greater than the electrical resistivity of the via conductor. small. Therefore, by forming the wiring of the first resin portion with metal pins, the electrical resistance of the entire laminated wiring board is lowered, and the mother board and the probe pins can be connected with low resistance. In addition, the structure provided with resin around the metal pin can relieve stress applied by the contact when the multilayer wiring board contacts the IC when used as a probe.
 また、前記第1樹脂部における前記コア基板側の面と対向する面に形成され、前記金属ピンの前記一方の端面に接続されるパッド電極を備えていてもよい。この場合、積層配線基板とマザー基板は半田により接続されるが、金属ピンの端面にパッド電極を設けることで、金属ピンの端面に直接めっきを施すよりもパッド電極にめっきが付着し易いため、半田付け性が向上し、積層配線基板とマザー基板の接続信頼性が向上する。また、パッド電極を大きくすることで、積層配線基板をマザー基板と接続する際の位置合わせを容易に行うことができる。 Further, a pad electrode formed on a surface of the first resin portion facing the core substrate side and connected to the one end surface of the metal pin may be provided. In this case, the laminated wiring board and the mother board are connected by soldering, but by providing a pad electrode on the end face of the metal pin, it is easier to attach the plating to the pad electrode than plating the end face of the metal pin directly. The solderability is improved, and the connection reliability between the multilayer wiring board and the mother board is improved. Further, by increasing the pad electrode, it is possible to easily perform alignment when connecting the laminated wiring board to the mother board.
 また、上記の積層配線基板を、被検査物の電気検査を行うプローブカードに使用するのが好ましい。こうすると、耐久性が高く、かつ、マザー基板との接続信頼性の高いプローブカードを提供することができる。 Moreover, it is preferable to use the above laminated wiring board for a probe card for performing an electrical inspection of an object to be inspected. In this way, it is possible to provide a probe card having high durability and high connection reliability with the mother board.
 本発明によれば、プローブカード用積層配線基板の全体の厚さを維持しつつ、セラミック積層部は薄く形成することができるため、セラミック積層部が厚いことによって発生する積層ずれを低減することができるとともに、積層配線基板のカット時や焼成時の問題を解決することができる。さらに、樹脂部に金属ピンを配置することにより、積層配線基板の放熱性が向上し、プローブカード使用時の基板の温度上昇を防ぐことができる。 According to the present invention, the ceramic laminated portion can be formed thin while maintaining the entire thickness of the probe card laminated wiring board, so that the stacking deviation caused by the thick ceramic laminated portion can be reduced. In addition, the problems at the time of cutting and firing the laminated wiring board can be solved. Furthermore, by disposing the metal pins in the resin portion, the heat dissipation of the multilayer wiring board is improved, and the temperature rise of the board when using the probe card can be prevented.
本発明の第1実施形態にかかるプローブカードの断面図である。It is sectional drawing of the probe card concerning 1st Embodiment of this invention. 図1のプローブカード用積層配線基板の断面図である。It is sectional drawing of the laminated wiring board for probe cards of FIG. 本発明の第2実施形態にかかる積層配線基板の断面図である。It is sectional drawing of the laminated wiring board concerning 2nd Embodiment of this invention. 本発明の第3実施形態にかかる積層配線基板の断面図である。It is sectional drawing of the laminated wiring board concerning 3rd Embodiment of this invention. 従来の積層配線基板の断面図である。It is sectional drawing of the conventional multilayer wiring board.
 <第1実施形態>
 本発明の一実施形態にかかるプローブカード1について、図1、図2を参照して説明する。なお、図1はプローブカード1の断面図、図2は図1のプローブカード1に搭載される積層配線基板3aの断面図である。
<First Embodiment>
A probe card 1 according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. 1 is a cross-sectional view of the probe card 1, and FIG. 2 is a cross-sectional view of a laminated wiring board 3a mounted on the probe card 1 of FIG.
 この実施形態にかかるプローブカード1は、図1に示すように、マザー基板2と、該マザー基板2の一方主面に実装された積層配線基板3aと、一端が積層配線基板3aに接続される複数のプローブピン5と、各プローブピン5を支持するプローブヘッド4と、プローブヘッド4を固定するカバー体32とを備え、例えば、半導体素子などの被検査物50の電気検査に使用される。 As shown in FIG. 1, the probe card 1 according to this embodiment includes a mother board 2, a laminated wiring board 3a mounted on one main surface of the mother board 2, and one end connected to the laminated wiring board 3a. A plurality of probe pins 5, a probe head 4 that supports each probe pin 5, and a cover body 32 that fixes the probe head 4 are provided, and are used for, for example, an electrical inspection of an object to be inspected 50 such as a semiconductor element.
 マザー基板2は、一方主面に積層配線基板3aを実装するための複数の実装電極6が形成されるとともに、他方主面に外部接続用の複数の外部電極7が形成される。ここで、各実装電極6は、マザー基板の内部に形成された配線電極30や複数のビア導体31により所定の外部電極7に接続される。マザー基板2は、例えば、ガラスエポキシ樹脂などで形成されている。なお、各プローブピン5を保持するプローブヘッド4は、マザー基板2に固定されたカバー体32に固定される。 The mother substrate 2 has a plurality of mounting electrodes 6 for mounting the multilayer wiring board 3a on one main surface, and a plurality of external electrodes 7 for external connection formed on the other main surface. Here, each mounting electrode 6 is connected to a predetermined external electrode 7 by a wiring electrode 30 and a plurality of via conductors 31 formed inside the mother substrate. The mother substrate 2 is made of, for example, glass epoxy resin. The probe head 4 that holds each probe pin 5 is fixed to a cover body 32 that is fixed to the mother board 2.
 積層配線基板3aは、コア基板8と、コア基板8に積層された第1樹脂部9と、第1樹脂部9の内部に配設された複数の金属ピン12とを備える。コア基板8は、第1樹脂部9側に配置されたセラミック積層部10と、セラミック積層部10におけるマザー基板2側の主面14と反対側の主面19に積層された第2樹脂部18とを有する。このとき、セラミック積層部10は、セラミック層10aと配線層10bが交互に積層されて形成される。なお、各セラミック層10aは、例えば、ホウケイ酸系ガラスを含有するセラミック(たとえば、アルミナ)を主成分とする低温同時焼成セラミック(LTCC)、高温焼成セラミック(HTCC)など、種々のセラミックで形成することができる。また、この実施形態では、セラミック積層部10が、4つのセラミック層10aと3つの配線層10bとで形成されているが、これらの層数は適宜変更することができる。 The laminated wiring board 3 a includes a core substrate 8, a first resin portion 9 laminated on the core substrate 8, and a plurality of metal pins 12 disposed inside the first resin portion 9. The core substrate 8 includes a ceramic laminated portion 10 disposed on the first resin portion 9 side and a second resin portion 18 laminated on a main surface 19 opposite to the main surface 14 on the mother substrate 2 side in the ceramic laminated portion 10. And have. At this time, the ceramic laminated portion 10 is formed by alternately laminating ceramic layers 10a and wiring layers 10b. Each ceramic layer 10a is formed of various ceramics such as a low-temperature co-fired ceramic (LTCC) or a high-temperature fired ceramic (HTCC) mainly composed of a ceramic (for example, alumina) containing borosilicate glass. be able to. In this embodiment, the ceramic laminated portion 10 is formed of four ceramic layers 10a and three wiring layers 10b. However, the number of these layers can be changed as appropriate.
 セラミック積層部10の各配線層10bには、各種配線電極15が形成されている。また、各セラミック層10aには、異なる配線層10bに形成された配線電極15同士を接続する複数のビア導体16が形成される。各配線電極15および各ビア導体16はそれぞれ、Cu、Ag、Al等の金属で形成される。各配線層10bに形成される各種配線電極15は、例えば、上記金属(Cu、Ag、Al等)を含有する導電性ペーストを用いたスクリーン印刷などで形成される。 Various wiring electrodes 15 are formed on each wiring layer 10 b of the ceramic laminated portion 10. Each ceramic layer 10a is formed with a plurality of via conductors 16 that connect the wiring electrodes 15 formed in different wiring layers 10b. Each wiring electrode 15 and each via conductor 16 are each formed of a metal such as Cu, Ag, or Al. The various wiring electrodes 15 formed in each wiring layer 10b are formed by screen printing using a conductive paste containing the metal (Cu, Ag, Al, etc.), for example.
 第2樹脂部18は、複数の樹脂層18aからなる積層体であり、セラミック積層部10のマザー基板2側と反対側の主面19に積層される。ここで、セラミック積層部10の主面19と反対側に位置する、第2樹脂部18の主面11には、各プローブピン5が接続される複数の接続電極21が形成される。なお、各接続電極21は、例えば、Cu等で形成された下地電極と、該下地電極上にNi/Auめっきが施されてなる表面電極とでそれぞれ形成することができる。 The second resin portion 18 is a laminated body composed of a plurality of resin layers 18a, and is laminated on the main surface 19 on the opposite side of the ceramic laminated portion 10 from the mother substrate 2 side. Here, a plurality of connection electrodes 21 to which the probe pins 5 are connected are formed on the main surface 11 of the second resin portion 18 located on the opposite side of the main surface 19 of the ceramic laminated portion 10. Each connection electrode 21 can be formed by, for example, a base electrode formed of Cu or the like and a surface electrode obtained by performing Ni / Au plating on the base electrode.
 各樹脂層18aには、各種配線電極20および複数のビア導体22が形成される。この場合、各配線電極20は、例えば、樹脂層18aの主面に、下地電極としてのTi膜をスパッタ等により成膜し、同じくスパッタ等によりTi膜上にCu膜を成膜する。そして、Cu膜上に、電解または無電解めっきにより、同じくCu膜を成膜することで形成することができる。なお、セラミック積層部10に形成された各配線電極15は、スクリーン印刷などで形成されるため厚膜パターンとなるのに対して、第2樹脂部18に形成された各配線電極20は、スパッタ等で成膜されるため薄膜パターンとなる。また、第2樹脂部18に形成された各配線電極20は、フォトリソグラフィ加工で細線化される。 In each resin layer 18a, various wiring electrodes 20 and a plurality of via conductors 22 are formed. In this case, for example, each wiring electrode 20 forms a Ti film as a base electrode on the main surface of the resin layer 18a by sputtering or the like, and similarly forms a Cu film on the Ti film by sputtering or the like. And it can form by forming a Cu film | membrane similarly on a Cu film | membrane by electrolysis or electroless plating. Each wiring electrode 15 formed in the ceramic laminated portion 10 is formed by screen printing or the like and thus has a thick film pattern, whereas each wiring electrode 20 formed in the second resin portion 18 is sputtered. Since the film is formed by a method such as that, a thin film pattern is formed. In addition, each wiring electrode 20 formed in the second resin portion 18 is thinned by photolithography.
 各接続電極21は、マザー基板2の他方主面に形成された複数の外部電極7にそれぞれ電気的に接続される。具体的には、図1および図2に示すように、各接続電極21は、それぞれ、第2樹脂部18に形成された各配線電極20および各ビア導体22、セラミック積層部10に形成された各配線電極15および各ビア導体16、マザー基板2に形成された配線電極30および各ビア導体31等を介して所定の各外部電極7に接続される。 Each connection electrode 21 is electrically connected to a plurality of external electrodes 7 formed on the other main surface of the mother substrate 2. Specifically, as shown in FIGS. 1 and 2, each connection electrode 21 is formed on each wiring electrode 20 and each via conductor 22 formed on the second resin portion 18, and on the ceramic laminated portion 10, respectively. Each wiring electrode 15 and each via conductor 16 are connected to each predetermined external electrode 7 via the wiring electrode 30 and each via conductor 31 formed on the mother substrate 2.
 第1樹脂部9は、コア基板8のマザー基板2側の主面14に積層され、主面14と対向する反対面13を有する。第1樹脂部9は、各金属ピン12をコア基板8の厚み方向に立設し、これらを固定した後、各金属ピン12を覆うように樹脂を積層し、硬化した後、厚さの調整と金属ピン12の頭出しのために、第1樹脂部9のうち主面14との反対面13を研磨して成形する。第1樹脂部9には、例えばエポキシ樹脂などの樹脂を使用することができる。また、第1樹脂部9の成形には、塗布方式、印刷方式、トランスファモールド方式、コンプレッションモールド方式などの技術を用いることができる。第1樹脂部9の反対面13とマザー基板2とは、半田により接続される。 The first resin portion 9 is laminated on the main surface 14 of the core substrate 8 on the mother substrate 2 side, and has an opposite surface 13 that faces the main surface 14. The first resin portion 9 is provided with the metal pins 12 standing in the thickness direction of the core substrate 8, fixing them, laminating the resin so as to cover the metal pins 12, curing, and then adjusting the thickness. In order to cue the metal pin 12, the surface 13 of the first resin portion 9 opposite to the main surface 14 is polished and molded. For the first resin portion 9, for example, a resin such as an epoxy resin can be used. In addition, techniques such as a coating method, a printing method, a transfer mold method, and a compression mold method can be used for forming the first resin portion 9. The opposite surface 13 of the first resin portion 9 and the mother substrate 2 are connected by solder.
 複数の金属ピン12は、コア基板8のマザー基板2側の主面14に設けられた複数の電極17に接合するように第1樹脂部9に配設され、コア基板8の配線層10bにより各プローブピン5と電気的に接続される。各金属ピン12は、例えば、Cu、Ag、Al等の金属で形成された線材をせん断加工するなどして形成することができる。また、第1樹脂部9の反対面13における各金属ピン12の露出部分である端面12aにはめっき処理が施されていてもよい。 The plurality of metal pins 12 are disposed in the first resin portion 9 so as to be joined to the plurality of electrodes 17 provided on the main surface 14 of the core substrate 8 on the mother substrate 2 side, and are formed by the wiring layer 10 b of the core substrate 8. Each probe pin 5 is electrically connected. Each metal pin 12 can be formed by, for example, shearing a wire formed of a metal such as Cu, Ag, or Al. Further, the end surface 12 a that is the exposed portion of each metal pin 12 on the opposite surface 13 of the first resin portion 9 may be plated.
 また、この実施形態では各金属ピン12の軸心(長さ方向)と垂直な方向の断面積が、各ビア導体16の軸心と垂直な方向の断面積よりも大きく形成される。各電極17は、各金属ピン12の前記断面積の大きさに合わせてコア基板8の主面14に形成され、各金属ピン12は各電極17に接合するように配設される。各電極17は、Cu、Ag、Al等の金属で形成される。なお、各金属ピン12の断面積の大きさは、ビア導体16の断面積と同じにする等、適宜変更が可能である。 In this embodiment, the cross-sectional area in the direction perpendicular to the axis (length direction) of each metal pin 12 is formed larger than the cross-sectional area in the direction perpendicular to the axis of each via conductor 16. Each electrode 17 is formed on the main surface 14 of the core substrate 8 in accordance with the size of the cross-sectional area of each metal pin 12, and each metal pin 12 is disposed so as to be joined to each electrode 17. Each electrode 17 is formed of a metal such as Cu, Ag, or Al. Note that the size of the cross-sectional area of each metal pin 12 can be changed as appropriate, such as the same as the cross-sectional area of the via conductor 16.
 したがって、上記した実施形態によれば、積層配線基板3aに第1樹脂部9を設けることによって、積層配線基板3aを所定の厚さで形成しつつ、セラミック積層部10の厚さを抑えることができる。なお、図1、図2には、セラミック積層部10よりも第1樹脂部9のほうが薄い構成が示されているが、セラミック積層部10よりも第1樹脂部9のほうが厚く形成されていてもよい。または、セラミック積層部10と第2樹脂部18の合計厚みよりも、第1樹脂部9の厚みを大きくしてもよい。本実施形態によると、セラミック積層部10の厚さを抑えることができるため、セラミック積層部10の厚さが増加することに起因する積層ずれの発生を低減することができるとともに、積層配線基板3aの焼成やカットが容易となるため、製造コストを下げることができる。また、積層配線基板3aのマザー基板2との接続をマザー基板2との熱膨張係数の差が小さい第1樹脂部9側で行うことができるため、積層配線基板3aとマザー基板2との接続信頼性の向上を図ることができる。さらに、第1樹脂部9を研磨することで積層配線基板3aの厚さの調整を行うことができるため、セラミック積層部10を研磨して厚さの調整を行う従来の方法よりも研磨加工が容易になる。 Therefore, according to the above-described embodiment, by providing the first resin portion 9 on the multilayer wiring substrate 3a, it is possible to suppress the thickness of the ceramic multilayer portion 10 while forming the multilayer wiring substrate 3a with a predetermined thickness. it can. 1 and 2 show a configuration in which the first resin portion 9 is thinner than the ceramic laminated portion 10, the first resin portion 9 is formed thicker than the ceramic laminated portion 10. Also good. Alternatively, the thickness of the first resin portion 9 may be larger than the total thickness of the ceramic laminated portion 10 and the second resin portion 18. According to the present embodiment, since the thickness of the ceramic multilayer portion 10 can be suppressed, the occurrence of misalignment due to the increase in the thickness of the ceramic multilayer portion 10 can be reduced, and the multilayer wiring board 3a. Since it becomes easy to sinter and cut, manufacturing cost can be reduced. Further, since the connection of the multilayer wiring substrate 3a to the mother substrate 2 can be performed on the first resin portion 9 side where the difference in thermal expansion coefficient from the mother substrate 2 is small, the connection between the multilayer wiring substrate 3a and the mother substrate 2 is possible. Reliability can be improved. Furthermore, since the thickness of the laminated wiring board 3a can be adjusted by polishing the first resin part 9, the polishing process is more than the conventional method of adjusting the thickness by polishing the ceramic laminated part 10. It becomes easy.
 また、各金属ピン12は、コア基板8内部の各ビア導体16よりも熱伝導率が高いため、積層配線基板3aの放熱性の向上を図ることができ、プローブカード使用時の積層配線基板3aの温度上昇を防ぐことができる。さらに、各金属ピン12の電気抵抗率は各ビア導体16の電気抵抗率よりも小さいため、第1樹脂部9の配線をビア導体で形成する場合と比較して、積層配線基板3a全体の電気抵抗が下がり、マザー基板2と各プローブピン5とを低抵抗で接続することができる。また、各金属ピン12の断面積を各ビア導体16の断面積よりも大きく形成することで、積層配線基板3aの電気抵抗をさらに下げることができる。 Moreover, since each metal pin 12 has higher thermal conductivity than each via conductor 16 in the core substrate 8, it is possible to improve heat dissipation of the multilayer wiring board 3a, and the multilayer wiring board 3a when the probe card is used. Temperature rise can be prevented. Furthermore, since the electrical resistivity of each metal pin 12 is smaller than the electrical resistivity of each via conductor 16, compared to the case where the wiring of the first resin portion 9 is formed of a via conductor, the electrical resistance of the entire multilayer wiring board 3 a is increased. The resistance decreases, and the mother board 2 and each probe pin 5 can be connected with low resistance. Further, by forming the cross-sectional area of each metal pin 12 to be larger than the cross-sectional area of each via conductor 16, the electrical resistance of the multilayer wiring board 3a can be further reduced.
 さらに、コア基板8に第2樹脂部18を設けることで、配線の細線化が容易になるため、端子ピッチが狭い半導体素子の電気検査に対応可能な積層配線基板3aを提供することができる。また、セラミック積層部10の両主面14、19に第1樹脂部9および第2樹脂部18を積層することで、両樹脂部9、18を緩衝材として機能させ、プローブカード使用時の物理的接触による応力や衝撃を緩和させることができる。したがって、セラミック積層部10の変形や破損を低減し、積層配線基板3aの耐久性を向上させることができるとともに、各配線電極15の断線の発生を低減することができる。 Furthermore, providing the second resin portion 18 on the core substrate 8 facilitates thinning of the wiring, so that it is possible to provide the multilayer wiring substrate 3a that can be used for electrical inspection of semiconductor elements having a narrow terminal pitch. Further, by laminating the first resin portion 9 and the second resin portion 18 on both the main surfaces 14 and 19 of the ceramic laminated portion 10, both the resin portions 9 and 18 function as a cushioning material, and the physical properties when the probe card is used. Stress and impact due to mechanical contact can be reduced. Therefore, deformation and breakage of the ceramic laminated portion 10 can be reduced, durability of the laminated wiring board 3a can be improved, and occurrence of disconnection of each wiring electrode 15 can be reduced.
 <第2実施形態>
 本発明の第2実施形態にかかる積層配線基板3bについて、図3を参照して説明する。なお、図3は積層配線基板3bの断面図である。
Second Embodiment
A laminated wiring board 3b according to a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view of the multilayer wiring board 3b.
 この実施形態にかかる積層配線基板3bが、図1、図2を参照して説明した第1実施形態と異なるところは、図3に示すように、第1樹脂部9に部品23が内蔵されていることである。その他の構成は第1実施形態の積層配線基板3aと同じであるため同一符号を付すことにより説明を省略する。 The laminated wiring board 3b according to this embodiment differs from the first embodiment described with reference to FIGS. 1 and 2 in that a component 23 is built in the first resin portion 9 as shown in FIG. It is that you are. Since other configurations are the same as those of the multilayer wiring board 3a of the first embodiment, description thereof is omitted by attaching the same reference numerals.
 この場合、コア基板8の一方の主面14に部品23が実装され、部品23は第1樹脂部9に内蔵された構成となっている。部品23は、例えば、チップコンデンサ、チップインダクタ、チップ抵抗、ヒューズチップ等で構成される。なお、この実施形態では、部品23が、電源ラインとグランドとを接続するバイパスコンデンサ(チップコンデンサ)で構成されている。 In this case, a component 23 is mounted on one main surface 14 of the core substrate 8, and the component 23 is built in the first resin portion 9. The component 23 includes, for example, a chip capacitor, a chip inductor, a chip resistor, a fuse chip, and the like. In this embodiment, the component 23 is configured by a bypass capacitor (chip capacitor) that connects the power supply line and the ground.
 このように、部品23を第1樹脂部9に内蔵すると、従来のようにマザー基板2に実装するよりも、各プローブピン5に近い位置に部品23を配置できるため、検査中に発生するノイズの除去能力の向上を図ることができる。また、従来はマザー基板2へ実装していた部品を積層配線基板3bに内蔵させることで、マザー基板2の実装領域を小さくすることができるため、プローブカード1の小型化を図ることができる。 As described above, when the component 23 is built in the first resin portion 9, the component 23 can be arranged at a position closer to each probe pin 5 than the conventional mounting on the mother board 2. The removal ability can be improved. In addition, since the mounting area of the mother board 2 can be reduced by incorporating components previously mounted on the mother board 2 in the multilayer wiring board 3b, the probe card 1 can be reduced in size.
 <第3実施形態>
 本発明の第3実施形態にかかる積層配線基板3cについて、図4を参照して説明する。なお、図4は積層配線基板3cの断面図である。
<Third Embodiment>
A laminated wiring board 3c according to a third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional view of the multilayer wiring board 3c.
 この実施形態にかかる積層配線基板3cが、図1、図2を参照して説明した第1実施形態と異なるところは、図4に示すように、各金属ピン12の端面12aにパッド電極24を設けたことである。その他の構成は第1実施形態の積層配線基板3aと同じであるため同一符号を付すことにより説明を省略する。 The laminated wiring board 3c according to this embodiment differs from the first embodiment described with reference to FIGS. 1 and 2 in that pad electrodes 24 are provided on the end surfaces 12a of the respective metal pins 12, as shown in FIG. It is provided. Since other configurations are the same as those of the multilayer wiring board 3a of the first embodiment, description thereof is omitted by attaching the same reference numerals.
 この場合、第1樹脂部9の反対面13の各金属ピン12の端面12aを覆うように、複数のパッド電極24が配置される。各パッド電極24は、接続される各金属ピン12の端面12aよりも大きく形成される。なお、各パッド電極24は、めっきにより形成してもよいし、導電性ペーストにめっき処理を施したものでもよい。また、第1樹脂部9の反対面13に他の電極が設けられていてもよい。 In this case, a plurality of pad electrodes 24 are arranged so as to cover the end surfaces 12a of the respective metal pins 12 on the opposite surface 13 of the first resin portion 9. Each pad electrode 24 is formed larger than the end surface 12a of each metal pin 12 to be connected. Each pad electrode 24 may be formed by plating, or may be a conductive paste that has been plated. Further, another electrode may be provided on the opposite surface 13 of the first resin portion 9.
 上記した実施形態によれば、各金属ピン12の端面12aを各パッド電極24で覆うことにより、各金属ピン12の端面12aに直接めっきを施す場合と比較して、各パッド電極24にめっきが付着し易いため、半田付け性の向上を図ることができる。また、各パッド電極24を各金属ピン12の端面12aよりも大きく形成することで、積層配線基板3cとマザー基板2の接続信頼性が向上するとともに、積層配線基板3cをマザー基板2と接続する際の位置合わせを容易に行うことができる。 According to the above-described embodiment, by covering the end surface 12a of each metal pin 12 with each pad electrode 24, compared with the case where the end surface 12a of each metal pin 12 is directly plated, each pad electrode 24 is plated. Since it adheres easily, the solderability can be improved. Further, by forming each pad electrode 24 larger than the end face 12a of each metal pin 12, the connection reliability between the multilayer wiring board 3c and the mother board 2 is improved, and the multilayer wiring board 3c is connected to the mother board 2. Position alignment can be easily performed.
 なお、本発明は上記した各実施形態に限定されるものではなく、その趣旨を逸脱しない限りにおいて、上記したもの以外に種々の変更を行なうことが可能である。例えば、上記した実施形態では、コア基板8はセラミック積層部10と第2樹脂部18とを有しているが、第2樹脂部18の部分もセラミックで形成していてもよい。 The present invention is not limited to the above-described embodiments, and various modifications other than those described above can be made without departing from the spirit of the invention. For example, in the above-described embodiment, the core substrate 8 includes the ceramic laminated portion 10 and the second resin portion 18, but the portion of the second resin portion 18 may also be formed of ceramic.
 本発明は、被検査物の電気検査に使用される種々のプローブカードに広く適用することができる。 The present invention can be widely applied to various probe cards used for electrical inspection of an object to be inspected.
 1  プローブカード
 3a~3c  積層配線基板
 5  プローブピン
 8  コア基板
 9  第1樹脂部
 10  セラミック積層部
 10a  セラミック層
 12  金属ピン
 18  第2樹脂部
 18a  樹脂層
 23  部品
 24  パッド電極
DESCRIPTION OF SYMBOLS 1 Probe card 3a-3c Multilayer wiring board 5 Probe pin 8 Core board 9 1st resin part 10 Ceramic laminated part 10a Ceramic layer 12 Metal pin 18 2nd resin part 18a Resin layer 23 Parts 24 Pad electrode

Claims (6)

  1.  複数のプローブピンが接続されるプローブカード用積層配線基板において、
     複数のセラミック層が積層されてなるセラミック積層部を有し、一方主面に前記複数のプローブピンが接続されるコア基板と、
     前記コア基板の他方主面に積層された第1樹脂部と、
     前記第1樹脂部に配設され、一方の端面が前記第1樹脂部における前記コア基板側の面と対向する面に設けられ、前記複数のプローブピンと電気的に接続される金属ピンと
     を備えることを特徴とするプローブカード用積層配線基板。
    In the multilayer wiring board for probe cards to which a plurality of probe pins are connected,
    A core substrate having a ceramic laminated portion formed by laminating a plurality of ceramic layers, and having a plurality of probe pins connected to one main surface;
    A first resin portion laminated on the other main surface of the core substrate;
    A metal pin disposed on the first resin portion, with one end surface provided on a surface facing the core substrate side surface of the first resin portion, and electrically connected to the plurality of probe pins. A laminated wiring board for a probe card characterized by
  2.  前記コア基板は、前記セラミック積層部における前記第1樹脂部側の面と対向する面に積層された第2樹脂部をさらに備え、
     前記第2樹脂部において、前記第1樹脂部側の面と対向する面が、前記コア基板の前記一方主面をなすことを特徴とする請求項1に記載のプローブカード用積層配線基板。
    The core substrate further includes a second resin portion laminated on a surface facing the surface on the first resin portion side in the ceramic laminate portion,
    2. The multilayer wiring board for probe cards according to claim 1, wherein a surface of the second resin portion that faces the surface on the first resin portion side forms the one main surface of the core substrate.
  3.  前記第1樹脂部に部品が内蔵されていることを特徴とする請求項1または2に記載のプローブカード用積層配線基板。 3. The probe card laminated wiring board according to claim 1, wherein a component is built in the first resin portion.
  4.  前記コア基板の内部に形成されるビア導体を備え、
     前記金属ピンの軸心と垂直な方向の断面積が、前記ビア導体の軸心に垂直な方向の断面積よりも大きいことを特徴とする請求項1ないし3のいずれかに記載のプローブカード用積層配線基板。
    Comprising via conductors formed inside the core substrate;
    4. The probe card according to claim 1, wherein a cross-sectional area in a direction perpendicular to the axis of the metal pin is larger than a cross-sectional area in a direction perpendicular to the axis of the via conductor. Multilayer wiring board.
  5.  前記第1樹脂部における前記コア基板側の面と対向する面に形成され、前記金属ピンの前記一方の端面に接続されるパッド電極を備えることを特徴とする請求項1ないし4のいずれかに記載のプローブカード用積層配線基板。 The pad electrode which is formed in the surface facing the said core substrate side surface in the said 1st resin part, and is connected to said one end surface of the said metal pin is provided. The laminated wiring board for probe cards as described.
  6.  請求項1ないし5のいずれかに記載のプローブカード用積層配線基板を備え、被検査物の電気検査を行うことを特徴とするプローブカード。 A probe card comprising the probe card multilayer wiring board according to claim 1 and performing an electrical inspection of an object to be inspected.
PCT/JP2016/078770 2015-09-30 2016-09-29 Probe card-use laminate wiring substrate and probe card equipped with same WO2017057542A1 (en)

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