CN115954419A - Manufacturing method of LED silver mirror chip - Google Patents

Manufacturing method of LED silver mirror chip Download PDF

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Publication number
CN115954419A
CN115954419A CN202211711628.3A CN202211711628A CN115954419A CN 115954419 A CN115954419 A CN 115954419A CN 202211711628 A CN202211711628 A CN 202211711628A CN 115954419 A CN115954419 A CN 115954419A
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etching
layer
manufacturing
photoetching
silver mirror
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李慧敏
齐佳鹏
钟伟华
张帆
林武
李景浩
李家昌
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Fujian Prima Optoelectronics Co Ltd
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Abstract

The invention relates to the technical field of semiconductor electronics, in particular to a manufacturing method of an LED silver mirror chip. The manufacturing method comprises the steps of evaporating an ITO conductive layer on a GaN epitaxial wafer, depositing an etching mask, photoetching and etching the etching mask to obtain a Mesa step surface, covering the Mesa step surface with photoresist, and etching to obtain a cutting channel; and etching the residual silicon dioxide by using a BOE solution, then photoetching again, evaporating a silver mirror to obtain a current expansion layer and a reflecting layer, and finally preparing a silicon dioxide protective layer and a metal electrode pad layer in sequence. The manufacturing method realizes one-time photoetching by adjusting the preparation steps, can reserve the area of the GaN layer and the area of the ITO thereon to the maximum extent, and increases the luminous efficiency.

Description

Manufacturing method of LED silver mirror chip
Technical Field
The invention relates to the technical field of semiconductor electronics, in particular to a manufacturing method of an LED silver mirror chip.
Background
An LED (secondary light emitting diode) is a semiconductor component, is used mostly as an indicator lamp, a display screen, and illumination, and becomes a fourth generation illumination light source or a green light source.
Chinese patent publication No. CN113299810A discloses an inverted silver mirror LED chip and a method for manufacturing the same, wherein a photolithography and etching technique is adopted to manufacture patterns arranged in a regular array on the surface of P-type gallium nitride of an inverted epitaxial wafer, and after passing through the patterns, total reflection is reduced, and the light extraction rate is improved; the surface patterning treatment of the P-type gallium nitride is utilized, the Ag reflection area is increased, and the light emitting of the LED is improved. However, this method requires multiple photolithography, each with a lithographic offset window of about 4 μm to prevent leakage and other electrical problems. Therefore, the more the number of the used photoetching is, the higher the manufacturing difficulty is, the more the photoetching offset windows need to be reserved, and the great waste of the light-emitting area is caused.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a manufacturing method of an LED silver mirror chip, and the LED silver mirror chip prepared by the method has the advantages of less photoetching times and large light-emitting area.
In order to solve the technical problems, the invention adopts the technical scheme that: a manufacturing method of an LED silver mirror chip comprises the following steps:
s1: evaporating an ITO conductive layer on the GaN epitaxial wafer, and then depositing a layer of silicon dioxide as an etching mask;
s2: photoetching the etching mask to obtain a Mesa photoetching graph and a cutting path photoetching graph;
s3: etching silicon dioxide of the cutting path photoetching pattern and the Mesa photoetching pattern by using a BOE solution, etching the ITO conductive layer by using an ITO etching solution, and then etching to obtain a Mesa step surface;
s4: covering the Mesa step surface with photoresist, and etching to obtain a cutting path;
s5: etching the residual silicon dioxide by using a BOE solution;
s6: performing photoetching again and then evaporating a silver mirror to obtain a current expanding layer and a reflecting layer;
s7: depositing a layer of silicon dioxide and etching to obtain a silicon dioxide protective layer;
s8: and evaporating the P-type bonding pad and the N-type bonding pad to obtain a metal electrode bonding pad layer, and injecting the metal electrode bonding pad layer into the etching hole to be connected and conducted with the current extension layer.
The invention has the beneficial effects that: according to the manufacturing method of the LED silver mirror chip, after ITO and silicon dioxide are evaporated, a Mesa photoetching pattern and a cutting path photoetching pattern are subjected to one-time photoetching, etching is carried out layer by layer, and a current expansion layer and a reflecting layer are subjected to synchronous photoetching and evaporation. Therefore, the original five-path (or four-path) etching is reduced into two paths, the photoetching number is reduced, and the exposure offset can be reduced, so that the etched P-GaN and ITO are reduced, the area of the GaN layer and the area of the ITO thereon are reserved to the maximum extent, the luminous efficiency is increased, and the brightness is improved. And the photoetching times are reduced, multiple processing flows can be reduced, the processing time is shortened, and the cost is saved.
Drawings
Fig. 1 is a schematic diagram illustrating a product structure of S1 in a method for manufacturing an LED silver mirror chip according to a first embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a product structure of S3 in the method for manufacturing an LED silver mirror chip according to the first embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a product structure of S4 in the method for manufacturing an LED silver mirror chip according to the first embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a product structure of S5 in the method for manufacturing an LED silver mirror chip according to the first embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a product structure of S6 in the method for manufacturing an LED silver mirror chip according to the first embodiment of the present invention;
fig. 6 is a schematic diagram illustrating a product structure of S7 in the method for manufacturing an LED silver mirror chip according to the first embodiment of the present invention;
fig. 7 is a schematic diagram illustrating a product structure of S8 in the method for manufacturing an LED silver mirror chip according to the first embodiment of the present invention;
description of reference numerals: 1. a sapphire substrate; 2. an N-type semiconductor layer; 3. a multiple quantum well layer; 4. a P-type semiconductor layer; 5. an ITO conductive layer; 6. etching the mask; 7. a current spreading layer; 8. a reflective layer; 9. a silicon dioxide protective layer; 10. a metal electrode pad layer; 11. and cutting a channel.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
The most key concept of the invention is as follows: the preparation steps are adjusted to realize one-time photoetching, so that the area of the GaN layer and the area of the ITO thereon can be reserved to the maximum extent, and the luminous efficiency is increased.
Referring to fig. 1 to 7, a method for manufacturing an LED silver mirror chip of the present invention includes the following steps:
s1: evaporating an ITO (indium tin oxide) conducting layer on the GaN epitaxial wafer, and then depositing a layer of silicon dioxide as an etching mask;
s2: photoetching the etching mask to obtain a Mesa photoetching graph and a cutting path photoetching graph;
s3: etching silicon dioxide of the cutting path photoetching pattern and the Mesa photoetching pattern by using a BOE solution, etching the ITO conductive layer by using an ITO etching solution, and then etching to obtain a Mesa step surface;
s4: covering the Mesa step surface with photoresist, and etching to obtain a cutting path;
s5: etching the residual silicon dioxide by using a BOE solution;
s6: performing photoetching again and then evaporating a silver mirror to obtain a current expanding layer and a reflecting layer;
s7: depositing a layer of silicon dioxide and etching to obtain a silicon dioxide protective layer;
s8: and evaporating the P-type bonding pad and the N-type bonding pad to obtain a metal electrode bonding pad layer, and injecting the metal electrode bonding pad layer into the etching hole to be connected and conducted with the current extension layer.
From the above description, the beneficial effects of the present invention are: in the prior art, when an LED silver mirror chip is prepared, evaporation (or deposition), photoetching and etching are needed layer by layer, and photoetching is needed for many times because the number of layers is increased on an epitaxial wafer. After the ITO and the silicon dioxide are evaporated, the Mesa photoetching pattern and the cutting path photoetching pattern are subjected to one-time photoetching, layer-by-layer etching is performed, and then the current expansion layer and the reflecting layer are subjected to synchronous photoetching and evaporation, so that the original five (or four) etching is reduced into two etching. The photoetching quantity is reduced, exposure offset can be reduced, etched P-GaN and etched ITO are reduced, the area of the GaN layer and the area of the ITO on the GaN layer are reserved to the maximum extent, the luminous efficiency is increased, and the brightness is improved. And the photoetching times are reduced, multiple processing flows can be reduced, the processing time is shortened, and the cost is saved.
The silicon dioxide protective layer is used for preventing silver mirror from being oxidized and preventing impurities such as moisture from being oxidized and corroded.
The cutting lines comprise Masa cutting lines and ISO cutting lines, and the two cutting lines are subjected to synchronous photoetching and etching, so that the photoetching number is reduced, and the luminous efficiency is increased.
Further, the ITO conductive layer has a thickness of
Figure BDA0004026367480000041
Further, the etching mask has a thickness of
Figure BDA0004026367480000042
Preferably, the etch mask has a thickness of
Figure BDA0004026367480000043
As can be seen from the above description, the role of the etch mask is to provide a sufficient window for preventing over-etching during etching.
Further, the specific steps of S2 are: and coating positive photoresist on the etching mask, and then sequentially drying, exposing and developing to obtain a Mesa photoetching pattern and a cutting path photoetching pattern.
From the above description, the Mesa lithography pattern and the scribe line lithography pattern obtained by one-time lithography can reduce exposure offset and increase the light emitting area.
Further, the coating thickness of the positive photoresist is 2.3 to 2.5 μm, and the exposure dose is 75 to 85mj. Preferably, the coating thickness of the positive photoresist is 2.4 μm, and the exposure amount of the exposure is 80mj.
Furthermore, the width of the photoetching pattern of the cutting path is 3-5 μm. Preferably, the width of the scribe line lithography pattern is 4 μm.
From the above description, the smaller the scribe line pattern is, the higher the chip yield is; however, when the scribe line pattern is too small, the cutting tool is difficult to position accurately.
Furthermore, the side etching amount of the ITO etching solution in S3 is 5-7 μm.
As can be seen from the above description, the core-grain pitch of the ITO obtained in the prior art is 34 μm, but under the photolithography process of the present invention, the pitch can be reduced to 18-22 μm, i.e. the unilateral ITO is enlarged by 7 μm, which increases the light-emitting area of the chip.
Further, the etching depth of the Mesa surface of Mesa in S3 is
Figure BDA0004026367480000044
Further, during the etching of S4, chlorine gas is used for etching, the etching time is 900S, the gas flow is 155cfm, and the etching depth is 155cfm
Figure BDA0004026367480000045
From the above description, the etching time is 1800s in the original ISO etching, and the etching time is shortened to adapt to the synchronous etching of the ISO cutting track and the Mesa cutting track.
Further, the width of the scribe line is 14 to 18 μm.
From the above description, the smaller the dicing lane, the higher the yield of the chip; the minimum width of the cutting line is determined by the cutting tool.
Furthermore, the negative photoresist is used for coating during S6 photoetching, and the exposure amount is 145-155 mj. Preferably, the exposure amount is 150mj.
Further, the thickness of the current spreading layer and the reflective layer are both
Figure BDA0004026367480000051
Preferably, both the thickness of the current spreading layer and the thickness of the reflecting layer are->
Figure BDA0004026367480000052
Further, the thickness of the silicon dioxide protective layer is
Figure BDA0004026367480000053
Preferably, the thickness of the protective layer of silicon dioxide is +>
Figure BDA0004026367480000054
As is apparent from the above description, the silica protective layer functions to protect the core particles from Ag oxidation, impurity contamination, and the like.
Referring to fig. 1 to 7, a first embodiment of the present invention is: the invention discloses a manufacturing method of an LED silver mirror chip, which comprises the following steps:
s1: sequentially growing a gallium nitride-based N-type semiconductor layer 2, a multi-quantum well layer 3 and a P-type semiconductor layer 4 on a sapphire substrate 1 by adopting a metal organic chemical vapor deposition method to obtain a GaN epitaxial wafer;
s2: the thickness of vapor deposition on the GaN epitaxial wafer is as follows
Figure BDA0004026367480000055
A layer of silicon dioxide is deposited as an etching mask 6 on the ITO (tin oxide) conducting layer 5, and the thickness of the etching mask 6 is->
Figure BDA0004026367480000056
S3: coating 2.4 mu m positive photoresist on the etching mask 6, drying at 110 ℃ for 90s, exposing with the exposure amount of 80mj, and developing at 135 ℃ for 90s to obtain a Mesa photoetching pattern, an overlay pattern and a cutting path photoetching pattern, wherein the width of the cutting path photoetching pattern is 4 mu m;
s4: etching silicon dioxide of the cutting path photoetching pattern and the Mesa photoetching pattern by using a BOE solution, etching the ITO conducting layer 5 by using an ITO etching solution, and etching N-GaN to obtain a Mesa step surface and an alignment, wherein the etching depth of the Mesa step surface is
Figure BDA0004026367480000057
The lateral etching amount of the ITO etching solution is 6 mu m;
s5: carrying out secondary photoetching registration by using positive photoresist, covering the Mesa surface and the engraving sleeve by using the photoresist, and etching by adopting a reactive coupling plasma mode to obtain a cutting path 11, wherein the width of the cutting path 11 is 16 mu m; during etching, chlorine is used for etching, the etching time is 900s, the gas flow is 155cfm, and the etching depth is 155cfm
Figure BDA0004026367480000058
S6: etching the residual silicon dioxide by using a BOE solution after removing the photoresist;
s7: the silver mirror is evaporated after photoetching again to obtain the thickness of
Figure BDA0004026367480000059
A current spreading layer 7 and a reflective layer 8; coating a negative photoresist during photoetching, wherein the drying condition is 100 ℃ for 90s, the exposure is 150mj, and the developing condition is 116 ℃ for 90s;
s8: depositing a layer with a thickness of
Figure BDA0004026367480000061
Etching the silicon dioxide to obtain a silicon dioxide protective layer 9;
s9: and evaporating the P-type bonding pad and the N-type bonding pad to obtain the metal electrode bonding pad layer 10, and injecting the etching holes to be connected and conducted with the current extension layer.
The performance test of the LED silver mirror chip of the first embodiment is carried out, and the test result is as follows: the ITO space is 20 μm, and the whole area of ITO is 41340 μm 2 。
Therefore, in the conventional LED flip chip, the ITO pitch is generally 34 μm, and the total area of the ITO is about 34592 μm 2 Compared with the conventional LED flip chip, the LED flip chip obtained by the invention has the advantages that the whole area of the ITO is enlarged by 6748 mu m 2 (about 19.5%) and the brightness enhancement ratio is about 5.57%.
The second embodiment of the invention is as follows: the invention discloses a manufacturing method of an LED silver mirror chip, which comprises the following steps:
s1: sequentially growing a gallium nitride-based N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer on a sapphire substrate by adopting a metal organic chemical vapor deposition method to obtain a GaN epitaxial wafer;
s2: the thickness of vapor deposition on the GaN epitaxial wafer is as follows
Figure BDA0004026367480000062
The ITO (tin oxide) conducting layer is deposited with a layer of silicon dioxide as an etching mask, and the thickness of the etching mask is->
Figure BDA0004026367480000063
S3: coating a positive photoresist with the thickness of 2.3 mu m on an etching mask, drying the etching mask at the temperature of 110 ℃ for 90s, exposing the etching mask with the exposure of 75mj, and developing the etching mask at the temperature of 135 ℃ for 90s to obtain a Mesa photoetching pattern, an overlay pattern and a cutting path photoetching pattern, wherein the width of the cutting path photoetching pattern is 3 mu m;
s4: etching silicon dioxide of the cutting path photoetching pattern and the Mesa photoetching pattern by using a BOE solution, etching the ITO conducting layer by using an ITO etching solution, and etching N-GaN to obtain a Mesa step surface and an alignment, wherein the etching depth of the Mesa step surface is
Figure BDA0004026367480000064
The lateral etching amount of the ITO etching solution is 5 mu m, and the ITO etching solution corrodes the ITO conductive layer;
s5: using positive photoresistCarrying out second photoetching registration, covering the Mesa surface and the engraving sleeve with photoresist, and etching by adopting a reactive coupling plasma mode to obtain a cutting channel, wherein the width of the cutting channel is 14 micrometers; during etching, chlorine is used for etching, the etching time is 900s, the gas flow is 155cfm, and the etching depth is 155cfm
Figure BDA0004026367480000065
S6: etching the residual silicon dioxide by using a BOE solution after photoresist removal;
s7: the silver mirror is evaporated after photoetching again to obtain the thickness of
Figure BDA0004026367480000071
A current spreading layer and a reflective layer; coating a negative photoresist during photoetching, wherein the drying condition is 100 ℃ for 90s, the exposure is 145mj, and the developing condition is 116 ℃ for 90s;
s8: depositing a layer with a thickness of
Figure BDA0004026367480000072
Etching the silicon dioxide to obtain a silicon dioxide protective layer;
s9: and evaporating the P-type bonding pad and the N-type bonding pad to obtain a metal electrode bonding pad layer, and injecting the metal electrode bonding pad layer into the etching hole to be connected and conducted with the current extension layer.
The third embodiment of the invention is as follows: the invention discloses a manufacturing method of an LED silver mirror chip, which comprises the following steps:
s1: sequentially growing a gallium nitride-based N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer on a sapphire substrate by adopting a metal organic chemical vapor deposition method to obtain a GaN epitaxial wafer;
s2: the thickness of vapor deposition on the GaN epitaxial wafer is as follows
Figure BDA0004026367480000073
A layer of silicon dioxide is deposited as an etching mask, and the thickness of the etching mask is ^ based on>
Figure BDA0004026367480000074
S3: coating a positive photoresist with the thickness of 2.5 mu m on an etching mask, drying the etching mask at the temperature of 110 ℃ for 90s, exposing the etching mask with the exposure of 85mj, and developing the etching mask at the temperature of 135 ℃ for 90s to obtain a Mesa photoetching pattern, an overlay pattern and a cutting path photoetching pattern, wherein the width of the cutting path photoetching pattern is 5 mu m;
s4: etching silicon dioxide of the cutting path photoetching pattern and the Mesa photoetching pattern by using a BOE solution, etching the ITO conducting layer by using an ITO etching solution, and etching N-GaN to obtain a Mesa step surface and an alignment, wherein the etching depth of the Mesa step surface is
Figure BDA0004026367480000075
The lateral etching amount of the ITO etching solution is 7 mu m, and the ITO etching solution etches the ITO conductive layer;
s5: carrying out secondary photoetching registration by using positive photoresist, covering the Mesa surface and the engraving sleeve by using the photoresist, and etching by adopting a reactive coupling plasma mode to obtain a cutting path, wherein the width of the cutting path is 18 mu m; during etching, chlorine is used for etching, the etching time is 900s, the gas flow is 155cfm, and the etching depth is 155cfm
Figure BDA0004026367480000076
S6: etching the residual silicon dioxide by using a BOE solution after removing the photoresist;
s7: the silver mirror is evaporated after photoetching again to obtain the thickness of
Figure BDA0004026367480000077
A current spreading layer and a reflective layer; coating a negative photoresist during photoetching, wherein the drying condition is 100 ℃ for 90s, the exposure is 155mj, and the developing condition is 116 ℃ for 90s;
s8: depositing a layer having a thickness of
Figure BDA0004026367480000081
Etching the silicon dioxide to obtain a silicon dioxide protective layer;
s9: and evaporating the P-type bonding pad and the N-type bonding pad to obtain a metal electrode bonding pad layer, and injecting the metal electrode bonding pad layer into the etching hole to be connected and conducted with the current extension layer.
In summary, according to the manufacturing method of the LED silver mirror chip provided by the invention, after the ITO and the silicon dioxide are evaporated, the Mesa lithography pattern and the scribe line lithography pattern are etched at one time, and then the etching is performed layer by layer, and then the current spreading layer and the reflective layer are simultaneously etched and evaporated, so that the original five (or four) etching is reduced to two. The photoetching quantity is reduced, exposure offset can be reduced, etched P-GaN and etched ITO are reduced, the area of the GaN layer and the area of the ITO on the GaN layer are reserved to the maximum extent, the luminous efficiency is increased, and the brightness is improved. And the photoetching times are reduced, multiple processing flows can be reduced, the processing time is shortened, and the cost is saved. The silicon dioxide protective layer is used for preventing the silver mirror from being oxidized and preventing impurities such as moisture from being oxidized and corroded.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.

Claims (10)

1. The manufacturing method of the LED silver mirror chip is characterized by comprising the following steps:
s1: evaporating an ITO conductive layer on the GaN epitaxial wafer, and depositing a layer of silicon dioxide as an etching mask;
s2: photoetching the etching mask to obtain a Mesa photoetching pattern and a cutting path photoetching pattern;
s3: etching silicon dioxide of the cutting path photoetching pattern and the Mesa photoetching pattern by using a BOE solution, etching the ITO conductive layer by using an ITO etching solution, and then etching to obtain a Mesa step surface;
s4: covering the Mesa step surface with photoresist, and etching to obtain a cutting path;
s5: etching the residual silicon dioxide by using a BOE solution;
s6: performing photoetching again and then evaporating a silver mirror to obtain a current expanding layer and a reflecting layer;
s7: depositing a layer of silicon dioxide and etching to obtain a silicon dioxide protective layer;
s8: and evaporating the P-type bonding pad and the N-type bonding pad to obtain a metal electrode bonding pad layer, and injecting the metal electrode bonding pad layer into the etching hole to be connected and conducted with the current extension layer.
2. The method for manufacturing the LED silver mirror chip according to claim 1, wherein the ITO conductive layer has a thickness of
Figure FDA0004026367470000011
3. The method for manufacturing the LED silver mirror chip according to claim 1, wherein the etching mask has a thickness of
Figure FDA0004026367470000012
4. The method for manufacturing the LED silver mirror chip according to claim 1, wherein the specific steps of S2 are as follows: and coating a positive photoresist on the etching mask, and then sequentially drying, exposing and developing to obtain a Mesa photoetching pattern and a cutting path photoetching pattern.
5. The method for manufacturing an LED silver mirror chip according to claim 4, wherein the coating thickness of the positive photoresist is 2.3-2.5 μm, and the exposure amount is 75-85 mj.
6. The method for manufacturing the LED silver mirror chip according to claim 1, wherein the width of the cutting street lithography pattern is 3-5 μm.
7. The method for manufacturing an LED silver mirror chip according to claim 1, wherein the amount of lateral etching of the ITO etching solution in S3 is 5 to 7 μm.
8. The method for manufacturing the LED silver mirror chip according to claim 1, wherein the width of the cutting street is 14 to 18 μm.
9. The method for manufacturing the LED silver mirror chip according to claim 1, wherein a negative photoresist is used for coating during the S6 photoetching, and the exposure amount is 145-155 mj.
10. The method for manufacturing the LED silver mirror chip according to claim 1, wherein the current spreading layer and the reflecting layer are both thick
Figure FDA0004026367470000021
/>
CN202211711628.3A 2022-12-29 2022-12-29 Manufacturing method of LED silver mirror chip Pending CN115954419A (en)

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