JP2011071443A - Method of manufacturing light emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a light emitting device which can reduce man hour and improve yield. <P>SOLUTION: The method has: a step of exposing a surface of a semiconductor layer of a first conductivity type by removing a part of a nitride semiconductor lamination structure; a step of forming a p-contact electrode 30 in a surface of a semiconductor layer of a second conductivity type; a step of forming an insulating layer 50 on the exposed semiconductor layer of a first conductivity type and on the semiconductor layer of a second conductivity type wherein the p-contact electrode 30 is formed; a step of forming a pattern 200 having a first exposed part and a second exposed part on the insulating layer 50; a step of forming the insulating layer 50 having a first opening in a position corresponding to the first exposed part and a second opening in a position corresponding to the second exposed part by removing the insulating layer 50 which is exposed to an outside from the first exposed part and the second exposed part: and a step of forming an electrode in the first opening and the second opening while leaving the pattern 200. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a light emitting device. In particular, the present invention relates to a method for manufacturing a light emitting device including a step of performing etching using a resist pattern as a mask.

  Conventionally, a step of preparing a substrate having an n-side contact layer, an active layer, and a p-side contact layer, a step of forming a p-contact electrode on the p-side contact layer, and a pattern made of a photoresist on the p-contact electrode Forming a p buffer electrode and an n electrode using the pattern as a mask, removing the pattern, and forming an insulating layer on substantially the entire surface of the substrate having the p buffer electrode and the n electrode. There is provided a light emitting device provided by a manufacturing method including a step of forming a pattern made of a photoresist having an opening on a p buffer electrode and an n electrode on an insulating layer, and a step of removing the insulating layer through the opening. It is known (see, for example, Patent Document 1).

JP 2008-041866 A

  However, since the light emitting element described in Patent Document 1 is manufactured through a process of forming a pattern made of a photoresist a plurality of times, there is a limit in reducing the manufacturing cost and the manufacturing time, and the photoresist. There is a high probability that a defect will occur due to contamination after the removal, and there is a limit to improving the yield.

  Accordingly, an object of the present invention is to provide a method for manufacturing a light emitting element capable of reducing the number of steps and improving the yield.

  In order to achieve the above object, the present invention provides a nitride semiconductor multilayer structure including a first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type. A semiconductor removing step of exposing a surface of the first semiconductor layer by removing a part of the structure; a transparent conductive layer forming step of forming a transparent conductive layer on the surface of the second semiconductor layer; An insulating layer forming step for forming an insulating layer on one semiconductor layer and on the second semiconductor layer on which the transparent conductive layer is formed; and a first exposure for exposing the insulating layer on the first semiconductor layer Forming a pattern on the insulating layer, the pattern forming step having a second exposed portion that exposes the insulating layer on the transparent conductive layer, and through the first exposed portion and the second exposed portion. By removing the exposed portion of the insulating layer, An insulating layer removing step for forming the first opening and the second opening in the edge layer, and the first opening and the second semiconductor layer on the first semiconductor layer with the pattern remaining. An electrode forming step of forming an electrode in the second opening above is provided.

  In the method for manufacturing a light emitting element, it is preferable that the method further includes a pattern removing step of removing the pattern after the electrode forming step.

  In the method for manufacturing a light emitting device, the first exposed portion and the second exposed portion may be formed to expand toward the insulating layer in the thickness direction of the pattern.

  According to the method for manufacturing a light-emitting element according to the present invention, the number of man-hours can be reduced and the yield can be improved.

FIG. 1A is a plan view of a light emitting device according to a first embodiment of the present invention. FIG. 1B is a longitudinal sectional view of the light emitting device according to the first embodiment of the present invention. 1C (a) and 1C (b) are partial enlarged views of a longitudinal section of the light emitting device according to the first embodiment of the present invention. FIG. 2A is a schematic diagram of a manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 2B is a schematic diagram of a manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 2C is a schematic diagram of a manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 2D is an enlarged vertical cross-sectional view of the p-side exposed portion in the manufacturing process of the light-emitting element according to the first embodiment of the present invention. FIG. 2E is a diagram illustrating a flow of a process of forming the p-side exposed portion.

[First Embodiment]
FIG. 1A shows an outline of the upper surface of the light emitting device according to the first embodiment of the present invention, and FIG. 1B shows an outline of a longitudinal section of the light emitting device according to the first embodiment of the present invention. Specifically, FIG. 1B shows an outline of a longitudinal section of the light-emitting element taken along the line AA of FIG. Furthermore, FIG. 1C (a) and (b) shows the outline | summary which expanded a part of longitudinal section of the light emitting element which concerns on the 1st Embodiment of this invention.

(Configuration of Light-Emitting Element 1)
As shown in FIG. 1B, the light emitting element 1 according to the first embodiment of the present invention includes, as an example, a sapphire substrate 10 having a C plane (0001), a buffer layer 20 provided on the sapphire substrate 10, An n-side contact layer 22 provided on the buffer layer 20, an n-side cladding layer 24 provided on the n-side contact layer 22, a light emitting layer 25 provided on the n side cladding layer 24, and provided on the light emitting layer 25 A nitride semiconductor multilayer structure including a p-side cladding layer 26 and a p-side contact layer 28 provided on the p-side cladding layer 26.

  The light-emitting element 1 includes a p-contact electrode 30 as a transparent conductive layer provided on the p-side contact layer 28, a p-buffer electrode 40 provided in a partial region on the p-contact electrode 30, and a p-side contact layer. 28, at least the surface of the n-side contact layer 22 is removed, and the n-side contact layer 22 and p are removed except for the n-electrode 42 provided on the n-side contact layer 22 and the p-buffer electrode 40 and the n-electrode 42. And an insulating layer 50 provided on the contact electrode 30. In the present embodiment, the insulating layer 50 is provided so as not to substantially overlap the p buffer electrode 40 and the n electrode 42. That is, the p buffer electrode 40 is provided on the p contact electrode 30 via the p side opening 52 provided in the insulating layer 50, and the n electrode 42 includes the n side opening 54 provided in the insulating layer 50. And provided on the n-side contact layer 22.

  Referring to FIG. 1A, in plan view of the light emitting element 1, the n-electrode 42 is disposed near the center of one side, and the p-buffer electrode 40 is disposed near the center of the opposite side of the one side. The p-contact electrode 30 is formed in a substantially U shape in plan view. That is, the p-contact electrode 30 has a recess 30b in a portion where the n-electrode 42 is disposed, and has two protrusions 30a extending from both ends of the bottom of the recess 30b toward the one side in plan view. Formed. The n electrode 42 is disposed between the two protrusions 30a in plan view.

1C, the n-side opening 54 of the insulating layer 50 is formed so as to be narrowed toward the n-side contact layer 22 side in the thickness direction of the insulating layer 50 (hereinafter, referred to as “a”). Such a shape is called “tapered shape”). That is, the n-side opening 54 is formed to have a side surface that is inclined in a direction away from the n-electrode 42 in the upward direction with respect to the normal direction of the surface of the n-side contact layer 22. The n-electrode 42 is formed to cover the side surface of the n-side opening 54 so as to completely block the lower end of the n-side opening 54. Thereby, the n-side contact layer 22 is not exposed, and the n-side contact layer 22 can be protected accurately.
As shown in FIG. 1C (b), the p-side opening 52 of the insulating layer 50 is formed so as to be narrowed toward the p-contact electrode 30 side in the thickness direction of the insulating layer 50. That is, the p-side opening 52 is formed to have a side surface that is inclined in a direction away from the p-buffer electrode 40 in the upward direction with respect to the normal direction of the surface of the p-contact electrode 30. In the present embodiment, the p buffer electrode 40 is formed separately from the side surface of the p-side opening 52, but may be formed so as to cover the side surface of the p-side opening 52, similarly to the n electrode 42.

(Nitride semiconductor multilayer structure)
Here, the buffer layer 20, the n-side contact layer 22, the n-side cladding layer 24, the light emitting layer 25, the p-side cladding layer 26, and the p-side contact layer 28 are each made of a group III nitride compound semiconductor. It is a layer. The group III nitride compound semiconductor is, for example, a quaternary group III nitride of Al _x Ga _y In _1-xy N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). A physical compound semiconductor can be used.

  In the present embodiment, the buffer layer 20 is made of AlN. The n-side contact layer 22 and the n-side cladding layer 24 are each formed from n-GaN doped with a predetermined amount of n-type dopant (for example, Si). The light emitting layer 25 has a multiple quantum well structure formed of InGaN / GaN / AlGaN. Further, the p-side cladding layer 26 and the p-side contact layer 28 are each formed from p-GaN doped with a predetermined amount of p-type dopant (for example, Mg).

(P contact electrode 30, p buffer electrode 40, n electrode 42)
The p contact electrode 30 is made of a conductive oxide. For example, the p-contact electrode 30 can be formed from ITO (Indium Tin Oxide). The material constituting the p buffer electrode 40 and the material constituting the n electrode 42 are the same. In addition, when forming the p buffer electrode 40 and the n electrode 42 from a multilayer, each layer structure is the same. For example, the p buffer electrode 40 and the n electrode 42 are formed of a metal material containing Ni or Cr, Au, and Al. In particular, when the n-side contact layer 22 is formed of n-type GaN, the n-electrode 42 can be formed including a Ni layer as a contact layer from the n-side contact layer 22 side, or the n-side contact layer It can be formed including a Cr layer as a contact layer from the side of 22. In particular, when the p contact electrode 30 is formed of a conductive oxide, the p buffer electrode 40 can be formed including a Ni layer as a contact layer from the p contact electrode 30 side, or the p contact electrode It can be formed including a Cr layer as a contact layer from the 30 side. Specifically, each of the p buffer electrode 40 and the n electrode 42 can be formed including a Ni layer, an Au layer, and an Al layer from the p contact electrode 30 side or the n side contact layer 22 side.

  The p buffer electrode 40 and the n electrode 42 in a plan view can be substantially circular or polygonal (for example, a triangle, a quadrangle, a pentagon, a hexagon, etc.). The size and / or shape of the p-buffer electrode 40 and the n-electrode 42 in plan view is taken into account, for example, by improving the ratio of the area of the light-emitting region (hereinafter referred to as “light-emitting area”) to the total area in plan view of 1 It can be set appropriately.

(Insulating layer 50)
The insulating layer 50 is mainly formed from, for example, silicon dioxide (SiO ₂ ) that is an insulating material.

  The light emitting element 1 configured as described above is a face-up type light emitting diode (LED) that emits light having a wavelength in a blue region. For example, the light emitting element 1 emits light having a peak wavelength of about 455 nm when the forward voltage is about 3 V and the forward current is 20 mA. The light emitting element 1 is formed in a substantially square shape when viewed from above. For example, the vertical dimension and the horizontal dimension of the light emitting element 1 are approximately 350 μm, respectively.

  Each layer from the buffer layer 20 to the p-side contact layer 28 provided on the sapphire substrate 10 is, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (Molecular Beam). Epitaxy (MBE), Halide Vapor Phase Epitaxy (HVPE), etc. Here, the buffer layer 20 is formed of AlN, but the buffer layer 20 can also be formed of GaN. In addition, the quantum well structure of the light emitting layer 25 may be a single quantum well structure or a strained quantum well structure instead of a multiple quantum well structure.

The insulating layer 50 is made of SiO ₂ , metal oxides such as titanium dioxide (TiO ₂ ), alumina (Al ₂ O ₃ ), tantalum pentoxide (Ta ₂ O ₅ ), silicon nitride (SiN), and aluminum nitride. It can also be formed from a nitride, such as (AlN), or an electrically insulating resin material, such as polyimide.

  Furthermore, the light emitting element 1 may be an LED that emits light having a peak wavelength in the ultraviolet region, the near ultraviolet region, or the green region, but the region of the peak wavelength of the light emitted by the LED is not limited thereto. In other modified examples, the planar dimension of the light emitting element 1 is not limited to this. For example, the planar dimension of the light emitting element 1 can be designed such that the vertical dimension and the horizontal dimension are each 1 mm, and the vertical dimension and the horizontal dimension can be different from each other.

(Manufacturing process of light-emitting element 1)
2A to 2C show an example of a manufacturing process of the light-emitting element according to the first embodiment. Specifically, (a) of FIG. 2A is a longitudinal sectional view of a light emitting device having a nitride semiconductor multilayer structure after being etched. FIG. 2B is a longitudinal sectional view of the light emitting device after the p contact electrode is formed. FIG. 2C is a longitudinal sectional view of the light emitting element after the insulating layer 50 is formed.

  First, a sapphire substrate 10 is prepared, and a nitride semiconductor multilayer structure including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer is formed on the sapphire substrate 10. Specifically, the buffer layer 20, the n-side contact layer 22, the n-side cladding layer 24, the light emitting layer 25, the p-side cladding layer 26, and the p-side contact layer 28 are formed on the sapphire substrate 10. A semiconductor multilayer structure is formed by epitaxial growth in this order (semiconductor multilayer structure forming step). Subsequently, a part from the p-side contact layer 28 to the n-side contact layer 22 is etched and removed using a photolithography technique and an etching technique (FIG. 2A (a), semiconductor removal step). Thereby, a part of the surface of the n-side contact layer 22 is exposed.

  Next, a p-contact electrode 30 as a transparent conductive layer is formed on substantially the entire surface on the p-side contact layer 28 (FIG. 2A (b), transparent conductive layer forming step). For example, a layer made of a transparent conductive material is formed on the entire surface including the exposed n-side contact layer 22 and the p-side contact layer 28, and then the p-contact electrode 30 is formed using a photolithography technique and an etching technique. . In the present embodiment, the p contact electrode 30 is made of ITO. The p contact electrode 30 is formed using, for example, a vacuum deposition method. The p-contact electrode 30 can also be formed by a sputtering method, a CVD method, a plasma CVD method, a vapor deposition method, a sol-gel method, or the like. Subsequently, the insulating layer 50 is formed on the entire surface of the n-side contact layer 22 and the p-side contact layer 28 on which the p-contact electrode 30 is formed by vacuum deposition (FIG. 2A (c), insulating layer forming step). . The insulating layer 50 is formed to have a thickness of 0.05 μm or more and 2.0 μm or less, for example. In addition, after forming the p-contact electrode 30 on the entire surface of the semiconductor multilayer structure, a part from the p-side contact layer 28 to the n-side contact layer 22 can be removed together with a part of the p-contact electrode 30 by etching. .

  FIG. 2B (a) is a longitudinal sectional view after a pattern is formed on the insulating layer, and FIG. 2B (b) is a longitudinal sectional view after a part of the insulating layer is removed. FIG. 2B (c) is a longitudinal sectional view after the electrodes are formed. FIG. 2C is a longitudinal sectional view after lift-off. Further, FIG. 2D is an enlarged longitudinal sectional view of the portion of the p-side exposed portion in FIG. 2B (a), and FIG. 2E shows an outline of the process flow for forming the portion of the p-side exposed portion.

  Subsequently, a pattern 200 made of a photoresist is formed on the insulating layer 50 by using a photolithography technique (FIG. 2B (a), pattern formation step). Specifically, this will be described with reference to FIG. 2E. First, a photoresist 210 is spin-coated on the surface of the substrate on which the insulating layer 50 is formed. As the photoresist 210, for example, a negative resist that has high sensitivity to exposure light and can improve throughput due to a short exposure time is used.

  After spin coating, the substrate is placed on a hot plate, and the substrate is baked at a predetermined temperature for a predetermined time to volatilize the flux in the photoresist (FIG. 2E (a), resist coating step). In the present embodiment, the photoresist 210 has a thickness of, for example, 2 μm or more and 4 μm or less by adjusting the amount of photoresist to be used, the spin coating rotation speed, and the like. Next, a photomask 300 is placed on the photoresist 210, and light 400 having a predetermined wavelength is irradiated from above the photomask 300 for a preset time (FIG. 2E (b), exposure step). Note that a photomask 300 having a mask pattern 302 having a predetermined shape is used as the photomask 300. Thereby, an acid generate | occur | produces in the part irradiated with the light 400. FIG. On the other hand, no acid is generated in a portion where the light 400 is not irradiated.

  Here, the light 400 is gradually absorbed by the photoresist 210 as it travels from the surface of the photoresist 210 toward the insulating layer 50. Therefore, the intensity of the light 400 on the surface of the photoresist 210 is the strongest, and the intensity of the light 400 in the vicinity of the insulating layer 50 is the weakest. As a result, the degree of reaction in which acid is generated in the photoresist 210 by the light 400 is the largest on the surface of the photoresist 210 and the smallest in the portion in contact with the insulating layer 50. Therefore, as shown in FIG. 2E (c), the portion where the acid is generated in the longitudinal section (hereinafter, simply referred to as “exposure portion 210b”) has a reverse taper shape extending downward, and no acid is generated. The portion (hereinafter simply referred to as “unexposed portion 210a”) has a tapered shape that narrows downward.

  Subsequently, the exposed photoresist 210 is subjected to heat treatment at a predetermined temperature for a predetermined time (reversal baking process). Thereby, due to the presence of the acid generated by the irradiation of the light 400, the crosslinking reaction of the resin material constituting the photoresist 210 proceeds in the exposed portion 210b. Next, the entire surface of the photoresist 210 is irradiated with light having a predetermined wavelength for a preset time (secondary exposure process). Thereby, the unexposed part 210a can be easily eluted in the developer. Thereafter, the unexposed portion 210a is removed by developing using a predetermined developer. Thereby, the n-side exposed portion 202 and the p-side exposed portion 204 are formed (FIG. 2B (a), FIG. 2E (d), development process).

  Here, in the present embodiment, as shown in FIG. 2D, the p-side exposed portion 204 in the longitudinal section of the pattern 200 has an inversely tapered shape. The angle at which the side surface is inclined with respect to the normal direction of the insulating layer 50 adjusts the exposure amount of the light 400 in the exposure process, the temperature and heat treatment time in the reversal baking process, the amount of light in the secondary exposure process, and the like. To make it less than 60 ° and less than 60 °.

  Next, etching (for example, dry etching) is performed on the insulating layer 50 using the pattern 200 as a mask. Thereby, the insulating layer 50 exposed to the outside from the n-side exposed portion 202 and the p-side exposed portion 204 is removed (FIG. 2B (b), insulating layer removing step). Here, the n-side opening 54 and the p-side opening 52 generated by the etching are both tapered.

  Subsequently, the p-buffer electrode 40 and the n-electrode 42 are formed in the p-side opening 52 and the n-side opening 54 using the vacuum deposition method with the pattern 200 remaining (FIG. 2B (c), electrode Forming step). In the present embodiment, the material constituting the p buffer electrode 40 and the material constituting the n electrode 42 are the same material. That is, the electrode is formed on the surface of the p-contact electrode 30 exposed by the p-side exposed portion 204, which is a region where the pattern 200 is not formed, and on the surface of the n-side contact layer 22 exposed by the n-side exposed portion 202. The p buffer electrode 40 and the n electrode 42 made of the same material are formed by simultaneously vacuum-depositing the material.

  Next, by removing the pattern 200 and the electrode layer 44 deposited on the pattern 200 by a lift-off method, the light-emitting element 1 according to the present embodiment is manufactured (FIG. 2C, pattern removal step).

  After the p buffer electrode 40 and the n electrode 42 are formed, ohmic contact and adhesion between the p contact electrode 30 and the p buffer electrode 40 and between the n side contact layer 22 and the n electrode 42 are ensured. Therefore, it is possible to perform a heat treatment for a predetermined time at a predetermined temperature and in a predetermined atmosphere. Further, the material constituting the p buffer electrode 40 and the material constituting the n electrode 42 can be different materials. In this case, the p buffer electrode 40 and the n electrode 42 are not formed simultaneously, but are formed separately.

  The n electrode 42 and the p buffer electrode 40 can also be formed by a sputtering method. The insulating layer 50 can also be formed by chemical vapor deposition (CVD). The light emitting element 1 formed through the above steps is mounted by flip chip bonding on a predetermined position of a substrate made of ceramic or the like in which a wiring pattern of a conductive material is formed in advance. And the light emitting element 1 mounted on the board | substrate can be packaged as a light-emitting device by sealing integrally with sealing materials, such as an epoxy resin, a silicone resin, or glass.

  In this embodiment, the pattern 200 is formed from a negative resist. However, when the shape of the p buffer electrode 40 and the n electrode 42 to be formed in a plan view is, for example, a shape including a thin line with a width of about several microns. A positive resist can also be used. In the case of using a positive resist, it is preferable to perform a surface modification process using Hexamethyldisilazane (HMDS) or the like on the surface of the insulating layer 50 before applying the positive resist.

(Effects of the first embodiment)
The manufacturing method of the light-emitting element 1 according to the present embodiment includes a pattern 200 for removing the insulating layer 50 in the insulating layer removing step, and a pattern for forming the p buffer electrode 40 and the n electrode 42 in the electrode forming step. Since 200 is made common, the etching pattern and the electrode forming pattern can be made common, so that the manufacturing process of the light emitting element 1 can be simplified. Thereby, manufacturing cost can be reduced. Furthermore, since the number of times the photomask 300 is used and the number of times the photoresist is removed can be reduced, the occurrence of defects due to contamination can be reduced, so that the yield can be improved.

  In addition, since the insulating layer 50 does not overlap the p buffer electrode 40 and the n electrode 42 in the light emitting element 1 according to the present embodiment, even if the size of the p buffer electrode 40 and the n electrode 42 in plan view is reduced, The same bonding area can be secured. Thereby, the light emission area of the light emitting element 1 can be expanded, and light extraction efficiency can be improved.

  While the embodiments of the present invention have been described above, the embodiments described above do not limit the invention according to the claims. In addition, it should be noted that not all the combinations of features described in the embodiments are essential to the means for solving the problems of the invention.

DESCRIPTION OF SYMBOLS 1 Light emitting element 10 Sapphire substrate 20 Buffer layer 22 n side contact layer 24 n side clad layer 25 light emitting layer 26 p side clad layer 28 p side contact layer 30 p contact electrode 30a protrusion part 30b recessed part 40 p buffer electrode 42 n electrode 44 electrode Layer 50 Insulating layer 52, 53 p-side opening 54 n-side opening 200 pattern 202 n-side exposed part 204 p-side exposed part 210 photoresist 210a unexposed part 210b exposed part 300 photomask 302 mask pattern 400 light

Claims (3)

By removing a part of the nitride semiconductor multilayer structure having the first semiconductor layer of the first conductivity type, the light emitting layer, and the second semiconductor layer of the second conductivity type different from the first conductivity type, A semiconductor removal step of exposing a surface of the first semiconductor layer;
A transparent conductive layer forming step of forming a transparent conductive layer on the surface of the second semiconductor layer;
An insulating layer forming step of forming an insulating layer on the exposed first semiconductor layer and on the second semiconductor layer on which the transparent conductive layer is formed;
Forming a pattern on the insulating layer having a first exposed portion that exposes the insulating layer on the first semiconductor layer and a second exposed portion that exposes the insulating layer on the transparent conductive layer Process,
An insulating layer removing step of forming the first opening and the second opening in the insulating layer by removing an exposed portion of the insulating layer through the first exposed portion and the second exposed portion;
Forming an electrode in the first opening on the first semiconductor layer and the second opening on the second semiconductor layer in a state in which the pattern is left. Method.   The manufacturing method of the light emitting element of Claim 1 further equipped with the pattern removal process of removing the said pattern after the said electrode formation process.   3. The method of manufacturing a light emitting device according to claim 2, wherein the first exposed portion and the second exposed portion are formed so as to expand toward the insulating layer in the thickness direction of the pattern.

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