CN116031337A - Manufacturing method of LED flip chip - Google Patents
Manufacturing method of LED flip chip Download PDFInfo
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- CN116031337A CN116031337A CN202211711601.4A CN202211711601A CN116031337A CN 116031337 A CN116031337 A CN 116031337A CN 202211711601 A CN202211711601 A CN 202211711601A CN 116031337 A CN116031337 A CN 116031337A
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Abstract
The invention relates to the technical field of semiconductor electronics, in particular to a manufacturing method of an LED flip chip. The manufacturing method comprises the steps of sequentially growing an N-GaN layer, a multiple quantum well layer and a P-GaN layer on a substrate, sequentially preparing a current blocking layer and an ITO layer, synchronously photoetching a Mesa surface and a dicing channel, and sequentially preparing the Mesa surface, the dicing channel, a current expansion layer, a DBR reflection layer and a metal electrode pad layer. The manufacturing method is to synchronously carry out photoetching operation on the Mesa surface and the dicing channel so as to reduce exposure offset and reserve the area of the GaN layer and the area of ITO on the GaN layer to the maximum extent.
Description
Technical Field
The invention relates to the technical field of semiconductor electronics, in particular to a manufacturing method of an LED flip chip.
Background
LED is an acronym for Light Emitting Diode, chinese called light emitting diode, and its constituent products are seen everywhere in life. Along with the updating iteration of the technology, the demand and the research and development quantity of the LED chip are gradually increased. In the case of multilayer film lamination, the light-emitting film layer and the conducting film layer are affected by photoetching offset, and a relatively wide window is required to be reserved.
The Chinese patent publication No. CN106025010A discloses a flip LED chip based on a conductive DBR structure and a manufacturing method thereof, wherein a buffer layer, an N-GaN layer, an active layer and a P-GaN layer are sequentially grown on a substrate, the active layer and the P-GaN layer are etched to form a Mesa step and expose part of the N-GaN layer, a DBR conductive reflecting layer and a metal reflecting layer are sequentially formed on the P-GaN layer step through evaporation and etching, an N metal conductive layer and a current expansion strip are arranged on the exposed part of the N-GaN layer, and an insulating layer is formed above the metal reflecting layer and above the exposed parts of the N metal conductive layer and the N-GaN layer; and a plurality of through holes are etched on the insulating layer, a P-type common metal layer and an N-type common metal layer are respectively arranged on the insulating layer, the P-type common metal layer is connected with the metal reflecting layer through the through holes, the N-type common metal layer is connected with the N-type metal conducting layer through the through holes, the insulating layer isolates the N-type metal conducting layer from the P-type common metal layer, and the DBR conducting reflecting layer is isolated from the N-type common metal layer. The preparation method improves the luminous reliability of the LED product and reduces the process difficulty and the manufacturing cost.
However, the preparation method needs to carry out multiple lithography, and is influenced by the alignment precision of an exposure machine, each lithography is provided with a lithography offset window of about 4 mu m, namely, the offset of a film layer pattern and a Mesa pattern or a pattern to be aligned in the subsequent process is not more than +/-2 mu m, otherwise, electric leakage or other electrical problems are easy to cause, so that the manufacturing difficulty is higher as the number of lithography tracks is higher; and the photoetching offset window is reserved in the multilayer film layers, so that the huge luminous area is wasted.
Disclosure of Invention
In order to overcome the defects in the prior art, the technical problem to be solved by the invention is to provide a manufacturing method of an LED flip chip, and the LED flip chip manufactured by the method has the advantages of less photoetching times and large light emitting area.
In order to solve the technical problems, the invention adopts the following technical scheme: a method of manufacturing an LED flip chip, comprising the steps of:
s1: sequentially growing an N-GaN layer, a multiple quantum well layer and a P-GaN layer on a substrate;
s2: preparing a current blocking layer above the P-GaN layer;
s3: evaporating an ITO layer above the current blocking layer;
s4: obtaining a Mesa photoetching pattern and a cutting path pattern after photoetching;
s5: etching by using ITO etching liquid, etching to obtain a Mesa surface, and synchronously etching the upper layer of the cutting channel pattern;
s6: using positive photoresist to cover and protect the exposed N-GaN layer, and etching to obtain a cutting path;
s7: forming a current expansion layer on the exposed parts of the N-GaN layer and the P-GaN layer through evaporation;
s8: forming a DBR reflection layer above the P-GaN layer by evaporation and etching;
s9: evaporating the P-type bonding pad and the N-type bonding pad to obtain a metal electrode bonding pad layer, and injecting DBR etching holes to be connected with the current expansion layer.
The invention has the beneficial effects that: according to the manufacturing method of the LED flip chip, the current blocking layer and the ITO layer are sequentially prepared, then the Mesa of the Mesa and the dicing channel are subjected to synchronous photoetching operation, and preconditions are provided for synchronous photoetching by exchanging manufacturing steps. Therefore, the photoetching quantity is reduced, the exposure offset is reduced, the area of the GaN layer and the area of the ITO (transparent conductive layer) on the GaN layer are reserved to the maximum extent, the luminous efficiency is increased, and the brightness is improved. The reduction of photoetching times can also reduce a plurality of processing flows, shorten the processing time and save the labor and equipment cost.
Drawings
Fig. 1 is a schematic diagram showing a product structure of S2 of a method for manufacturing an LED flip chip according to an embodiment of the present invention;
FIG. 2 is a schematic diagram showing the structure of the product of S3 of the method for manufacturing an LED flip chip according to the embodiment of the present invention;
FIG. 3 is a schematic diagram showing the structure of the product of S5 of the method for manufacturing an LED flip chip according to the embodiment of the present invention;
FIG. 4 is a schematic diagram showing the structure of the product of S6 of the method for manufacturing an LED flip chip according to the embodiment of the present invention;
FIG. 5 is a schematic diagram showing the structure of the product of S7 of the method for manufacturing an LED flip chip according to the embodiment of the present invention;
FIG. 6 is a schematic diagram showing the structure of the product of S8 of the method for manufacturing an LED flip chip according to the embodiment of the present invention;
fig. 7 is a schematic diagram showing the structure of the product of S9 of the method for manufacturing an LED flip chip according to the embodiment of the present invention;
description of the reference numerals: 1. a substrate; 2. an N-GaN layer; 3. a multiple quantum well layer; 4. a P-GaN layer; 5. a current blocking layer; 6. an ITO layer; 7. a current spreading layer; 8. a DBR reflection layer; 9. a metal electrode pad layer; 10. cutting the channel;
Detailed Description
In order to describe the technical contents, the achieved objects and effects of the present invention in detail, the following description will be made with reference to the embodiments in conjunction with the accompanying drawings.
The most critical concept of the invention is as follows: the Mesa step surface and the dicing street are subjected to synchronous photoetching operation to reduce exposure offset and keep the area of the GaN layer and the area of the ITO (transparent conductive layer) on the GaN layer to the maximum extent.
Referring to fig. 1 to 7, a method for manufacturing an LED flip chip according to the present invention includes the following steps:
s1: sequentially growing an N-GaN layer, a multiple quantum well layer and a P-GaN layer on a substrate;
s2: preparing a current blocking layer above the P-GaN layer;
s3: evaporating an ITO layer above the current blocking layer;
s4: obtaining a Mesa photoetching pattern and a cutting path pattern after photoetching;
s5: etching by using ITO etching liquid, etching to obtain a Mesa surface, and synchronously etching the upper layer of the cutting channel pattern;
s6: using positive photoresist to cover and protect the exposed N-GaN layer, and etching to obtain a cutting path;
s7: forming a current expansion layer on the exposed parts of the N-GaN layer and the P-GaN layer through evaporation;
s8: forming a DBR reflection layer above the P-GaN layer by evaporation and etching;
s9: evaporating the P-type bonding pad and the N-type bonding pad to obtain a metal electrode bonding pad layer, and injecting DBR etching holes to be connected with the current expansion layer.
From the above description, the beneficial effects of the invention are as follows: the DBR is also called a distributed Bragg reflector, and the existing manufacturing method of the LED flip chip sequentially comprises the steps of preparing a Meas step surface, a cutting channel, a current blocking layer and an ITO layer; according to the invention, the manufacturing steps are exchanged, the current blocking layer and the ITO layer are sequentially prepared, and then the step surface of the Mesa and the cutting channel are subjected to synchronous photoetching operation, so that one-time photoetching is reduced, exposure offset is reduced, the etched P-GaN and ITO are reduced, the area of the GaN layer and the area of the ITO (transparent conductive layer) on the GaN layer are reserved to the maximum extent, the luminous efficiency is increased, and the brightness is improved. The reduction of photoetching times can also reduce a plurality of processing flows, shorten the processing time and save the labor and equipment cost.
The cutting lines comprise Masa cutting lines and ISO cutting lines, and the invention carries out synchronous photoetching and etching on the two cutting lines, reduces the quantity of photoetching and increases the luminous efficiency.
Further, the specific steps of S2 are as follows:
s21: depositing silicon dioxide on the surface of the P-GaN layer;
s22: photoetching silicon dioxide;
s23: and (3) adopting BOE corrosive liquid (high-purity ammonium fluoride corrosive liquid) to carry out corrosion and photoresist removal to obtain the current blocking layer.
Further, the deposition thickness of the silicon dioxide in S2 is
From the above description, 2100-3000 can meet the requirement of current blocking effect, and the excessively thick deposition time is prolonged to waste productivity.
Further, the specific steps of S4 are as follows: and (3) coating positive photoresist, and then sequentially exposing and developing to prepare a Mesa photoetching pattern and a cutting path pattern.
Further, in S4: the coating thickness of the positive photoresist is 90-110 mu m, and the exposure quantity of exposure is 140-160 mj. Preferably, the positive photoresist is coated to a thickness of 100 μm and exposed to an exposure of 150mj.
Further, the overlay is obtained in S4 and S5.
Further, the width of the scribe line pattern is 3.5 to 4.5 μm. Preferably, the width of the scribe line pattern is 4 μm.
From the above description, the smaller the scribe line pattern, the higher the chip yield; however, when the scribe line pattern is too small, it is difficult to precisely position the scribe tool.
Further, the etching amount of the ITO etching solution is 5-7 μm.
From the above description, the core particle distance of the ITO obtained in the prior art is 34 μm, but under the photoetching process of the invention, the distance can be reduced to 18-22 μm, namely, the unilateral ITO is enlarged by 7 μm, so that the luminous area of the chip is increased.
Further, in S5, etching is performed by using an ITO etching solution, wherein the etching time is 60-70s+30-40S (two times of etching, one etching time is 60-70S, and one etching time is 30-40S).
From the above description, it is known that the etching time of the ITO etching solution in the prior art is 50 to 60s+20 to 30s, and the etching time is prolonged to accommodate the increased thickness when the photoresist is coated.
Further, the etching depth of the Mesa step surface in S5 is
Further, chlorine is used for etching in S6 etching, the etching time is 900S, the gas flow is 155cfm, and the etching depth is the same as that of the conventional method
From the above description, the etching time is 1800s when the ISO is etched, and the etching time is shortened to adapt to synchronous etching of the ISO cutting line and the Mesa cutting line.
Further, the width of the scribe line in S6 is 14 to 18. Mu.m.
From the above description, the smaller the dicing streets, the higher the chip yield; the minimum width of the scribe line is determined by the cutting tool.
Further, the current spreading layer is composed of a metal electrode composed of an N-GaN layer and a P-GaN layer.
Further, the DBR reflection layer is made of SiO 2 With Ti 3 O 5 Alternately arranged.
Further, the DBR reflection layer is made of SiO 2 With Ti 3 O 5 The 47 layers are alternately arranged in an ABAB manner.
Referring to fig. 1 to 7, a first embodiment of the present invention is as follows: a method of manufacturing an LED flip chip, comprising the steps of:
s1: sequentially growing an N-GaN layer 2, a multiple quantum well layer 3 and a P-GaN layer 4 on a substrate 1;
s2: a current blocking layer 5 was prepared over the P-GaN layer:
s21: deposition on the surface of P-GaN layer
Silica of (a);
s22: photoetching silicon dioxide;
s23: and (5) performing corrosion and photoresist removal by using a BOE corrosive liquid to obtain the current blocking layer 5 and the first alignment.
S3: evaporating an ITO layer 6 above the current blocking layer;
s4: coating 100 mu m positive photoresist, drying at 110 ℃ for 90 seconds, and then sequentially exposing with 150mj exposure and developing at 135 ℃ for 120 seconds to prepare a Mesa photoetching pattern, a cutting path pattern and a second overlay pattern; the width of the scribe line pattern was 4 μm;
s5: firstly, etching by using ITO etching liquid, wherein the side etching amount of the ITO etching liquid is 5-7 mu m, the etching is performed twice, the etching time is 65s for one time, and the etching time is 35s for one time; etching to obtain a Mesa and a second overlay, and synchronously etching the upper layer of the cutting channel pattern; the etching depth of the Mesa of the Mesa is
S6: using positive photoresist to cover and protect the second alignment and the exposed N-GaN layer, and obtaining a cutting channel 10 after etching, wherein the width of the cutting channel is 16 mu m; during etching, chlorine is used for etching, the etching time is 900s, the gas flow is 155cfm, and the etching depth is high
S7: forming a current expansion layer 7 on the exposed parts of the N-GaN layer 2 and the P-GaN layer 4 by vapor deposition, wherein the current expansion layer is formed by a metal electrode consisting of the N-GaN layer 2 and the P-GaN layer 4;
s8: forming a DBR reflection layer 8 over the P-GaN layer by vapor deposition and etching, the BR reflection layer 8 being made of SiO 2 With Ti 3 O 5 47 layers are alternately arranged in an ABAB mode;
s9: the P-type bonding pad and the N-type bonding pad are evaporated to obtain a metal electrode bonding pad layer 9, and the metal electrode bonding pad layer 9 is injected into DBR etching holes to be connected and conducted with the current expansion layer 7.
Performance test is performed on the LED flip chip in the first embodiment, and the test result is that: the ITO spacing was 20 μm and the ITO overall area was 86400. Mu.m 2 。
As can be seen, the conventional LED flip chip has an ITO pitch of typically 34 μm and an ITO overall area of about 77356 μm 2 Compared with the conventional LED flip chip, the LED flip chip has the advantages that the integral area of ITO is enlarged to 9044 mu m 2 (about 11.7%) and the brightness ratio was raised by about 3.44%.
The second embodiment of the invention is as follows: a method of manufacturing an LED flip chip, comprising the steps of:
s1: sequentially growing an N-GaN layer, a multiple quantum well layer and a P-GaN layer on a substrate;
s2: preparing a current blocking layer over the P-GaN layer:
s21: deposition on the surface of P-GaN layer
Silica of (a); />
S22: photoetching silicon dioxide;
s23: and (3) adopting BOE corrosive liquid to carry out corrosion and photoresist removal to obtain the current blocking layer and the first alignment.
S3: evaporating an ITO layer above the current blocking layer;
s4: coating positive photoresist with the thickness of 90 mu m, drying at the temperature of 110 ℃ for 90 seconds, and then sequentially exposing with 140mj exposure and developing at the temperature of 135 ℃ for 120 seconds to prepare a Mesa photoetching pattern, a cutting path pattern and a second overlay pattern; the width of the scribe line pattern was 3.5 μm;
s5: firstly, etching by using ITO etching liquid, wherein the side etching amount of the ITO etching liquid is 5-7 mu m, and the etching is performed twice, the etching time is 60s for one time, and the etching time is 30s for one time; etching to obtain a Mesa and a second overlay, and synchronously etching the upper layer of the cutting channel pattern; the etching depth of the Mesa of the Mesa is
S6: covering and protecting the second alignment and bare N-GaN layer with positive photoresist to obtain dicing streets with width of 14 μm after etchingThe method comprises the steps of carrying out a first treatment on the surface of the During etching, chlorine is used for etching, the etching time is 900s, the gas flow is 155cfm, and the etching depth is high
S7: forming a current expansion layer on the exposed parts of the N-GaN layer and the P-GaN layer by vapor deposition, wherein the current expansion layer is formed by a metal electrode consisting of the N-GaN layer and the P-GaN layer;
s8: forming a DBR reflection layer above the P-GaN layer by vapor deposition and etching, wherein the BR reflection layer is formed by SiO 2 With Ti 3 O 5 47 layers are alternately arranged in an ABAB mode;
s9: evaporating the P-type bonding pad and the N-type bonding pad to obtain a metal electrode bonding pad layer, and injecting DBR etching holes to be connected with the current expansion layer.
The third embodiment of the invention is as follows: a method of manufacturing an LED flip chip, comprising the steps of:
s1: sequentially growing an N-GaN layer, a multiple quantum well layer and a P-GaN layer on a substrate;
s2: preparing a current blocking layer over the P-GaN layer:
s21: deposition on the surface of P-GaN layer
Silica of (a);
s22: photoetching silicon dioxide;
s23: and (3) adopting BOE corrosive liquid to carry out corrosion and photoresist removal to obtain the current blocking layer and the first alignment.
S3: evaporating an ITO layer above the current blocking layer;
s4: coating positive photoresist with the thickness of 110 mu m, drying at the temperature of 110 ℃ for 90 seconds, and then sequentially exposing at the exposure of 160mj and developing at the temperature of 135 ℃ for 120 seconds to prepare a Mesa photoetching pattern, a cutting path pattern and a second overlay pattern; the width of the scribe line pattern was 4.5 μm;
s5: firstly, etching by using ITO etching liquid, wherein the side etching amount of the ITO etching liquid is 5-7 mu m, and the etching is performed twice, the etching time is 70s for one time, and the etching time is 40s for one time; etching to obtain a Mesa and a second overlay, and synchronously etching the upper layer of the cutting channel pattern; the etching depth of the Mesa of the Mesa is
S6: using positive photoresist to cover and protect the second alignment and the exposed N-GaN layer, and obtaining a cutting channel after etching, wherein the width of the cutting channel is 18 mu m; during etching, chlorine is used for etching, the etching time is 900s, the gas flow is 155cfm, and the etching depth is high
S7: forming a current expansion layer on the exposed parts of the N-GaN layer and the P-GaN layer by vapor deposition, wherein the current expansion layer is formed by a metal electrode consisting of the N-GaN layer and the P-GaN layer;
s8: forming a DBR reflection layer above the P-GaN layer by vapor deposition and etching, wherein the BR reflection layer is formed by SiO 2 With Ti 3 O 5 47 layers are alternately arranged in an ABAB mode;
s9: evaporating the P-type bonding pad and the N-type bonding pad to obtain a metal electrode bonding pad layer, and injecting DBR etching holes to be connected with the current expansion layer.
In summary, the method for manufacturing the LED flip chip provided by the invention sequentially prepares the current blocking layer and the ITO layer, and then performs synchronous photoetching operation on the Mesa of the Mesa and the dicing channel. The invention provides preconditions for realizing synchronous photoetching by changing manufacturing steps, changing photoresist thickness and other process parameters, reduces the photoetching quantity by synchronous photoetching, thereby reducing exposure offset and etched P-GaN and ITO, thereby reserving the area of a GaN layer and the area of ITO (transparent conductive layer) on the GaN layer to the maximum extent, increasing the luminous efficiency and improving the brightness. The reduction of photoetching times can also reduce a plurality of processing flows, shorten the processing time and save the labor and equipment cost.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent changes made by the specification and drawings of the present invention, or direct or indirect application in the relevant art, are included in the scope of the present invention.
Claims (9)
1. A method of manufacturing an LED flip chip, comprising the steps of:
s1: sequentially growing an N-GaN layer, a multiple quantum well layer and a P-GaN layer on a substrate;
s2: preparing a current blocking layer above the P-GaN layer;
s3: evaporating an ITO layer above the current blocking layer;
s4: obtaining a Mesa photoetching pattern and a cutting path pattern after photoetching;
s5: etching by using ITO etching liquid, etching to obtain a Mesa surface, and synchronously etching the upper layer of the cutting channel pattern;
s6: using positive photoresist to cover and protect the exposed N-GaN layer, and etching to obtain a cutting path;
s7: forming a current expansion layer on the exposed parts of the N-GaN layer and the P-GaN layer through evaporation;
s8: forming a DBR reflection layer above the P-GaN layer by evaporation and etching;
s9: evaporating the P-type bonding pad and the N-type bonding pad to obtain a metal electrode bonding pad layer, and injecting DBR etching holes to be connected with the current expansion layer.
2. The method for manufacturing the LED flip chip according to claim 1, wherein the specific step of S2 is:
s21: depositing silicon dioxide on the surface of the P-GaN layer;
s22: photoetching silicon dioxide;
s23: and (5) adopting BOE corrosive liquid to carry out corrosion and photoresist removal to obtain the current blocking layer.
3. The method for manufacturing the LED flip chip according to claim 1, wherein the specific step of S4 is: and (3) coating positive photoresist, and then sequentially exposing and developing to prepare a Mesa photoetching pattern and a cutting path pattern.
4. The method for manufacturing an LED flip chip according to claim 3, wherein in S4: the coating thickness of the positive photoresist is 90-110 mu m, and the exposure quantity of the exposure is 140-160 mj.
5. The method of manufacturing a flip-chip LED chip of claim 1, wherein the scribe line pattern has a width of 3.5 to 4.5 μm.
6. The method of manufacturing a flip-chip LED chip according to claim 1, wherein the etching solution for ITO has a lateral etching amount of 5 to 7 μm.
7. The method of manufacturing a flip-chip LED chip of claim 1, wherein the dicing streets in S6 have a width of 14 to 18 μm.
8. The method of manufacturing a flip-chip LED chip of claim 1, wherein said current spreading layer is composed of a metal electrode composed of an N-GaN layer and a P-GaN layer.
9. The method of manufacturing a flip-chip LED package according to claim 1, wherein the DBR reflective layer is made of SiO 2 With Ti 3 O 5 Alternately arranged.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116705925A (en) * | 2023-08-08 | 2023-09-05 | 江西兆驰半导体有限公司 | Forward-mounted high-voltage LED chip and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116705925A (en) * | 2023-08-08 | 2023-09-05 | 江西兆驰半导体有限公司 | Forward-mounted high-voltage LED chip and preparation method thereof |
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