CN115954042A - nand flash power-down test device, nand flash power-down test method and storage medium - Google Patents
nand flash power-down test device, nand flash power-down test method and storage medium Download PDFInfo
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Abstract
The application discloses a NAND Flash power-down test Device, a power-down test method and a storage medium, wherein the power-down test Device comprises a Device serving as a power-down test object and a Host Device serving as a power-down test machine, and the Device comprises an NAND Flash module; the Host equipment is connected with the NAND Flash module and used for sending a first driving command to the raw NAND to control a target physical block and/or a target page in the raw NAND to perform power failure test under the condition of the raw NAND; under the condition of a NAND chip comprising a flash memory controller, a first indication command is sent to the flash memory controller of the NAND chip to indicate the flash memory controller to determine a target physical block and/or a target page to perform power failure test, so that the hit probability and the test efficiency of the power failure test are improved.
Description
Technical Field
The application relates to the technical field of memory chips, in particular to a nand flash power failure testing device, a nand flash power failure testing method and a memory medium.
Background
A memory chip produced by a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) process has a special structure, as shown in fig. 1, memory cells in the memory chip are each composed of a switch tube (control tube for short) for control and a switch tube (data tube for short) for storage, and the electrical characteristics of the memory cells are controlled by an SWL (SEL-word, word line control signal) and a WL (word line ), so that the output current of the memory cells is read out on a BL (bit line) to realize data reading and writing.
At present, when a memory chip performs a program-erase operation and finds that a memory cell has an error, the memory chip usually completes the current operation and records the address of the defective memory cell, and then performs a replacement operation on the memory cell.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the application provides a NAND Flash power failure testing device, a NAND Flash power failure testing method and a storage medium, instructions in a power failure testing process can be simplified, a target physical block and/or a target page in NAND Flash can be designated for power failure testing, and hit probability and testing efficiency of the power failure testing are improved.
In a first aspect, an embodiment of the present application provides a nand flash power down testing apparatus, including:
the Device equipment serving as a power failure test object comprises an NAND Flash module;
as the Host equipment of the power failure testing machine, connecting the NAND Flash module, wherein the Host equipment is used for:
under the condition that the NAND Flash module is a raw NAND, sending a first driving command to the raw NAND to control a power-down scene and a power-down time of a target physical block and/or a target page in the raw NAND;
and under the condition that the NAND Flash module is an NAND chip comprising a Flash controller, sending a first indication command to the Flash controller of the NAND chip to indicate the Flash controller to determine a power-down scene and a power-down time of a target physical block and/or a target page.
In some embodiments, the Host Device includes an application processor communicatively coupled to the Device and configured to power the Device.
In some embodiments, the Host device is further configured to:
when the NAND Flash module is a raw NAND, sending a second driving command to the raw NAND to carry out reading test on the target physical block and/or the target page after completing the power-down test;
and under the condition that the NAND Flash module is a NAND chip containing a Flash controller, sending a second instruction command to the Flash controller of the NAND chip after completing the power failure test so as to instruct the Flash controller to perform read test on the target physical block and/or the target page.
In a second aspect, an embodiment of the present application further provides a nand flash power-down testing method, which is applied to a Host device in the nand flash power-down testing apparatus in the embodiment of the first aspect, and the power-down testing method includes:
under the condition that the NAND Flash module is a raw NAND, sending a first driving command to the raw NAND to control a power-down scene and a power-down time of a target physical block and/or a target page in the raw NAND;
alternatively, the first and second liquid crystal display panels may be,
and under the condition that the NAND Flash module is an NAND chip comprising a Flash controller, sending a first indication command to the Flash controller of the NAND chip to indicate the Flash controller to determine a power-down scene and a power-down time of a target physical block and/or a target page.
In some embodiments, the sending a first drive command to the raw NAND comprises:
programming the target physical block and/or the target page in the raw NAND according to a power failure test case, wherein the power failure test case comprises a preset power failure time and an address of the target physical block and/or the target page;
and powering off the Device equipment according to a preset power-down time in the programming process.
In some embodiments, the sending a first indication command to a flash controller of the NAND chip comprises:
sending a power failure test case to the flash memory controller to indicate the flash memory controller to run the power failure test case, wherein the power failure test case comprises a preset power failure time and an address of a target physical block and/or a target page;
and when receiving a power-down notice returned by the flash memory controller, cutting off the power supply to the Device equipment.
In some embodiments, the preset power-down time is a time when the NAND Flash module is in a busy state of the programming operation, or a time when the NAND Flash module is in the busy state of the programming operation and is delayed for a period of time.
In some embodiments, further comprising:
when detecting that the Device is powered down, powering on the Device again;
and when the whole power failure test is finished, sending a second driving command to the raw NAND to perform a reading test on the target physical block and/or the target page.
In some embodiments, further comprising:
when detecting that the Device is powered down, powering on the Device again;
and when the whole power failure test is finished, sending a second instruction command to a flash memory controller of the NAND chip to instruct the flash memory controller to perform a reading test on the target physical block and/or the target page.
In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, where computer-executable instructions are stored, and the computer-executable instructions are configured to cause a computer to execute the power failure test method according to the second aspect.
The nand flash power failure test device, the nand flash power failure test method and the storage medium provided by the embodiment of the application have the following beneficial effects at least: by constructing a Host-Device as a test platform and sending a test command to the Device through the Host, the Device is completely tested by the Host in a power-down mode when the NAND Flash is in a programming state; the embodiment of the application can perform power failure test aiming at specific physical block, page position and specific programming moment of NAND Flash, improves hit probability and test efficiency of the power failure test, and in addition, can perform reading test on the target physical block and the target page after performing the power failure test on the target physical block and the target page to obtain power failure test data of a lower layer.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the claimed subject matter and are incorporated in and constitute a part of this specification, illustrate embodiments of the claimed subject matter and together with the example serve to explain the principles of the claimed subject matter.
Fig. 1 is a schematic structural diagram of a power failure testing apparatus provided in an embodiment of the present application;
FIG. 2 is a flowchart of a power down test method for raw NAND according to an embodiment of the present disclosure;
FIG. 3 is a flowchart of a method for testing a NAND chip including a flash memory controller for power down according to an embodiment of the present disclosure;
FIG. 4 is a flowchart of a power down flow method of raw NAND according to an embodiment of the present disclosure;
FIG. 5 is a flowchart of a power-down flow method for a NAND chip including a flash memory controller according to an embodiment of the present disclosure;
FIG. 6 is a flow chart of a raw NAND power down-power up and read test provided by an embodiment of the present application;
FIG. 7 is a flowchart illustrating powering down-up and read testing of a NAND chip including a flash controller according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
The existing NAND Flash power-down test method mainly comprises the following steps: and product-level power-down tests, such as SSD and eMMC file power-down tests. The product-level power failure test mainly refers to that a series of commands are sent by a CPU/APU connected with a module according to a corresponding communication protocol to enable the module to normally run in various states such as a read-write wiper and the like, and power supply to the module is cut off at random time, so that a single module power failure test behavior is completed, and the power failure test is completed after the operation is circulated until a set power failure test standard is reached.
The existing scheme has some disadvantages:
(1) The power failure test cannot be carried out on a specific physical block, a page position and a specific programming moment of the NAND Flash;
(2) The method can not perform correlation analysis of the NAND Flash characteristic layer and the physical structure characteristic on the NAND Flash with the power failure abnormal data phenomenon;
(3) The power-down hit probability and the power-down test efficiency are relatively low.
Based on this, the embodiment of the application provides a nand flash power failure testing device, a power failure testing method and a storage medium, which can perform power failure testing at specific time aiming at a target physical block and a target page, simplify command interaction in the power failure testing process through a host-device command, and improve hit probability and testing efficiency of the power failure testing.
The embodiments of the present application will be further explained with reference to the drawings.
Referring to (a) and (b) of fig. 1, an embodiment of the first aspect of the present application provides a nand flash power down test apparatus, including:
the Device equipment serving as a power failure test object comprises a NAND Flash module;
as the Host equipment of the power-down test machine, connecting the NAND Flash module, wherein the Host equipment is used for:
under the condition that the NAND Flash module is a raw NAND, sending a first driving command to the raw NAND to control a power-down scene and a power-down time of a target physical block and/or a target page in the raw NAND;
and under the condition that the NAND Flash module is a NAND chip comprising a Flash controller, sending a first indication command to the Flash controller of the NAND chip to indicate the Flash controller to determine a power-down scene and a power-down time of the target physical block and/or the target page.
According to the embodiment of the application, the Host-Device is constructed to serve as a test platform, and the HOST is used for completely powering down the Device when the NAND Flash is in a programming state by utilizing the communication between the Host and the Device, so that the power down test is realized. Specifically, the Device refers to raw NAND or a module embedded with NAND Flash and a Flash memory controller, such as eMMC, UFS, SSD, etc., and is mainly responsible for communicating with Host or driving NAND Flash (except for raw NAND, which is directly driven by Host for power down test); the Host may be an Application Processor (APU) generally, and is responsible for supplying power to the devices and implementing communication between the devices or driving NAND Flash (if the Device is raw NAND, the Host is required to drive NAND Flash, and if the Device is a module embedded with NAND Flash, the Host is not required to drive NAND Flash, and is changed to send an instruction to a Flash memory controller).
Therefore, for the raw NAND, the Host directly executes the power-down test through the first driving command, designates the target physical block or the target page, writes preset test data through programming operation, and directly powers off the raw NAND in the programming operation process, so that the power-down test is completed once, and then the Host continues to power on the Device and repeatedly executes the programming-power-down process until the whole power-down test is completed. For the NAND chip comprising the flash memory controller, host indirectly executes the power failure test through a first indication command, host indicates a Device to execute a preset power failure test process, the flash memory controller internally programs a target physical block or a specified target page according to the first indication command, the flash memory controller controls the power failure time and informs the Host to power off when the power failure time is reached, and therefore the Host does not directly execute the power failure test. Compared with the current power-down test scheme, the Host-Device does not need to be subjected to internal complex software layer calculation conversion and other operations, and the method has the advantages of greatly reducing delay influence and improving flexibility of power-down time selection.
It can be understood that the first driving command, the first indication command, and the like in the embodiment of the present application are not standard protocol commands corresponding to the NAND Flash, and the standard protocol commands obviously cannot implement the power failure test of the present solution, so that the embodiment of the present application specifies a target physical block or a target page through private commands (the first driving command, the first indication command, and the like) by adjusting the driving of the NAND Flash, and the number of commands sent by host is small; for the NAND chip comprising the flash memory controller, the private command directly indicates the flash memory controller to control the power-down time, but not Host to directly control, the device runs in a non-firmware environment, no background operation is performed, the response speed is improved, and therefore the test efficiency is greatly improved.
Therefore, it can be seen that the Host Device includes an application processor, and the application processor is communicatively connected to the Device and powers the Device. That is, the power-off operation is completed by Host.
Wherein the Host device is further configured to:
when the NAND Flash module is a raw NAND, sending a second driving command to the raw NAND to perform reading test on the target physical block and/or the target page after completing the power failure test;
and under the condition that the NAND Flash module is a NAND chip comprising a Flash controller, sending a second instruction command to the Flash controller of the NAND chip after completing the power failure test so as to instruct the Flash controller to perform a reading test on the target physical block and/or the target page.
Because the Host sends the power failure test command every time, which physical blocks, pages and blocks in the NAND Flash are used for power failure test, and which blocks and pages are normally programmed. Therefore, host can enable Device to read data, threshold voltage distribution and other information of physical block page of NAND Flash to be tested by sending a command, and further visually observe whether abnormal data loss caused by power failure occurs in NAND Flash.
Referring to fig. 2 and fig. 3, a second aspect embodiment of the present application provides a nand flash power-down testing method, which is applied to a Host device in the nand flash power-down testing apparatus of the first aspect embodiment, and the power-down testing method includes:
step S100, under the condition that the NAND Flash module is a raw NAND, sending a first driving command to the raw NAND to control a power-down scene and a power-down time of a target physical block and/or a target page in the raw NAND;
alternatively, the first and second liquid crystal display panels may be,
step S200, under the condition that the NAND Flash module is a NAND chip comprising a Flash controller, sending a first indication command to the Flash controller of the NAND chip to indicate the Flash controller to determine a power-down scene and a power-down time of a target physical block and/or a target page.
Similarly, the power down test method in the embodiment of the second aspect is also that the Host performs the power down test on the raw NAND or instructs the flash memory controller to perform the power down test through the first driving command or the first instruction command. Reference may be made in detail to the description of the embodiments of the first aspect, which is not repeated here.
Referring to fig. 4, for sending the first driving command to the raw NAND in step S100, the following steps may be specifically included:
step S110, programming a target physical block and/or a target page in the raw NAND according to a power failure test case, wherein the power failure test case comprises a preset power failure time and the address of the target physical block and/or the target page;
and step S120, powering off the Device equipment according to the preset power-off time in the programming process.
Referring to fig. 5, the step S200 of sending the first instruction command to the flash memory controller of the NAND chip may specifically include the following steps:
step S210, sending a power failure test case to a flash memory controller to instruct the flash memory controller to run the power failure test case, wherein the power failure test case comprises a preset power failure time and an address of a target physical block and/or a target page;
step S220, when receiving the power down notification returned by the flash memory controller, cutting off power supply to the Device.
No matter for raw NAND or a NAND chip comprising a flash memory controller, a preset power-down time can be set through a power-down test case, and the address of a target physical block and/or a target page can be specified. Under the condition of raw NAND, the Host directly dominates the power failure test process, under the condition that the NAND chip of the flash memory controller is included, the flash memory controller dominates a power failure scene and power failure opportunity, and notifies the Host to perform power failure at the moment when power failure is needed, and the Host immediately cuts off the power supply of the Device equipment after receiving the notification.
The method can set different power-down moments, for example, the preset power-down moment is a moment when the NAND Flash module is in the busy state of the programming operation, or a moment when the NAND Flash module is in the busy state of the programming operation and is delayed for a period of time. The programming states of the NAND Flash are Ready and Busy, the power-down opportunity is determined by Host in the traditional power-down test process, and the hit rate is not high enough because it is unclear whether the NAND Flash is in the Ready state or the Busy state at the current moment (only the power-down in the Busy state is effective power-down test). According to the method and the device, the Host direct-coupled raw NAND or the flash memory controller controls the power-down time, the current programming state can be clearly known, and the problem that the hit rate is not high enough can be avoided. Based on this, the embodiment of the application can also set that a period of time (such as 100 microseconds) is delayed from the power-down time to the back as the actual power-down time, then the Host is notified to power down the Device, and the NAND Flash can be completely powered down at different programmed specific times by specifying the delay parameter.
Referring to fig. 6, in an embodiment, in the case of raw NAND, after the power down test is completed, the method further includes:
step S310, when detecting that the Device is powered down, powering on the Device again;
and step S320, when the whole power failure test is finished, sending a second driving command to the raw NAND to perform a reading test on the target physical block and/or the target page.
Referring to fig. 7, in an embodiment, in the case of a NAND chip including a flash memory controller, after the power down test is completed, the method further includes:
step S410, when detecting that the Device is powered down, powering on the Device again;
step S420, when the entire power failure test is completed, sending a second instruction command to the flash memory controller of the NAND chip to instruct the flash memory controller to perform a read test on the target physical block and/or the target page.
And each time the power failure is finished for one target physical block and/or target page, the Host powers on the Device again for the next power failure until the power failure times are met or all addresses in the NAND Flash are traversed and finished. And then executing a reading test to enable the Device to read the data, threshold voltage distribution and other information of the physical block page of the NAND Flash to be tested, and further visually observing whether the NAND Flash has abnormal data loss caused by power failure.
Embodiments of the present application further provide a computer-readable storage medium, which stores computer-executable instructions for causing a computer to perform the power failure testing method according to the second aspect.
The terms "first," "second," "third," "fourth," and the like in the description of the application and the above-described figures, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances such that the embodiments of the application described herein may be implemented, for example, in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
It should be understood that in the description of the embodiments of the present application, a plurality (or a plurality) means two or more, and more than, less than, more than, etc. are understood as excluding the present number, and more than, less than, etc. are understood as including the present number.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a portable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other media capable of storing program codes.
It should also be appreciated that the various implementations provided in the embodiments of the present application can be combined arbitrarily to achieve different technical effects.
While the preferred embodiments of the present invention have been described, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and such equivalent modifications or substitutions are included in the scope of the present invention defined by the claims.
Claims (10)
1. The utility model provides a nand flash power down testing arrangement which characterized in that includes:
the Device equipment serving as a power failure test object comprises a NAND Flash module;
as the Host equipment of the power failure testing machine, connecting the NAND Flash module, wherein the Host equipment is used for:
under the condition that the NAND Flash module is a raw NAND, sending a first driving command to the raw NAND to control a power-down scene and a power-down time of a target physical block and/or a target page in the raw NAND;
and under the condition that the NAND Flash module is an NAND chip comprising a Flash controller, sending a first indication command to the Flash controller of the NAND chip to indicate the Flash controller to determine a power-down scene and a power-down time of a target physical block and/or a target page.
2. The power-down test apparatus of claim 1, wherein the Host Device comprises an application processor, and the application processor is communicatively connected to the Device and powers the Device.
3. The power-down test apparatus of claim 2, wherein the Host device is further configured to:
when the NAND Flash module is a raw NAND, sending a second driving command to the raw NAND to perform reading test on the target physical block and/or the target page after completing the power-down test;
and under the condition that the NAND Flash module is a NAND chip containing a Flash controller, sending a second instruction command to the Flash controller of the NAND chip after completing the power failure test so as to instruct the Flash controller to perform read test on the target physical block and/or the target page.
4. A nand flash power-down test method applied to a Host device in the nand flash power-down test apparatus as claimed in any one of claims 1 to 3, the power-down test method comprising:
under the condition that the NAND Flash module is a raw NAND, sending a first driving command to the raw NAND to control a power-down scene and a power-down time of a target physical block and/or a target page in the raw NAND;
alternatively, the first and second electrodes may be,
and under the condition that the NAND Flash module is a NAND chip comprising a Flash memory controller, sending a first indication command to the Flash memory controller of the NAND chip to indicate the Flash memory controller to determine a power-down scene and a power-down time of a target physical block and/or a target page.
5. The power-down test method according to claim 4, wherein the sending the first driving command to the raw NAND comprises:
programming the target physical block and/or the target page in the raw NAND according to a power failure test case, wherein the power failure test case comprises a preset power failure time and an address of the target physical block and/or the target page;
and powering off the Device equipment according to a preset power-down time in the programming process.
6. The method according to claim 4, wherein the sending a first instruction command to the flash controller of the NAND chip comprises:
sending a power failure test case to the flash memory controller to indicate the flash memory controller to run the power failure test case, wherein the power failure test case comprises a preset power failure time and an address of a target physical block and/or a target page;
and when receiving a power-down notice returned by the flash memory controller, cutting off the power supply to the Device equipment.
7. The power-down test method according to claim 5 or 6, wherein the preset power-down time is a time when the NAND Flash module is in a busy state of programming operation, or a time when the NAND Flash module is in the busy state of programming operation and is delayed for a period of time.
8. The power-down test method of claim 5, further comprising:
when detecting that the power failure of the Device equipment is completed, powering on the Device equipment again;
and when the whole power failure test is finished, sending a second driving command to the raw NAND to carry out a reading test on the target physical block and/or the target page.
9. The power-down test method of claim 6, further comprising:
when detecting that the Device is powered down, powering on the Device again;
and when the whole power failure test is finished, sending a second instruction command to a flash memory controller of the NAND chip to instruct the flash memory controller to carry out a reading test on the target physical block and/or the target page.
10. A computer-readable storage medium having stored thereon computer-executable instructions for causing a computer to perform the power loss testing method of any one of claims 4 to 9.
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| CN116483641A (en) * | 2023-06-14 | 2023-07-25 | 深圳市晶存科技有限公司 | Method, system and medium for abnormal power failure detection of hard disk |
| CN116564398A (en) * | 2023-05-26 | 2023-08-08 | 北京得瑞领新科技有限公司 | Method and device for detecting nor flash memory and embedded equipment |
| CN116578448A (en) * | 2023-04-27 | 2023-08-11 | 珠海妙存科技有限公司 | Chip power-down log processing method and system |
| CN116705137A (en) * | 2023-05-08 | 2023-09-05 | 深圳市晶存科技有限公司 | Test mode switching method for solid state disk |
| CN116994635A (en) * | 2023-06-28 | 2023-11-03 | 珠海妙存科技有限公司 | Flash memory power failure detection method and system, electronic equipment and storage medium |
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2022
- 2022-12-20 CN CN202211639011.5A patent/CN115954042A/en active Pending
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| CN116705137B (en) * | 2023-05-08 | 2024-04-02 | 深圳市晶存科技有限公司 | Test mode switching method for solid state disk |
| CN116564398A (en) * | 2023-05-26 | 2023-08-08 | 北京得瑞领新科技有限公司 | Method and device for detecting nor flash memory and embedded equipment |
| CN116564398B (en) * | 2023-05-26 | 2023-12-22 | 北京得瑞领新科技有限公司 | Method and device for detecting nor flash memory and embedded equipment |
| CN116483641A (en) * | 2023-06-14 | 2023-07-25 | 深圳市晶存科技有限公司 | Method, system and medium for abnormal power failure detection of hard disk |
| CN116483641B (en) * | 2023-06-14 | 2024-04-02 | 深圳市晶存科技有限公司 | Method, system and medium for abnormal power failure detection of hard disk |
| CN116994635A (en) * | 2023-06-28 | 2023-11-03 | 珠海妙存科技有限公司 | Flash memory power failure detection method and system, electronic equipment and storage medium |
| CN116994635B (en) * | 2023-06-28 | 2024-04-09 | 珠海妙存科技有限公司 | Flash memory power failure detection method and system, electronic equipment and storage medium |
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