CN116564398A - Method and device for detecting nor flash memory and embedded equipment - Google Patents
Method and device for detecting nor flash memory and embedded equipment Download PDFInfo
- Publication number
- CN116564398A CN116564398A CN202310611984.6A CN202310611984A CN116564398A CN 116564398 A CN116564398 A CN 116564398A CN 202310611984 A CN202310611984 A CN 202310611984A CN 116564398 A CN116564398 A CN 116564398A
- Authority
- CN
- China
- Prior art keywords
- flash memory
- test
- read
- data
- target block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 71
- 238000012360 testing method Methods 0.000 claims abstract description 256
- 238000001514 detection method Methods 0.000 claims abstract description 102
- 230000002159 abnormal effect Effects 0.000 claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000004590 computer program Methods 0.000 claims description 6
- 238000013500 data storage Methods 0.000 abstract description 2
- 239000000243 solution Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
The invention relates to the technical field of data storage, and provides a method and a device for detecting a nor flash memory and embedded equipment, wherein the method comprises the following steps: in the production test stage, controlling the embedded device containing the nor flash memory to run pre-burnt test special firmware after power-on so as to enable the embedded device to enter a nor flash memory detection mode; in the nor flash memory detection mode, performing read-write pressure test on physical blocks to be detected in the nor flash memory one by one so as to detect abnormal physical blocks in the nor flash memory; and after all physical blocks in the nor flash memory are tested, exiting the nor flash memory detection mode and generating a detection log according to the detected abnormal physical blocks. The invention automatically realizes the nor flash memory detection of the embedded equipment in the production test stage by burning the special firmware in the embedded equipment, thereby not only simplifying the detection flow and improving the detection efficiency, but also avoiding the problems that the performance such as the starting time of the equipment is influenced by the detection during the normal power-on use period of the embedded equipment.
Description
Technical Field
The present invention relates to the field of data storage technologies, and in particular, to a method and an apparatus for detecting a nor flash memory, and an embedded device.
Background
When the nor flash memory (flash) is used for the embedded equipment, key data for ensuring the normal operation of the equipment, including firmware, equipment information, operation logs and the like, are stored, so that the nor flash memory can cause fatal influence on products once the nor flash memory fails.
In the prior art, the nor flash memory is detected during each power-on period in the use process of the embedded equipment, and the detection method can prolong the starting time and reduce the use experience of products. And because the service life of the nor flash is limited, the service life of the nor flash can be shortened by frequently erasing part of sectors in the detection process under the scene of frequent power-on and power-off of hardware equipment. And the original data of the nor flash memory can be erased and temporary test data can be written in during the detection period, and if abnormal power failure occurs, the nor flash data can be damaged, so that the subsequent use is affected.
Disclosure of Invention
The present invention has been made in view of the above problems, and provides a method, an apparatus, and an embedded device for detecting a nor flash memory, which overcome or at least partially solve the above problems.
In one aspect of the present invention, there is provided a method for detecting a nor flash memory, the method comprising:
in the production test stage, controlling the embedded equipment containing the nor flash memory to run pre-burnt test special firmware after power-on so as to enable the embedded equipment to enter a nor flash memory detection mode;
in a nor flash memory detection mode, performing read-write pressure test on physical blocks to be detected in the nor flash memory one by one so as to detect abnormal physical blocks in the nor flash memory;
and after all physical blocks in the nor flash memory are tested, exiting the nor flash memory detection mode and generating a detection log according to the detected abnormal physical blocks.
Further, the step of performing the read-write pressure test on the physical blocks to be detected in the nor flash memory one by one includes:
selecting one physical block to be detected in the nor flash memory as a target block, and writing original data in the target block into an SRAM of the embedded device;
writing first test special data in a preset test data set into the target block;
performing a read operation on the target block to obtain read data of the first test specific data;
comparing whether the read data of the first test special data is consistent with the read data of the first test special data;
if the first test special data is inconsistent with the read data of the first test special data, recording the target block as an abnormal physical block, and sequentially selecting the next physical block to be detected in the nor flash memory as a new target block according to a preset test execution sequence so as to perform a read-write pressure test on the new target block.
Further, the method further comprises:
if the first test special data is consistent with the read data of the first test special data, executing the read-write pressure test for the target block for preset times according to different test special data in a preset test data set;
and if any one of the test special data and the read data of the test special data are inconsistent in the repeatedly executed read-write pressure test, recording the target block as an abnormal physical block.
Further, the method further comprises:
if the target block is not recorded as an abnormal physical block, writing original data of the target block which is written in the SRAM in advance back to the target block;
performing a read operation on the target block to obtain read data of original data, and comparing whether the original data of the target block is consistent with the read data of the original data;
if the original data of the target block is inconsistent with the read data of the original data, recording the target block as an abnormal physical block, and sequentially selecting the next physical block to be detected in the nor flash memory as a new target block according to a preset test execution sequence to perform a read-write pressure test on the new target block.
Further, the method further comprises:
after receiving a command of inserting errors into a specified physical block issued by a host, judging whether a target block to be detected is the specified physical block or not before performing a read-write pressure test on any target block in the nor flash memory;
if yes, performing error injection on the read data of the special test data when the read operation is performed on the target block to obtain the read data of the special test data;
after the current read-write pressure test is executed on the target block, whether the detection method of the current nor flash memory is effective is judged according to whether the target block is recorded as an abnormal physical block, and if the target block is recorded as the abnormal physical block, the detection method of the current nor flash memory is judged to be effective.
Further, the method further comprises:
before the read-write pressure test is carried out on physical blocks to be detected in the nor flash memory one by one, any physical block is selected as a marking block in the nor flash memory;
writing a test mark in the mark block to identify that the nor flash memory is in a read-write pressure test;
after all physical blocks to be detected in the nor flash memory are detected, clearing test marks in the mark blocks; wherein,,
the marked block is not used as a physical block to be detected of the nor flash memory.
Further, the method further comprises:
judging whether a power-off signal is detected after performing a read-write pressure test on any physical block to be detected in the nor flash memory;
if the power-off signal is detected, stopping detecting the nor flash memory, and recording the abnormal power-off event in a detection log;
and if the power-off signal is not detected after the read-write pressure test is performed on all the physical blocks to be detected in the nor flash memory, clearing the test mark in the mark block.
Further, the method further comprises:
judging whether a test mark exists in the mark block or not when the embedded equipment is electrified and initialized;
if yes, the detection of the enabling nor flash memory is forbidden, and the abnormal power-down event of the nor flash memory in the last test is prompted, so that the test special firmware burning is conducted on the nor flash memory again to finish the detection of the nor flash memory, and after the test special firmware is burned again, the test mark in the mark block is cleared.
Another aspect of the present invention further provides a device for detecting a nor flash memory, which is characterized in that the device includes:
the detection mode control module is used for controlling the embedded equipment containing the nor flash memory to run pre-burnt special test firmware after power-on in the production test stage so as to enable the embedded equipment to enter a nor flash memory detection mode;
the target block testing module is used for carrying out read-write pressure test on physical blocks to be detected in the nor flash memory one by one in a nor flash memory detection mode so as to detect abnormal physical blocks in the nor flash memory;
and the detection mode control module is also used for exiting the detection mode of the nor flash memory and generating a detection log according to the detected abnormal physical blocks after all physical blocks in the nor flash memory are tested.
In another aspect, the present invention further provides an embedded device, where the embedded device includes a controller, where the controller includes a memory, a processor, and a computer program stored on the memory and capable of running on the processor, and where the processor implements the steps of the method for detecting a nor flash memory described above when the processor executes the computer program.
According to the method and device for detecting the nor flash memory and the embedded equipment, provided by the embodiment of the invention, in the production test stage, the embedded equipment containing the nor flash memory is controlled to run pre-burnt special test firmware after being electrified so that the embedded equipment enters a nor flash memory detection mode; in a nor flash memory detection mode, performing read-write pressure test on physical blocks to be detected in the nor flash memory one by one so as to detect abnormal physical blocks in the nor flash memory; and after all physical blocks in the nor flash memory are tested, exiting the nor flash memory detection mode and generating a detection log according to the detected abnormal physical blocks. The invention automatically realizes the nor flash memory detection of the embedded equipment in the production test stage by burning the special firmware in the embedded equipment, thereby not only simplifying the detection flow and improving the detection efficiency, but also avoiding the problems that the performance such as the starting time of the equipment is influenced by the detection during the normal power-on use period of the embedded equipment.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a flowchart of a method for detecting nor flash memory according to an embodiment of the present invention;
FIG. 2 is a timing chart of a method for detecting nor flash memory according to an embodiment of the present invention;
FIG. 3 is a timing chart of a method for detecting a nor flash memory according to another embodiment of the present invention;
FIG. 4 is a timing chart of a method for detecting a nor flash memory according to another embodiment of the present invention;
FIG. 5 is a timing chart of a method for detecting a nor flash memory according to another embodiment of the present invention;
fig. 6 is a block diagram of a detecting device for nor flash memory according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 schematically shows a flowchart of a method for detecting a nor flash memory according to an embodiment of the present invention. Referring to fig. 1, the method for detecting the nor flash memory according to the embodiment of the invention specifically includes the following steps:
s1, in a production test stage, controlling the embedded device containing the nor flash memory to run pre-burnt test special firmware after power-on so as to enable the embedded device to enter a nor flash memory detection mode.
In the embodiment of the invention, the test proprietary firmware is burned in the embedded device, in particular, the nor flash memory of the embedded device in the production test stage. It should be noted that, although the nor flash memory can implement direct access execution of the embedded device, since the location of the nor flash memory stored in the test proprietary firmware also needs to be tested, when the test proprietary firmware is run to detect the nor flash memory, the embodiment of the invention loads the program of the test proprietary firmware into the RAM of the embedded device to run.
S2, in a nor flash memory detection mode, performing read-write pressure test on physical blocks to be detected in the nor flash memory one by one so as to detect abnormal physical blocks in the nor flash memory.
And S3, after all physical blocks in the nor flash memory are tested, exiting the nor flash memory detection mode and generating a detection log according to the detected abnormal physical blocks.
In the embodiment of the invention, the detection log is generated according to the detected abnormal physical blocks, so that related staff can analyze and maintain the nor flash memory of the embedded equipment according to the detection log. If the nor flash memory needs to be maintained, the test flow is re-entered after the maintenance.
In the embodiment of the present invention, the step of performing the read-write pressure test on the physical blocks to be detected in the nor flash memory one by one includes: selecting one physical block to be detected in the nor flash memory as a target block, and writing original data in the target block into an SRAM of the embedded device; writing first test special data in a preset test data set into the target block; performing a read operation on the target block to obtain read data of the first test specific data; comparing whether the read data of the first test special data is consistent with the read data of the first test special data; if the first test special data is inconsistent with the read data of the first test special data, recording the target block as an abnormal physical block, and sequentially selecting the next physical block to be detected in the nor flash memory as a new target block according to a preset test execution sequence so as to perform a read-write pressure test on the new target block. It should be noted that, when the read-write pressure test is performed on the nor flash memory, the original data in the target block needs to be stored in the SRAM, and the original data needs to be read for comparison in the subsequent comparison, so that a storage space twice as large as the physical block of the nor flash memory should be opened up in the SRAM for storing temporary data.
In the embodiment of the invention, the preset special data for the test is written into the target block, and the special data for the test is read to judge whether the written special data for the test is consistent with the read special data for the test, so that the quick one-time read-write pressure test for the target is realized. According to actual needs, when the nor flash memory is detected, the read-write pressure test of the target block can be realized by completing the read-write pressure test of the target block for multiple times. When only one read-write pressure test is needed to be completed on the target block, if the read data of the first test special data is consistent with the read data of the first test special data, the target block passes the read-write pressure test. The embodiment of the invention fully verifies the stability of each physical block of the nor flash memory by executing the read-write pressure test for multiple times on the target block in the test stage, and solves the problems of long starting time and poor user experience caused by frequently executing the read-write pressure test on the physical block of the nor flash memory when the power is on in the use process. Meanwhile, the problem that the service life of the nor flash memory is shortened due to the fact that the read-write-erase operation is frequently executed on the nor flash memory is effectively avoided.
Specifically, when multiple read-write pressure tests are required to be completed on the target block, the method further comprises: if the first test special data is consistent with the read data of the first test special data, executing the read-write pressure test for the target block for preset times according to different test special data in a preset test data set; if any special data of the test and the read data of the special data of the test are inconsistent in the repeatedly executed read-write pressure test, recording the target block as an abnormal physical block, and sequentially selecting the next physical block to be detected in the nor flash memory as a new target block according to a preset test execution sequence so as to perform the read-write pressure test on the new target block. Accordingly, if the test-dedicated data and the read data of the test-dedicated data are identical in the read-write pressure test repeatedly performed, the target block passes the read-write pressure test.
Further, in order to ensure that the original data in the nor flash memory is not damaged in the test process, the embodiment of the invention further includes detecting the original data, so that the method for detecting the nor flash memory according to the embodiment of the invention further includes: if the target block is not recorded as an abnormal physical block (passing a read-write pressure test), writing original data of the target block which is written in the SRAM in advance back to the target block; performing a read operation on the target block to obtain read data of original data, and comparing whether the original data of the target block is consistent with the read data of the original data; if the original data of the target block is inconsistent with the read data of the original data, recording the target block as an abnormal physical block, and sequentially selecting the next physical block to be detected in the nor flash memory as a new target block according to a preset test execution sequence to perform a read-write pressure test on the new target block.
It should be noted that, in the embodiment of the present invention, by comparing whether the original data of the target block and the read data of the original data are consistent to verify whether the original data are successfully written back, only if the original data are successfully written back, it can be shown that the read-write pressure test of the target block has no influence on the original data of the target block, so that the stability of the nor flash memory in the subsequent use process of the embedded device is further ensured. Correspondingly, if the original data of the target block is consistent with the read data of the original data, the next physical block to be detected in the nor flash memory is sequentially selected as a new target block according to a preset test execution sequence so as to carry out a read-write pressure test on the new target block.
Fig. 2 schematically shows a timing flowchart of a method for detecting a nor flash memory according to an embodiment of the present invention. Referring to fig. 2, a specific timing control flow of a method for detecting a nor flash memory according to an embodiment of the present invention includes the following steps:
s10, starting, namely starting to enter a nor flash memory detection mode after the embedded device is powered on;
s11, initializing an SRAM area of the embedded equipment;
in the embodiment of the invention, initializing the SRAM area of the embedded device specifically comprises opening up an area twice as much as the storage space of the physical block for storing temporary data.
S12, selecting one physical block in the nor flash memory as a target block;
s13, writing original data in the target block into an SRAM area;
s14, erasing the original data in the target block;
s15, checking an erasing result; executing the next step if all the erasing is performed, and executing the erasing operation again if all the erasing is not performed;
s16, writing test special data into the target block;
s17, reading and comparing the special test data;
s18, judging whether the data comparison is consistent; if the data comparison is consistent, executing step S20, and if the data comparison is inconsistent, executing step S19;
s19, failing to test the target block; after step S19 is performed, step S25 is performed;
s20, erasing the special test data in the target block;
s21, writing original data into a target block;
s22, reading and rewriting original data to compare;
s23, judging whether the data comparison is consistent; if the data comparison is consistent, the target block passes the test to execute the step S25, and if the data comparison is inconsistent, the step S24 is executed;
s24, failing to test the target block; after step S24 is performed, step S25 is performed;
s25, judging whether the physical block test is completed or not; executing step S26 if all physical block tests are completed; if all physical blocks are not tested, executing step S12;
s26, after the test is completed, a detection log is generated.
The above embodiment is a detailed time sequence flow step of the method for detecting the nor flash memory, and a specific implementation manner of the method is described in detail in the foregoing embodiment. In addition, the embodiment of the invention only provides a flow for executing the read-write pressure test on the target block once, and if the read-write pressure test is required to be executed for a plurality of times, the corresponding flow is added.
Further, when the nor flash memory is detected, the original data in the target block is temporarily stored in the SRAM of the embedded device, and if unexpected power failure occurs, the original data of the target block is lost, so that once abnormal power failure occurs during the nor flash memory test, the original data of the nor flash memory is irreversibly damaged, and if some key data is erased or some parameters are rewritten just before the power failure, the subsequent test result is misjudged and even the embedded device cannot normally operate. Therefore, it is necessary to record and prompt the abnormal power failure event during the test, so that the operator can re-perform the factory test on the equipment.
Therefore, the method for detecting the nor flash memory in the embodiment of the invention further comprises the following steps: before the read-write pressure test is carried out on physical blocks to be detected in the nor flash memory one by one, any physical block is selected as a marking block in the nor flash memory; writing a test mark in the mark block to identify that the nor flash memory is in a read-write pressure test; after all physical blocks to be detected in the nor flash memory are detected, clearing test marks in the mark blocks; it should be noted that, in order to avoid erroneous judgment of nor flash memory detection caused by erasing the test identifier in the tag block, the tag block in the embodiment of the present invention is not used as a physical block to be detected of the nor flash memory.
Further, since the capacitor discharge may last for several seconds when the embedded device is powered down, this period may support the normal operation of the embedded device firmware. Therefore, in order to avoid continuous influence on a plurality of physical blocks, the method for detecting the nor flash memory according to the embodiment of the invention further includes: judging whether a power-off signal is detected after performing a read-write pressure test on any physical block to be detected in the nor flash memory; if the power-off signal is detected, stopping detecting the nor flash memory, and recording the abnormal power-off event in a detection log; and if the power-off signal is not detected after the read-write pressure test is performed on all the physical blocks to be detected in the nor flash memory, clearing the test mark in the mark block.
Fig. 3 schematically shows a timing flowchart of a method for detecting a nor flash memory according to another embodiment of the present invention. Referring to fig. 3, in the method for detecting nor flash memory according to the embodiment of the present invention, the control of the timing sequence flow of the test mark in the test stage includes the following steps:
s20, starting to start to enter a nor flash memory detection mode after the embedded device is powered on;
s21, selecting a mark block from the nor flash memory and writing a test mark into the mark block;
s22, executing a read-write pressure test on a target block in the nor flash memory, and executing a step S23 after executing the read-write pressure test once on the target block each time;
s23, judging whether abnormal power failure is detected, namely whether a power failure signal is detected, if the power failure signal is detected, executing a step S26, and if the power failure signal is not detected, executing a step S24;
s24, judging whether all physical block tests are completed; step S25 is executed if all physical blocks are tested, and step S22 is executed if all physical blocks are not tested; in the case of executing step S22, the execution may be continued according to the predetermined flow of the method for detecting the nor flash memory.
S25, clearing the test marks in the mark blocks;
s26, the detection is finished, and a corresponding detection log generation step is further included.
It should be noted that, according to the characteristics of the Nor flash memory, the data stored in the Nor flash memory after power failure is also retained, so that whether the Nor flash memory has an abnormal power failure event in the last test can be determined by determining whether the test flag in the flag block is cleared. Therefore, the method for detecting the nor flash memory in the embodiment of the invention further comprises the following steps: judging whether a test mark exists in the mark block or not when the embedded equipment is electrified and initialized; if yes, the detection of the enabling nor flash memory is forbidden, and the abnormal power-down event of the nor flash memory in the last test is prompted, so that the test special firmware burning is conducted on the nor flash memory again to finish the detection of the nor flash memory, and after the test special firmware is burned again, the test mark in the mark block is cleared. In the embodiment of the invention, the test mark in the mark block can be cleared only by re-burning the test special firmware, and any test instruction received by the firmware can not be executed before the test mark is correctly processed, so that the normal test result is prevented from being interfered by the parameter error stored in the nor flash memory.
In a specific implementation process, the detection of the test mark in the mark block and the subsequent control flow are as shown in fig. 4:
s31, powering up and initializing the embedded equipment;
s32, judging whether a mark block of the nor flash memory is provided with a test mark; steps S33 and S34 are performed if there is [ test flag ], and step S35 is performed if there is no [ test flag ];
s33, prompting errors to reproduce the test;
s34, refusing to execute if the test command is received, and prompting that the test cannot be executed;
s36, detecting normal operation nor flash memory;
and S36, ending, and executing step S36 after executing steps S33, S34 and S35.
Further, the detection method of the nor flash memory in the embodiment of the invention also provides an error insertion detection method so as to verify the effectiveness of the detection method of the nor flash memory. Specifically, the embodiment of the invention further comprises the following steps: after receiving a command of inserting errors into a specified physical block issued by a host, judging whether a target block to be detected is the specified physical block or not before performing a read-write pressure test on any target block in the nor flash memory; if yes, performing error injection on the read data of the special test data when the read operation is performed on the target block to obtain the read data of the special test data; after the current read-write pressure test is executed on the target block, whether the detection method of the current nor flash memory is effective is judged according to whether the target block is recorded as an abnormal physical block, and if the target block is recorded as the abnormal physical block, the detection method of the current nor flash memory is judged to be effective. Conversely, if the target block is not recorded as an abnormal physical block, the current detection method is proved to be invalid. The method is used for verifying the effectiveness of the method by setting a plurality of target blocks as designated physical blocks and judging whether the designated blocks are all recorded as abnormal physical blocks after the test is completed. The method for detecting the validity of the nor flash memory is flexible and high in operability, and the stability of the nor flash memory after detection is further ensured.
In a specific implementation process, a specific flow of the error injection method in the embodiment of the present invention is shown in fig. 5:
s50, starting to start to enter a nor flash memory detection mode after the embedded device is powered on;
s51, receiving a command of inserting errors into the Nth physical block issued by the host;
s52, starting the nor flash memory detection;
s53, judging whether all physical blocks are detected completely, if not, executing the step S55, and if so, executing the step S54;
s54, ending;
s55, detecting the next physical block;
s56, judging whether the current physical block is an Nth physical block, if so, executing a step S58, and if not, executing a step S57;
s57, executing the current physical block detection according to the normal flow, recording the detection result, and returning to execute the step S53 after the current physical block detection is finished;
s58, when the current physical block is executed according to the normal flow and the step S17 is detected, the read special data for testing is forcedly injected with errors; in the embodiment of the invention, the forced injection error is one or more bits in the read data which are forced to be changed when the special data for testing is read;
s59, recording the test result of the Nth physical block, and returning to execute the step S53 after the recording is finished.
In the embodiment of the invention, after the nor flash memory detection is completed, the validity of the method is verified by judging whether the Nth physical block is recorded as an abnormal physical block.
For the purposes of simplicity of explanation, the methodologies are shown and described as a series of acts, it is to be understood and appreciated by one of ordinary skill in the art that the methodologies are not limited by the order of acts, as some acts may, in accordance with the methodologies, take place in other order or concurrently. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
Fig. 6 schematically shows a structural diagram of a detection device of a nor flash memory according to an embodiment of the present invention. Referring to fig. 6, the detection apparatus for a nor flash memory according to the embodiment of the present invention specifically includes a detection mode control module 601 and a target block test module 602, where:
the detection mode control module 601 is configured to control, in a production test stage, an embedded device including a nor flash memory to run pre-burned test proprietary firmware after power-on, so that the embedded device enters a nor flash memory detection mode;
the target block test module 602 is configured to perform a read-write pressure test on physical blocks to be detected in the nor flash memory one by one in a nor flash memory detection mode, so as to detect abnormal physical blocks in the nor flash memory;
the detection mode control module 601 is further configured to exit the nor flash detection mode and generate a detection log according to the detected abnormal physical blocks after all physical blocks in the nor flash are tested.
Further, the target block testing module 602 specifically includes:
the target block data processing unit is used for selecting one physical block to be detected in the nor flash memory as a target block and writing original data in the target block into the SRAM of the embedded equipment;
a writing unit, configured to write first test dedicated data in a preset test data set into the target block;
a reading unit, configured to perform a read operation on the target block to obtain read data of the first test-specific data;
the comparison unit is used for comparing whether the first test special data is consistent with the read data of the first test special data or not;
and the log record control unit is used for recording the target block as an abnormal physical block if the first test special data and the read data of the first test special data are inconsistent, and sequentially selecting the next physical block to be detected in the nor flash memory as a new target block according to a preset test execution sequence so as to carry out read-write pressure test on the new target block.
Further, the target block testing module 602 is further configured to execute a read-write pressure test for the target block for a preset number of times according to different test-specific data in a preset test data set if the first test-specific data is consistent with the read data of the first test-specific data; and if any one of the test special data and the read data of the test special data are inconsistent in the repeatedly executed read-write pressure test, recording the target block as an abnormal physical block.
Further, the writing unit is further configured to write original data of a target block written in the SRAM in advance back to the target block if the target block is not recorded as an abnormal physical block;
the reading unit is further used for performing a reading operation on the target block to obtain the read data of the original data, and comparing whether the original data of the target block and the read data of the original data are consistent;
the log record control unit is further configured to record the target block as an abnormal physical block if the original data of the target block is inconsistent with the read data of the original data, and sequentially select a next physical block to be detected in the nor flash memory as a new target block according to a preset test execution sequence to perform a read-write pressure test on the new target block.
Further, the detecting device for the nor flash memory according to the embodiment of the invention further includes:
the physical block judging module is used for judging whether the target block to be detected is the designated physical block or not before any target block in the nor flash memory is subjected to read-write pressure test after receiving a command of inserting errors into the designated physical block issued by the host;
the error injection module is used for performing error injection on the read data of the special test data when the read operation is performed on the target block to obtain the read data of the special test data if the error injection module is used for performing the read operation on the target block to obtain the read data of the special test data;
and the validity judging module is used for judging whether the detection method of the current nor flash memory is valid according to whether the target block is recorded as an abnormal physical block after the current read-write pressure test is executed on the target block, and judging that the detection method of the current nor flash memory is valid if the target block is recorded as the abnormal physical block.
Further, the detecting device for the nor flash memory according to the embodiment of the invention further includes:
the marking block designating module is used for selecting any physical block in the nor flash memory as a marking block before the physical blocks to be detected in the nor flash memory are subjected to read-write pressure test one by one;
the mark writing module is used for writing a test mark in the mark block so as to identify that the nor flash memory is in a read-write pressure test;
the mark clearing module is used for clearing test marks in the mark blocks after all physical blocks to be detected in the nor flash memory are detected; the marked block is not used as a physical block to be detected of the nor flash memory.
Further, the detecting device for the nor flash memory according to the embodiment of the invention further includes:
the power-off signal detection module is used for judging whether a power-off signal is detected after the read-write pressure test is carried out on any physical block to be detected in the nor flash memory once;
the power-down recording module is used for stopping detection of the nor flash memory if the power-down signal is detected, and recording the abnormal power-down event in the detection log;
and the mark clearing module is also used for clearing the test mark in the mark block if the power-off signal is not detected after the read-write pressure test is performed on all the physical blocks to be detected in the nor flash memory.
Further, the detecting device for the nor flash memory according to the embodiment of the invention further includes:
the mark judging module is used for judging whether a test mark exists in the mark block or not when the embedded equipment is electrified and initialized;
the target block test module 602 is further configured to prohibit enabling detection of the nor flash memory and prompt that an abnormal power failure event occurs in the nor flash memory in the last test if the target block test module exists, so as to re-burn the test-specific firmware of the nor flash memory to complete detection of the nor flash memory, and clear the test flag in the flag block after re-burning the test-specific firmware.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
Further, an embodiment of the present invention also provides an embedded device, where the embedded device includes a storage controller, where the storage controller includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the steps of the method as described above when the processor executes the program. For example, steps S1 to S3 shown in fig. 1. Alternatively, the processor may implement the functions of each module/unit in the above-described embodiment of the detecting device for nor flash memory when executing the computer program, for example, the detecting mode control module 601 and the target block test module 602 shown in fig. 6.
According to the method and device for detecting the nor flash memory and the embedded equipment, provided by the embodiment of the invention, in the production test stage, the embedded equipment containing the nor flash memory is controlled to run pre-burnt special test firmware after being electrified so that the embedded equipment enters a nor flash memory detection mode; in a nor flash memory detection mode, performing read-write pressure test on physical blocks to be detected in the nor flash memory one by one so as to detect abnormal physical blocks in the nor flash memory; and after all physical blocks in the nor flash memory are tested, exiting the nor flash memory detection mode and generating a detection log according to the detected abnormal physical blocks. The invention automatically realizes the nor flash memory detection of the embedded equipment in the production test stage by burning the special firmware in the embedded equipment, thereby not only simplifying the detection flow and improving the detection efficiency, but also avoiding the problems that the performance such as the starting time of the equipment is influenced by the detection during the normal power-on use period of the embedded equipment.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, any of the claimed embodiments can be used in any combination.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for detecting nor flash memory, the method comprising:
in the production test stage, controlling the embedded equipment containing the nor flash memory to run pre-burnt test special firmware after power-on so as to enable the embedded equipment to enter a nor flash memory detection mode;
in a nor flash memory detection mode, performing read-write pressure test on physical blocks to be detected in the nor flash memory one by one so as to detect abnormal physical blocks in the nor flash memory;
and after all physical blocks in the nor flash memory are tested, exiting the nor flash memory detection mode and generating a detection log according to the detected abnormal physical blocks.
2. The method of claim 1, wherein the performing read-write pressure test on physical blocks to be detected in the nor flash memory one by one comprises:
selecting one physical block to be detected in the nor flash memory as a target block, and writing original data in the target block into an SRAM of the embedded device;
writing first test special data in a preset test data set into the target block;
performing a read operation on the target block to obtain read data of the first test specific data;
comparing whether the read data of the first test special data is consistent with the read data of the first test special data;
if the first test special data is inconsistent with the read data of the first test special data, recording the target block as an abnormal physical block, and sequentially selecting the next physical block to be detected in the nor flash memory as a new target block according to a preset test execution sequence so as to perform a read-write pressure test on the new target block.
3. The method according to claim 2, wherein the method further comprises:
if the first test special data is consistent with the read data of the first test special data, executing the read-write pressure test for the target block for preset times according to different test special data in a preset test data set;
and if any one of the test special data and the read data of the test special data are inconsistent in the repeatedly executed read-write pressure test, recording the target block as an abnormal physical block.
4. A method according to claim 2 or 3, characterized in that the method further comprises:
if the target block is not recorded as an abnormal physical block, writing original data of the target block which is written in the SRAM in advance back to the target block;
performing a read operation on the target block to obtain read data of original data, and comparing whether the original data of the target block is consistent with the read data of the original data;
if the original data of the target block is inconsistent with the read data of the original data, recording the target block as an abnormal physical block, and sequentially selecting the next physical block to be detected in the nor flash memory as a new target block according to a preset test execution sequence to perform a read-write pressure test on the new target block.
5. The method according to claim 2, wherein the method further comprises:
after receiving a command of inserting errors into a specified physical block issued by a host, judging whether a target block to be detected is the specified physical block or not before performing a read-write pressure test on any target block in the nor flash memory;
if yes, performing error injection on the read data of the special test data when the read operation is performed on the target block to obtain the read data of the special test data;
after the current read-write pressure test is executed on the target block, whether the detection method of the current nor flash memory is effective is judged according to whether the target block is recorded as an abnormal physical block, and if the target block is recorded as the abnormal physical block, the detection method of the current nor flash memory is judged to be effective.
6. The method according to claim 1, wherein the method further comprises:
before the read-write pressure test is carried out on physical blocks to be detected in the nor flash memory one by one, any physical block is selected as a marking block in the nor flash memory;
writing a test mark in the mark block to identify that the nor flash memory is in a read-write pressure test;
after all physical blocks to be detected in the nor flash memory are detected, clearing test marks in the mark blocks; wherein,,
the marked block is not used as a physical block to be detected of the nor flash memory.
7. The method of claim 6, wherein the method further comprises:
judging whether a power-off signal is detected after performing a read-write pressure test on any physical block to be detected in the nor flash memory;
if the power-off signal is detected, stopping detecting the nor flash memory, and recording the abnormal power-off event in a detection log;
and if the power-off signal is not detected after the read-write pressure test is performed on all the physical blocks to be detected in the nor flash memory, clearing the test mark in the mark block.
8. The method of claim 6, wherein the method further comprises:
judging whether a test mark exists in the mark block or not when the embedded equipment is electrified and initialized;
if yes, the detection of the enabling nor flash memory is forbidden, and the abnormal power-down event of the nor flash memory in the last test is prompted, so that the test special firmware burning is conducted on the nor flash memory again to finish the detection of the nor flash memory, and after the test special firmware is burned again, the test mark in the mark block is cleared.
9. A device for detecting nor flash memory, the device comprising:
the detection mode control module is used for controlling the embedded equipment containing the nor flash memory to run pre-burnt special test firmware after power-on in the production test stage so as to enable the embedded equipment to enter a nor flash memory detection mode;
the target block testing module is used for carrying out read-write pressure test on physical blocks to be detected in the nor flash memory one by one in a nor flash memory detection mode so as to detect abnormal physical blocks in the nor flash memory;
and the detection mode control module is also used for exiting the detection mode of the nor flash memory and generating a detection log according to the detected abnormal physical blocks after all physical blocks in the nor flash memory are tested.
10. An embedded device, characterized in that the embedded device comprises a controller, the controller comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method according to any of claims 1-8 when the computer program is executed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310611984.6A CN116564398B (en) | 2023-05-26 | 2023-05-26 | Method and device for detecting nor flash memory and embedded equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310611984.6A CN116564398B (en) | 2023-05-26 | 2023-05-26 | Method and device for detecting nor flash memory and embedded equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116564398A true CN116564398A (en) | 2023-08-08 |
| CN116564398B CN116564398B (en) | 2023-12-22 |
Family
ID=87491462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310611984.6A Active CN116564398B (en) | 2023-05-26 | 2023-05-26 | Method and device for detecting nor flash memory and embedded equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116564398B (en) |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070021963A1 (en) * | 2003-03-04 | 2007-01-25 | Netac Technology Co., Ltd | Data management method for slash memory medium |
| JP2007241618A (en) * | 2006-03-08 | 2007-09-20 | Matsushita Electric Ind Co Ltd | Nonvolatile storage device and its write determination method |
| US20100275094A1 (en) * | 2009-04-28 | 2010-10-28 | Panasonic Corporation | Nonvolatile memory device and nonvolatile memory controller |
| CN103854704A (en) * | 2012-12-03 | 2014-06-11 | 上海斐讯数据通信技术有限公司 | Automatic detection method and automatic detection device of flash memory bad block |
| CN104991137A (en) * | 2015-06-30 | 2015-10-21 | 小米科技有限责任公司 | Equipment testing method and device |
| CN108682442A (en) * | 2018-05-23 | 2018-10-19 | 武汉忆数存储技术有限公司 | A kind of different encapsulation flash chip on-line testing and sorting technique and test system |
| US20190130990A1 (en) * | 2017-11-02 | 2019-05-02 | National Tsing Hua University | Method and system for testing firmware of solid-state storage device, and electronic apparatus |
| CN110993013A (en) * | 2019-11-13 | 2020-04-10 | 深圳佰维存储科技股份有限公司 | eMMC (enhanced multimedia card) volume production test method and device |
| CN111400162A (en) * | 2019-01-02 | 2020-07-10 | 阿里巴巴集团控股有限公司 | Test method and test system |
| CN114822669A (en) * | 2022-06-29 | 2022-07-29 | 北京得瑞领新科技有限公司 | Flash memory error injection system, solid-state storage device and test system |
| CN115101116A (en) * | 2022-07-27 | 2022-09-23 | 山东云海国创云计算装备产业创新中心有限公司 | Welding abnormity detection method, device, equipment and medium for solid state disk storage particles |
| CN115547395A (en) * | 2022-08-31 | 2022-12-30 | 深圳大普微电子科技有限公司 | Test method, system and flash memory device |
| CN115954042A (en) * | 2022-12-20 | 2023-04-11 | 珠海妙存科技有限公司 | nand flash power-down test device, nand flash power-down test method and storage medium |
-
2023
- 2023-05-26 CN CN202310611984.6A patent/CN116564398B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070021963A1 (en) * | 2003-03-04 | 2007-01-25 | Netac Technology Co., Ltd | Data management method for slash memory medium |
| JP2007241618A (en) * | 2006-03-08 | 2007-09-20 | Matsushita Electric Ind Co Ltd | Nonvolatile storage device and its write determination method |
| US20100275094A1 (en) * | 2009-04-28 | 2010-10-28 | Panasonic Corporation | Nonvolatile memory device and nonvolatile memory controller |
| CN103854704A (en) * | 2012-12-03 | 2014-06-11 | 上海斐讯数据通信技术有限公司 | Automatic detection method and automatic detection device of flash memory bad block |
| CN104991137A (en) * | 2015-06-30 | 2015-10-21 | 小米科技有限责任公司 | Equipment testing method and device |
| US20190130990A1 (en) * | 2017-11-02 | 2019-05-02 | National Tsing Hua University | Method and system for testing firmware of solid-state storage device, and electronic apparatus |
| CN108682442A (en) * | 2018-05-23 | 2018-10-19 | 武汉忆数存储技术有限公司 | A kind of different encapsulation flash chip on-line testing and sorting technique and test system |
| CN111400162A (en) * | 2019-01-02 | 2020-07-10 | 阿里巴巴集团控股有限公司 | Test method and test system |
| CN110993013A (en) * | 2019-11-13 | 2020-04-10 | 深圳佰维存储科技股份有限公司 | eMMC (enhanced multimedia card) volume production test method and device |
| CN114822669A (en) * | 2022-06-29 | 2022-07-29 | 北京得瑞领新科技有限公司 | Flash memory error injection system, solid-state storage device and test system |
| CN115101116A (en) * | 2022-07-27 | 2022-09-23 | 山东云海国创云计算装备产业创新中心有限公司 | Welding abnormity detection method, device, equipment and medium for solid state disk storage particles |
| CN115547395A (en) * | 2022-08-31 | 2022-12-30 | 深圳大普微电子科技有限公司 | Test method, system and flash memory device |
| CN115954042A (en) * | 2022-12-20 | 2023-04-11 | 珠海妙存科技有限公司 | nand flash power-down test device, nand flash power-down test method and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116564398B (en) | 2023-12-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7050343B2 (en) | Built-in testing methodology in flash memory | |
| US7904637B2 (en) | Information processing apparatus, lifetime monitoring method and program for monitoring lifetime of storage device including flash memory | |
| US5767647A (en) | Non-volatile memory controlling apparatus and applications of the same to electronic computer peripheral equipment | |
| KR100881025B1 (en) | Apparatus and method for managing data security | |
| JP2002351685A (en) | Data updating method and controller for nonvolatile memory | |
| WO2007021962A2 (en) | Methods and apparatus for programming secure data into programmable and irreversible cells | |
| CN105469832A (en) | Integrated circuit and memory self test method for integrated circuit | |
| CN112328358A (en) | Dual-system starting method based on virtual machine and storage medium | |
| CN117219146A (en) | Safety start-oriented on-chip efuse read-write control device and method | |
| EP1394810B1 (en) | Nonvolatile storage device and self-repair method for the same | |
| CN116564398B (en) | Method and device for detecting nor flash memory and embedded equipment | |
| CN111897685A (en) | Method and device for checking data in power failure, storage medium and electronic equipment | |
| CN110875078A (en) | Processing system and method for abnormal power failure of storage device | |
| CN114895845A (en) | EMmC data storage control method and embedded mainboard | |
| US6917220B2 (en) | Semiconductor device and a method for checking state transition thereof | |
| JP2868001B1 (en) | Disk array device control method and disk array device | |
| CN110674038A (en) | Method and device for classifying error information in software test | |
| CN109101279B (en) | Compatibility starting method of multi-version system | |
| JP3431582B2 (en) | Desk storage device and processing method when hang-up occurs applied to the device | |
| CN108920210A (en) | A kind of method, system and the associated component of load store control software | |
| JPH1050005A (en) | Method for managing defect on optical disk and device therefor | |
| CN109215724A (en) | The method and device of memory automatic detection and rehabilitation | |
| CN113345505B (en) | Flash memory and working method thereof | |
| CN107305790B (en) | Self-testing method and device of non-volatile memory | |
| JPH10333996A (en) | Recording/reproducing device and its method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |