CN116578448A - Chip power-down log processing method and system - Google Patents
Chip power-down log processing method and system Download PDFInfo
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- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2231—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test interrupt circuits
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Abstract
The embodiment of the application provides a chip power-down log processing method and a system, wherein the system comprises an upper computer, a host end and a chip equipment end, the upper computer is connected with at least one host end, and the host end is connected with the chip equipment end; the method comprises the steps that an upper computer sends power-down testing commands to a plurality of host computers, and the host computers forward the power-down testing commands to a chip device; executing a power-down test command by the chip equipment end and generating a power-down operation to generate a power-down log; the upper computer performs overall analysis on the power-down logs of the plurality of chip equipment ends to obtain log analysis results; the upper computer sends power-down test commands to a plurality of host terminals simultaneously or respectively without operating each host terminal so as to perform power-down test of the corresponding chip equipment terminal, thereby improving the efficiency.
Description
Technical Field
The embodiment of the application relates to the field of memories, in particular to a chip power-down log processing method and system.
Background
At present, when a memory chip performs a program-erase operation and finds that an error occurs in a memory cell, the memory chip usually completes the current operation and records the addresses of the defective memory cells, and then performs a replacement operation on those memory cells.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The application aims to solve at least one of the technical problems existing in the related art to a certain extent, and the embodiment of the application provides a chip power failure log processing method and a system.
An embodiment of a first aspect of the present application provides a chip power-down log processing method, which is applied to a chip power-down log processing system, where the chip power-down log processing system includes an upper computer, a host end and a chip device end, the upper computer is connected with at least one host end, and the host end is connected with the chip device end;
the chip power-down log processing method comprises the following steps:
transmitting power-down commands to a plurality of host terminals simultaneously or respectively through the upper computer, wherein the power-down commands are used for controlling power-down scenes and power-down moments of the chip equipment terminals;
forwarding a power-down test command to the chip equipment end through the host end;
executing the power-down test command through the chip equipment end and generating a power-down operation to generate a power-down log;
forwarding the power-down log to the host through the chip equipment end;
the power-down log is sent to the upper computer through the host end;
and carrying out overall analysis on the power-down logs of the chip equipment ends through the upper computer to obtain log analysis results.
According to certain embodiments of the first aspect of the present application, the chip device side includes a NAND Flash module, and the NAND Flash module is raw NAND; the step of executing the power-down test command by the chip equipment end and generating a power-down operation to generate a power-down log comprises the following steps:
programming a target flash memory block and/or a target data page in the raw NAND according to a first power-down test case in the power-down test command, wherein the first power-down test case comprises preset power-down time and addresses of the target flash memory block and/or the target data page;
and in the programming process, generating a power-down log by carrying out power-down operation on the chip equipment end according to a preset power-down time.
In some embodiments of the first aspect of the present application, the method for processing a power-down log of a chip further includes:
when the chip equipment end is detected to complete the power-down test, the chip equipment end is powered on again;
and sending a first read command to the raw NAND through the upper computer and the host computer to carry out read test on the target flash memory block and/or the target data page.
According to certain embodiments of the first aspect of the present application, the chip device side includes a NAND Flash module, which is a NAND chip including a Flash memory controller; the step of executing the power-down test command by the chip equipment end and generating a power-down operation to generate a power-down log comprises the following steps:
transmitting a second power-down test case in the power-down test command to the flash memory controller to instruct the flash memory controller to run the second power-down test case, wherein the second power-down test case comprises preset power-down time and an address of a target flash memory block and/or a target data page;
and when a power-down notification returned by the flash memory controller according to a preset power-down time is received, generating a power-down log for the power-down operation of the chip equipment terminal.
In some embodiments of the first aspect of the present application, the method for processing a power-down log of a chip further includes:
when the chip equipment end is detected to complete the power-down test, the chip equipment end is powered on again;
and sending a second read command to the flash memory controller through the upper computer and the host end so as to instruct the flash memory controller to carry out read test on the target flash memory block and/or the target data page.
An embodiment of the second aspect of the present application is a chip power-down log processing system, which includes an upper computer, a host end and a chip device end, wherein the upper computer is connected with at least one of the host ends, and the host end is connected with the chip device end;
the chip device side is configured to: executing the power-down command and generating a power-down operation to generate a power-down log, and forwarding the power-down log to the host end;
the upper computer is configured to: simultaneously or respectively sending power failure test commands to a plurality of host terminals, and carrying out overall analysis on power failure logs of a plurality of chip equipment terminals to obtain log analysis results;
the host side is configured to: forwarding a power-down command to the chip equipment end and forwarding a power-down log to the host end;
the power-down command is used for controlling a power-down scene and power-down time of the chip equipment end.
According to certain embodiments of the second aspect of the present application, the chip device side includes a NAND Flash module, and the NAND Flash module is raw NAND;
the chip device side is further configured to: programming a target flash memory block and/or a target data page in the raw NAND according to a first power-down test case in the power-down test command; when power is lost in the programming process, generating a power-down log;
the first power-down test case comprises preset power-down time and addresses of target flash memory blocks and/or target data pages.
In certain embodiments of the second aspect of the present application, the host computer and the host side are further configured to: when the chip equipment end is detected to complete the power-down test, the chip equipment end is powered on again; and sending a first read command to the raw NAND to perform read test on the target flash memory block and/or the target data page.
In some embodiments of the second aspect of the present application, the chip device side includes a NAND Flash module, the NAND Flash module being a NAND chip including a Flash controller; the chip device side is further configured to: transmitting a second power down test case in the power down test command to the flash memory controller to instruct the flash memory controller to run the second power down test case; sending a power-down notification according to a preset power-down time through the flash memory controller, and generating a power-down log in response to power-down operation;
the second power-down test case comprises preset power-down time and addresses of target flash memory blocks and/or target data pages.
In certain embodiments of the second aspect of the present application, the host computer and the host side are further configured to: when the chip equipment end is detected to complete the power-down test, the chip equipment end is powered on again; and sending a second read command to the flash memory controller to instruct the flash memory controller to perform a read test on the target flash memory block and/or the target data page.
The scheme has at least the following beneficial effects: the upper computer sends power-down test commands to a plurality of host terminals simultaneously or respectively without operating each host terminal so as to perform power-down test of the corresponding chip equipment terminal, thereby improving the efficiency. In addition, the upper computer can be combined with the power-down logs of a plurality of chip equipment ends to carry out overall analysis; and each host computer end does not need to wait for completing all power-down tests on the chip equipment end and then analyzes the power-down tests, so that the analysis can be performed preferentially according to the power-down logs of the completed partial power-down tests, the analysis while testing is realized, and the analysis efficiency and the analysis effect of the power-down tests are improved.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and do not limit the application.
FIG. 1 is a schematic diagram of a chip power down log processing system, wherein a chip device side includes raw NAND;
FIG. 2 is a schematic diagram of a chip power down log processing system, wherein the chip device side includes a Flash controller and a NAND Flash;
FIG. 3 is a step diagram of a method for processing a chip power down log;
FIG. 4 is a step diagram of a power down test step for a chip device side including raw NAND;
FIG. 5 is a step diagram of a power down test step for a chip device side including a Flash controller and NAND Flash;
FIG. 6 is a step diagram for a read step for a chip device side including raw NAND;
fig. 7 is a step diagram of a read test step for a chip device side including a Flash controller and NAND Flash.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It should be noted that although functional block division is performed in a device diagram and a logic sequence is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart. The terms first, second and the like in the description, in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
Embodiments of the present application will be further described below with reference to the accompanying drawings.
For the power-down test of the Flash memory chip, a Host-Device can be constructed as a test platform, and the power-down test of the Host to the Device is realized by utilizing the communication between the Host and the Device when the NAND Flash is in a programming state. However, the Host and the Device are connected in a one-to-one correspondence, and when the power-down test is performed, each Host needs to be operated to perform the power-down test of the corresponding Device, which is relatively inefficient.
In order to solve the above problems, the embodiments of the present application provide a chip power-down log processing system, where the chip power-down log processing system includes an upper computer, a host end and a chip device end, the upper computer is connected with at least one host end, and the host end is connected with the chip device end.
The chip equipment end comprises a NAND Flash module. The NAND Flash module is one type of Flash memory, which belongs to a nonvolatile memory device (Non-volatile Memory Device), and latches charges through a Floating Gate (Floating Gate) based on a Floating Gate transistor design, and electrons reaching the Gate are trapped even after removing a voltage because the Floating Gate is electrically isolated. Data is stored in such devices without being lost even if power is lost.
The NAND Flash module is raw NAND or a NAND chip containing a Flash memory controller.
Referring to fig. 1, raw Flash refers to an original NAND Flash memory chip that has not been processed by a controller or an operating system. It is simply the NAND chip itself, with no additional control logic to manage and process the data. The original NAND Flash chip needs to access and manage the stored data by a main control chip and related software. Thus, using the raw NAND Flash chip requires the use of specific chip read-write controllers that can interact with the operating system level software to better manage data and storage. The raw NAND Flash chip is typically used in advanced embedded systems because it requires precise control in order to fully exploit its excellent memory performance.
Referring to fig. 2, a NAND chip including a flash memory controller includes a flash memory controller and a memory unit, the flash memory controller determining a read-write speed and a data processing capability of the chip. The main functions of the controller are decoding read-write instructions, managing page turning, bad block management, ECC (Error Correction Code) error correction and the like. The controller is also responsible for data transfer with the I/O interface of the system. Memory cells are typically composed of a series of transistors. The state of the transistor may be represented as high or low so that binary data may be stored. Each memory cell has a plurality of memory cells therein, such that each memory cell can hold a plurality of bits.
The chip power-down log processing system improves the efficiency by applying the following chip power-down log processing method.
Referring to fig. 3, the chip power down log processing method includes, but is not limited to, the following steps:
step S100, simultaneously or respectively sending power-down test commands to a plurality of host terminals through an upper computer;
step S200, forwarding a power-down test command to a chip device end through a host end;
step S300, executing a power-down test command through a chip device end and generating a power-down operation to generate a power-down log;
step S400, forwarding a power-down log to a host computer end through a chip equipment end;
step S500, a power-down log is sent to an upper computer through a host end;
and S600, carrying out overall analysis on the power-down logs of the plurality of chip equipment ends through the upper computer to obtain log analysis results.
The power-down command is used for controlling a power-down scene and power-down time of the chip equipment end.
In this embodiment, the power-down command may be sent to multiple Host terminals simultaneously or separately by the Host computer, without operating each Host to perform the power-down test of the corresponding Device, thereby improving efficiency.
In addition, the upper computer can be combined with the power-down logs of a plurality of chip equipment ends to carry out overall analysis; and each host computer end does not need to wait for completing all power-down tests on the chip equipment end and then analyzes the power-down tests, so that the analysis can be performed preferentially according to the power-down logs of the completed partial power-down tests, the analysis while testing is realized, and the analysis efficiency and the analysis effect of the power-down tests are improved.
It can be understood that the upper computer is an electronic computer, and can be a desktop computer, a notebook computer, a small notebook computer, a tablet computer, an ultrabook and the like; the intelligent electronic device can run according to a program and automatically process mass data at high speed.
The Host side is a Host, which may be an application processor (Application Processor Unit, APU) generally and is responsible for powering devices and implementing inter-Device communication or driving NAND Flash (if a Device is a raw NAND, the Host is required to drive NAND Flash, and if the Device is a module embedded with NAND Flash, the Host is not required to drive NAND Flash, and instead the Host sends instructions to the Flash controller).
The chip Device is a Device, which refers to a raw NAND or a module embedded with a NAND Flash and a Flash controller, such as eMMC, UFS, SSD, and is mainly responsible for communicating with a Host or driving the NAND Flash (except raw NAND, which is directly driven by the Host to perform power-down test).
The upper computer transmits the power-down test command to the plurality of host terminals simultaneously or respectively, and the power-down test command is forwarded to the chip equipment terminals through the host terminals, so that the power-down test is performed by simultaneously controlling the plurality of chip equipment terminals through the upper computer, and the test efficiency is improved.
Referring to fig. 4, when the NAND Flash module is raw NAND, a power down command is executed by a chip device side and a power down operation occurs to generate a power down log, including but not limited to the following steps:
step S311, programming a target flash memory block and/or a target data page in the raw NAND according to a first power-down test case in a power-down test command;
step S312, generating a power-down log by generating a power-down operation to the chip equipment end according to a preset power-down time in the programming process.
The first power-down test case comprises preset power-down time and addresses of target flash memory blocks and/or target data pages.
In this embodiment, for the raw NAND, the Host directly sends a power-down test command to perform a power-down test, designates a target physical block or designates a target page, then writes preset test data through a programming operation, directly powers down the raw NAND during the programming operation, thereby completing a power-down test, and then the Host continues to power up the Device and repeatedly performs a program-power-down process until the whole power-down test is completed.
Referring to fig. 5, when the NAND Flash module is a NAND chip including a Flash memory controller, a power-down command is executed by a chip device side and a power-down operation occurs to generate a power-down log, including, but not limited to, the following steps:
step S321, a second test-down case in the test-down command is sent to the flash memory controller to instruct the flash memory controller to run the second test-down case;
step S322, when a power-down notification returned by the flash memory controller according to a preset power-down time is received, a power-down operation is performed on the chip equipment end to generate a power-down log.
The second power-down test case comprises preset power-down time and addresses of target flash memory blocks and/or target data pages.
In this embodiment, for a NAND chip including a flash memory controller, an upper computer indirectly executes a power-down test by sending a power-down command through a Host end, a Host instructs a Device to execute a predetermined power-down test process, the flash memory controller performs a programming operation on a target physical block or a designated target page internally according to the power-down command, the flash memory controller controls a power-down timing, and notifies the Host of power-down when the power-down timing is reached, so that the Host does not directly execute the power-down test.
Compared with the scheme of the current power-down test, the method has the advantages that through the cooperation among the upper computer, the host computer and the chip equipment, operations such as calculation and conversion of an internal complex software layer are not needed, delay influence is greatly reduced, and the flexibility of selection of power-down time is improved.
It can be understood that the power-down test command and the like in the embodiment of the application are not standard protocol commands corresponding to the NAND Flash, and the standard protocol commands obviously cannot realize the power-down test in the scheme, so that the embodiment of the application can specify the target physical block or the target page through the private command by adjusting the drive of the NAND Flash, and the number of commands sent by the Host is small; for the NAND chip comprising the flash memory controller, the private command directly indicates the flash memory controller to control the power-down time, but not the Host directly controls, the Device runs in a non-firmware environment, no background operation is caused, the response speed is improved, and therefore the test efficiency is greatly improved.
It will be appreciated that the Host Device includes an application processor that is communicatively coupled to and powers the Device. That is, the power-off operation is completed by the Host.
Different power-down time can be set, for example, the preset power-down time is the time when the NAND Flash module is in the busy state of the programming operation, or the time when the NAND Flash module is in the busy state of the programming operation and is delayed for a period of time. The programming states of the NAND Flash are divided into a Ready state and a Busy state, the power-down time is determined by a Host in the traditional power-down test process, and the hit rate is not high enough because whether the NAND Flash is in the Ready state or the Busy state at the current moment (only the power-down test is effective in the Busy state) is unclear. The Host is directly connected with the raw NAND or the flash memory controller is used for controlling the power-down time, so that the current programming state can be clearly known, and the problem of insufficient hit rate can be avoided. Based on this, the embodiment of the application can also set a time delay (for example, 100 microseconds) after the power-down time as the actual power-down time, then inform Host to power down the Device, and by specifying the time delay parameter, the NAND Flash can completely power down at different specific times of programming.
Referring to fig. 6, when the NAND Flash module is raw NAND, the chip power-down log processing method further includes:
step S331, when detecting that the chip equipment end completes the power-down test, powering up the chip equipment end again;
in step S332, the host computer and the host computer send the first read command to the raw NAND to perform the read test on the target flash memory block and/or the target data page.
Referring to fig. 7, when the NAND Flash module is a NAND chip including a Flash controller, the chip power-down log processing method further includes:
step S341, when the chip equipment end is detected to complete the power-down test, powering up the chip equipment end again;
in step S342, a second read command is sent to the flash memory controller through the host and the host to instruct the flash memory controller to perform a read test on the target flash memory block and/or the target data page.
And (3) completing power-down of one target physical block and/or target page each time, then the Host re-powers down the Device power-up next time until the power-down times are met or all addresses in the NAND Flash are traversed. And then, executing a reading test, so that the Device reads information such as data of a target physical block and/or a target page of the NAND Flash, threshold voltage distribution and the like, and further intuitively observing whether the NAND Flash has abnormal data loss caused by power failure.
In the power failure test process, a power failure log is generated at the chip equipment end.
The chip equipment end sends a power-down log to the host end; the host receives the power-down log sent by the chip equipment end and sends the power-down log to the upper computer; the upper computer receives power-down logs of a plurality of chip equipment ends sent by a plurality of host computer ends, and performs overall analysis by combining the power-down logs of the plurality of chip equipment ends to obtain log analysis results.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the application, the scope of which is defined by the claims and their equivalents.
While the preferred embodiment of the present application has been described in detail, the present application is not limited to the embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present application, and the equivalent modifications or substitutions are intended to be included in the scope of the present application as defined in the appended claims.
Claims (10)
1. The chip power-down log processing method is characterized by being applied to a chip power-down log processing system, wherein the chip power-down log processing system comprises an upper computer, a host end and a chip equipment end, the upper computer is connected with at least one host end, and the host end is connected with the chip equipment end;
the chip power-down log processing method comprises the following steps:
transmitting power-down commands to a plurality of host terminals simultaneously or respectively through the upper computer, wherein the power-down commands are used for controlling power-down scenes and power-down moments of the chip equipment terminals;
forwarding a power-down test command to the chip equipment end through the host end;
executing the power-down test command through the chip equipment end and generating a power-down operation to generate a power-down log;
forwarding the power-down log to the host through the chip equipment end;
the power-down log is sent to the upper computer through the host end;
and carrying out overall analysis on the power-down logs of the chip equipment ends through the upper computer to obtain log analysis results.
2. The method for processing the chip power-down log according to claim 1, wherein the chip device side comprises a NAND Flash module, and the NAND Flash module is raw NAND; the step of executing the power-down test command by the chip equipment end and generating a power-down operation to generate a power-down log comprises the following steps:
programming a target flash memory block and/or a target data page in the raw NAND according to a first power-down test case in the power-down test command, wherein the first power-down test case comprises preset power-down time and addresses of the target flash memory block and/or the target data page;
and in the programming process, generating a power-down log by carrying out power-down operation on the chip equipment end according to a preset power-down time.
3. The method for processing a chip power down log according to claim 2, further comprising:
when the chip equipment end is detected to complete the power-down test, the chip equipment end is powered on again;
and sending a first read command to the raw NAND through the upper computer and the host computer to carry out read test on the target flash memory block and/or the target data page.
4. The method for processing the chip power-down log according to claim 1, wherein the chip device side comprises a NAND Flash module, and the NAND Flash module is a NAND chip comprising a Flash controller; the step of executing the power-down test command by the chip equipment end and generating a power-down operation to generate a power-down log comprises the following steps:
transmitting a second power-down test case in the power-down test command to the flash memory controller to instruct the flash memory controller to run the second power-down test case, wherein the second power-down test case comprises preset power-down time and an address of a target flash memory block and/or a target data page;
and when a power-down notification returned by the flash memory controller according to a preset power-down time is received, generating a power-down log for the power-down operation of the chip equipment terminal.
5. The method for processing a chip power down log according to claim 4, further comprising:
when the chip equipment end is detected to complete the power-down test, the chip equipment end is powered on again;
and sending a second read command to the flash memory controller through the upper computer and the host end so as to instruct the flash memory controller to carry out read test on the target flash memory block and/or the target data page.
6. The chip power-down log processing system is characterized by comprising an upper computer, a host computer end and a chip equipment end, wherein the upper computer is connected with at least one host computer end, and the host computer end is connected with the chip equipment end;
the chip device side is configured to: executing the power-down command and generating a power-down operation to generate a power-down log, and forwarding the power-down log to the host end;
the upper computer is configured to: simultaneously or respectively sending power failure test commands to a plurality of host terminals, and carrying out overall analysis on power failure logs of a plurality of chip equipment terminals to obtain log analysis results;
the host side is configured to: forwarding a power-down command to the chip equipment end and forwarding a power-down log to the host end;
the power-down command is used for controlling a power-down scene and power-down time of the chip equipment end.
7. The chip power down log processing system according to claim 6, wherein the chip device side comprises a NAND Flash module, the NAND Flash module being raw NAND;
the chip device side is further configured to: programming a target flash memory block and/or a target data page in the raw NAND according to a first power-down test case in the power-down test command; when power is lost in the programming process, generating a power-down log;
the first power-down test case comprises preset power-down time and addresses of target flash memory blocks and/or target data pages.
8. The system of claim 7, wherein the host computer and the host side are further configured to: when the chip equipment end is detected to complete the power-down test, the chip equipment end is powered on again; and sending a first read command to the raw NAND to perform read test on the target flash memory block and/or the target data page.
9. The chip power down log processing system according to claim 6, wherein the chip device side comprises a NAND Flash module, the NAND Flash module being a NAND chip comprising a Flash controller; the chip device side is further configured to: transmitting a second power down test case in the power down test command to the flash memory controller to instruct the flash memory controller to run the second power down test case; sending a power-down notification according to a preset power-down time through the flash memory controller, and generating a power-down log in response to power-down operation;
the second power-down test case comprises preset power-down time and addresses of target flash memory blocks and/or target data pages.
10. The system of claim 9, wherein the host computer and the host side are further configured to: when the chip equipment end is detected to complete the power-down test, the chip equipment end is powered on again; and sending a second read command to the flash memory controller to instruct the flash memory controller to perform a read test on the target flash memory block and/or the target data page.
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| US20230064884A1 (en) * | 2021-08-31 | 2023-03-02 | Yangtze Memory Technologies Co., Ltd. | Power-down test of firmware of a memory system |
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