CN115865046B

CN115865046B - Butterworth low-pass filtering method and filter based on FPGA

Info

Publication number: CN115865046B
Application number: CN202310113232.7A
Authority: CN
Inventors: 徐徐; 汪许苗树; 杨世飞; 孙磊; 邹小勇; 刘宗斌
Original assignee: Nanjing Chaos Data Technology Co ltd
Current assignee: Nanjing Chaos Data Technology Co ltd
Priority date: 2023-02-15
Filing date: 2023-02-15
Publication date: 2023-05-02
Anticipated expiration: 2043-02-15
Also published as: CN115865046A

Abstract

The invention discloses a Butterworth low-pass filtering method and a filter based on an FPGA, wherein the method comprises the following steps: the front end and the rear end of the original data respectively extend a plurality of points; filtering for the first time; turning over the filtering result; filtering for the second time; turning over again, wherein the obtained data is the data of the original data after Butterworth low-pass filtering; when the array is turned over, a reverse writing and forward reading mode is adopted in the FPGA, namely: and writing from the end position of the memory towards the direction of the memory head address, and finally sequentially reading from the memory head address. According to the invention, the memory is operated in the FPGA in a reverse write and forward read mode, no extra resource and clock period are consumed, and secondary filtering is performed in the FPGA, so that zero phase deviation can be realized; by adding the PING-PONG with the specific position trigger mode, the memory space is reasonably operated, and the head and tail waveforms are subjected to edge extension, so that marginal distortion can be eliminated.

Description

Butterworth low-pass filtering method and filter based on FPGA

Technical Field

The invention belongs to the technical field of filtering, and particularly relates to a Butterworth low-pass filtering method and a filter based on an FPGA.

Background

In digital signal processing, low-pass filtering is often required to eliminate or greatly reduce noise outside the desired frequency band, and current anti-aliasing low-pass filtering functions are often implemented in pure hardware in analog-to-digital converters (ADs). In practical use, the digital filter in the analog-to-digital converter (AD) can easily achieve above 60dB, but the cut-off frequency and the transition-band waveform are usually fixed completely by hardware, so that flexibility is lacking. The FPGA chip is internally provided with a large number of programmable gate arrays (LUTs), embedded DSPs (digital signal processors) and DRAMs or BRAMs or even plug-in DDR3 or DDR4, and various flexible and efficient parallel algorithms can be conveniently and rapidly designed to meet various technical requirements in digital signal processing. The low-pass filter based on the FPGA design can flexibly realize various filtering, so that the cost of AD hardware can be correspondingly reduced, and the low-pass filter can supplement the AD filtering of pure hardware.

Butterworth is taken as a common filter, the band of the Butterworth has maximum flatness, and the integrity of signals can be guaranteed to the greatest extent, but due to the specificity of the algorithm, problems such as marginal point distortion and phase deviation and the like are usually accompanied in the process of realizing the algorithm by the FPGA. Particularly, the problem of marginal point distortion usually adopts a head-tail discarding mode or an initial value adding mode, but the two modes are unreliable in practical application, a large amount of real data can be lost by discarding the head-tail, and the initial value adding mode is difficult to adapt to all input signals, so that Butterworth low-pass filtering is not well applied to the FPGA engineering design at the present stage.

Accordingly, it is desirable to provide an FPGA-based butterworth low-pass filter that can solve the problems of marginal waveform distortion and phase offset.

Disclosure of Invention

The invention aims to provide a Butterworth low-pass filtering method and a Butterworth low-pass filter based on an FPGA, which solve the problems of marginal waveform distortion and phase offset.

In order to achieve the above purpose, the technical scheme of the invention is as follows:

a butterworth low pass filtering method based on an FPGA, the method comprising the steps of:

1) The front end and the rear end of the original data X respectively extend a plurality of points to obtain an X array;

2) First filtering: { Y, Y } = filter (b, a, X)

3) Turning over the y array to obtain y1; turning over the Y array to obtain Y1;

4) And (3) secondary filtering: { Z, Z } = filter (b, a, Y1)

5) Turning over the z array to obtain z1, wherein z1 is data of the original data x after Butterworth low-pass filtering;

wherein b and a are Butterworth coefficients, X is data of each edge of front and rear ends of original data X, Y is data of the original data X after first filtering, Y is data of the original data X after first filtering, Z is data of the original data Y1 after second filtering, and Z is data of the original data X after second filtering;

when the array is turned over, a reverse writing and forward reading mode is adopted in the FPGA, namely: and writing from the end position of the memory towards the direction of the memory head address, and finally sequentially reading from the memory head address.

Further, the method comprises the steps of:

6) Discarding a plurality of points of each edge topology of the front end and the back end: the Z array is ignored.

Furthermore, two different memory address spaces are controlled through PING-PONG operation, head-tail waveform edge topology is carried out, namely, the points of the waveform at the moment are complemented by utilizing a plurality of points at the tail of the waveform at the last moment and the head of the waveform at the next moment, and then the points of the edge topology are abandoned.

Further, the following embodiments are:

when filtering the data in the PONG address space, waiting for writing a plurality of points which need to be extended from the first address in the PING address space to finish, and starting the filtering operation; at this time, the data of a plurality of points needing to be extended at the tail of the PING address space at the last moment are not disappeared, so that the extension is realized; when filtering the data in the PING address space, performing the same operation; and while reading the extended points in the memory, new data is not allowed to be written into the memory spaces of the points at the same time.

Further, determining the number of points to be extended according to the fixed point number precision of the coefficients b and a, the sampling rate, the anti-aliasing cutoff frequency and the frequency of the input signal;

the larger the frequency of the input signal is, the more points of marginal distortion are counted, and the more points need to be extended; the larger the anti-aliasing cut-off frequency, the more points the marginal distortion is, and the more points need to be extended.

Further, the calculation method of the point number of the marginal distortion is as follows:

under the worst condition, using all the data at each moment after filtering, namely all the data at each moment before filtering, and taking the absolute value as the error of all the sampling points; the error exceeding the threshold is a marginal distortion point.

Further, the number of points requiring the edge topology is equal to or greater than the number of points of the marginal distortion.

The Butterworth low-pass filter based on the FPGA adopts the Butterworth low-pass filtering method based on the FPGA.

Compared with the prior art, the invention has the following advantages:

1. and in the FPGA, the memory is operated in a write-down and read-forward mode, no extra resources and clock cycles are consumed, and secondary filtering is performed in the FPGA, so that zero phase deviation is realized.

2. And the memory space is reasonably operated by the way of PING-PONG plus specific position triggering, and the head and tail waveforms are subjected to edge extension, so that marginal distortion is eliminated.

3. The influence of the multivariable on the marginal distortion point is analyzed, so that the point number of the edge topology is needed when the worst condition is judged according to the actual project requirement.

Drawings

Fig. 1 is a signal diagram before and after conventional butterworth filtering;

FIG. 2 is a schematic diagram of address space before and after filtering according to the present invention;

FIG. 3 is a schematic diagram of the head-to-tail edge topology and PING-PONG operation of the present invention;

fig. 4 (a) is an example of an anti-aliasing butterworth low pass filter according to an embodiment of the invention;

FIG. 4 (b) is a graph showing the number of distortion points of the anti-aliasing Butterworth low pass filter according to the present invention as the frequency of the input signal varies;

fig. 4 (c) is a graph showing the change of the distortion point number of the anti-aliasing butterworth low pass filter according to the embodiment of the present invention according to the filter cut-off frequency.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.

The invention provides a Butterworth low-pass filtering method and a Butterworth low-pass filter based on an FPGA, which have zero phase deviation and no distortion of marginal waveforms.

1. Phase deviation phenomenon

In general, the butterworth filtering based on the FPGA has a phase deviation, and as shown in fig. 1, the peak position has a phase deviation of two points on the waveform after filtering. The left side of fig. 1 is a pre-filtered signal, and the right side is a conventional butterworth-filtered signal, and it can be seen that the data of the first 20 points after filtering are completely different from the original data, which is a marginal distortion phenomenon. In addition, it can be seen that the filtered phase is entirely deviated by 2 points (the 81 st point of the negative peak position on the figure becomes 83 rd point in the filtered position).

The solving method of the phase deviation based on the FPGA comprises the following steps:

1) First filtering: y=filter (b, a, x)

2) Turning over the y array;

3) And (3) secondary filtering: z=filter (b, a, y 1)

4) The z-th array is flipped.

Where b and a are configurable butterworth coefficients, and the values of b and a come from MATLAB designed filters. x is the original data, y is the data after the first filtering, y1 is the data after the flipping, and z is the data after the second filtering.

And (3) secondary filtering: and (3) canceling the phase deviation of N points in the positive direction generated by the first filtering and the phase deviation of N points in the opposite direction generated by the second filtering, and finally eliminating each other to reach zero phase deviation.

And (3) reverse writing and forward reading: when the method is specifically implemented in the FPGA, the step 2) and the step 4) write from the end position of the memory to the first address direction of the memory when writing into the memory, so that the flip can be realized without any extra resources and clock cycles, as shown in fig. 2. The address space 0x10000000-0x1FFFFFFF before filtering is shown on the left side of FIG. 2, and the address space 0x20000000-0x2FFFFFFF after filtering is shown on the right side. Each time the filtered result is placed in the new address space, a reverse placement is used, for example, each point occupies 4 bytes (32 bits), and then when the filtered address space on the right is placed, the first point is 0x2FFFFFFC.

2. Marginal waveform distortion phenomenon

The butterworth filtering based on FPGA generally has the problem of waveform distortion of tens of points at the head and tail, and the case of waveform distortion of the head before filtering and after filtering is shown in fig. 1. This is because the essence of the butterworth N-th order filtering algorithm is to calculate the n+1th point by using the first N points of the pre-filtered signal and the first N points of the post-filtered signal (2N points in total), but there are not enough points at the beginning, so that considerable errors occur at a considerable number of points in the head of the waveform. The distortion point of the tail is because the tail of the result of the first filtering is taken as the head of the second filtering in the second filtering. The calculation in the FPGA taking 4 th order butterworth filtering as an example is as follows:

a0*y0 = b0*x0

a0*y1 = b0*x1 + b1*x0 - a1*y0

a0*y2 = b0*x2 + b1*x1 + b2*x0 - a1*y1 - a2*y0

a0*y3 = b0*x3 + b1*x2 + b2*x1 + b3*x0 - a1*y2 -a2*y1 - a3*y0

a0*y4 = b0*x4 + b1*x3 + b2*x2 + b3*x1 + b4*x0 -a1*y3 - a2*y2 - a3*y1 - a4*y0

a0*y5 = b0*x5 + b1*x4 + b2*x3 + b3*x2 + b4*x1 -a1*y4 - a2*y3 - a3*y2 - a4*y1

a0*y6 = b0*x6 + b1*x5 + b2*x4 + b3*x3 + b4*x2 -a1*y5 - a2*y4 - a3*y3 - a4*y2

......

wherein b and a are Butterworth coefficients.

The marginal waveform distortion solving method based on the FPGA comprises the following steps:

1) The front end and the rear end each extend a plurality of points: x array

2) First filtering: { Y, Y } = filter (b, a, X)

4) And (3) secondary filtering: { Z, Z } = filter (b, a, Y1)

5) Turning over the z array;

6) Discarding several points of front and back end edge topology: the Z array is ignored.

Wherein X is the numerical value of a plurality of supplementary points of the head-tail edge extension before the first filtering, Y is the numerical value of the supplementary points after the first filtering, and Z is the supplementary points after the second filtering.

When head-tail waveform edge topology is carried out, the problem of insufficient point number is solved by utilizing a plurality of points at the tail end of the last second waveform and the head of the next second waveform, and then the points of the edge topology are removed, as shown in fig. 3. The left of the upper half of fig. 3 is the pre-filtered PING address space, corresponding to data at 1,3,5,7, … … seconds; the right side of the upper half part is a pre-filtering PONG address space corresponding to the data of 2,4,6,8 and … … seconds; the lower half is the filtered PING address space and PONG address space. For example: when the data X before the 2 nd second filtering is put into the post-filtering PONG address space through filtering, the data reading of the filtering module is started after the point number of the 3 rd second header in the pre-filtering PING address space is required to be written, and the time consumed by the filtering module is required to be small enough, so that the completion before the 3 rd second data is covered with the 1 st second end data is ensured. Namely: extracting the head and tail (points along the topology) of the PING address space before filtering the data of the PING address space; if the data of the PING address space is filtered, the head and tail (number of points along the topology) of the PING address space need to be extracted.

The essence of the extension scheme is: when filtering all data in the PING address space, the filtering operation can be started after a plurality of points needing to be extended after the beginning of the PING head address are written, at the moment, the last data in the PING address space of the last second is not disappeared, and the data coverage of the PING of the next second is required to be read in advance and prevented-! The same operation is required when filtering all data in the PING address space. Special care needs to be taken to ensure that new data cannot be written to the memory space at the same time as the extended points in memory are read.

The number of points to be extended is changed under the influence of fixed point number precision of b and a coefficients in the FPGA, the sampling rate and the anti-aliasing cutoff frequency of the filter, the frequency of an input signal and the like. Therefore, it is important to find out under what conditions the number of marginal distortion points is the largest, and it is first necessary to figure out the influence of each variable on the marginal distortion point.

Fig. 4 (a) is an anti-aliasing butterworth low pass filter, 50kHz@0DB,58kHz@1DB,61.5kHz@20DB, with a sampling rate of 128K. This filter is affected by different variables in fig. 4 (b) and 4 (c). Fig. 4 (b) is a graph of the number of distortion points of the filter for input signals of different frequencies of the fixed filter in a practical environment, with the frequency of the input signals being different. Fig. 4 (c) is a graph of the distortion point of an input signal of a fixed frequency as it is filtered with different anti-aliasing butterworth low pass filters, as the filter cut-off frequency varies.

In a practical environment, for a fixed sampling rate and a corresponding anti-aliasing low-pass filter, the number of bits of the fixed points of the b and a coefficients in the FPGA is also fixed, and then the number of points of the marginal distortion mainly changes according to the difference of the frequency of the input signal, and the greater the frequency of the input signal, the greater the number of points of the marginal distortion, as shown in fig. 4 (b).

In a practical environment, the number of bits of the fixed point numbers of the b and a coefficients in the FPGA is also fixed for an input signal with a fixed frequency, and it can be found that the number of points of the marginal distortion also varies according to the difference of the cut-off frequency of the anti-aliasing butterworth low pass filter, and the larger the cut-off frequency of the anti-aliasing butterworth low pass filter, the more the number of points of the marginal distortion, as shown in fig. 4 (c).

The original signal of the actual environment is affected by noise, the fixed point number precision digits of the b and a coefficients in the FPGA also have great influence on the filtering time, the digits precision of the original signal and the like, and the factors can change the error of the Butterworth filtering algorithm, so that the marginal distortion point number also needs to be calculated according to the specific design and the actual environment, and the calculation method comprises the following steps:

under the worst condition, using all data after filtering and every second which are derived from the memory, namely all data before filtering, and then taking absolute values to see the errors of all sampling points; the error exceeding the threshold value is the marginal distortion point, and the point number of the edge topology is slightly larger than the point number of the marginal distortion. For example, if the number of the data is defined as undistorted data, and if the number of the data is less than 150, the data is defined as marginal distortion points, and the number of points needing to be extended can be a plurality of points which are more than the marginal distortion points. The key point of finding the worst condition is that the fixed point number precision of b and a coefficients needs to be comprehensively considered, the sampling rate and the filter anti-aliasing cut-off frequency, the input signal frequency range and amplitude, and the digital bit width of the input signal.

The threshold can be defined according to the corresponding analog power size of the digital quantity, and different analog power scaling factors, the reference voltage range of the AD chip and the accuracy (16-bit or 24-bit AD) of the AD chip can all influence the threshold. For example, the input analog power is-30V to +30V, the analog power is scaled by 24 times, the AD reference voltage is-1.25 to +1.25V, and the digital value is calculated by 1V/24/2.5 (2≡23) = 139810 digital value, namely, 1 millivolt corresponds to 139.8 digital value. This need is defined by project requirements and hardware design.

In summary, when the phase deviation problem is solved by the secondary filtering based on the FPGA: when the FPGA interacts with the memory, the memory data is written from the tail address in each filtering and written, and is read from the head address in each filtering and reading, so that extra resources and clock cycles are not consumed.

When the problem of marginal distortion is solved by head-to-tail edge rubbing based on FPGA: through PING-PONG operation, the front and back second data in different address spaces are reasonably utilized, and the processing is read and timely completed when appropriate, so that the new data is prevented from being covered, and the defect that the Butterworth filtering algorithm lacks 2N points is overcome. In addition, as for the specific point number of the marginal distortion, the influence of different variables on the point number is provided, and the point number of the marginal distortion when the worst condition is found in practice is described.

It should be noted that each step/component described in the present application may be split into more steps/components, or two or more steps/components or part of the operations of the steps/components may be combined into new steps/components, as needed for implementation, to achieve the object of the present invention.

It will be readily appreciated by those skilled in the art that the foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims

1. A butterworth low-pass filtering method based on an FPGA, characterized in that the method comprises the steps of:

2) First filtering: { Y, Y } = filter (b, a, X)

4) And (3) secondary filtering: { Z, Z } = filter (b, a, Y1)

controlling two different memory address spaces through PING-PONG operation, performing head-tail waveform edge extension, namely supplementing the points of the waveform at the moment by utilizing a plurality of points at the tail of the waveform at the last moment and the head of the waveform at the next moment, and then discarding the points of the edge extension; the edge topology is as follows:

when filtering the data in the PONG address space, waiting for writing a plurality of points which need to be extended from the first address in the PING address space to finish, and starting the filtering operation; at this time, the data of a plurality of points needing to be extended at the tail of the PING address space at the last moment are not disappeared, so that the extension is realized; when filtering the data in the PING address space, performing the same operation; and while reading the points along the extension in the memory, new data are not allowed to be written into the memory spaces of the points at the same time;

2. The FPGA-based butterworth low-pass filtering method according to claim 1, further comprising the steps of:

3. The butterworth low-pass filtering method based on the FPGA according to claim 1, wherein the number of points needing extension is determined according to the fixed point number precision of b and a coefficients, the sampling rate, the anti-aliasing cut-off frequency and the frequency of an input signal;

4. The butterworth low-pass filtering method based on the FPGA according to claim 3, wherein the calculation method of the number of points of the marginal distortion is:

5. The FPGA-based butterworth low-pass filtering method according to claim 4, wherein the number of points requiring the edge topology is equal to or greater than the number of points of the marginal distortion.

6. An FPGA-based butterworth low-pass filter, characterized in that the filter employs the FPGA-based butterworth low-pass filtering method of any one of claims 1 to 5.