CN110311679B

CN110311679B - Analog-to-digital converter for probability calculation sequence generation

Info

Publication number: CN110311679B
Application number: CN201910678511.1A
Authority: CN
Inventors: 梁涛
Original assignee: North University of China
Current assignee: North University of China
Priority date: 2019-07-25
Filing date: 2019-07-25
Publication date: 2022-11-01
Anticipated expiration: 2039-07-25
Also published as: CN110311679A

Abstract

An analog-to-digital converter for probability calculation sequence generation belongs to the field of integrated circuits. The method aims to solve the problems that the traditional sequence generator cannot directly obtain a centralized distribution sequence, and even if a circuit is redesigned, the process of converting a binary representation into a determined sequence is still faced, and the process is easy to generate a single event upset phenomenon. The invention can directly generate the analog signal into the sequence which can be processed by the probability operation, saves the processes of binary representation and subsequent conversion in the middle and can enhance the insensitivity of the ADC to the bit upset; in addition, the sequences generated by the invention are distributed in a centralized way, which is beneficial to improving the precision of multiplication operation in probability calculation, and the sequence distributed in a centralized way enhances the error correction capability of the system for single bit inversion. The invention is mainly applied to high-performance arithmetic units, digital signal processing units, communication coding and decoding units and the like based on probability calculation.

Description

Analog-to-digital converter for probability calculation sequence generation

Technical Field

The invention belongs to the field of integrated circuits, and particularly relates to an active resistance type analog-to-digital converter for probability calculation sequence generation.

Background

Probability computation is a weightless numerical computation system that uses the fraction of "1" s in a binary random bit stream to characterize the size of the data. For example, in the following formula, for decimal fraction 0.25, it is represented by binary 0.01, and in probability calculation, it can be represented by 0001, 0100, 00100100100, and so on.

(0.25)₁₀＝(0×2⁰+0×2^-1+1×2^-2)₁₀＝(0.01)₂

＝(0001)_SC4＝(00100100)_SC8＝(11000000)_SC8 (1)

One of the outstanding advantages of probability computation is that when values are generated as random bit sequences, their original complex arithmetic operations can be implemented by very simple hardware logic circuits; for example, addition may be implemented by a data selector, multiplication may be implemented by an AND gate, division may be implemented by a JK flip-flop, and so on.

Another important feature of probability calculation is fault tolerance, especially against bit flipping errors due to external radiation.

In the random sequence, the error caused by the error of one bit is very small; for example, in the sequence 00100100100, the error caused by the single-bit flipping is only 1/8, but in the conventional binary system, the error amplitude of the single-bit flipping can reach 0.5 at most.

The above advantage is derived from the fact that in the probability calculation, the weight of each bit is equal. Of course, these advantages come at the expense of some accuracy and speed, and probabilistic calculations are considered to be a great advantage in systems with small scale, low power consumption, and high fault tolerance requirements.

A typical probability computation system first includes a sequence generator that converts the signal into a random sequence of bits that the probability computation system can process.

The conventional sequence generator is constructed as shown in fig. 1, and a digital comparator is used to compare a value to be converted (which can be normalized to be between 0 and 1 in advance and represented by binary) with N random numbers between 0 and 1, so as to obtain a desired random sequence D^N. The N random numbers are derived from a Linear Feedback Shift Register (LFSR), and the representation of the signal from the input to the binary form is implemented by an analog-to-digital converter (ADC). Although the probability calculation has better fault-tolerant performance, the binary system is very sensitive to bit flipping under the standard CMOS processUnder the irradiation of high-energy particles, a memory cell (such as a register) can cause bit flipping of stored data, i.e. a Single Event Upset (SEU) phenomenon.

The conventional sequence generator comprises a random number generator and an ADC based on the LFSR, and one of the random number generator and the ADC is used for greatly influencing the performance of the sequence generator if the LFSR is turned over under the influence of SEU. Secondly, the ADC is used as an interface for digital and analog signals, and digital storage units such as registers are inevitably included in the ADC, so that if the ADC is exposed to an irradiation environment for a long time, a risk is brought to reliable operation of the system. The ADC can adopt a triple-modular redundancy structure to reinforce the memory cell, but this only reduces the probability of errors occurring in the circuit, and cannot fundamentally eliminate the influence caused by bit flipping. At present, the mainstream ADCs are designed for converting analog signals into corresponding binary representations, and ADCs for generating random sequences have not been reported. If an SEU occurs in the ADC as a data source, a great deviation and error will occur in the subsequent operation. According to the existing experimental report, the ADC with the reinforced design still has the phenomenon of single event upset under the bombardment of Ge particles.

In addition, according to recent research, it is shown that if a random sequence participating in operation is converted into a determined sequence, such as a centrally distributed sequence and a uniformly distributed sequence, the operation accuracy is greatly improved. However, the conventional sequence generator cannot directly obtain such a sequence, and needs to redesign the circuit, but still faces the problem that a single event upset phenomenon is easy to occur in the process of converting the binary representation into the determined sequence, so that the above problems need to be solved.

Disclosure of Invention

The invention provides an analog-digital converter for generating a probability calculation sequence, which aims to solve the problems that a traditional sequence generator cannot directly obtain a concentrated distribution sequence, and a process of converting a binary representation into a determined sequence can be met even if a circuit is redesigned, and the process is easy to generate a single event upset phenomenon.

An analog-to-digital converter for generating a probability calculation sequence comprises a sample-and-hold circuit, a comparator, two level shift circuits, a bidirectional shift register, a buffer, a forward amplifying circuit, a low-pass filter, a subtracter, a voltage division circuit and a control voltage generator;

the two level shift circuits are respectively defined as a first level shift circuit and a second level shift circuit;

a sample-and-hold circuit for holding the clock Clk at the sample-and-hold_SUnder the action of (3), collecting analog voltage signals to obtain analog voltage V_SInput to the positive input end of the comparator;

the comparator is used for comparing the voltage signals received by the positive input end and the negative input end of the comparator to obtain a comparison result and sending a logic level corresponding to the comparison result to the first level shift circuit;

the first level shift circuit is used for shifting down the logic level output by the comparator, then taking the logic level as a new logic level after the comparison result is shifted, and sending the new logic level to the bidirectional shift register;

a second level shift circuit for shifting the switching clock Clk_DAfter the corresponding logic level is shifted, it is used as the switching clock Clk_DThe shifted new logic level is sent to a bidirectional shift register;

wherein the comparison result is compared with the switching clock Clk_DWhen the logic level before shifting is '1', the corresponding logic high level V_DDComparison result and switching clock Clk_DWhen the logic level before shifting is '0', the logic level corresponds to a logic low level 0;

comparison result and switching clock Clk_DWhen the new logic level after shifting is '1', the corresponding logic high level is 0.5V_DDComparison result and switching clock Clk_DWhen the new logic level after shifting is '0', the corresponding logic low level is-0.5V_DD(ii) a Bidirectional shift register at switching clock Clk_DUnder the action of the shifted new logic level, the shift direction of the output sequence is determined according to the new logic level shifted according to the comparison result, and the shifted N-bit concentrated sequence D is obtained₁ ^N＝[d’₁，d’₂……d’_N]；

d’₁To d'_NRespectively representing the digital signals of 1 st to Nth bits from low bit to high bit, wherein N is an integer;

a buffer for buffering the shifted N-bit concentrated sequence D₁ ^N＝[d’1，d’₂……d’_N]After the logic level corresponding to the digital signal of each bit is shifted up, the concentrated sequence D of N bits is output^N＝[d₁，d₂……d_N]And d'₁To d'_NRespectively correspond to d₁To d_NThe logical relationship is opposite;

d₁to d_NRespectively representing the 1 st to the Nth digital signals from the low position to the high position;

a voltage divider circuit for dividing the reference voltage V_REFDividing voltage, and simultaneously sending the obtained voltage delta V to a forward amplifying circuit, a control voltage generator and a subtraction input end of a subtracter;

a control voltage generator for generating a voltage control signal V based on the received voltage Δ V_CTLAnd a voltage control signal V is provided_CTLSending to a forward amplifying circuit;

a forward amplifier circuit for controlling the voltage V according to the received voltage_CTLAnd a digital signal d'₁To d'_NAmplifying the voltage delta V to output a voltage V_ASending the signal to a low-pass filter for filtering, and then sending the signal to a subtracted input end of a subtracter;

difference voltage V output by subtracter_BTo the negative input of the comparator;

T_S＝KT_Dand satisfy N>K>N/2；

Wherein, T_SHolding clock Clk for sampling_SPeriod of (a), T_DFor switching clocks Clk_DK is a coefficient;

n bit concentration sequence D₁ ^NIn each bit digital signal, the logic high level is 0.5V_DDThe logic low level corresponding to each bit digital signal is-0.5V_DD；

Sequence D in N-bit set^NIn each bit digital signal, the logic high level is V_DDThe logic low level corresponding to each bit digital signal is 0.

Preferably, when the comparison result outputted from the first level shift circuit is a logic level '1', the value in the lowest bit of the bidirectional shift register output sequence is controlled to shift to the right and '0' is complemented in the lowest bit, and when the comparison result outputted from the first level shift circuit is a logic level '0', the value in the highest bit of the bidirectional shift register output sequence is controlled to shift to the left and '1' is complemented in the highest bit.

Preferably, the bidirectional shift register is formed by cascading N register units, and the register units are implemented by using D flip-flops.

Preferably, the forward amplifying circuit includes an operational amplifier OP₁Resistance R₁And N voltage-controlled switch active resistors R_A,1To R_A,N；

N voltage-controlled switch active resistors R_A,1To R_A,NConnected in series to an operational amplifier OP after being connected in parallel₁Between the inverting input of (a) and power ground;

n voltage-controlled switch active resistors R_A,1To R_A,NRespectively used for receiving digital signals d'₁To d'_N；

N voltage-controlled switch active resistors R_A,1To R_A,NWhile receiving the voltage control signal V_CTL；

Operational amplifier OP₁The non-inverting input end of the voltage divider is used for receiving the voltage delta V output by the voltage divider;

operational amplifier OP₁As the voltage output terminal of the forward amplifying circuit, and a resistor R₁Is connected to a resistor R₁And the other end of (1) and an operational amplifier OP₁The inverting input end of the first switch is connected;

operational amplifier OP₁Positive power supply input terminal and power supply V_DDConnected, operational amplifier OP₁Negative power supply input terminal and power supply V_SSIs connected, and V_DD＝－V_SS。

Preferably, the N voltage-controlled switch active resistors have the same structure, and each voltage-controlled switch active resistor includes 3 PMOS transistors M_p1To M_p3And 5 NMOS transistors M_n1To M_n5；

NMOS tube M_n2The grid of the voltage-controlled switch is used as a fixed connecting end of the voltage-controlled switch active resistor and the operational amplifier OP₁The inverting input end of the first switch is connected;

the negative output end of the 1V power supply is used as the other fixed connecting end of the voltage-controlled switch active resistor and is connected with the power supply ground;

PMOS tube M_p3The drain electrode of the voltage-controlled switch is used as a voltage control end of the voltage-controlled switch active resistor;

PMOS tube M_p3The grid of the voltage-controlled switch is used as a switch control end of the voltage-controlled switch active resistor;

the positive output end of the 1V power supply is simultaneously connected with the NMOS tube M_n1Grid electrode and NMOS tube M_n1Drain electrode of (D), PMOS tube M_p1Source electrode of PMOS transistor M_p2Source electrode and NMOS tube M_n5Is connected with the drain electrode of the transistor;

NMOS tube M_n1Source electrode of (D) is simultaneously connected with NMOS tube M_n2Grid electrode and NMOS tube M_n2Drain electrode of (1), NMOS tube M_n3Drain electrode of PMOS transistor M_p1Is connected with the drain electrode of the transistor; PMOS tube M_p1The grid electrode of the PMOS transistor M is simultaneously connected with the PMOS transistor M_p2Grid and PMOS transistor M_p2Drain electrode of (1), NMOS tube M_n4Is connected with the drain electrode of the transistor;

NMOS tube M_n2Source electrode of the NMOS transistor M_n3Source electrode and NMOS tube M_n4Source electrode of PMOS transistor M_p3Source electrode and NMOS transistor M_n5Is connected with the source electrode of the transistor;

NMOS tube M_n3Grid and NMOS tube M_n4The grid electrodes of the grid electrodes are all connected with a power ground;

PMOS tube M_p3Grid and NMOS tube M_n5Is connected to the gate of (a).

Preferably, d 'is due to'₁To d'_NRespectively correspond to d₁To d_NIn the opposite logical relationship, the voltage V_AThe expression of (a) is:

i is an integer.

Preferably, d 'is due to'₁To d'_NRespectively correspond to d₁To d_NIs opposite, the difference voltage V_BThe expression of (a) is:

i is an integer.

Preferably, the data transmission method of the bidirectional shift register is serial input and parallel output.

When the random sequence generated by the circuit of fig. 1 is used for multiplication, the precision cannot be guaranteed to be high. Research has proved that the accuracy of calculation can be effectively improved by using the sequence with determined distribution, and the basic idea is to fix the generation mode of two sequences, wherein one sequence is in centralized distribution (1 is centralized at one end), the other sequence is in uniform distribution (1 is distributed approximately at equal intervals in the sequence), and the uniform distribution can be obtained by centralized distribution. The concentrated distribution sequence can be obtained by binary value conversion, but a counter is required, the scale of a circuit is increased, the binary representation can deteriorate the single event upset resistance of the sequence, and most importantly, the counter wastes a large number of clock cycles in the conversion process. The sequence generated by the structure disclosed by the invention is distributed in a centralized manner, so that the conversion process is omitted, and the method is specifically shown in fig. 9.

The invention has the following beneficial effects:

on one hand, the analog-to-digital converter for generating the probability calculation sequence is a novel ADC structure, can directly generate a sequence which can be processed by probability calculation from an analog signal, saves the processes of binary representation and subsequent conversion in the middle, and can enhance the insensitivity of the ADC to bit flipping; in addition, the sequences generated by the invention are distributed in a centralized way, which is beneficial to improving the probabilityThe precision of multiplication operation in calculation and the concentrated distribution sequence enhance the error correction capability of the system for single bit inversion. E.g. the original sequence [ d ]₁d₂d₃d₄]＝[1 1 1 1]Original sequence [ d ]₁d₂d₃d₄]＝[1 1 1 1]Turned over to be [ 10 1 ]]. Because the sequence is concentrated and distributed, 1 and 0 are concentrated and distributed, the second bit in the sequence can be conveniently known to be overturned, the overturned bit can be directly corrected in the subsequent processing process, and the time for determining the overturned bit is reduced.

On the other hand, in order to reduce the occupied chip area, N resistors required by the ADC are designed to be replaced by N voltage control switch active resistors built by MOS (metal oxide semiconductor) transistors, the active resistors are controlled to be switched on and off by digital signals of specific logic levels, and the resistance value in the on state is controlled by external voltage. The invention is mainly suitable for occasions with low requirements on speed and precision and high requirements on fault tolerance.

The ADC structure of the invention has more output bits, and is suitable for on-chip integration and forming a probability calculation SOC chip with other circuits.

Due to the technical characteristics, the invention is mainly applied to a high-performance operation unit based on probability calculation, a digital signal processing unit, a communication coding and decoding unit and the like.

Drawings

FIG. 1 is a schematic diagram of a sequence generation process of a conventional random sequence generator;

FIG. 2 is a schematic diagram of an analog-to-digital converter for probability calculation sequence generation according to the present invention;

fig. 3 is a schematic diagram of a specific structure of the bidirectional shift register 5, the voltage divider circuit 10, the low-pass filter 8 and the subtractor 9 in the specific embodiment;

FIG. 4 shows the analog voltage V obtained by the bidirectional shift register 3 according to the sampling_SAdjusting the working principle schematic diagram of sequence output;

FIG. 5 is a schematic diagram of the buffer 6, in which a dotted line portion is an internal schematic diagram of the i-th inverter stage;

FIG. 6 is a schematic diagram of the active resistor of the voltage controlled switch of the present invention;

FIG. 7 is a simulation result diagram of the simulation circuit of the voltage controlled switch active resistor and its equivalent impedance in the switching state; wherein the content of the first and second substances,

FIG. 7 (a) is a simulation circuit diagram of a voltage divider circuit composed of voltage-controlled switch active resistors;

fig. 7 (b) is a graph of a simulation result of the divided voltage value of the divided voltage circuit in fig. 7 (a), that is: an R + terminal voltage simulation result diagram of the voltage-controlled active resistor in a switch state;

FIG. 7 (b 1) shows the value when V_CTLWhen the voltage is not less than-0.5V, the voltage of the R + end of the active resistor is controlled in a voltage-controlled mode under a switching state;

FIG. 7 (b 2) shows the value when V_CTLWhen the voltage is not less than-1V, the voltage of the R + end of the active resistor is controlled in a voltage-controlled mode in a switching state;

FIG. 7 (b 3) shows the value when V_CTLWhen the voltage is = 1.5V, a simulation waveform diagram of the voltage of the R + end of the active resistor is controlled in a voltage-controlled mode in a switch state;

FIG. 7 (b 4) shows the value when V_CTLWhen the voltage is not less than-2V, the voltage of the R + end of the active resistor is controlled in a voltage-controlled mode in a switching state;

FIG. 8 is a schematic diagram of the operation of the level shift circuit of the present invention, wherein the portion circled by the dotted line is a schematic diagram of the structure of the level shift circuit;

fig. 9 is a simplified sequence generation process diagram of an analog-to-digital converter for probability calculation sequence generation according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.

Referring to fig. 2, the present embodiment is described, and the analog-to-digital converter for probability calculation sequence generation according to the present embodiment includes a sample-and-hold circuit 1, a comparator 2, two level shift circuits, a bidirectional shift register 5, a buffer 6, a forward amplifier circuit 7, a low-pass filter 8, a subtractor 9, a voltage divider circuit 10, and a control voltage generator 11;

two level shift circuits are respectively defined as a first level shift circuit 3 and a second level shift circuit 4;

a sample-and-hold circuit 1 for holding a clock Clk at a sample-and-hold_SUnder the action of (3), collecting analog voltage signals to obtain analog voltage V_SInput to the positive input of the comparator 2;

the comparator 2 is used for comparing the voltage signals received by the positive input end and the negative input end to obtain a comparison result, and sending a logic level corresponding to the comparison result to the first level shift circuit 3;

a first level shift circuit 3, which is used for shifting down the logic level output by the comparator 2, and then sending the new logic level as the comparison result to the bidirectional shift register 5;

a second level shift circuit 4 for shifting the switching clock Clk_DThe corresponding logic level is shifted and then used as a switch clock Clk_DThe shifted new logic level is sent to the bidirectional shift register 5;

comparison result and switching clock Clk_DWhen the shifted new logic level is '1',corresponding to logic high level 0.5V_DDComparison result and switching clock Clk_DWhen the new logic level after shifting is '0', the corresponding logic low level is-0.5V_DD(ii) a Bidirectional shift register 5 at switching clock Clk_DUnder the action of the shifted new logic level, the shift direction of the output sequence is determined according to the new logic level shifted according to the comparison result, and the shifted N-bit concentrated sequence D is obtained₁ ^N＝[d’₁，d’₂……d’_N]；

d’₁To d'_NRespectively representing the digital signals from 1 st to Nth bits from low bit to high bit, wherein N is an integer;

a buffer 6 for aligning the shifted sequences D1 in the N-bit set^N＝[d’₁，d’₂……d’_N]After the logic level corresponding to the digital signal of each bit is shifted up, the concentrated sequence D of N bits is output^N＝[d₁，d₂……d_N]And d'₁To d'_NRespectively correspond to d₁To d_NThe logical relationship is opposite;

a voltage divider circuit 10 for dividing the reference voltage V_REFVoltage division is carried out, and the obtained voltage delta V is simultaneously sent to the subtracting input ends of the forward amplifying circuit 7, the control voltage generator 11 and the subtracter 9;

a control voltage generator 11 for generating a voltage control signal V based on the received voltage Δ V_CTLAnd applies the voltage control signal V_CTLSent to a forward amplifying circuit 7;

a forward amplifier circuit 7 for controlling the voltage V according to the received voltage_CTLAnd a digital signal d'₁To d'_NAmplifying the voltage delta V to output a voltage V_ASending the signal to a low-pass filter 8 for filtering, and then sending the signal to a subtracted input end of a subtracter 9;

the difference voltage V output by the subtracter 9_BTo the negative input of comparator 2;

T_S＝KT_Dand satisfy N>K>N/2；

sequence D in N-bit set₁ ^NIn each bit digital signal, the logic high level is 0.5V_DDThe logic low level corresponding to each bit digital signal is-0.5V_DD；

According to the embodiment, the analog signals can be directly generated into the concentrated distribution sequence of probability operation processing, and the processes of binary representation and subsequent conversion are omitted.

The logic level is '0' to represent low level, and the logic level is '1' to represent high level;

the amplification factor of the forward amplifier circuit 7 is represented by the sequence d'₁To d'_NThe number of the ` 1 ` s in (A) is determined. The logic levels of the signals before and after shifting in the buffer 6 are in the following relationship, d'_iHigh level of (d) corresponds to_iLow level of (d)'_iLow level of (2) corresponds to high level of di, i.e.

Namely: the two logic relations are reversed.

Sampling clock Clk_SPeriod T of_SIs Clk_DPeriod T_DK times of (1), satisfies N>K>N/2, the rising edge of the sampling clock represents the new analog potential input to the comparator 2, and also represents the completion of the conversion of the corresponding digital sequence of the last sampled analog potential.

If the comparison result output by the comparator 2 is in one sampling period T_SWhen the internal voltage is kept at the low level, the bidirectional shift register 5 is located at the highest bit d 'from the right side'_NShifting into multiple 1 states, or left shift 1; the comparison result output by the comparator 2 is in one sampling period T_SWhen the internal state is kept at the high level, the bidirectional shift register 5 has the least significant bit d 'from the left side'₁Shift into multiple 0 states, or right shift complement 0.

The invention relates to an analog-to-digital converter for generating a probability calculation sequence, which is a novel ADC (analog-to-digital converter) structure D^N＝[d₁～d_N]I.e. the output of the ADC of the present invention, from low to high, is d₁To d_NThat is, the sequence to be output finally by probability calculation, and the sequence is distributed in a centralized manner, that is: if present, a '1' is concentrated in the lower position, and if present, a '0' is concentrated in the upper position

The comparator 2 can be powered by a single power supply V_DDThe bidirectional shift register 5 can be powered by two power supplies V_DAnd V_SPower supply and having V_D＝－V_S＝0.5V_DDThe first level shift circuit 3 shifts the logic level of the comparator output by 0.5V_DDThe required logic levels of the bi-directional shift register 5 are obtained.

Externally inputted switching clock Clk_DRespectively correspond to V_DDAnd 0, and therefore, the logic level needs to be shifted down by 0.5V through the second level shift circuit 4 as well_DDThe required logic level of the bi-directional shift register 5 is obtained.

The data transmission mode of the bidirectional shift register 5 is serial input and parallel output.

Referring to fig. 2, the preferred embodiment is described, in which the bidirectional shift register 5 is formed by cascading N register units, and the register units are implemented by using D flip-flops.

In the preferred embodiment, the bidirectional shift register 5 is a conventional bidirectional shift register 5 formed by cascading N register units, which can be implemented by the conventional technique, and specifically, referring to fig. 3, the shift operation of the bidirectional shift register 5 is performed by a switching clock Clk_DOutputs logic signals d '1 to d'_NHigh level is V_DRepresenting a logic 1, low level V_SRepresenting a logic 0. Due to d'_IDoes not match the subsequent stage of the ADC, and therefore needs to be d'_iThen addA first buffer 6 for obtaining a new logic signal d_i。

The comparison result output by the comparator 2 is Comp_outShifted by 0.5V by a level shift circuit_DDObtaining the new logic Signal Comp'_outIs input to the bidirectional shift register 5.

The bidirectional shift register 5 is formed by cascading N register units, the register units are realized by adopting D flip-flops, see fig. 3, and the D flip-flops are formed by V flip-flops_DAnd V_SSupplied with power and having V_D＝－V_S＝0.5V_DDClock signal of D flip-flop is Clk'_DBy a switching clock Clk_DShifted by 0.5V_DDAnd then obtaining the compound.

Thus, logic Signal Comp'_out、Clk’_DAnd the register unit outputs d'₁～d’_NCorresponding high level is V_DNamely: logic 1, low level is V_SNamely: a logic 0. Each D flip-flop has two data inputs Dri and Dli when the clock signal Clk'_DWhen the rising edge arrives, the D flip-flop latches the value of Dri or Dli, specifically selects whether Dri or Dli is latched, and the comparator 2 outputs a signal Comp'_outDetermining;

is Comp'_outAt high, dri is selected as the input to the D flip-flop, i.e.: latch value of Dri, 'Comp'_outWhen low, select Dli as the input of D flip-flop, namely: the value of Dli is latched. The output of the N-stage D flip-flop is D 'from low to high'₁To d'_NAnd outputs the lowest bit d'₁D flip-flop U₁Represents that the highest bit d 'is output'_ND flip-flop U_NIndicating and so on. The output Dout of the previous stage D trigger is connected with the input port Dri of the next stage D trigger; the output Dout of the next-stage D trigger is connected with the input port Dli of the previous-stage D trigger, and the cascade connection is finished by analogy; u shape₁Input port Dri of (1) is connected to low level V_S，U_NIs connected to a high level V_D(ii) a Clock Clk, set input R, receive signal Comp 'of all D flip-flops'_outThe terminals Dout are all connected together.

Referring to fig. 2 to 4, the preferred embodiment is described, in which when the comparison result output by the first level shift circuit 3 is logic level '1', the value in the lowest bit of the output sequence of the bidirectional shift register 5 is controlled to shift to the right and to complement '0' in the lowest bit, and when the comparison result output by the first level shift circuit 3 is logic level '0', the value in the highest bit of the output sequence of the bidirectional shift register 5 is controlled to shift to the left and to complement '1' in the highest bit.

Principle analysis:

the shifting principle of the present invention is analyzed with specific reference to fig. 3 and 4; FIG. 4 shows an analog voltage V obtained by the bidirectional shift register 3 according to sampling_SAdjusting the working principle schematic diagram of sequence output;

(A) At the beginning of power-on, i.e., at time t =0, the states of the bidirectional shift register 5 are all Set to 1 by the Set signal Set, as shown in fig. 4; then, if Comp'_outWhen the clock signal is held high, the sequence outputted from the bidirectional shift register 5 is the least significant bit d'₁Become 0 one by one; if Comp'_outWhen the state is kept at low level, the state of the shift register is changed from the most significant bit d 'by the clock signal'_NAnd become 1 one by one.

(B) At t = t₀At time instant d 'from the bidirectional shift register 5'₁To

Are all 0, and the rest are 1; see FIG. 4, if Comp'_outIn a sampling period T_SWhen the internal voltage is kept at the low level, the bidirectional shift register 5 is located at the highest bit d 'from the right side'_NShifting into multiple 1 states, or left shift 1; if Comp'_outIn a sampling period T_SWhen the internal holding is high, the bidirectional shift register 5 is located at the lowest bit d 'from the left side'₁Shift into multiple 0 states, or right shift complement 0. Notably, due to d'₁～d’_NAre respectively V_DAnd V_SThis does not match the requirements of the post-stage logic of a typical ADC, and therefore requires d 'to be output at each register'_iThen a buffer circuit is added to enable a new logic signal d_iAre respectively V_DDAnd 0.

As shown in fig. 3, the voltage divider circuit 10 is implemented by the prior art, and a specific structure of the voltage divider circuit 10 is specifically shown, wherein the voltage divider circuit 10 is formed by R₉、R₁₀And R₁₁Composition, reference voltage V_REFAfter partial pressure, obtaining delta V, delta V and V_REFThe relationship of (A) is as follows,

the present preferred embodiment is described with reference to fig. 2 and 3, and in the present preferred embodiment, the forward amplifying circuit 7 includes an operational amplifier OP₁Resistance R₁And N voltage-controlled switch active resistors R_A,1To R_A,N；

N voltage-controlled switch active resistors R_A,1To R_A,NThe voltage control terminal receives the voltage control signal V at the same time_CTL；

Operational amplifier OP₁The non-inverting input terminal of (a) is used for receiving the voltage Δ V output by the voltage dividing circuit 10;

operational amplifier OP₁As the voltage output terminal of the forward amplifying circuit 7, and a resistor R₁Is connected to a resistor R₁And the other end of (1) and an operational amplifier OP₁The inverting input end of the first switch is connected;

operational amplifier OP₁Positive power supply input terminal and power supply V_DDConnected, operational amplifier OP₁Negative power supply input terminal and power supply V_SSAre connected, and V_DD＝－V_SS。

In the preferred embodiment, the invention adopts N voltage-controlled switch active resistors R_A,1To R_A,NFor reducing the chip area occupied by the forward amplifying circuit 7, the active resistor is controlled to be turned on and off by a digital signal of a specific logic level, and the resistance value in the on state is controlled by an external voltage.

The specific structures of the bidirectional shift register 5, the voltage dividing circuit 10, the low-pass filter 8 and the subtracter 9 in the invention can be realized by the prior art, and the invention provides a specific structure of the bidirectional shift register 5, the voltage dividing circuit 10, the low-pass filter 8 and the subtracter 9, which is specifically shown in fig. 3;

referring to fig. 6, the preferred embodiment is described, in which the structures of N voltage-controlled switch active resistors are the same, and each voltage-controlled switch active resistor includes 3 PMOS transistors M_p1To M_p3And 5 NMOS transistors M_n1To M_n5；

the positive output end of the 1V power supply is simultaneously connected with the NMOS tube M_n1Grid electrode and NMOS tube M_n1Drain electrode of PMOS transistor M_p1Source electrode of PMOS transistor M_p2Source electrode and NMOS tube M_n5Is connected with the drain electrode of the transistor;

NMOS tube M_n1Source electrode of the NMOS transistor M_n2Grid of (1), NMOS tube M_n2Drain electrode of (1), NMOS tube M_n3Drain electrode of PMOS transistor M_p1Is connected with the drain electrode of the transistor; PMOS tube M_p1Grid electrode of the PMOS transistor M_p2Grid and PMOS transistor M_p2Drain electrode of (1), NMOS tube M_n4Is connected with the drain electrode of the transistor;

NMOS tube M_n2Source electrode of the NMOS transistor M_n3Source electrode and NMOS tube M_n4Source electrode of PMOS transistor M_p3Source electrode of (1) and NMOS transistor M_n5Is connected to the source of (a);

PMOS tube M_p3Grid and NMOS tube M_n5Is connected to the gate of (a).

In the preferred embodiment, the voltage-controlled switch active resistor comprises 3 PMOS transistors M_p1To M_p3And 5 NMOS transistors M_n1To M_n5Wherein M is_n1～M_n4、M_p1、M_p2All work in a saturation region or a cut-off region, and the saturation region or the cut-off region forms a main body part of the active resistor; m_p3、M_n5A switching section operating in a linear region or a cut-off region; the substrates of all the MOS tubes are connected with the source electrodes thereof. One end of the active resistor is fixedly grounded, and the other end is R⁺If at R⁺End external excitation source V_inThen can be measured by R⁺Seen-in equivalent resistance R_eq＝V_in/I_in. There are two control ports for the active resistor: switch control terminal d'_iAnd a voltage control terminal V_CTL。

As shown in FIG. 6, the main body of the active resistor is powered by an externally connected 1V power supply as the positive power supply, and the negative power supply is based on d'_iState of (1) power supply or V_CTLPower supply:

when d'_iWhen =1, M_n5Conducting M_p3Cut off due to d'_iHigh level of V_D＝0.5V_DD，M_n5Easily satisfy V_gs–V_th,n>V_ds，V_gsIs the voltage between the gate and the source, V_dsIs the voltage between drain and source, V_th,nIs the threshold voltage of the NMOS tube; then M_n5A linear region operating as a transfer gate so that the negative power supply of the body portion approaches 1V;

when d'_iWhen =0, M_n5Cut-off M_p3Is turned on due to d'_iLow level of V_S＝–0.5V_DDAppropriately select V_CTLVoltage of (e.g., -1V) to cause M_p3Satisfy | V_gs–V_th，p|>|V_dsI, then M_p3Operating in the linear region, corresponding to a transfer gate, so that the negative supply to the body portion approaches V_CTL，V_th，pIs the threshold voltage of the PMOS tube.

In conclusion, when d'_iWhen the current is 1, both the positive power supply and the negative power supply of the main body part are 1V, and the MOS tube is cut off, so that the equivalent impedance of the active resistor is very large, namely, the active resistor is cut off;

when d'_iWhen =0, V is selected appropriately_CTLThe MOS tube of the main body part works in a saturation region, and the active resistor can work normally at the moment. D'_iEquivalent resistance R of =0_eqTo be connected with V_CTLControl of (2).

The result of simulating the active resistance structure by using a certain 0.5 μm CMOS BCD double-well process is shown in FIG. 7; fig. 7 (a) is a built simulation circuit diagram, an 8k resistor and an active resistor are connected in series to form a voltage division circuit, a switch control end of the active resistor is connected with a square wave signal, and the high and low levels of the square wave signal are respectively V_Dand-V_SAnd V is_D＝–V_S＝0.5V_DD=2.5V, the voltage control terminal is connected with a variable analog voltage V_CTLThe width to length ratio of each tube is indicated in FIG. 6 (in μm). FIG. 7 (b) shows different control voltages V_CTLSimulation result of when the switching signal is at high level V_DEquivalent resistance R of active resistor_eqThe voltage is far greater than 8k and close to cut-off, so the difference between the partial voltage value V (R +) and 0.5V is very small; when the switching signal is at a high level V_SThe equivalent resistance R of the active resistor_eqTo be connected with V_CTLThe control is carried out by controlling the temperature of the air conditioner,

according to different V_CTLThe value of V (R +) can be calculated_eqE.g. V_CTLR of =1_eqIs 15k. Because the size of the MOS tube can be smaller, the chip area occupied by the active resistor can be greatly reduced, and the resistance value can be V_CTLAnd (6) adjusting.

Referring to FIGS. 2 and 3, the present preferred embodiment is illustrated, in this preferred embodiment, as d'₁To d'_NRespectively correspond to d₁To d_NIn the opposite logical relationship, the voltage V_ASum and difference voltage V_BThe expression of (a) is:

i is an integer.

As shown in fig. 2 and 3, the voltage controlled switch active resistor R_A,1～R_A,NAre respectively output d 'by bidirectional shift register'₁～d’_NAnd (4) controlling. When d'_iAt logic high level (corresponding to d)_iLow level) corresponding to the active resistance R_A，iIs made of V_CTLDetermining; when d'_iAt its logic low level (corresponding to d)_iHigh level), R_A，iPresenting a larger resistance, equivalent to an open circuit. R_A,1～R_A,NAre connected in series at OP after being connected in parallel₁Between the negative input terminal and the analog ground, and their voltage control terminals are all connected to V_CTLSignal, therefore R_A，iResistance R presented in the on-state_eqAre identical, provided that R_eq＝R₁Then the equivalent parallel resistance can be expressed as,

the equivalent resistance R_A，eqAnd OP₁And R₁The forward amplifying circuit is formed by the components together, and the voltage V of the point A_AIt can be expressed as follows,

V_Apassing through a forward low-pass filter with pass-band gain of 1 to filter out high-frequency switching noise, and subtracting a voltage of DeltaV by a subtracter 9 to obtain V_BAs shown in the following formula, V_BIs connected with the negative end of the comparator 2,

in FIG. 3, when the analog voltage V is sampled_S>V_BShi, comp'_outIs high level, the shift register outputs a clock signal Clk'_DIs right shifted by 0 corresponding to ADC output D^NThen it is right shift 1,V_BGradually increasing; when V is_S<V_BShi, comp'_outIs at low level, the output of the shift register is at Clk'_DIs left shifted by 1 corresponding to the ADC output D^NThen it is left shift 0,V_BAnd gradually decreases. During a certain sampling period duration, the ADC dynamically adjusts D^NIn 1 is V_BIs gradually approaching to V_S(ii) a When the sampling period is finished, namely the ADC finishes sampling the analog voltage V_STo a digital sequence D^NConversion of (V)_BShould be consistent with V_SAs close as possible, thereby realizing the use of D^NThe ratio of 1 in V_S。

Therefore, when V_SAnd V_BTaking the minimum value of 0, corresponding to D^NThe total number of the compounds is 0; when V is_BAnd V_ATaking the maximum value, i.e. the full-scale voltage V_DDWhen corresponds to D^NIf V is 1, the formula II shows that_B＝V_DDIf N.DELTA.V is true, then DELTA.V is the resolution of the ADC, D^NIs a digital sequence of the ADC output.

Referring to FIG. 5, the preferred embodiment will be described, wherein the buffer 6 is composed of N buffer units, and the N buffer units are used for d'₁To d'_NThe corresponding logic level is inverted and level up shifting is achieved.

Buffer unit toolThe bulk structure can be realized by the prior art, specifically refer to fig. 5, in which one inverter is composed of one NMOS and one PMOS, and fig. 5 has 3 inverters (specifically, see the oval dashed box), one negative feedback PMOS and one NMOS; d'_iIs 0.5V respectively_DDand-0.5V_DD，d_iAre respectively V_DDAnd 0, and d'_iHigh level of (d) corresponds to_iLow level of d'_iLow level of (d) corresponds to_iI =1,2,3, … … N.

The positive and negative power supplies of the inverter inside the buffer unit are respectively V_DDAnd 0. When d'_iWhen the voltage is high level, the input of the corresponding first-stage inverter is connected with 0.5V_DDFirst stage inverter input and V_DDA negative feedback PMOS tube is arranged between the first and the second inverter, the grid of the PMOS tube is connected with the output of the first inverter, if the output potential of the first inverter can make the PMOS tube conducted, the input of the first inverter is pulled up to V_DDAt this time, the output of the first-stage inverter is close to 0 potential, and is shaped by the following multi-stage inverters to finally output d_iIs close to 0; the size of the first-stage phase inverter can be reasonably designed to ensure that the on-resistance of the NMOS tube is smaller than that of the PMOS tube, so that the buffer works more reliably. When d'_iWhen the voltage is low, the grid of the PMOS tube in the first-stage inverter is connected with-0.5V_DDIt is enough to make the PMOS tube conduct and work in linear region, and at this time, the negative feedback PMOS tube and NMOS tube in the first stage inverter are necessarily cut off, so that the output of the first stage inverter is close to V_DDAnd finally output d is shaped by a subsequent multi-stage inverter_iIs close to V_DD. Thus, the odd inverters are d'_iHigh level of (d) corresponds to_iLow level of (d)'_iLow level of (d) corresponds to_iHigh level of (i.e. i)

Sequence D^N＝[d₁～d_N]As the final output of the ADC.

In the invention, the level shift circuit can be realized by adopting the prior artThe specific structure of the shift circuit can be seen in FIG. 8, as V_DDFor example, =5V, since the bidirectional shift register 5 is composed of V_DAnd V_SPower supply, and V_D＝–V_S＝0.5V_DD=2.5V, and the output of the comparator Comp_outAt V_DDAnd 0 is high and low, and therefore needs to be shifted by 0.5V_DDA new logic signal Comp 'results after = 2.5V'_outThe input is used in a bidirectional shift register. Similarly, the input clock Clk 'of the level shift circuit'_DIs also made of Clk_DObtained through level shift operation. The structure of the level shift circuit is shown in fig. 8, which operates on a principle similar to the buffer unit of fig. 5, except that the level shift circuit is mainly composed of an even number of inverters having specific sizes and positive and negative power supplies, respectively, V_D＝0.5V_DDAnd V_S＝-0.5V_DDFirst stage inverter input and V_SThe negative feedback tube in between is NMOS tube, since the inverter stage number is even number, comp_outAnd Comp'_outIn phase.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.

Claims

1. An analog-to-digital converter for probability calculation sequence generation is characterized by comprising a sampling and holding circuit (1), a comparator (2), two level shift circuits, a bidirectional shift register (5), a buffer (6), a forward amplifying circuit (7), a low-pass filter (8), a subtracter (9), a voltage division circuit (10) and a control voltage generator (11);

the two level shift circuits are respectively defined as a first level shift circuit (3) and a second level shift circuit (4);

a sample-and-hold circuit (1) for holding a clock Clk at a sample-and-hold time_SUnder the action of (3), collecting analog voltage signals to obtain analog voltage V_SInput to the positive input end of the comparator (2);

the comparator (2) is used for comparing the voltage signals received by the positive input end and the negative input end of the comparator to obtain a comparison result, and sending a logic level corresponding to the comparison result to the first level shift circuit (3);

a first level shift circuit (3) for shifting down the logic level outputted from the comparator (2), and then sending the new logic level shifted as the comparison result to the bidirectional shift register (5);

a second level shift circuit (4) for shifting the switching clock Clk_DAfter the corresponding logic level is shifted, it is used as the switching clock Clk_DThe shifted new logic level is sent to a bidirectional shift register (5);

comparison result and switching clock Clk_DWhen the new logic level after shifting is '1', the corresponding logic high level is 0.5V_DDComparison result and switching clock Clk_DWhen the new logic level after shifting is '0', the corresponding logic low level is-0.5V_DD(ii) a A bidirectional shift register (5) for switching the clock Clk_DUnder the action of the shifted new logic level, the shift direction of the output sequence is determined according to the new logic level shifted according to the comparison result, and the shifted N-bit concentrated sequence D is obtained₁ ^N＝[d’₁，d’₂……d’_N]；

d’₁To d'_NRespectively representing the 1 st to Nth digit signals from low to high, N being an integer；

A buffer (6) for aligning the shifted sequences D in the N-bit set₁ ^N＝[d’₁，d’₂……d’_N]After the logic level corresponding to the digital signal of each bit is shifted up, the concentrated sequence D of N bits is output^N＝[d₁，d₂……d_N]And d'₁To d'_NRespectively correspond to d₁To d_NThe logical relationship is opposite;

a voltage divider circuit (10) for dividing the reference voltage V_REFVoltage division is carried out, and the obtained voltage delta V is simultaneously sent to the positive amplification circuit (7), the control voltage generator (11) and the subtraction input end of the subtracter (9);

a control voltage generator (11) for generating a voltage control signal V based on the received voltage DeltaV_CTLAnd applies the voltage control signal V_CTLSending to a forward amplifier circuit (7);

a forward amplifier circuit (7) for controlling the voltage V according to the received voltage_CTLAnd a digital signal d'₁To d'_NAmplifying the voltage delta V to output a voltage V_AThe signal is sent to a low-pass filter (8) for filtering and then sent to the input end of a subtracter (9);

the difference voltage V output by the subtracter (9)_BTo the negative input of the comparator (2);

T_S＝KT_Dand satisfy N>K>N/2；

Sequence D in N-bit set^NIn the middle, each bit digital signal corresponds to a logic high level V_DDEach bit of digital signal is pairedThe corresponding logic low level is 0.

2. An analog-to-digital converter for probability calculation sequence generation according to claim 1, characterized in that when the comparison result outputted from the first level shift circuit (3) is logic level '1', the value in the lowest bit of the output sequence of the bidirectional shift register (5) is controlled to shift to the right and to complement '0' in the lowest bit, and when the comparison result outputted from the first level shift circuit (3) is logic level '0', the value in the highest bit of the output sequence of the bidirectional shift register (5) is controlled to shift to the left and to complement '1' in the highest bit.

3. An analog-to-digital converter for probability calculation sequence generation according to claim 1, characterized in that the bidirectional shift register (5) is cascaded by N register units, and the register units are implemented with D flip-flops.

4. An analog-to-digital converter for probability calculation sequence generation according to claim 1, characterized in that the forward amplifying circuit (7) comprises an operational amplifier OP₁Resistance R₁And N voltage-controlled switch active resistors R_A，1To R_A，N；

N voltage-controlled switch active resistors R_A，1To R_A,NConnected in series to an operational amplifier OP after being connected in parallel₁Between the inverting input of (a) and power ground;

Operational amplifier OP₁The non-inverting input end of the voltage divider is used for receiving the voltage delta V output by the voltage divider circuit (10);

operational amplifier OP₁As the voltage output terminal of the forward amplifying circuit (7), and a resistor R₁Is connected to a resistor R₁And the other end of (1) and an operational amplifier OP₁The inverting input end of the first switch is connected;

5. The ADC of claim 4, wherein N voltage controlled switch active resistors have the same structure, and each voltage controlled switch active resistor comprises 3 PMOS transistors M_p1To M_p3And 5 NMOS transistors M_n1To M_n5；

the negative output end of the 1V power supply is connected with the power ground as the other fixed connection end of the voltage-controlled switch active resistor;

NMOS tube M_n1Source electrode of the NMOS transistor M_n2Grid electrode and NMOS tube M_n2Drain electrode of (1), NMOS tube M_n3Drain electrode of PMOS transistor M_p1Is connected with the drain electrode of the transistor; PMOS tube M_p1Grid electrode of the PMOS transistor M_p2Grid and PMOS transistor M_p2Drain electrode of (1), NMOS tube M_n4Is connected with the drain electrode of the transistor;

NMOS tube M_n2Source electrode of the NMOS transistor M_n3Source electrode and NMOS tube M_n4Source electrode of PMOS transistor M_p3Source electrode and NMOS transistor M_n5Is connected to the source of (a);

NMOS tube M_n3Grid and NMOS tube M_n4The grids of the grid-connected transistors are all connected with a power ground;

PMOS tube M_p3Grid and NMOS tube M_n5Is connected to the gate of (a).

6. The analog-to-digital converter for probability calculation sequence generation of claim 1, wherein d 'is due'₁To d'_NRespectively correspond to d₁To d_NIn the opposite logical relationship, the voltage V_AThe expression of (a) is:

i is an integer.

7. The analog-to-digital converter for probability calculation sequence generation of claim 1, wherein d 'is due'₁To d'_NRespectively correspond to d₁To d_NIs opposite, the difference voltage V_BThe expression of (a) is:

i is an integer.

8. An analog-to-digital converter for probability calculation sequence generation according to claim 1, characterized in that the data transmission mode of the bidirectional shift register (5) is serial input and parallel output.