CN110311679A - A kind of analog-digital converter generated for probability calculation sequence - Google Patents
A kind of analog-digital converter generated for probability calculation sequence Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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Abstract
A kind of analog-digital converter generated for probability calculation sequence, belongs to integrated circuit fields.Integrated distribution sequence can not be directly obtained in order to solve traditional sequence generator, and even if being designed again circuit, but still binary representation can be faced to the process for determining that sequence is converted, and the problem of single-particle inversion phenomenon easily occurs for the process.Analog signal can be directly generated the sequence that probabilistic operation is capable of handling by the present invention, and centre eliminates the process of binary representation and subsequent conversion, can enhance ADC to the insensitivity of bit reversal；In addition, being conducive to the precision for improving multiplying in probability calculation in centralization distribution by the sequence that the present invention generates, and the sequence of this integrated distribution enhances the error correcting capability that system inverts single-bit.Present invention is mainly applied to high performance computation unit, digital signal processing units based on probability calculation, communicate codec unit etc..
Description
Technical field
The invention belongs to integrated circuit fields, and in particular to a kind of active pull-up pattern generated for probability calculation sequence
Number converter.
Background technique
Probability calculation is a kind of numerical value computing system of no weight, it is used shared by " 1 " in binary system random bit stream
Ratio carrys out the size of characterize data.Such as in following formula, for decimal fraction 0.25, with being represented in binary as 0.01, in probability
In calculating, it can be indicated with 0001,0100,00100100 etc..
(0.25)10=(0 × 20+0×2-1+1×2-2)10=(0.01)2
=(0001)SC4=(00100100)SC8=(11000000)SC8 (1)
One outstanding advantages of probability calculation are, after numerical value is generated by random bit sequence, the original arithmetic of complexity
Operation can be realized by very simple hardware logic electric circuit；For example, addition can realize that multiplication can by a data selector
With by one and Men Shixian, removing rule can be by JK flip-flop realization etc..
Another important feature of probability calculation is exactly fault-tolerance, especially for the bit brought by the external world radiates
Overturn mistake.
In random sequence, it is very small that error brought by mistake, which occurs, for a bit；By taking pure decimal as an example, than
In sequence 00100100, error brought by single bit upset is only 1/8, but in traditional binary system, single-bit is turned over
The raw wrong amplitude of forwarding can reach 0.5.
Above-mentioned advantage has benefited from probability calculation, and the weight of each of which bit is all same.Certainly, these advantages are
To sacrifice a part of accuracy and speed as cost, probability calculation is considered more demanding in small-scale, low-power consumption, fault-tolerance
System in have great advantage.
One typical probability calculation system first has to comprising sequence generator, and sequence generator converts a signal into generally
The manageable random bit sequence of rate computing system.
Traditional sequence generator is constituted as shown in Figure 1, using digital comparator, and numerical value to be converted (can preparatory normalizing
Change between 0~1, and with binary representation) with random number between N number of 0~1 gradually compared with, available required stochastic ordering
Arrange DN.N number of random number is to be obtained by linear feedback shift register (LFSR), and signal is expressed as binary system shape from being input to
Formula is realized by analog-digital converter (ADC).Although probability calculation itself has preferable error resilience performance, binary system pair
Bit reversal is very sensitive, and storage unit (such as register), can under the irradiation by high energy particle under standard CMOS process
To lead to the bit flipping of stored data, i.e. single-particle inversion (SEU) phenomenon.
It include randomizer and ADC based on LFSR in conventional sequence generator, if one, LFSR are by SEU shadow
Sound occurs as overturning, by the performance of strong influence sequence generator.Secondly, interface of the ADC as digital and analog signaling,
Middle necessarily includes the digital storage units such as register, also can be to the reliable of system if ADC is exposed under radiation environment for a long time
Operation brings risk.ADC can reinforce storage unit using triplication redundancy structure, but this can only make circuit mistake occur
Probability reduce, can not be inherently eliminated bit reversal bring influence.Currently, the ADC of mainstream is for that will simulate letter
It number is converted to corresponding binary representation and designs, the ADC for generating random sequence is not yet reported that.If as data
SEU has occurred in the ADC in source, and subsequent operation will be made to generate huge deviation and mistake.According to existing Experimental report, pass through
Still there is single-particle inversion phenomenon under the bombardment of Ge particle in the ADC of Design of Reinforcement.
In addition, according to newest studies have shown that such as being concentrated if the random sequence for participating in operation is converted into determine sequence
It is distributed and is uniformly distributed sequence, then operational precision will be greatly improved.And traditional sequence generator can not directly obtain
Such sequence needs to design circuit again, but still can face binary representation to determine sequence conversion during,
The problem of single-particle inversion phenomenon easily occurs, therefore, problem above urgent need to resolve.
Summary of the invention
The present invention is in order to solve traditional sequence generator and can not directly obtain integrated distribution sequence, and even if to circuit
Again it is designed, but still binary representation can be faced to the process for determining that sequence is converted, and the process easily occurs single-particle and turns over
The problem of turning phenomenon, the present invention provides a kind of analog-digital converters generated for probability calculation sequence.
A kind of analog-digital converter generated for probability calculation sequence, including sampling hold circuit, comparator, two level
Shift circuit, bidirectional shift register, buffer, positive amplifying circuit, low-pass filter, subtracter, bleeder circuit and control
Voltage generator；
Two level shift circuits are respectively defined as the first level shift circuit and second electrical level shift circuit；
Sampling hold circuit, for keeping clock Clk in samplingSUnder the action of, analog voltage signal is acquired, is obtained
The analog voltage V obtainedSIt is input to the positive input terminal of comparator；
Comparator obtains comparison result, and will compare for being compared to its positive and negative received voltage signal of input terminal
It send compared with logic level corresponding to result to the first level shift circuit；
First level shift circuit moves as comparative result after moving down to the logic level that comparator exports
New logic level behind position, and it is passed to bidirectional shift register；
Second electrical level shift circuit, for switch clock ClkDAfter corresponding logic level is shifted, as opening
Close clock ClkDNew logic level after displacement, and it is passed to bidirectional shift register；
Wherein, comparison result and switch clock ClkDWhen logic level before displacement is ' 1 ', counterlogic high level VDD,
Comparison result and switch clock ClkDWhen logic level before displacement is ' 0 ', counterlogic low level 0；
Comparison result and switch clock ClkDWhen new logic level after displacement is ' 1 ', counterlogic high level 0.5VDD,
Comparison result and switch clock ClkDWhen new logic level after displacement is ' 0 ', counterlogic low level -0.5VDD；Bi-directional shift
Register, in switch clock ClkDNew logic electricity under the action of new logic level after displacement, after being shifted according to comparison result
Sequence D is concentrated in the flat direction of displacement for determining output sequence, the position N after being shifted1 N=[d '1, d '2……d’N]；
d’1To d 'NIt respectively indicates from low to high direction, the digital signal of 1 to N, N is integer；
Buffer, for concentrating sequence D to the position N after displacement1 N=[d ' 1, d '2……d’N] in bits per inch word signal institute
After corresponding logic level moves up, N concentration sequence Ds are exportedN=[d1, d2……dN], and d '1To d 'NRespectively with its corresponding to
d1To dNLogical relation is opposite；
d1To dNIt respectively indicates from low to high direction, the digital signal of 1 to N；
Bleeder circuit, for reference voltage VREFIt is divided, and the voltage Δ V of acquisition is sent to forward direction simultaneously and is amplified
Circuit, the subtracting input for controlling voltage generator and subtracter；
Voltage generator is controlled, voltage Δ V generates voltage control signal V based on the receivedCTL, and by voltage control signal
VCTLIt send to positive amplifying circuit；
Positive amplifying circuit, based on the received voltage control signal VCTLAnd digital signal d '1To d 'NTo voltage Δ V into
Row amplification, the voltage V of outputAIt send to low-pass filter after being filtered, then send to the minuend input terminal of subtracter；
The difference voltage V of subtracter outputBIt send to the negative input end of comparator；
TS=KTD, and meet N > K > N/2；
Wherein, TSClock Clk is kept for samplingSPeriod, TDFor switch clock ClkDPeriod, K is coefficient；
N concentration sequence Ds1 NIn, logic high corresponding to bits per inch word signal is 0.5VDD, bits per inch word signal institute
Corresponding logic low is -0.5VDD；
N concentration sequence DsNIn, logic high corresponding to bits per inch word signal is VDD, corresponding to bits per inch word signal
Logic low be 0.
Preferably, when the comparison result of the first level shift circuit output is logic level ' 1 ', bi-directional shift is controlled
Numerical value in register output sequence lowest order moves to right, and mends ' 0 ' in lowest order, when the comparison of the first level shift circuit output
When being as a result logic level ' 0 ', the numerical value controlled in bidirectional shift register output sequence highest order is moved to left, and is mended in highest order
‘1’。
Preferably, bidirectional shift register is cascaded by N number of register cell, and the register cell is touched using D
Device is sent out to realize.
Preferably, positive amplifying circuit includes operational amplifier OP1, resistance R1With N number of votage control switch active pull-up RA,1
To RA,N；
N number of votage control switch active pull-up RA,1To RA,NOperational amplifier OP is connected on after parallel connection1Inverting input terminal and electricity
Between the ground of source；
N number of votage control switch active pull-up RA,1To RA,NSwitch control terminal be respectively used to receive digital signal d '1To d 'N；
N number of votage control switch active pull-up RA,1To RA,NVoltage controling end receive voltage control signal V simultaneouslyCTL；
Operational amplifier OP1Non-inverting input terminal be used for receive bleeder circuit output voltage Δ V；
Operational amplifier OP1Voltage output end of the output end as positive amplifying circuit, with resistance R1One end connection,
Resistance R1The other end and operational amplifier OP1Inverting input terminal connection；
Operational amplifier OP1Positive supply input terminal and power supply VDDConnection, operational amplifier OP1Negative supply input terminal with
Power supply VSSConnection, and VDD=-VSS。
Preferably, the structure of N number of votage control switch active pull-up is identical, and each votage control switch active pull-up includes 3
PMOS tube Mp1To Mp3With 5 NMOS tube Mn1To Mn5；
NMOS tube Mn2Grid as votage control switch active pull-up a fixed connection end and operational amplifier OP1It is anti-
The connection of phase input terminal；
The negative output terminal of 1V power supply is connect as another fixed connection end of votage control switch active pull-up with power ground；
PMOS tube Mp3Voltage controling end of the drain electrode as votage control switch active pull-up；
PMOS tube Mp3Switch control terminal of the grid as votage control switch active pull-up；
The positive output end of 1V power supply simultaneously with NMOS tube Mn1Grid, NMOS tube Mn1Drain electrode, PMOS tube Mp1Source electrode,
PMOS tube Mp2Source electrode, NMOS tube Mn5Drain electrode connection；
NMOS tube Mn1Source electrode simultaneously with NMOS tube Mn2Grid, NMOS tube Mn2Drain electrode, NMOS tube Mn3Drain electrode,
PMOS tube Mp1Drain electrode connection；PMOS tube Mp1Grid simultaneously with PMOS tube Mp2Grid, PMOS tube Mp2Drain electrode, NMOS tube
Mn4Drain electrode connection；
NMOS tube Mn2Source electrode simultaneously with NMOS tube Mn3Source electrode, NMOS tube Mn4Source electrode, PMOS tube Mp3Source electrode and
NMOS tube Mn5Source electrode connection；
NMOS tube Mn3Grid and NMOS tube Mn4Grid connect with power ground；
PMOS tube Mp3Grid and NMOS tube Mn5Grid connection.
Preferably, due to d '1To d 'NRespectively with its corresponding to d1To dNLogical relation on the contrary, then voltage VAExpression
Formula are as follows:
I is integer.
Preferably, due to d '1To d 'NRespectively with its corresponding to d1To dNLogical relation on the contrary, then difference voltage VB's
Expression formula are as follows:
I is integer.
Preferably, the data transfer mode of bidirectional shift register is serial input, parallel output.
When the random sequence generated with Fig. 1 circuit does multiplying, precision does not ensure that very high.Existing research proves
The accuracy of calculating can be effectively improved using the sequence of determining distribution, basic ideas are by the generation mode of two sequences
Fixed, one of sequence is in centralization distribution (1 concentrates at one end), and in the distribution of uniform formula, (1 is in another sequence in the sequence
Approximation is spacedly distributed), being uniformly distributed can be obtained by centralization distribution.Integrated distribution sequence can be converted by binary numeral
It obtains, but needs by counter, this can be such that the scale of circuit increases, and binary representation can be such that sequence anti-single particle overturns
Degradation, most important is that counter can make conversion process waste a large amount of clock cycle.And open structure of the present invention is given birth to
At sequence inherently centralization distribution, the process of conversion is eliminated, referring specifically to Fig. 9.
The invention has the beneficial effects that:
On the one hand, a kind of analog-digital converter generated for probability calculation sequence of the present invention is a kind of novel ADC
Structure, analog signal can be directly generated the sequence that probabilistic operation is capable of handling by it, centre eliminate binary representation and after
The process of continuous conversion, can enhance ADC to the insensitivity of bit reversal；In addition, the sequence generated by the present invention is in centralization
Distribution is conducive to the precision for improving multiplying in probability calculation, and the sequence of this integrated distribution enhances system for list
The error correcting capability of bit reversal.Such as original series [d1d2d3d4]=[1 11 1], original series [d1d2d3d4]=[1 11
1] become [1 01 1] after overturning.Since the integrated distribution formula of sequence is specific, 1 and 0 is integrated distribution, therefore, can be very square
Just learn that second is flipped in sequence, directly the flip bit can be corrected in subsequent processes, reduce
Determine the time for being flipped position.
On the other hand, to reduce shared chip area, N number of resistance needed for ADC is designed to the N number of pressure built by metal-oxide-semiconductor
It controls switch active resistance to replace, which is turned on and off by the Digital Signals of specific logic levels, and opens shape
Resistance value under state is controlled by external voltage.Fault-tolerance is required the present invention is mainly suitable for requiring less high to speed and precision
Higher occasion.
ADC structure output digit of the present invention is more, and suitable Embedded simultaneously forms probability calculation SOC chip with other circuits.
Due to these technical characterstics, present invention is mainly applied to high performance computation unit, number letters based on probability calculation
Number processing unit, communication codec unit etc. can be extensive based on the said units that concentration sequence generator of the present invention is constituted
Applied to neural network, control logic, the fields such as communication system.
Detailed description of the invention
Fig. 1 is the sequence generation process schematic illustration of traditional random sequence generator；
Fig. 2 is a kind of schematic illustration of analog-digital converter generated for probability calculation sequence of the present invention；
Fig. 3 is bidirectional shift register 5, bleeder circuit 10, low-pass filter 8 and the subtracter 9 in specific embodiment
Concrete structure schematic diagram；
Fig. 4 is the analog voltage V that bidirectional shift register 3 is obtained according to samplingS, adjust the working principle that sequence exports and show
It is intended to；
Fig. 5 is the schematic illustration of buffer 6, wherein dotted portion is the inside schematic illustration of i-stage phase inverter；
Fig. 6 is the schematic illustration of the votage control switch active pull-up in the present invention；
Fig. 7 is for the artificial circuit of the votage control switch active pull-up in the present invention and its in the equivalent impedance under switch state
Simulation result diagram；Wherein,
Fig. 7 (a) is the artificial circuit figure for the bleeder circuit being made of votage control switch active pull-up；
Fig. 7 (b) is the simulation result diagram of the partial pressure value of bleeder circuit in Fig. 7 (a), namely: it is voltage-controlled active under switch state
The end the R+ voltage simulation result diagram of resistance；
Fig. 7 (b1) is to work as VCTLWhen=- 0.5V, the simulation waveform of the end the R+ voltage of voltage-controlled active pull-up under switch state；
Fig. 7 (b2) is to work as VCTLWhen=- 1V, the simulation waveform of the end the R+ voltage of voltage-controlled active pull-up under switch state；
Fig. 7 (b3) is to work as VCTLWhen=- 1.5V, the simulation waveform of the end the R+ voltage of voltage-controlled active pull-up under switch state；
Fig. 7 (b4) is to work as VCTLWhen=- 2V, the simulation waveform of the end the R+ voltage of voltage-controlled active pull-up under switch state；
Fig. 8 is the working principle diagram of the level shift circuit in the present invention, wherein the part that virtual coil is drawn is level shift
The structural schematic diagram of circuit；
Fig. 9 is a kind of sequence generation process letter of analog-digital converter generated for probability calculation sequence of the present invention
Figure.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without making creative work it is obtained it is all its
Its embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
Illustrate present embodiment, a kind of modulus generated for probability calculation sequence described in present embodiment referring to fig. 2
Converter, including sampling hold circuit 1,2, two level shift circuits of comparator, bidirectional shift register 5, buffer 6, just
To amplifying circuit 7, low-pass filter 8, subtracter 9, bleeder circuit 10 and control voltage generator 11；
Two level shift circuits are respectively defined as the first level shift circuit 3 and second electrical level shift circuit 4；
Sampling hold circuit 1, for keeping clock Clk in samplingSUnder the action of, analog voltage signal is acquired,
The analog voltage V of acquisitionSIt is input to the positive input terminal of comparator 2；
Comparator 2 obtains comparison result, and will compare for being compared to its positive and negative received voltage signal of input terminal
It send compared with logic level corresponding to result to the first level shift circuit 3；
First level shift circuit 3, after the logic level for exporting to comparator 2 moves down, as comparative result
New logic level after displacement, and it is passed to bidirectional shift register 5；
Second electrical level shift circuit 4, for switch clock ClkDAfter corresponding logic level is shifted, as opening
Close clock ClkDNew logic level after displacement, and it is passed to bidirectional shift register 5；
Wherein, comparison result and switch clock ClkDWhen logic level before displacement is ' 1 ', counterlogic high level VDD,
Comparison result and switch clock ClkDWhen logic level before displacement is ' 0 ', counterlogic low level 0；
Comparison result and switch clock ClkDWhen new logic level after displacement is ' 1 ', counterlogic high level 0.5VDD,
Comparison result and switch clock ClkDWhen new logic level after displacement is ' 0 ', counterlogic low level -0.5VDD；Bi-directional shift
Register 5, in switch clock ClkDNew logic electricity under the action of new logic level after displacement, after being shifted according to comparison result
Sequence D is concentrated in the flat direction of displacement for determining output sequence, the position N after being shifted1 N=[d '1, d '2……d’N]；
d’1To d 'NIt respectively indicates from low to high direction, the digital signal of 1 to N, N is integer；
Buffer 6, for concentrating sequence D 1 to the position N after displacementN=[d '1, d '2……d’N] in bits per inch word signal institute
After corresponding logic level moves up, N concentration sequence Ds are exportedN=[d1, d2……dN], and d '1To d 'NRespectively with its corresponding to
d1To dNLogical relation is opposite；
d1To dNIt respectively indicates from low to high direction, the digital signal of 1 to N；
Bleeder circuit 10, for reference voltage VREFIt is divided, and the voltage Δ V of acquisition is sent to forward direction simultaneously and is put
Big circuit 7, the subtracting input for controlling voltage generator 11 and subtracter 9；
Voltage generator 11 is controlled, voltage Δ V generates voltage control signal V based on the receivedCTL, and voltage is controlled and is believed
Number VCTLIt send to positive amplifying circuit 7；
Positive amplifying circuit 7, based on the received voltage control signal VCTLAnd digital signal d '1To d 'NTo voltage Δ V into
Row amplification, the voltage V of outputAIt send to low-pass filter 8 after being filtered, then send to the minuend input terminal of subtracter 9；
The difference voltage V that subtracter 9 exportsBIt send to the negative input end of comparator 2；
TS=KTD, and meet N > K > N/2；
Wherein, TSClock Clk is kept for samplingSPeriod, TDFor switch clock ClkDPeriod, K is coefficient；
N concentration sequence Ds1 NIn, logic high corresponding to bits per inch word signal is 0.5VDD, bits per inch word signal institute
Corresponding logic low is -0.5VDD；
N concentration sequence DsNIn, logic high corresponding to bits per inch word signal is VDD, corresponding to bits per inch word signal
Logic low be 0.
Analog signal can be directly generated the integrated distribution sequence of probabilistic operation processing, eliminate two by present embodiment
System indicates and the process of subsequent conversion.
Logic level of the present invention is ' 0 ' expression low level, and logic level is ' 1 ' expression high level；
The amplification factor of positive amplifying circuit 7 is by sequence d '1To d 'NIn ' 1 ' number determine.For buffer 6,
There are following relationship, d ' for the logic level of displacement front and back signaliHigh level correspond to diLow level, d 'iLow level it is corresponding
The high level of di, i.e.,That is: the two logical relation reverse phase.
Sampling clock ClkSCycle TSFor ClkDCycle TDK times, meet N > K > N/2, the rising edge of sampling clock represents
New simulation current potential is input to comparator 2, while also represent the corresponding Serial No. of simulation current potential that one samples and turning
It changes and finishes.
If the comparison result that comparator 2 exports is in a sampling period TSInterior holding low level, then bidirectional shift register 5
From right side highest order d 'NMultiple 1 states are moved into, or move to left benefit 1；The comparison result that comparator 2 exports is a sampling week
Phase TSInterior holding high level, then bidirectional shift register 5 is from left side lowest order d '1Multiple 0 states are moved into, or move to right benefit 0.
A kind of analog-digital converter generated for probability calculation sequence of the present invention is a kind of novel ADC structure, DN
=[d1~dN], it is the output of ADC of the present invention, position is d respectively from low to high1To dN, that is, probability calculation will finally export
Sequence, the sequence in centralization distribution, it may be assumed that ' 1 ' if it exists, then ' 1 ' concentrates on low level, ' 0 ' if it exists, then ' 0 ' concentrates on
It is high-order
Comparator 2 can be by single supply VDDPower supply, bidirectional shift register 5 can be by dual power supply VDAnd VSPower supply, and have VD=-
VS=0.5VDD, the logic level that the first level shift circuit 3 exports comparator shifts 0.5VDDObtain bidirectional shift register 5
Required logic level.
Externally input switch clock ClkDLow and high level respectively correspond as VDDWith 0, therefore, it is also desirable to by the second electricity
Logic level is moved down 0.5V by translational shifting circuit 4DDLogic level needed for obtaining bidirectional shift register 5.
The data transfer mode of bidirectional shift register 5 is serial input, parallel output.
Illustrate this preferred embodiment referring to fig. 2, in this preferred embodiment, bidirectional shift register 5 is by N number of register
It is unit cascaded to form, and the register cell is realized using d type flip flop.
In this preferred embodiment, bidirectional shift register 5 is the prior art, and N number of register cell cascade forms two-way
Shift register 5, can be realized by the prior art, referring specifically to Fig. 3, when 5 shifting function of bidirectional shift register is switched
Clock ClkDControl, output logic signal d ' 1~d 'N, high level VDRepresent logic 1, low level VSRepresent logical zero.Due to
d’ILow and high level and ADC late-class circuit mismatch, therefore, it is necessary in d 'iLater plus first-level buffer device 6, new patrol is obtained
Collect signal di。
The comparison result that comparator 2 exports is Compout, 0.5V is shifted by level shift circuitDDNew logic letter is obtained afterwards
Number Comp 'outIt is input to bidirectional shift register 5.
Bidirectional shift register 5 is cascaded by N number of register cell, and register cell is realized using d type flip flop, referring to
Fig. 3, and d type flip flop is by VDAnd VSPower supply, and have VD=-VS=0.5VDD, the clock signal of d type flip flop is Clk 'D, by switching
Clock ClkDBy shifting 0.5VDDAfter obtain.
Therefore, logical signal Comp 'out、Clk’DAnd register cell exports d '1~d 'NCorresponding high level is VD,
That is: logic 1, low level VS, it may be assumed that logical zero.There are two data input pin Dri and Dli for each d type flip flop, work as clock signal
Clk’DWhen rising edge arrives, d type flip flop latches the value of Dri or Dli, and specific choice latches the value of Dri or Dli, by comparing
2 output signal Comp ' of deviceoutIt determines；
Work as Comp 'outWhen for high level, input of the Dri as d type flip flop is selected, it may be assumed that the value for latching Dri works as Comp 'out
When for low level, input of the Dli as d type flip flop is selected, it may be assumed that latch the value of Dli.The output of N grades of d type flip flops position from low to high
It is d ' respectively1To d 'N, export lowest order d '1D type flip flop U1It indicates, exports highest order d 'ND type flip flop UNIt indicates, according to
This analogizes.The output Dout of previous stage d type flip flop meets the input port Dri of rear stage d type flip flop；Rear stage d type flip flop it is defeated
Dout meets the input port Dli of previous stage d type flip flop out, and so on completes cascade；U1Input port Dri meet low level VS,
UNInput port Dli meet high level VD；Clock Clk, the set input R of all d type flip flops receive signal Comp 'out's
The end Dout is connected together.
Illustrate this preferred embodiment to Fig. 4 referring to fig. 2, in this preferred embodiment, when the first level shift circuit 3 is defeated
When comparison result out is logic level ' 1 ', the numerical value controlled in 5 output sequence lowest order of bidirectional shift register is moved to right, and
' 0 ' is mended in lowest order, when the comparison result of the first level shift circuit 3 output is logic level ' 0 ', control bi-directional shift is posted
Numerical value in 5 output sequence highest order of storage moves to left, and mends ' 1 ' in highest order.
Principle analysis:
Shifting principle of the invention is analyzed referring specifically to 3 and Fig. 4；Fig. 4 is bidirectional shift register 3 according to sampling
The analog voltage V of acquisitionS, the operation principle schematic diagram of adjustment sequence output；
(A), beginning is powered on, i.e., t=0 moment, the state of bidirectional shift register 5 are set signal Set and all set 1, such as
Shown in Fig. 4；Later, if Comp 'outHigh level is remained, then bidirectional shift register 5 exports under the action of clock signal
Sequence by lowest order d '1Become 0 one by one；If Comp 'outLow level is remained, then shifts and posts under the action of clock signal
Storage state is by highest order d 'NBecome 1 one by one.
(B), in t=t0At the moment, bidirectional shift register 5 is from d '1It arrivesIt is 0, remaining is 1；Such as Fig. 4, if
Comp’outIn a sampling period TSInterior holding low level, then bidirectional shift register 5 is from right side highest order d 'NMove into multiple 1
State, or move to left benefit 1；If Comp 'outIn a sampling period TSInterior holding high level, then bidirectional shift register 5 from
Left side lowest order d '1Multiple 0 states are moved into, or move to right benefit 0.Significantly, since d '1~d 'NLow and high level difference
For VDAnd VS, the requirement mismatch of this and the rear level logic circuit of general ADC, it is therefore desirable to export d ' in each registeriLater
Add a buffer circuits, so that new logical signal diLow and high level be V respectivelyDDWith 0.
As shown in figure 3, bleeder circuit 10 is realized using the prior art, and the one kind for showing in particular bleeder circuit 10 is specific
Structure, bleeder circuit 10 is by R9、R10And R11Composition, reference voltage VREFΔ V, Δ V and V are obtained after dividingREFRelational expression such as
Under,
Illustrate this preferred embodiment referring to figs. 2 and 3, in this preferred embodiment, positive amplifying circuit 7 includes operation
Amplifier OP1, resistance R1With N number of votage control switch active pull-up RA,1To RA,N；
N number of votage control switch active pull-up RA,1To RA,NOperational amplifier OP is connected on after parallel connection1Inverting input terminal and electricity
Between the ground of source；
N number of votage control switch active pull-up RA,1To RA,NSwitch control terminal be respectively used to receive digital signal d '1To d 'N；
N number of votage control switch active pull-up RA,1To RA,NVoltage controling end receive voltage control signal V simultaneouslyCTL；
Operational amplifier OP1Non-inverting input terminal be used for receive bleeder circuit 10 output voltage Δ V；
Operational amplifier OP1Voltage output end of the output end as positive amplifying circuit 7, with resistance R1One end connection,
Resistance R1The other end and operational amplifier OP1Inverting input terminal connection；
Operational amplifier OP1Positive supply input terminal and power supply VDDConnection, operational amplifier OP1Negative supply input terminal with
Power supply VSSConnection, and VDD=-VSS。
In this preferred embodiment, the present invention uses N number of votage control switch active pull-up RA,1To RA,NIt is put for reducing forward direction
Chip area shared by big circuit 7, which is turned on and off by the Digital Signals of specific logic levels, and opens shape
Resistance value under state is controlled by external voltage.
The specific structure of bidirectional shift register 5, bleeder circuit 10, low-pass filter 8 and subtracter 9 in the present invention, can
It is achieved by the prior art, and The present invention gives bidirectional shift register 5, bleeder circuit 10, low-pass filter 8 and subtracters
9 a kind of specific structure, referring specifically to Fig. 3；
Illustrate this preferred embodiment referring to Fig. 6, in this preferred embodiment, the structure of N number of votage control switch active pull-up
Identical, each votage control switch active pull-up includes 3 PMOS tube Mp1To Mp3With 5 NMOS tube Mn1To Mn5；
NMOS tube Mn2Grid as votage control switch active pull-up a fixed connection end and operational amplifier OP1It is anti-
The connection of phase input terminal；
The negative output terminal of 1V power supply is connect as another fixed connection end of votage control switch active pull-up with power ground；
PMOS tube Mp3Voltage controling end of the drain electrode as votage control switch active pull-up；
PMOS tube Mp3Switch control terminal of the grid as votage control switch active pull-up；
The positive output end of 1V power supply simultaneously with NMOS tube Mn1Grid, NMOS tube Mn1Drain electrode, PMOS tube Mp1Source electrode,
PMOS tube Mp2Source electrode, NMOS tube Mn5Drain electrode connection；
NMOS tube Mn1Source electrode simultaneously with NMOS tube Mn2Grid, NMOS tube Mn2Drain electrode, NMOS tube Mn3Drain electrode,
PMOS tube Mp1Drain electrode connection；PMOS tube Mp1Grid simultaneously with PMOS tube Mp2Grid, PMOS tube Mp2Drain electrode, NMOS tube
Mn4Drain electrode connection；
NMOS tube Mn2Source electrode simultaneously with NMOS tube Mn3Source electrode, NMOS tube Mn4Source electrode, PMOS tube Mp3Source electrode and
NMOS tube Mn5Source electrode connection；
NMOS tube Mn3Grid and NMOS tube Mn4Grid connect with power ground；
PMOS tube Mp3Grid and NMOS tube Mn5Grid connection.
In this preferred embodiment, votage control switch active pull-up includes 3 PMOS tube Mp1To Mp3With 5 NMOS tube Mn1Extremely
Mn5, wherein Mn1~Mn4、Mp1、Mp2It works in saturation region or cut-off region, they constitute the main part of active pull-up；Mp3、Mn5
Work constitutes switch sections in linear zone or cut-off region；The substrate of all metal-oxide-semiconductors is connected with its source electrode.The active pull-up
One end dead earth, other end R+If in R+Hold external driving source Vin, then can measure by R+The equivalent impedance R seen intoeq
=Vin/Iin.Control port that there are two active pull-ups: switch control terminal d 'iWith voltage controling end VCTL。
As shown in fig. 6, the main part of active pull-up is powered by external 1V power supply as positive supply, negative supply then basis
d’iState selection 1V power supply or VCTLPower supply:
Work as d 'iWhen=1, Mn5M is connectedp3Cut-off, due to d 'iHigh level be VD=0.5VDD, Mn5It is easily met Vgs–
Vth,n>Vds, VgsFor grid and voltage between source electrodes, VdsFor drain electrode and voltage between source electrodes, Vth,nFor the threshold voltage of NMOS tube；Then
Mn5Work is equivalent to a transmission gate, to make the negative supply of main part close to 1V in linear zone；
Work as d 'iWhen=0, Mn5End Mp3Conducting, due to d 'iLow level be VS=-0.5VDD, suitably selection VCTLVoltage
(such as -1V) makes Mp3Meet | Vgs–VTh, p|>|Vds|, then Mp3Work is equivalent to a transmission gate, to make main body in linear zone
Partial negative supply is close to VCTL, VTh, pFor the threshold voltage of PMOS tube.
To sum up, work as d 'iWhen=1, the positive-negative power of main part is 1V, and metal-oxide-semiconductor is ended, therefore the active pull-up
Equivalent impedance it is very big, be equivalent to and be turned off；
Work as d 'iWhen=0, suitably selection VCTLThe metal-oxide-semiconductor of main part is set to work in saturation region, at this time the active pull-up
It can work normally.In d 'iWhen=0, equivalent impedance ReqBy VCTLControl.
Emulating the active pull-up structure using certain 0.5 μm of CMOS BCD twin well process, to obtain result as shown in Figure 7；Wherein, scheme
7 (a) the artificial circuit figure to be built, 8k resistance and active pull-up are composed in series bleeder circuit, the switch control of active pull-up
A square-wave signal is terminated, the low and high level of square-wave signal is respectively VDWith-VS, and VD=-VS=0.5VDD=2.5V, voltage control
One variable analog voltage V of system terminationCTL, the breadth length ratio of each pipe indicates (unit is μm) in Fig. 6.Such as Fig. 7 (b)
For different control voltage VCTLUnder simulation result, when switching signal be high level VDWhen, the equivalent resistance R of active pull-upeqMuch
Greater than 8k close to shutdown, therefore partial pressure value V (R+) and 0.5V gap are minimum；When switching signal is high level VSWhen, active electricity
The equivalent resistance R of resistanceeqBy VCTLControl,
According to different VCTLThe value of lower V (R+) can calculate Req, such as VCTL=-1 corresponding ReqFor 15k.Due to
The size of metal-oxide-semiconductor can obtain smaller, and therefore, chip area shared by active pull-up can greatly reduce, and resistance value can be by
VCTLIt adjusts.
Illustrate this preferred embodiment referring to figs. 2 and 3, in this preferred embodiment, due to d '1To d 'NRespectively with its institute
Corresponding d1To dNLogical relation on the contrary, then voltage VAWith difference voltage VBExpression formula are as follows:
I is integer.
As shown in Figures 2 and 3, votage control switch active pull-up RA,1~RA,ND ' is exported by bidirectional shift register respectively1~
d’NControl.Work as d 'i(to correspond to d when its logic highiFor low level), corresponding active pull-up RA, iResistance value by VCTLCertainly
It is fixed；Work as d 'i(to correspond to d when its logic lowiFor high level), RA, iLarger resistance value is presented, is equivalent to open circuit.RA,1~RA,NAnd
OP is connected on after connection1Negative input end and simulation ground between, and their voltage controling end all meets VCTLSignal, therefore RA, iIt is connecing
The impedance R presented under logical stateeqIt is identical, it is assumed that Req=R1, then equivalent parallel resistance can be expressed as,
Equivalent resistance RA, eqWith amplifier OP1And R1Positive amplifying circuit is collectively constituted, then the voltage V of A pointAIt can be with table
It is shown as,
VAThe positive low-pass filter for being 1 by passband gain, filters out the switching noise of high frequency, then by subtracter 9
The voltage for subtracting a Δ V obtains VBIt is shown below, VBThe negative terminal of comparator 2 is connect,
In Fig. 3, as the analog voltage V of samplingS>VBWhen, Comp 'outFor high level, shift register output is in clock signal
Clk’DUnder the action of move to right benefit 0, corresponding A DC exports DNIt is then to move to right benefit 1, VBIt incrementally increases；Work as VS<VBWhen, Comp 'outIt is low
Level, shift register output is in Clk 'DUnder the action of move to left benefit 1, corresponding A DC exports DNIt is then to move to left benefit 0, VBIt gradually reduces.
During some sampling period continues, ADC dynamic adjustment DNIn 1 number make VBGradually approach VS；At the end of the sampling period
It carves, i.e. ADC completes sampling analogue voltage VSTo Serial No. DNConversion, VBIt should be with VSAs close possible to realize use
DNIn ratio shared by 1 characterize VS。
Therefore, work as VSAnd VBWhen being minimized 0, corresponding DNIn be all 0；Work as VBAnd VAIt is maximized i.e. full range voltage VDD
When, corresponding DNIn be all 1, by formula two it is found that if VB=VDD=N Δ V is set up, then Δ V is the resolution ratio of ADC, DNFor ADC
The Serial No. of output.
Illustrate this preferred embodiment referring to Fig. 5, in this preferred embodiment, buffer 6 is made of N number of buffer cell, N
A buffer cell is respectively used to d '1To d 'NCorresponding logic level negates, and realizes that level moves up.
The specific structure of buffer unit can be achieved by the prior art, referring specifically to one NMOS and one in 5, Fig. 5
The phase inverter that PMOS is constituted, share in Fig. 53 phase inverters (being specifically shown in oval dotted line frame), a negative-feedback PMOS and
One NMOS；d'iLow and high level be 0.5V respectivelyDDWith -0.5VDD, diLow and high level be V respectivelyDDWith 0, and d 'iHeight electricity
It is flat to correspond to diLow level, d 'iLow level correspond to diHigh level, i=1,2,3 ... ... N.
The positive-negative power of phase inverter inside buffer unit is V respectivelyDDWith 0.Work as d 'iWhen for high level, then the is corresponded to
The input of level-one phase inverter meets 0.5VDD, first order phase inverter inputs and VDDBetween there are a negative-feedback PMOS tube, the PMOS tube
Grid connect the output of first order phase inverter, if first order phase inverter output current potential can be such that the PMOS tube is connected, the first order
Phase inverter input is pulled to VDD, at this moment first order phase inverter is exported close to 0 current potential, process multistage phase inverter shaping thereafter, most
Output d eventuallyiIt is close to 0；The size that first order phase inverter can be rationally designed makes NMOS transistor conduction resistance be less than PMOS tube, then delays
Rushing device work will be more reliable.Work as d 'iWhen for low level, the PMOS tube grid in first order phase inverter meets -0.5VDD, this is enough
The PMOS tube is connected and works in linear zone, and the NMOS tube in negative-feedback PMOS tube and first order phase inverter is inevitable at this time
Cut-off thus makes the output of first order phase inverter close to VDD, process multistage phase inverter shaping final output d thereafteriIt is close to VDD。
Odd number phase inverter so just makes d 'iHigh level just correspond to diLow level, d 'iLow level correspond to diHigh level,
I.e.Sequence DN=[d1~dN] final output as ADC.
In the present invention, level shift circuit be can be implemented by using the prior art, and the specific structure of level shift circuit can be found in
Fig. 8, with VDDFor=5V, since bidirectional shift register 5 is by VDAnd VSPower supply, and VD=-VS=0.5VDD=2.5V, and compare
The output Comp of deviceoutWith VDDIt is used as low and high level with 0, therefore needs shifted 0.5VDDNew logical signal is obtained after=2.5V
Comp’outIt is input in bidirectional shift register and uses.Similarly, the input clock Clk ' of level shift circuitDIt is also by ClkDThrough
Over level shifting function obtains.The structure of level shift circuit is as shown in figure 8, the working principle of the circuit and the buffering of Fig. 5
Device unit is similar, and difference is, level shift circuit is mainly had the reverse phase of specific dimensions and positive and negative power supply by even number
Device is constituted, and the positive-negative power of phase inverter is V respectivelyD=0.5VDDAnd VS=-0.5VDD, first order phase inverter inputs and VSBetween
Negative-feedback pipe is NMOS tube, since phase inverter series is even number, CompoutWith Comp 'outSame phase.
Although describing the present invention herein with reference to specific embodiment, it should be understood that, these realities
Apply the example that example is only principles and applications.It should therefore be understood that can be carried out to exemplary embodiment
Many modifications, and can be designed that other arrangements, without departing from spirit of the invention as defined in the appended claims
And range.It should be understood that different appurtenances can be combined by being different from mode described in original claim
Benefit requires and feature described herein.It will also be appreciated that the feature in conjunction with described in separate embodiments can be used
Other embodiments.
Claims (8)
1. a kind of analog-digital converter generated for probability calculation sequence, which is characterized in that including sampling hold circuit (1), ratio
Compared with device (2), two level shift circuits, bidirectional shift register (5), buffer (6), positive amplifying circuit (7), low-pass filtering
Device (8), subtracter (9), bleeder circuit (10) and control voltage generator (11)；
Two level shift circuits are respectively defined as the first level shift circuit (3) and second electrical level shift circuit (4)；
Sampling hold circuit (1), for keeping clock Clk in samplingSUnder the action of, analog voltage signal is acquired, is obtained
Analog voltage VSIt is input to the positive input terminal of comparator (2)；
Comparator (2) obtains comparison result, and will compare for being compared to its positive and negative received voltage signal of input terminal
As a result corresponding logic level is sent to the first level shift circuit (3)；
First level shift circuit (3), after being used to move down the logic level that comparator (2) export, as comparative result
New logic level after displacement, and it is passed to bidirectional shift register (5)；
Second electrical level shift circuit (4), for switch clock ClkDAfter corresponding logic level is shifted, as switch
Clock ClkDNew logic level after displacement, and it is passed to bidirectional shift register (5)；
Wherein, comparison result and switch clock ClkDWhen logic level before displacement is ' 1 ', counterlogic high level VDD, compare
As a result with switch clock ClkDWhen logic level before displacement is ' 0 ', counterlogic low level 0；
Comparison result and switch clock ClkDWhen new logic level after displacement is ' 1 ', counterlogic high level 0.5VDD, compare
As a result with switch clock ClkDWhen new logic level after displacement is ' 0 ', counterlogic low level -0.5VDD；Bi-directional shift deposit
Device (5), in switch clock ClkDNew logic level under the action of new logic level after displacement, after being shifted according to comparison result
Sequence D is concentrated in the direction of displacement for determining output sequence, the position N after being shifted1 N=[d '1, d '2……d’N]；
d’1To d 'NIt respectively indicates from low to high direction, the digital signal of 1 to N, N is integer；
Buffer (6), for concentrating sequence D to the position N after displacement1 N=[d '1, d '2……d’N] in bits per inch word signal institute it is right
After the logic level answered moves up, N concentration sequence Ds are exportedN=[d1, d2……dN], and d '1To d 'NRespectively with its corresponding to d1
To dNLogical relation is opposite；
d1To dNIt respectively indicates from low to high direction, the digital signal of 1 to N；
Bleeder circuit (10), for reference voltage VREFIt is divided, and the voltage Δ V of acquisition is sent to forward direction simultaneously and is amplified
Circuit (7), the subtracting input for controlling voltage generator (11) and subtracter (9)；
It controls voltage generator (11), voltage Δ V generates voltage control signal V based on the receivedCTL, and by voltage control signal
VCTLIt send to positive amplifying circuit (7)；
Positive amplifying circuit (7), based on the received voltage control signal VCTLAnd digital signal d '1To d 'NVoltage Δ V is carried out
Amplification, the voltage V of outputAIt send to low-pass filter (8) after being filtered, then send to the minuend input terminal of subtracter (9)；
The difference voltage V of subtracter (9) outputBIt send to the negative input end of comparator (2)；
TS=KTD, and meet N > K > N/2；
Wherein, TSClock Clk is kept for samplingSPeriod, TDFor switch clock ClkDPeriod, K is coefficient；
N concentration sequence Ds1 NIn, logic high corresponding to bits per inch word signal is 0.5VDD, corresponding to bits per inch word signal
Logic low be -0.5VDD；
N concentration sequence DsNIn, logic high corresponding to bits per inch word signal is VDD, patrol corresponding to bits per inch word signal
Collecting low level is 0.
2. a kind of analog-digital converter generated for probability calculation sequence according to claim 1, which is characterized in that when the
When the comparison result of one level shift circuit (3) output is logic level ' 1 ', bidirectional shift register (5) output sequence is controlled
Numerical value in lowest order moves to right, and mends ' 0 ' in lowest order, when the comparison result of the first level shift circuit (3) output is logic
When level ' 0 ', the numerical value controlled in bidirectional shift register (5) output sequence highest order is moved to left, and mends ' 1 ' in highest order.
3. a kind of analog-digital converter generated for probability calculation sequence according to claim 1, which is characterized in that two-way
Shift register (5) is cascaded by N number of register cell, and the register cell is realized using d type flip flop.
4. a kind of analog-digital converter generated for probability calculation sequence according to claim 1, which is characterized in that positive
Amplifying circuit (7) includes operational amplifier OP1, resistance R1With N number of votage control switch active pull-up RA, 1To RA, N；
N number of votage control switch active pull-up RA, 1To RA,NOperational amplifier OP is connected on after parallel connection1Inverting input terminal and power ground it
Between；
N number of votage control switch active pull-up RA,1To RA,NSwitch control terminal be respectively used to receive digital signal d '1To d 'N；
N number of votage control switch active pull-up RA,1To RA,NVoltage controling end receive voltage control signal V simultaneouslyCTL；
Operational amplifier OP1Non-inverting input terminal be used for receive bleeder circuit (10) output voltage Δ V；
Operational amplifier OP1Voltage output end of the output end as positive amplifying circuit (7), with resistance R1One end connection, electricity
Hinder R1The other end and operational amplifier OP1Inverting input terminal connection；
Operational amplifier OP1Positive supply input terminal and power supply VDDConnection, operational amplifier OP1Negative supply input terminal and power supply
VSSConnection, and VDD=-VSS。
5. a kind of analog-digital converter generated for probability calculation sequence according to claim 4, which is characterized in that N number of
The structure of votage control switch active pull-up is identical, and each votage control switch active pull-up includes 3 PMOS tube Mp1To Mp3With 5 NMOS
Pipe Mn1To Mn5；
NMOS tube Mn2Grid as votage control switch active pull-up a fixed connection end and operational amplifier OP1Reverse phase it is defeated
Enter end connection；
The negative output terminal of 1V power supply is connect as another fixed connection end of votage control switch active pull-up with power ground；
PMOS tube Mp3Voltage controling end of the drain electrode as votage control switch active pull-up；
PMOS tube Mp3Switch control terminal of the grid as votage control switch active pull-up；
The positive output end of 1V power supply simultaneously with NMOS tube Mn1Grid, NMOS tube Mn1Drain electrode, PMOS tube Mp1Source electrode, PMOS
Pipe Mp2Source electrode, NMOS tube Mn5Drain electrode connection；
NMOS tube Mn1Source electrode simultaneously with NMOS tube Mn2Grid, NMOS tube Mn2Drain electrode, NMOS tube Mn3Drain electrode, PMOS tube
Mp1Drain electrode connection；PMOS tube Mp1Grid simultaneously with PMOS tube Mp2Grid, PMOS tube Mp2Drain electrode, NMOS tube Mn4Leakage
Pole connection；
NMOS tube Mn2Source electrode simultaneously with NMOS tube Mn3Source electrode, NMOS tube Mn4Source electrode, PMOS tube Mp3Source electrode and NMOS tube
Mn5Source electrode connection；
NMOS tube Mn3Grid and NMOS tube Mn4Grid connect with power ground；
PMOS tube Mp3Grid and NMOS tube Mn5Grid connection.
6. a kind of analog-digital converter generated for probability calculation sequence according to claim 1, which is characterized in that due to
d’1To d 'NRespectively with its corresponding to d1To dNLogical relation on the contrary, then voltage VAExpression formula are as follows:
I is integer.
7. a kind of analog-digital converter generated for probability calculation sequence according to claim 1, which is characterized in that due to
d’1To d 'NRespectively with its corresponding to d1To dNLogical relation on the contrary, then difference voltage VBExpression formula are as follows:
I is integer.
8. a kind of analog-digital converter generated for probability calculation sequence according to claim 1, which is characterized in that two-way
The data transfer mode of shift register (5) is serial input, parallel output.
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