CN115882821A

CN115882821A - Digital filter, filtering method and electronic equipment

Info

Publication number: CN115882821A
Application number: CN202111160750.1A
Authority: CN
Inventors: 邓伟翔; 郭燕; 王恒杰
Original assignee: Sanechips Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd
Priority date: 2021-09-30
Filing date: 2021-09-30
Publication date: 2023-03-31
Also published as: WO2023050729A1

Abstract

The application discloses a digital filter, a filtering method and electronic equipment. The digital filter includes a data filtering module, wherein the data filtering module includes: the processing unit is used for correcting the n input data to be processed to obtain processed data; wherein the processing data comprises uncorrected input data and corrected data, and n is an integer greater than or equal to 2; and the filtering unit is used for filtering the processing data to obtain target data, wherein the target data is unmodified input data. According to the technical scheme, burrs generated by inconsistency of input data in a long-distance mode can be eliminated, and the power consumption of the digital filter is reduced.

Description

Digital filter, filtering method and electronic equipment

Technical Field

The present disclosure relates to the field of digital circuit design technologies, and in particular, to a digital filter, a filtering method, and an electronic device.

Background

Digital filters are fundamental building blocks in digital signal processing systems. For a digital filter with time slots, the time division multiplexing technology can greatly reduce the number of multipliers in the digital filter, thereby reducing the area and power consumption of the digital filter. However, current digital filters still do not effectively reduce power consumption.

Disclosure of Invention

The embodiment of the application mainly aims to provide a digital filter, a filtering method and electronic equipment, and aims to reduce power consumption.

In a first aspect, an embodiment of the present application provides a digital filter, which includes a data filtering module, where the data filtering module includes:

the processing unit is used for correcting n input data to be processed to obtain processed data; wherein the processing data comprises unmodified input data and modified data, and n is an integer greater than or equal to 2;

and the filtering unit is used for outputting target data based on the processing data, wherein the target data is unmodified input data.

In some embodiments, the processing unit comprises:

the first input end of the AND gate inputs the input data, and the second input end of the AND gate inputs a filtering mark; wherein the filter flag is a flag corresponding to a filter condition of the input data;

and the output end of the AND gate is connected with the input end of the filtering unit.

In some embodiments, the bit width of the filter flag is the same as the bit width of the input data corresponding to the target data, and each bit of the filter flag corresponding to the target data is 1;

the bit width of the filtering mark is the same as the bit width of the input data corresponding to the processing data, and each bit of the filtering mark corresponding to the correction data is 0.

In some embodiments, the processing unit further comprises:

the input end of the NOR gate is connected with the No. 1, no. 2, no. 8230, no. 8230and No. n-1 filtering marks, the output end of the NOR gate is connected with the input end of the No. n AND gate, and the output signal of the NOR gate is used as the filtering mark of the No. n AND gate.

In some embodiments, the filtering unit includes an or gate, an input terminal of the or gate is connected to an output terminal of the and gate, and an output terminal of the or gate serves as an output terminal of the data filtering module.

In some embodiments, the digital filter further comprises: the input end of the multiplier is connected with the output end of the data filtering module, the output end of the multiplier is connected with the input end of the first adder, and the output end of the first adder is connected with the input end of the first adder.

In some embodiments, the digital filter further comprises:

and the input end of the second adder is connected with the output end of the first adder, and the output end of the second adder is used as the output end of the digital filter.

In some embodiments, the digital filter further comprises:

the delay module is used for delaying the input data, the input end of the delay module receives the input data, and the output end of the delay module is connected with the input end of the data filtering module and the input end of the next-stage delay module.

In a second aspect, an embodiment of the present application provides a digital filtering method, based on the digital filter provided in the first aspect, including the following steps:

the device is used for correcting n input data to be processed to obtain processed data; wherein the processing data comprises unmodified input data and modified data, and n is an integer greater than or equal to 2;

and filtering the processed data to obtain target data, wherein the target data is unmodified input data.

In some embodiments, the performing modification processing on n input data to be processed to obtain processed data includes:

and performing correction processing on the n input data to be processed through an and operation based on a filtering mark and the input data to obtain processing data, wherein the filtering mark is a mark corresponding to a filtering condition of the input data.

In some embodiments, the filtering marks include a first filtering mark and a second filtering mark, and the second filtering mark is obtained by performing or operating 0 th, 1 st, 2 nd, 8230, and (n-2) th filtering marks and performing a reverse operation.

In some embodiments, the performing a modification process on the n input data to be processed based on the filter flag and the input data by an and operation to obtain processed data includes:

under the condition that a multiplier performs effective calculation, correcting the n input data to be processed through AND operation on the basis of the first filtering mark, the second filtering mark and the input data to obtain processed data;

and under the condition that the multiplier performs invalid calculation, performing correction processing on the n input data to be processed through AND operation based on a second filtering mark and the input data to obtain processed data.

In a third aspect, an embodiment of the present application provides an electronic device, including a digital filter that processes input data to be processed, where the digital filter provided in the first aspect of the present application is used as the digital filter.

According to the digital filter, the input data to be processed are corrected through the processing unit to obtain the processed data, and other input data with inconsistent data length are modified into the corrected data except for the target data, so that the influence of inconsistent input data length is avoided, burrs are eliminated, and the power consumption of the digital filter is reduced.

Drawings

FIG. 1 is a basic schematic diagram of a digital filter in an embodiment of the present application;

FIG. 2 is a schematic diagram of a multiplier and adder in a digital filter using 1;

FIG. 3 is a timing diagram of an input to a second data filtering block in a digital filter that is sometimes multiplexed;

fig. 4 is a schematic structural diagram of a digital filter according to an embodiment of the present application;

FIG. 5 is a timing diagram of a digital filter according to an embodiment of the present application;

FIG. 6 is a timing diagram of a data filtering module in an embodiment of the present application;

FIG. 7 is a timing diagram of a data filtering module after adding a NOR gate in an embodiment of the present application;

fig. 8 is a schematic structural diagram of a digital filter according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of another digital filter provided in an embodiment of the present application;

fig. 10 is a flowchart of a digital filtering method according to an embodiment of the present application.

Detailed Description

In order to enable those skilled in the art to better understand the technical solution of the present application, the following detailed description is provided for a server provided in the present application with reference to the accompanying drawings.

Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but which may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," 8230; \8230 "; when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The embodiments described herein may be described with reference to plan views and/or cross-sectional views through idealized schematic representations of the present application. Accordingly, the example illustrations can be modified in accordance with manufacturing techniques and/or tolerances. Accordingly, the embodiments are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on a manufacturing process. Thus, the regions illustrated in the figures have schematic properties, and the shapes of the regions shown in the figures illustrate specific shapes of regions of elements, but are not intended to be limiting.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present application and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The basic principle of a digital filter is to implement the operation y (t) = x (t) × h (n), where x (t) represents input data, h (n) represents filter coefficients, and y (t) represents output data, i.e. to implement a convolution of input data and filter coefficients. Fig. 1 is a basic schematic diagram of a digital filter. As shown in FIG. 1, Z ^-1 A delay term representing the input data,

denotes a multiplier, ". Lambda." denotes an adder, h ₀ 、h ₁ 、……、h _n-1 、h _n Representing the filter coefficients.

Since the multipliers occupy a large area of the digital filter, in the digital filter with time slots, a time division multiplexing technique is often used to reduce the number of multipliers in the digital filter, so as to reduce the area of the digital filter. For example, the time division multiplexing ratio is 1: the digital filter of n can reduce the number of multipliers to 1/n of the original number.

Fig. 2 is a schematic diagram of multipliers and adders in a digital filter employing the 1. As shown in fig. 2, the digital filter includes a plurality of time division multiplexing modules 210 and a plurality of second adders 220, wherein the input end of the second adder 220 receives the output signal of the time division multiplexing module 210 at the same stage as the second adder 220, and the output signal of the second adder 220 at the next stage is added step by the second adder 220.

Each time division multiplexing module 210 includes a first data filtering module 201, a second data filtering module 202, a multiplier 203, and a first adder 204, where the first data filtering module 201 is configured to filter a filter coefficient, the first data filtering module 201 includes an input end and an output end, the input end of the first data filtering module 201 receives filter coefficients h (0), h (1), \8230, 8230, h (n-1), and a filter condition sel, and the output end of the first data filtering module 201 is connected to a first input end of the multiplier 203. The second data filtering module 202 is configured to filter the input data, the second data filtering module 202 includes an input end and an output end, the input end of the second data filtering module 202 receives the input data x (0), x (1), \ 8230 \ x (n-1), and the filtering condition sel, and the output end of the second data filtering module 202 is connected to the second input end of the multiplier 203. A first input terminal of the multiplier 203 is connected to the output terminal of the first data filtering module 201, a second input terminal of the multiplier 203 is connected to the output terminal of the second data filtering module 202, an output terminal of the multiplier 203 is connected to the input terminal of the first adder 204, and an output terminal of the first adder 204 is connected to the input terminal, so that the feedback signal of the first adder 204 is input to the first adder 204 for time division multiplexing.

In some embodiments, the first data filtering module 201 and the second data filtering module 202 respectively filter the filter coefficients and the input data by the filter condition sel as the input of the multiplier 203, so as to reduce the number and volume of the multipliers to 1/n.

In actual use, the input data x (0), x (1), \ 8230 \ 8230;, x (n-1) input to the second data filtering module 202 is continuously changed, and the input data has different lengths, so that the input data arrives at the input end of the second data filtering module 202 at different times, and thus, glitches are generated at the input end of the second data filtering module 202, and there are more or less input signals and glitches at the input end of the second data filtering module 202.

Fig. 3 is a timing diagram of the input to the second data filtering block in a digital filter that is sometimes multiplexed. As shown in fig. 3, the input data x (0), x (1), \8230;, and x (n) have different growth times, which results in a large amount of glitches at the input end of the second data filtering module, and thus, the power consumption is increased.

In order to eliminate the glitch at the input end of the second data filtering module, the digital filter in the digital filter is improved. The digital filter receives a plurality of input data and outputs a target data, and the target data is a portion of the plurality of input data, such as one or more input data. For the convenience of the description,

fig. 4 is a schematic structural diagram of a digital filter according to an embodiment of the present application. As shown in fig. 4, the digital filter includes a data filtering module 41 for filtering the input data. The data filtering module 41 includes a processing unit 401 and a filtering unit 402.

The processing unit 401 is configured to perform modification processing on a plurality of input data to be processed to obtain processed data, where the processed data includes unmodified input data and modified data.

Where the input data is a digital code of the discrete signal to be processed. After the input data is modified, the modified data does not affect other input data (e.g., target data), does not transmit a transition at the input of the filtering unit, and is easily filtered by the filtering unit 402. In some embodiments, the process data includes an unmodified input data, and at least one modified input data. The correction data may be a fixed value that facilitates the filtering unit 402 to select the target data from the processed data without affecting the run length of the target data. For example, the correction data is 0 or other suitable value.

For convenience of description, the plurality of input data is expressed as n input data, where n is an integer greater than or equal to 2.

In some embodiments, within a preset clock cycle, performing modification processing on n input data to obtain processed data, where the processed data is to identify and modify the input data, and the processed data includes the input data itself to be filtered and modified data after the input data is modified. For example, after the input data is processed, if the input data is still the input data itself, the input data is the target data; if corrected, the input data is the data to be filtered out. In other words, only one input data is kept unchanged in the preset clock period, and other input data is corrected, so that the filtering unit is favorable for filtering.

And a filtering unit 402, configured to filter the processing data to obtain target data, where the target data is unmodified input data.

In some embodiments, the target data is input data that is not modified by the processing unit 401, i.e. the target data is one of the input data. After being filtered by the filtering unit 402, the target data is output. Other input data are modified by the processing unit 401 to fixed values that are easily filtered, which fixed values are not filtered by the filtering unit 402, and therefore input data that are not modified are not filtered out by the filtering unit.

In this embodiment, the processing unit 401 and the filtering unit 402 work together to retain the required input data, and the other input data is modified into modified data that is easily filtered and does not jump at the input end of the filtering unit. For example, after the input data is modified to 0 by the processing unit, no jump occurs at the input end of the filtering unit, and the glitch is eliminated, thereby reducing the power consumption.

The digital filter provided by the embodiment of the application carries out correction processing on a plurality of input data to be processed through the processing unit to obtain the processed data, and modifies other input data with inconsistent data length into the corrected data except the target data, so that the influence of inconsistent data length is avoided, burrs are eliminated, the power consumption of the digital filter is reduced, and the digital filter is beneficial to filtering of the filtering unit and is convenient for selecting the target data.

In some embodiments, the processing unit 401 includes and gates 4011, and the number of and gates 4011 is not less than the number of input data. In this embodiment, the number of the and gates 4011 is the same as the number of the input data, a first input terminal of each and gate 4011 inputs an input data, a second input terminal of each and gate 4011 inputs a filter flag, and an output terminal of each and gate 4011 is connected to an input terminal of the filter unit 402. The and gate 4011 filter-modifies the input data by means of the filter flag, leaves the required input data unchanged, and modifies the unnecessary input data into the correction data.

The filtering flag is a flag corresponding to a filtering condition of the input data, and the filtering condition may be preset by a user.

For example, the processing unit 401 includes n and gates 4011, first input terminals of the n and gates 4011 respectively access input data x (0), x (1), 8230, and x (n-1), second input terminals respectively access filtering marks m (0), m (1), 8230, and m (n-1), and output terminals of the n and gates 4011 are all connected to the filtering unit 402. The method comprises the steps of inputting data x (0), x (1), 8230, outputting processed data after the data x (n-1) and corresponding filtering marks m (0), m (1), 8230, m (n-1) pass through an AND gate 4011.

In some embodiments, the bit width of the filter flag is the same as the bit width of the input data corresponding to the target data, and each bit of the filter flag corresponding to the target data is 1; the bit width of the filter flag is the same as the bit width of the input data corresponding to the processing data and each bit of the filter flag corresponding to the processing data is 0.

For example, when the digital filter takes the input data x (0) as the target data according to the filter condition sel, each bit of the filter flag m (0) corresponding to the input data x (0) is 1, and the bit width of the filter flag m (0) is the same as the bit width of the input data x (0), in other words, the filter flag m (0) is 1 of the bit width length of the input data x (0). The method comprises the steps of processing data x (1), x (2), 8230, wherein each bit of the m (n-1) is 0, and the filtering marks m (1), m (2) and 8230, which correspond to the data x (n-1), are 0, and the bit widths of the m (1), m (2), 8230, m (n-1) are the same as those of the corresponding input data x (1), x (2), 8230, x (n-1), in other words, the bit widths of the m (1), m (2), 8230, x (2), 8230, m (n-1) are 0 of the corresponding input data x (1), x (2), 8230, x (821) and the bit width length of the x (n-1). For example, the filtering flag m (1) is 0 of the bit width length of the input data x (1), the filtering flag m (2) is 0 of the bit width length of the input data x (2), and so on, the filtering flag m (n-1) is 0 of the bit width length of the input data x (n-1).

In this embodiment, each bit in the filter flag is set to "0" and "1", each bit of the filter flag corresponding to the target data is set to "1", each bit of the filter flag corresponding to the correction data is set to "0", and thus, other input data except the target data is easily filtered, that is, other input data except the target data is corrected to be the correction data without generating a jump, so as to eliminate a glitch generated by other input data.

Fig. 5 is a timing diagram of a digital filter according to an embodiment of the present application. Referring to fig. 4 and 5, the input data x (0) and the filter mark m (0) are anded by the and gate 4011 to obtain the output data q (0), the input data x (1) and the filter mark m (1) are anded by the and gate 4011 to obtain the output data q (1), the input data x (2) and the filter mark m (2) are anded by the and gate 4011 to obtain the output data q (2), and so on, the input data x (n-1) and the filter mark m (n-1) are anded by the and gate 4011 to obtain the output data q (n-1). In fig. 5, the input data x (0) is used as the target signal, and the filter flag m (0) is 1 of the bit width length of the input data x (0), so the output data q (0) is the same as the target data x (0), i.e., a ₀ Other input data x (1), x (2), and (8230) \ 8230;, x (n-1) is filtered data, corresponding filtering marks m (1), m (2), and (8230); \8230; m (n-1) is 0, and output data q (1), q (2), and (8230); q (n-1) is corrected data, that is, 0. Will output the numberAccording to q (0), q (1), \8230;, q (n-1) input to the filter unit 402, since the correction data is 0, no glitch is caused at the input end of the filter unit 402, and the local IR drop (the more current and resistance causes the drop, the larger the IR drop) is greatly improved.

In the digital filter provided by the embodiment of the application, the processing unit is used for correcting a plurality of input data to be processed to obtain uncorrected input data and corrected fixed data, so that the corrected fixed data does not jump at the input end of the filtering unit, and the uncorrected input data is output as target data by the filtering unit. In addition, the register registers different input data, outputs the input data when needed, the power consumption is far larger than that of the direct processing unit and the filtering unit, the processing delay of the circuit is increased by the register, and the processing efficiency is low.

In practical applications, the data filtering module outputs the output result to the multiplier, but the multiplier sometimes does not perform calculation, i.e. belongs to non-calculation term output, and fig. 6 is a timing diagram of another data filtering module in the embodiment of the present application. As shown in fig. 6, the processing unit 401 sequentially processes input data x (0), x (1), \8230;, and x (n-1) in accordance with the clock cycle CLK, and modifies other input data in the same clock cycle into corrected data. Thus, the output of the processing unit 401 in accordance with the clock cycle CLK is in turn a ₀ 、b ₁ 、……、c _n And the output of the processing unit 401 is set to 0 for some subsequent clock cycle. In order to reduce power consumption, if the output of the digital filter module 41 is set to 0, the signal output by the non-calculation term is easy to invert, and the power consumption caused by inversion is larger.

Based on this, in some embodiments, as shown in fig. 4, the filtering unit is an or gate 4021, an input terminal of the or gate 4021 is connected to an output terminal of the and gate 4011, and an output terminal of the or gate 4021 serves as an output terminal of the data filtering module. For example, output data q (0), q (1), \8230;, q (n-1) are connected to an input terminal of or gate 4021, and an output terminal of or gate 4021 may be connected to a multiplier.

As shown in fig. 4, the processing unit further includes a nor gate 4012, inputs of the nor gate 4012 are respectively connected to 1 st, 2 nd, 8230, and n-1 th filtering marks, an output of the nor gate 4012 is connected to an input of the nth and gate 4011, and an output signal of the nor gate 4012 serves as the filtering mark of the nth and gate 4011.

For example, the nor gate 4012 is provided with n input terminals, which are respectively connected to the filtering marks m (0), m (1), and \8230 \8230andm (n-1), and the output terminal of the nor gate 4012 is connected to the input terminal of the nth and gate 4011.

In some embodiments, the filtering indicia includes a first filtering indicia and a second filtering indicia, and the second filtering indicia is obtained by performing or operating on 0 th, 1 st, 2 nd, \8230 \ 8230;, n-2 nd filtering indicia (i.e., the first n-1 filtering indicia) and reversing the operation. The first filtering indicia is obtained in a conventional manner and is not limited in this application.

And under the condition that the multiplier performs effective calculation, performing correction processing on n input data to be processed through AND operation on the basis of the first filtering mark, the second filtering mark and the input data to obtain processed data. And under the condition that the multiplier performs invalid calculation, performing correction processing on the n input data to be processed through AND operation on the basis of the second filtering marks and the input data to obtain processed data.

For example, in the case where the multiplier does not perform calculation, each bit of the filter flags m (0), m (1), \8230, m (n-1) is 0, the output of the nor gate 4012 is 1, the output of the nor gate 4012 is and-operated with the input data x (t), the holding value cn is obtained, and the output data q (n) is and-operated with the last input data, and then the holding value cn is output through the filter unit 402.

FIG. 7 is a timing diagram of the data filtering module after the addition or not of the NOR gate in the embodiment of the present application. As shown in fig. 7, the processing unit 401 processes the input data x (0), x (1), \ 8230 \ 8230;, x (n-1) in sequence according to the clock cycle CLK, and filters out other input data in the same clock cycle. Thus, while the multiplier is performing an active calculation, the processing unit 401 is sequentially a according to the output of the clock cycle CLK ₀ 、b ₁ 、……、c _n When the multiplier performs the invalid calculation, the processing unit 401 holds x (n-1) by the second filter flag m (n-1)In the item, the output of the processing unit 401 is not 0. The cn is output by the processing unit 401, so that the output data of the filtering unit 402 is the cn value, and the signal output by the non-computation item is prevented from being inverted when the multiplier performs invalid computation, thereby reducing the power consumption caused by inversion.

Fig. 8 is a schematic structural diagram of a digital filter according to an embodiment of the present application. As shown in fig. 8, the digital filter includes a first data filtering module 801, a second data filtering module 802, a multiplier 80/3, and a first adder 804, wherein an input of the multiplier 803 is connected to an output of the first data filtering module 801, an output of the multiplier 803 is connected to an input of the first adder 803, and an output of the first adder 804 is connected to an input thereof. The structure and principle of the first data filtering module 801 are the same as those of the data filtering module provided in this embodiment, and are not described herein again. The second data filtering module 802 may employ an existing data filtering module.

As described above, the multiplier 803 may filter the calculations as needed or may not filter the calculations. When the multiplier 803 filters the calculation, the first data filtering module 801 filters target data from input data in different clock cycles CLK and filters other input data to eliminate glitches between the input data and reduce power consumption, and when the multiplier 803 does not perform calculation, the first data filtering module 801 outputs the holding value cn to avoid inversion of non-calculation item output and reduce power consumption caused by inversion.

Fig. 9 is a schematic structural diagram of another digital filter according to an embodiment of the present application. As shown in fig. 9, the digital filter includes a plurality of first data filtering modules 901, second data filtering modules 902, multipliers 903, first adders 904, and second adders 905, where the structure and the summation principle of the data filtering modules 901 are the same as those of the data filtering modules provided in this embodiment, and are not described herein again.

In the present embodiment, each first data filtering module 901 corresponds to a multiplier 903, a first adder 904 and a second adder 905. Each second data filtering module 902 corresponds to a multiplier 903, a first adder 904 and a second adder 905, the input end of the multiplier 903 is connected with the output ends of the first data filtering module 901 and the second data filtering module 902, the output end of the multiplier 903 is connected with the input end of the first adder 904, the output end of the first adder 904 is connected with the input end thereof to realize time division multiplexing, and the output end of the first adder 904 is simultaneously connected with the input end of the second adder 905. A first input of the second adder 905 is connected to an output of the first adder 904, and a second input of the second adder 905 is connected to an output of the other second adder, that is, the second adder 905 simultaneously receives an output signal of the first adder 904 and an output signal of the other second adder 905. The second data filtering module 902 is used for filtering the filter coefficients, which may adopt an existing data filtering module, or may filter the data filtering module provided by the present application.

In some embodiments, the digital filter further comprises a delay module 906 for delaying the input data x (t), an input of the delay module 906 receiving the input data, and an output of the delay module 906 connected to an input of the data filtering module and an input of the next stage delay module. When the delay block 906 is the last stage, the output of the delay block 906 is connected only to the input of the data filter block.

In some embodiments, there is one delay module 906 per input data, and each delay module 906 may delay the input data corresponding thereto according to actual circumstances. The operation principle and operation of the delay module 906 are not improved, and are the same as the conventional delay module 906, and are not described in detail herein.

It should be noted that the digital filter provided in this embodiment may be applied to application scenarios such as video, audio, communication signal rate conversion, filtering processing, and the like, and completes up-sampling and down-sampling of a digital signal, so as to implement various encryption algorithms requiring a large number of multipliers.

In a second aspect of the present application, a digital filtering method is provided based on the digital filter provided above, and fig. 10 is a flowchart of a digital filtering method provided in an embodiment of the present application. As shown in fig. 4 and 10, the digital filtering method includes:

step S1001, which is used for correcting n input data to be processed to obtain processed data; wherein, the processing data comprises unmodified input data and modified data, and n is an integer greater than or equal to 2.

Wherein the input data is a digital code of a discrete signal to be processed. The input data is correctable, and after being corrected to corrected data, no transition is sent at the input of the filtering unit and is easily rejected by the filtering unit 402. In some embodiments, the process data includes an unmodified input data, and at least one modified input data. The correction data may be a fixed value that enables the filter unit 402 to be selected from the processed data. For example, the correction data is 0 or other suitable value.

In some embodiments, within a preset clock cycle, n input data are subjected to modification processing to obtain processed data, where the processed data includes modified data obtained by performing modification processing on the input data and the input data itself. For example, after the input data x (0) is filtered, if the processed data is the input data itself, the input data is the target data. In other words, only one input data is kept unchanged and other input data is corrected in a preset clock period, so that the filtering unit is favorable for filtering.

In step S1002, target data is output based on the processed data, wherein the target data is input data that is not corrected.

In some embodiments, the target data is input data that is not modified by the processing unit 401, i.e. the target data is one of the input data. After being filtered by the filtering unit 402, the target data is output. Other input data is modified by the processing unit 401 to a fixed value that is easily filtered, which is easily filtered by the filtering unit 402, so that the modified input data is filtered by the filtering unit.

The embodiment of the application reserves required input data, and other input data are corrected into correction data which are easily filtered and do not jump at the input end of the filtering unit. For example, after the input data is modified to 0 by the processing unit, the input end of the filtering unit jumps, and burrs are eliminated, so that the power consumption caused by the burrs is reduced.

According to the digital filtering method provided by the embodiment of the application, the input data to be processed are corrected to obtain the processed data, the filter unit outputs the input data which is not corrected in the processed data as the target data, other input data are corrected into the corrected data, the corrected data are easy to eliminate by the filter unit, jumping at the input end of the filter unit is avoided, burrs are eliminated, and therefore the power consumption of the digital filter is reduced.

In some embodiments, the modifying n input data to be processed to obtain the processed data includes: and performing correction processing on n pieces of input data to be processed by and operation based on the filter flag and the input data to obtain processed data, wherein the filter flag is a flag corresponding to a filter condition of the input data.

In some embodiments, the input data is modified by using an and gate and a filter flag m (0), m (1), 8230, m (n-1) is a flag corresponding to a filter condition of the input data, and the filter condition can be preset by a user.

For example, n AND gates are provided, the first input end of each AND gate is respectively connected with input data x (0), x (1), 8230, and x (n-1), the second input end of each AND gate is respectively connected with filtering marks m (0), m (1), and 8230, the 8230, and the m (n-1), and the output end of each AND gate is the result of AND operation of one input data and one filtering mark, namely the input data x (0), x (1), and 8230, the x (n-1) and the corresponding filtering marks m (0), m (1), and 8230, and the m (n-1) are subjected to AND operation to obtain n processed data.

In some embodiments, the bit width of the filter flag is the same as the bit width of the input data corresponding to the target data, and each bit of the filter flag corresponding to the target data is 1; the bit width of the filter flag is the same as the bit width of the input data corresponding to the processed data, and each bit of the filter flag corresponding to the corrected data is 0.

For example, if it is determined according to the filter conditions selThe input data x (0) is filtered in the first clock cycle, so that the filtering marks m (0) are 1 in each bit, the filtering marks m (1), m (2), \8230, the filtering marks 8230, and the filtering marks m (n-1) are 0 in each bit. The processed data obtained by performing an AND operation on the input data x (0) and the filter flag m (0) is the input data x (0) itself, i.e., a ₀ (ii) a Furthermore, since the bit width of the filter flag is the same as the bit width of the corresponding input data, the processing data is always maintained at a during the first clock cycle ₀ . The processed data obtained after the AND operation of the input data x (1), x (2), and the corresponding filtering marks m (1), m (2), and the corresponding filtering marks m (8230), wherein the processing data of the m (n-1) is 0, and the bit width of the filtering marks is the same as the bit width of the corresponding input data, so that the processed data is always 0 in the first clock cycle. Thus, the process data includes an a ₀ And n-1 0, in the first clock period, the processing data corresponding to the input data x (0) is always kept a ₀ The processing data corresponding to the input data x (1), x (2), and \8230;, and x (n-1) always remains 0.

At some time period, the calculation result of the multiplier is adopted. But in some time periods the calculation of the multiplier is not used. In order to reduce power consumption, the digital filter does not perform data processing during a period in which the calculation result of the multiplier is determined not to be employed.

In some embodiments, the filter indicia includes a first filter indicia and a second filter indicia, wherein the second filter indicia is obtained by performing or operating on 0 th, 1 st, 2 nd, \8230, and/or (n-2) th filter indicia (i.e., the first n-1 filter indicia) and reversing the filter indicia.

In the case of calculation by the multiplier, correction processing is performed on n pieces of input data to be processed by an and operation based on the first filter flag and the input data, and processed data is obtained. And under the condition that the multiplier does not perform calculation, performing correction processing on the n input data to be processed through AND operation based on the second filtering marks and the input data to obtain processed data.

Under the condition that the multiplier does not perform calculation, the processing data is a holding value, and the signal output by a non-calculation item is prevented from being inverted when the multiplier does not perform calculation, so that the power consumption caused by inversion is reduced.

Before filtering by using a digital filter and a digital filtering method, it is necessary to determine whether a multiplier in the digital filter can perform time division multiplexing, and if time division multiplexing can be performed, the data filter and the filtering method provided by the present application may be adopted. If the digital filter has signal inversion output by non-calculation items, the digital filter with the NOR gate additionally arranged in the processing unit can be adopted to avoid the inversion, so that the power consumption caused by the inversion is reduced.

A third aspect of the embodiments of the present application provides an electronic device, including a digital filter that performs modification processing on input data to be processed, where the digital filter is the digital filter provided in the first aspect of the embodiments of the present application.

According to the electronic device provided by the embodiment of the application, the digital filter corrects a plurality of input data to be processed through the processing unit to obtain the processed data, the filter unit outputs the input data which is not corrected in the processed data as the target data, the input data reaches the filter unit after being corrected without jumping, burrs generated among the input data are eliminated, and therefore the power consumption of the digital filter is reduced, namely the power consumption of the electronic device is reduced.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, and functional modules/units in the devices, as claimed above, may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

Example embodiments have been applied herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the application as set forth in the appended claims.

Claims

1. A digital filter comprising a data filtering module, wherein the data filtering module comprises:

and the filtering unit is used for filtering the processing data to obtain target data, wherein the target data is unmodified input data.

2. The digital filter according to claim 1, wherein the processing unit comprises:

3. The digital filter according to claim 2, wherein the bit width of the filtering flag is the same as the bit width of the input data corresponding to the target data, and each bit of the filtering flag corresponding to the target data is 1;

4. The digital filter of claim 2, wherein the processing unit further comprises:

5. The digital filter according to claim 2, wherein the filter unit comprises an or gate, an input of the or gate is connected to an output of the and gate, and an output of the or gate serves as an output of the data filter module.

6. The digital filter according to any of claims 1-5, wherein the digital filter further comprises: the input end of the multiplier is connected with the output end of the data filtering module, the output end of the multiplier is connected with the input end of the first adder, and the output end of the first adder is connected with the input end of the first adder.

7. The digital filter of claim 6, further comprising:

8. The digital filter according to any of claims 1-5, wherein the digital filter further comprises:

9. A digital filtering method, characterized in that the digital filter according to any one of claims 1-8 comprises the steps of:

10. The digital filtering method according to claim 9, wherein the performing modification processing on n input data to be processed to obtain processed data comprises:

11. The digital filtering method according to claim 10, wherein the bit width of the filtering flag is the same as the bit width of the input data corresponding to the target data, and each bit of the filtering flag corresponding to the target data is 1;

the bit width of the filtering mark is the same as the bit width of the input data corresponding to the processing data, and the bit position of the filtering mark corresponding to the correction data is 0.

12. The digital filtering method according to claim 10, wherein the filtering marks comprise a first filtering mark and a second filtering mark, and the second filtering mark is obtained by performing or operating 0 th, 1 st, 2 nd, 8230 \ 8230;, n-2 nd filtering marks and performing inversion.

13. The digital filtering method according to claim 12, wherein the obtaining the processed data by performing a modification process on the n input data to be processed based on the filter flag and the input data by an and operation comprises:

and under the condition that the multiplier performs invalid calculation, performing correction processing on the n input data to be processed through AND operation on the basis of the second filtering marks and the input data to obtain processed data.

14. An electronic device comprising a digital filter for processing input data to be processed, wherein the digital filter is the digital filter of any one of claims 1-8.